cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

pipeline.json (1826B)

      1[
      2  {
      3    "EventCode": "0xC7",
      4    "EventName": "STALL_SB_FULL",
      5    "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
      6  },
      7  {
      8    "EventCode": "0xE0",
      9    "EventName": "OTHER_IQ_DEP_STALL",
     10    "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
     11  },
     12  {
     13    "EventCode": "0xE1",
     14    "EventName": "IC_DEP_STALL",
     15    "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
     16  },
     17  {
     18    "EventCode": "0xE2",
     19    "EventName": "IUTLB_DEP_STALL",
     20    "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
     21  },
     22  {
     23    "EventCode": "0xE3",
     24    "EventName": "DECODE_DEP_STALL",
     25    "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
     26  },
     27  {
     28    "EventCode": "0xE4",
     29    "EventName": "OTHER_INTERLOCK_STALL",
     30    "BriefDescription": "Cycles there is an interlock other than  Advanced SIMD/Floating-point instructions or load/store instruction"
     31  },
     32  {
     33    "EventCode": "0xE5",
     34    "EventName": "AGU_DEP_STALL",
     35    "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
     36  },
     37  {
     38    "EventCode": "0xE6",
     39    "EventName": "SIMD_DEP_STALL",
     40    "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
     41  },
     42  {
     43    "EventCode": "0xE7",
     44    "EventName": "LD_DEP_STALL",
     45    "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
     46  },
     47  {
     48    "EventCode": "0xE8",
     49    "EventName": "ST_DEP_STALL",
     50    "BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
     51  }
     52]