pipeline.json (6297B)
1[ 2 { 3 "ArchStdEvent": "STALL_FRONTEND" 4 }, 5 { 6 "ArchStdEvent": "STALL_BACKEND" 7 }, 8 { 9 "PublicDescription": "No operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed", 10 "EventCode": "0xE1", 11 "EventName": "STALL_FRONTEND_CACHE", 12 "BriefDescription": "No operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed" 13 }, 14 { 15 "PublicDescription": "No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is an instruction L1 TLB miss being processed", 16 "EventCode": "0xE2", 17 "EventName": "STALL_FRONTEND_TLB", 18 "BriefDescription": "No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is an instruction L1 TLB miss being processed" 19 }, 20 { 21 "PublicDescription": "No operation issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and there is a pre-decode error being processed", 22 "EventCode": "0xE3", 23 "EventName": "STALL_FRONTEND_PDERR", 24 "BriefDescription": "No operation issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and there is a pre-decode error being processed" 25 }, 26 { 27 "PublicDescription": "No operation issued due to the backend interlock.This event counts every cycle that issue is stalled and there is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded", 28 "EventCode": "0xE4", 29 "EventName": "STALL_BACKEND_ILOCK", 30 "BriefDescription": "No operation issued due to the backend interlock.This event counts every cycle that issue is stalled and there is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded" 31 }, 32 { 33 "PublicDescription": "No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock that is due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded", 34 "EventCode": "0xE5", 35 "EventName": "STALL_BACKEND_ILOCK_AGU", 36 "BriefDescription": "No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock that is due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded" 37 }, 38 { 39 "PublicDescription": "No operation issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled and there is an interlock that is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded", 40 "EventCode": "0xE6", 41 "EventName": "STALL_BACKEND_ILOCK_FPU", 42 "BriefDescription": "No operation issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled and there is an interlock that is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded" 43 }, 44 { 45 "PublicDescription": "No operation issued due to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load", 46 "EventCode": "0xE7", 47 "EventName": "STALL_BACKEND_LD", 48 "BriefDescription": "No operation issued due to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load" 49 }, 50 { 51 "PublicDescription": "No operation issued due to the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store", 52 "EventCode": "0xE8", 53 "EventName": "STALL_BACKEND_ST", 54 "BriefDescription": "No operation issued due to the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store" 55 }, 56 { 57 "PublicDescription": "No operation issued due to the backend, load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)", 58 "EventCode": "0xE9", 59 "EventName": "STALL_BACKEND_LD_CACHE", 60 "BriefDescription": "No operation issued due to the backend, load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)" 61 }, 62 { 63 "PublicDescription": "No operation issued due to the backend, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load which has missed in the L1 TLB", 64 "EventCode": "0xEA", 65 "EventName": "STALL_BACKEND_LD_TLB", 66 "BriefDescription": "No operation issued due to the backend, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load which has missed in the L1 TLB" 67 }, 68 { 69 "PublicDescription": "No operation issued due to the backend, store, STB full.This event counts every cycle there is a stall in the Wr stage due to a store which is waiting due to the STB being full", 70 "EventCode": "0xEB", 71 "EventName": "STALL_BACKEND_ST_STB", 72 "BriefDescription": "No operation issued due to the backend, store, STB full.This event counts every cycle there is a stall in the Wr stage due to a store which is waiting due to the STB being full" 73 }, 74 { 75 "PublicDescription": "No operation issued due to the backend, store, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a store which has missed in the L1 TLB", 76 "EventCode": "0xEC", 77 "EventName": "STALL_BACKEND_ST_TLB", 78 "BriefDescription": "No operation issued due to the backend, store, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a store which has missed in the L1 TLB" 79 } 80]