cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

atcpmu.json (7816B)

      1[
      2  {
      3	"PublicDescription": "Conditional branch",
      4    "EventCode": "0x102",
      5    "EventName": "cond_br",
      6    "BriefDescription": "V3 Conditional branch"
      7  },
      8  {
      9	"PublicDescription": "Taken conditional branches",
     10    "EventCode": "0x103",
     11    "EventName": "taken_cond_br",
     12    "BriefDescription": "V3 Taken Conditional branch"
     13  },
     14  {
     15	"PublicDescription": "Prefetch Instruction",
     16    "EventCode": "0x104",
     17    "EventName": "prefetch_inst",
     18    "BriefDescription": "V3 Prefetch Instruction"
     19  },
     20  {
     21	"PublicDescription": "RET Inst",
     22    "EventCode": "0x105",
     23    "EventName": "ret_inst",
     24    "BriefDescription": "V3 RET Inst"
     25  },
     26  {
     27	"PublicDescription": "JR(non-RET) instructions",
     28    "EventCode": "0x106",
     29    "EventName": "jr_inst",
     30    "BriefDescription": "V3 JR(non-RET) instructions"
     31  },
     32  {
     33	"PublicDescription": "JAL/JRAL instructions",
     34    "EventCode": "0x107",
     35    "EventName": "jal_jral_inst",
     36    "BriefDescription": "V3 JAL/JRAL instructions"
     37  },
     38  {
     39	"PublicDescription": "NOP instructions",
     40    "EventCode": "0x108",
     41    "EventName": "nop_inst",
     42    "BriefDescription": "V3 NOP instructions"
     43  },
     44  {
     45	"PublicDescription": "SCW instructions",
     46    "EventCode": "0x109",
     47    "EventName": "scw_inst",
     48    "BriefDescription": "V3 SCW instructions"
     49  },
     50  {
     51	"PublicDescription": "ISB/DSB instructions",
     52    "EventCode": "0x10a",
     53    "EventName": "isb_dsb_inst",
     54    "BriefDescription": "V3 ISB/DSB instructions"
     55  },
     56  {
     57	"PublicDescription": "CCTL instructions",
     58    "EventCode": "0x10b",
     59    "EventName": "cctl_inst",
     60    "BriefDescription": "V3 CCTL instructions"
     61  },
     62  {
     63	"PublicDescription": "Taken Interrupts",
     64    "EventCode": "0x10c",
     65    "EventName": "taken_interrupts",
     66    "BriefDescription": "V3 Taken Interrupts"
     67  },
     68  {
     69	"PublicDescription": "Loads Completed",
     70    "EventCode": "0x10d",
     71    "EventName": "load_completed",
     72    "BriefDescription": "V3 Loads Completed"
     73  },
     74  {
     75	"PublicDescription": "uITLB accesses",
     76    "EventCode": "0x10e",
     77    "EventName": "uitlb_access",
     78    "BriefDescription": "V3 uITLB accesses"
     79  },
     80  {
     81	"PublicDescription": "uDTLB accesses",
     82    "EventCode": "0x10f",
     83    "EventName": "udtlb_access",
     84    "BriefDescription": "V3 uDTLB accesses"
     85  },
     86  {
     87	"PublicDescription": "MTLB accesses",
     88    "EventCode": "0x110",
     89    "EventName": "mtlb_access",
     90    "BriefDescription": "V3 MTLB accesses"
     91  },
     92  {
     93	"PublicDescription": "DATA_DEPENDENCY_STALL_CYCLES",
     94    "EventCode": "0x112",
     95    "EventName": "data_dependency_stall",
     96    "BriefDescription": "V3 DATA_DEPENDENCY_STALL_CYCLES"
     97  },
     98  {
     99	"PublicDescription": "DATA_CACHE_MISS_STALL_CYCLES",
    100    "EventCode": "0x113",
    101    "EventName": "dcache_miss_stall",
    102    "BriefDescription": "V3 DATA_CACHE_MISS_STALL_CYCLES"
    103  },
    104  {
    105	"PublicDescription": "ILM access",
    106    "EventCode": "0x118",
    107    "EventName": "ilm_access",
    108    "BriefDescription": "V3 ILM accesses"
    109  },
    110  {
    111	"PublicDescription": "LSU BIU CYCLES",
    112    "EventCode": "0x119",
    113    "EventName": "lsu_biu_cycles",
    114    "BriefDescription": "V3 LSU BIU CYCLES"
    115  },
    116  {
    117	"PublicDescription": "HPTWK BIU CYCLES",
    118    "EventCode": "0x11a",
    119    "EventName": "hptwk_biu_cycles",
    120    "BriefDescription": "V3 HPTWK BIU CYCLES"
    121  },
    122  {
    123	"PublicDescription": "DMA BIU CYCLES",
    124    "EventCode": "0x11b",
    125    "EventName": "dma_biu_cycles",
    126    "BriefDescription": "V3 DMA BIU CYCLES"
    127  },
    128  {
    129	"PublicDescription": "CODE CACHE FILL BIU CYCLES",
    130    "EventCode": "0x11c",
    131    "EventName": "icache_fill_biu_cycles",
    132    "BriefDescription": "V3 CODE CACHE FILL BIU CYCLES"
    133  },
    134  {
    135	"PublicDescription": "LEAGAL UNALIGN DCACHE ACCESS",
    136    "EventCode": "0x11d",
    137    "EventName": "legal_unalined_dcache_access",
    138    "BriefDescription": "V3 LEAGAL UNALIGN DCACHE ACCESS"
    139  },
    140  {
    141	"PublicDescription": "PUSH25 instructions",
    142    "EventCode": "0x11e",
    143    "EventName": "push25_inst",
    144    "BriefDescription": "V3 PUSH25 instructions"
    145  },
    146  {
    147	"PublicDescription": "SYSCALL instructions",
    148    "EventCode": "0x11f",
    149    "EventName": "syscall_inst",
    150    "BriefDescription": "V3 SYSCALL instructions"
    151  },
    152  {
    153	"PublicDescription": "conditional branch miss",
    154    "EventCode": "0x202",
    155    "EventName": "cond_br_miss",
    156    "BriefDescription": "V3 conditional branch miss"
    157  },
    158  {
    159	"PublicDescription": "taken conditional branch miss",
    160    "EventCode": "0x203",
    161    "EventName": "taken_cond_br_miss",
    162    "BriefDescription": "V3 taken conditional branch miss"
    163  },
    164  {
    165	"PublicDescription": "Prefetch Instructions with cache hit",
    166    "EventCode": "0x204",
    167    "EventName": "prefetch_icache_hit",
    168    "BriefDescription": "V3 Prefetch Instructions with cache hit"
    169  },
    170  {
    171	"PublicDescription": "RET mispredict",
    172    "EventCode": "0x205",
    173    "EventName": "ret_mispredict",
    174    "BriefDescription": "V3 RET mispredict"
    175  },
    176  {
    177	"PublicDescription": "Immediate J instructions",
    178    "EventCode": "0x206",
    179    "EventName": "imm_j_inst",
    180    "BriefDescription": "V3 Immediate J instructions"
    181  },
    182  {
    183	"PublicDescription": "Multiply instructions",
    184    "EventCode": "0x207",
    185    "EventName": "mul_inst",
    186    "BriefDescription": "V3 Multiply instructions"
    187  },
    188  {
    189	"PublicDescription": "16 bits instructions",
    190    "EventCode": "0x208",
    191    "EventName": "sixteen_bits_inst",
    192    "BriefDescription": "V3 16 bits instructions"
    193  },
    194  {
    195	"PublicDescription": "Failed SCW instructions",
    196    "EventCode": "0x209",
    197    "EventName": "fail_scw_inst",
    198    "BriefDescription": "V3 Failed SCW instructions"
    199  },
    200  {
    201	"PublicDescription": "ld-after-st conflict replays",
    202    "EventCode": "0x20a",
    203    "EventName": "ld_af_st_conflict",
    204    "BriefDescription": "V3 ld-after-st conflict replays"
    205  },
    206  {
    207	"PublicDescription": "Exception taken",
    208    "EventCode": "0x20c",
    209    "EventName": "exception_taken",
    210    "BriefDescription": "V3 Exception taken"
    211  },
    212  {
    213	"PublicDescription": "Stores completed",
    214    "EventCode": "0x20d",
    215    "EventName": "store_completed",
    216    "BriefDescription": "V3 Stores completed"
    217  },
    218  {
    219	"PublicDescription": "uITLB miss",
    220    "EventCode": "0x20e",
    221    "EventName": "uitlb_miss",
    222    "BriefDescription": "V3 uITLB miss"
    223  },
    224  {
    225	"PublicDescription": "uDTLB miss",
    226    "EventCode": "0x20f",
    227    "EventName": "udtlb_miss",
    228    "BriefDescription": "V3 uDTLB miss"
    229  },
    230  {
    231	"PublicDescription": "MTLB miss",
    232    "EventCode": "0x210",
    233    "EventName": "mtlb_miss",
    234    "BriefDescription": "V3 MTLB miss"
    235  },
    236  {
    237	"PublicDescription": "Empty instructions queue stall cycles",
    238    "EventCode": "0x212",
    239    "EventName": "empty_inst_q_stall",
    240    "BriefDescription": "V3 Empty instructions queue stall cycles"
    241  },
    242  {
    243	"PublicDescription": "Data write back",
    244    "EventCode": "0x213",
    245    "EventName": "data_wb",
    246    "BriefDescription": "V3 Data write back"
    247  },
    248  {
    249	"PublicDescription": "DLM access",
    250    "EventCode": "0x218",
    251    "EventName": "dlm_access",
    252    "BriefDescription": "V3 DLM access"
    253  },
    254  {
    255	"PublicDescription": "LSU BIU request",
    256    "EventCode": "0x219",
    257    "EventName": "lsu_biu_req",
    258    "BriefDescription": "V3 LSU BIU request"
    259  },
    260  {
    261	"PublicDescription": "HPTWK BIU request",
    262    "EventCode": "0x21a",
    263    "EventName": "hptwk_biu_req",
    264    "BriefDescription": "V3 HPTWK BIU request"
    265  },
    266  {
    267	"PublicDescription": "DMA BIU request",
    268    "EventCode": "0x21b",
    269    "EventName": "dma_biu_req",
    270    "BriefDescription": "V3 DMA BIU request"
    271  },
    272  {
    273	"PublicDescription": "Icache fill BIU request",
    274    "EventCode": "0x21c",
    275    "EventName": "icache_fill_biu_req",
    276    "BriefDescription": "V3 Icache fill BIU request"
    277  },
    278  {
    279	"PublicDescription": "External events",
    280    "EventCode": "0x21d",
    281    "EventName": "external_events",
    282    "BriefDescription": "V3 External events"
    283  },
    284  {
    285	"PublicDescription": "POP25 instructions",
    286    "EventCode": "0x21e",
    287    "EventName": "pop25_inst",
    288    "BriefDescription": "V3 POP25 instructions"
    289  }
    290]