cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

cache.json (2668B)

      1[
      2  {
      3    "EventCode": "0x1003C",
      4    "EventName": "PM_EXEC_STALL_DMISS_L2L3",
      5    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3."
      6  },
      7  {
      8    "EventCode": "0x1E054",
      9    "EventName": "PM_EXEC_STALL_DMISS_L21_L31",
     10    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from another core's L2 or L3 on the same chip."
     11  },
     12  {
     13    "EventCode": "0x34054",
     14    "EventName": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT",
     15    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, without a dispatch conflict."
     16  },
     17  {
     18    "EventCode": "0x34056",
     19    "EventName": "PM_EXEC_STALL_LOAD_FINISH",
     20    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the NTF instruction merged with another load in the LMQ; cycles in which the NTF instruction is waiting for a data reload for a load miss, but the data comes back with a non-NTF instruction."
     21  },
     22  {
     23    "EventCode": "0x3006C",
     24    "EventName": "PM_RUN_CYC_SMT2_MODE",
     25    "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."
     26  },
     27  {
     28    "EventCode": "0x300F4",
     29    "EventName": "PM_RUN_INST_CMPL_CONC",
     30    "BriefDescription": "PowerPC instructions completed by this thread when all threads in the core had the run-latch set."
     31  },
     32  {
     33    "EventCode": "0x4C016",
     34    "EventName": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT",
     35    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict."
     36  },
     37  {
     38    "EventCode": "0x4D014",
     39    "EventName": "PM_EXEC_STALL_LOAD",
     40    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction executing in the Load Store Unit."
     41  },
     42  {
     43    "EventCode": "0x4D016",
     44    "EventName": "PM_EXEC_STALL_PTESYNC",
     45    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruction executing in the Load Store Unit."
     46  },
     47  {
     48    "EventCode": "0x401EA",
     49    "EventName": "PM_THRESH_EXC_128",
     50    "BriefDescription": "Threshold counter exceeded a value of 128."
     51  },
     52  {
     53    "EventCode": "0x400F6",
     54    "EventName": "PM_BR_MPRED_CMPL",
     55    "BriefDescription": "A mispredicted branch completed. Includes direction and target."
     56  }
     57]