cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

translation.json (6633B)

      1[
      2  {
      3    "EventCode": "0x4c054",
      4    "EventName": "PM_DERAT_MISS_16G",
      5    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G",
      6    "PublicDescription": ""
      7  },
      8  {
      9    "EventCode": "0x3c054",
     10    "EventName": "PM_DERAT_MISS_16M",
     11    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M",
     12    "PublicDescription": ""
     13  },
     14  {
     15    "EventCode": "0x1c056",
     16    "EventName": "PM_DERAT_MISS_4K",
     17    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K",
     18    "PublicDescription": ""
     19  },
     20  {
     21    "EventCode": "0x2c054",
     22    "EventName": "PM_DERAT_MISS_64K",
     23    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K",
     24    "PublicDescription": ""
     25  },
     26  {
     27    "EventCode": "0x4e048",
     28    "EventName": "PM_DPTEG_FROM_DL2L3_MOD",
     29    "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request",
     30    "PublicDescription": ""
     31  },
     32  {
     33    "EventCode": "0x3e048",
     34    "EventName": "PM_DPTEG_FROM_DL2L3_SHR",
     35    "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request",
     36    "PublicDescription": ""
     37  },
     38  {
     39    "EventCode": "0x1e042",
     40    "EventName": "PM_DPTEG_FROM_L2",
     41    "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request",
     42    "PublicDescription": ""
     43  },
     44  {
     45    "EventCode": "0x1e04e",
     46    "EventName": "PM_DPTEG_FROM_L2MISS",
     47    "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a data side request",
     48    "PublicDescription": ""
     49  },
     50  {
     51    "EventCode": "0x2e040",
     52    "EventName": "PM_DPTEG_FROM_L2_MEPF",
     53    "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request",
     54    "PublicDescription": ""
     55  },
     56  {
     57    "EventCode": "0x1e040",
     58    "EventName": "PM_DPTEG_FROM_L2_NO_CONFLICT",
     59    "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request",
     60    "PublicDescription": ""
     61  },
     62  {
     63    "EventCode": "0x4e042",
     64    "EventName": "PM_DPTEG_FROM_L3",
     65    "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request",
     66    "PublicDescription": ""
     67  },
     68  {
     69    "EventCode": "0x3e042",
     70    "EventName": "PM_DPTEG_FROM_L3_DISP_CONFLICT",
     71    "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request",
     72    "PublicDescription": ""
     73  },
     74  {
     75    "EventCode": "0x2e042",
     76    "EventName": "PM_DPTEG_FROM_L3_MEPF",
     77    "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request",
     78    "PublicDescription": ""
     79  },
     80  {
     81    "EventCode": "0x1e044",
     82    "EventName": "PM_DPTEG_FROM_L3_NO_CONFLICT",
     83    "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request",
     84    "PublicDescription": ""
     85  },
     86  {
     87    "EventCode": "0x1e04c",
     88    "EventName": "PM_DPTEG_FROM_LL4",
     89    "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request",
     90    "PublicDescription": ""
     91  },
     92  {
     93    "EventCode": "0x2e048",
     94    "EventName": "PM_DPTEG_FROM_LMEM",
     95    "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request",
     96    "PublicDescription": ""
     97  },
     98  {
     99    "EventCode": "0x2e04c",
    100    "EventName": "PM_DPTEG_FROM_MEMORY",
    101    "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request",
    102    "PublicDescription": ""
    103  },
    104  {
    105    "EventCode": "0x4e04a",
    106    "EventName": "PM_DPTEG_FROM_OFF_CHIP_CACHE",
    107    "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request",
    108    "PublicDescription": ""
    109  },
    110  {
    111    "EventCode": "0x1e048",
    112    "EventName": "PM_DPTEG_FROM_ON_CHIP_CACHE",
    113    "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request",
    114    "PublicDescription": ""
    115  },
    116  {
    117    "EventCode": "0x2e046",
    118    "EventName": "PM_DPTEG_FROM_RL2L3_MOD",
    119    "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request",
    120    "PublicDescription": ""
    121  },
    122  {
    123    "EventCode": "0x1e04a",
    124    "EventName": "PM_DPTEG_FROM_RL2L3_SHR",
    125    "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request",
    126    "PublicDescription": ""
    127  },
    128  {
    129    "EventCode": "0x2e04a",
    130    "EventName": "PM_DPTEG_FROM_RL4",
    131    "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request",
    132    "PublicDescription": ""
    133  },
    134  {
    135    "EventCode": "0x300fc",
    136    "EventName": "PM_DTLB_MISS",
    137    "BriefDescription": "Data PTEG reload",
    138    "PublicDescription": "Data PTEG Reloaded (DTLB Miss)"
    139  },
    140  {
    141    "EventCode": "0x1c058",
    142    "EventName": "PM_DTLB_MISS_16G",
    143    "BriefDescription": "Data TLB Miss page size 16G",
    144    "PublicDescription": ""
    145  },
    146  {
    147    "EventCode": "0x4c056",
    148    "EventName": "PM_DTLB_MISS_16M",
    149    "BriefDescription": "Data TLB Miss page size 16M",
    150    "PublicDescription": ""
    151  },
    152  {
    153    "EventCode": "0x2c056",
    154    "EventName": "PM_DTLB_MISS_4K",
    155    "BriefDescription": "Data TLB Miss page size 4k",
    156    "PublicDescription": ""
    157  },
    158  {
    159    "EventCode": "0x3c056",
    160    "EventName": "PM_DTLB_MISS_64K",
    161    "BriefDescription": "Data TLB Miss page size 64K",
    162    "PublicDescription": ""
    163  },
    164  {
    165    "EventCode": "0x200f6",
    166    "EventName": "PM_LSU_DERAT_MISS",
    167    "BriefDescription": "DERAT Reloaded due to a DERAT miss",
    168    "PublicDescription": "DERAT Reloaded (Miss)"
    169  },
    170  {
    171    "EventCode": "0x20066",
    172    "EventName": "PM_TLB_MISS",
    173    "BriefDescription": "TLB Miss (I + D)",
    174    "PublicDescription": ""
    175  }
    176]