cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

basic.json (3441B)

      1[
      2	{
      3		"Unit": "CPU-M-CF",
      4		"EventCode": "0",
      5		"EventName": "CPU_CYCLES",
      6		"BriefDescription": "Cycle Count",
      7		"PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state."
      8	},
      9	{
     10		"Unit": "CPU-M-CF",
     11		"EventCode": "1",
     12		"EventName": "INSTRUCTIONS",
     13		"BriefDescription": "Instruction Count",
     14		"PublicDescription": "This counter counts the total number of instructions executed by the CPU."
     15	},
     16	{
     17		"Unit": "CPU-M-CF",
     18		"EventCode": "2",
     19		"EventName": "L1I_DIR_WRITES",
     20		"BriefDescription": "Level-1 I-Cache Directory Write Count",
     21		"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes."
     22	},
     23	{
     24		"Unit": "CPU-M-CF",
     25		"EventCode": "3",
     26		"EventName": "L1I_PENALTY_CYCLES",
     27		"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
     28		"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
     29	},
     30	{
     31		"Unit": "CPU-M-CF",
     32		"EventCode": "4",
     33		"EventName": "L1D_DIR_WRITES",
     34		"BriefDescription": "Level-1 D-Cache Directory Write Count",
     35		"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes."
     36	},
     37	{
     38		"Unit": "CPU-M-CF",
     39		"EventCode": "5",
     40		"EventName": "L1D_PENALTY_CYCLES",
     41		"BriefDescription": "Level-1 D-Cache Penalty Cycle Count",
     42		"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache."
     43	},
     44	{
     45		"Unit": "CPU-M-CF",
     46		"EventCode": "32",
     47		"EventName": "PROBLEM_STATE_CPU_CYCLES",
     48		"BriefDescription": "Problem-State Cycle Count",
     49		"PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state."
     50	},
     51	{
     52		"Unit": "CPU-M-CF",
     53		"EventCode": "33",
     54		"EventName": "PROBLEM_STATE_INSTRUCTIONS",
     55		"BriefDescription": "Problem-State Instruction Count",
     56		"PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state."
     57	},
     58	{
     59		"Unit": "CPU-M-CF",
     60		"EventCode": "34",
     61		"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
     62		"BriefDescription": "Problem-State Level-1 I-Cache Directory Write Count",
     63		"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes while the CPU is in the problem state."
     64	},
     65	{
     66		"Unit": "CPU-M-CF",
     67		"EventCode": "35",
     68		"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
     69		"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
     70		"PublicDescription": "This counter counts the total number of penalty cycles for level-1 instruction cache or unified cache while the CPU is in the problem state."
     71	},
     72	{
     73		"Unit": "CPU-M-CF",
     74		"EventCode": "36",
     75		"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
     76		"BriefDescription": "Problem-State Level-1 D-Cache Directory Write Count",
     77		"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes while the CPU is in the problem state."
     78	},
     79	{
     80		"Unit": "CPU-M-CF",
     81		"EventCode": "37",
     82		"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
     83		"BriefDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count",
     84		"PublicDescription": "This counter counts the total number of penalty cycles for level-1 data cache while the CPU is in the problem state."
     85	}
     86]