cache.json (39699B)
1[ 2 { 3 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 4 "CollectPEBSRecord": "2", 5 "Counter": "0,1,2,3,4,5", 6 "EventCode": "0x34", 7 "EventName": "MEM_BOUND_STALLS.IFETCH", 8 "PEBScounters": "0,1,2,3,4,5", 9 "SampleAfterValue": "200003", 10 "UMask": "0x38", 11 "Unit": "cpu_atom" 12 }, 13 { 14 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in DRAM or MMIO (Non-DRAM).", 15 "CollectPEBSRecord": "2", 16 "Counter": "0,1,2,3,4,5", 17 "EventCode": "0x34", 18 "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", 19 "PEBScounters": "0,1,2,3,4,5", 20 "SampleAfterValue": "200003", 21 "UMask": "0x20", 22 "Unit": "cpu_atom" 23 }, 24 { 25 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the L2 cache.", 26 "CollectPEBSRecord": "2", 27 "Counter": "0,1,2,3,4,5", 28 "EventCode": "0x34", 29 "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", 30 "PEBScounters": "0,1,2,3,4,5", 31 "SampleAfterValue": "200003", 32 "UMask": "0x8", 33 "Unit": "cpu_atom" 34 }, 35 { 36 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the last level cache or other core with HITE/F/M.", 37 "CollectPEBSRecord": "2", 38 "Counter": "0,1,2,3,4,5", 39 "EventCode": "0x34", 40 "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", 41 "PEBScounters": "0,1,2,3,4,5", 42 "SampleAfterValue": "200003", 43 "UMask": "0x10", 44 "Unit": "cpu_atom" 45 }, 46 { 47 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 48 "CollectPEBSRecord": "2", 49 "Counter": "0,1,2,3,4,5", 50 "EventCode": "0x34", 51 "EventName": "MEM_BOUND_STALLS.LOAD", 52 "PEBScounters": "0,1,2,3,4,5", 53 "SampleAfterValue": "200003", 54 "UMask": "0x7", 55 "Unit": "cpu_atom" 56 }, 57 { 58 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", 59 "CollectPEBSRecord": "2", 60 "Counter": "0,1,2,3,4,5", 61 "EventCode": "0x34", 62 "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", 63 "PEBScounters": "0,1,2,3,4,5", 64 "SampleAfterValue": "200003", 65 "UMask": "0x4", 66 "Unit": "cpu_atom" 67 }, 68 { 69 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", 70 "CollectPEBSRecord": "2", 71 "Counter": "0,1,2,3,4,5", 72 "EventCode": "0x34", 73 "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", 74 "PEBScounters": "0,1,2,3,4,5", 75 "SampleAfterValue": "200003", 76 "UMask": "0x1", 77 "Unit": "cpu_atom" 78 }, 79 { 80 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.", 81 "CollectPEBSRecord": "2", 82 "Counter": "0,1,2,3,4,5", 83 "EventCode": "0x34", 84 "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", 85 "PEBScounters": "0,1,2,3,4,5", 86 "SampleAfterValue": "200003", 87 "UMask": "0x2", 88 "Unit": "cpu_atom" 89 }, 90 { 91 "BriefDescription": "Counts the number of load ops retired that hit in DRAM.", 92 "CollectPEBSRecord": "2", 93 "Counter": "0,1,2,3,4,5", 94 "Data_LA": "1", 95 "EventCode": "0xd1", 96 "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", 97 "PEBS": "1", 98 "PEBScounters": "0,1,2,3,4,5", 99 "SampleAfterValue": "200003", 100 "UMask": "0x80", 101 "Unit": "cpu_atom" 102 }, 103 { 104 "BriefDescription": "Counts the number of load ops retired that hit in the L2 cache.", 105 "CollectPEBSRecord": "2", 106 "Counter": "0,1,2,3,4,5", 107 "Data_LA": "1", 108 "EventCode": "0xd1", 109 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 110 "PEBS": "1", 111 "PEBScounters": "0,1,2,3,4,5", 112 "SampleAfterValue": "200003", 113 "UMask": "0x2", 114 "Unit": "cpu_atom" 115 }, 116 { 117 "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache.", 118 "CollectPEBSRecord": "2", 119 "Counter": "0,1,2,3,4,5", 120 "EventCode": "0xd1", 121 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", 122 "PEBS": "1", 123 "PEBScounters": "0,1,2,3,4,5", 124 "SampleAfterValue": "200003", 125 "UMask": "0x4", 126 "Unit": "cpu_atom" 127 }, 128 { 129 "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.", 130 "CollectPEBSRecord": "2", 131 "Counter": "0,1,2,3,4,5", 132 "EventCode": "0x04", 133 "EventName": "MEM_SCHEDULER_BLOCK.ALL", 134 "PEBScounters": "0,1,2,3,4,5", 135 "SampleAfterValue": "20003", 136 "UMask": "0x7", 137 "Unit": "cpu_atom" 138 }, 139 { 140 "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.", 141 "CollectPEBSRecord": "2", 142 "Counter": "0,1,2,3,4,5", 143 "EventCode": "0x04", 144 "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", 145 "PEBScounters": "0,1,2,3,4,5", 146 "SampleAfterValue": "20003", 147 "UMask": "0x2", 148 "Unit": "cpu_atom" 149 }, 150 { 151 "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.", 152 "CollectPEBSRecord": "2", 153 "Counter": "0,1,2,3,4,5", 154 "EventCode": "0x04", 155 "EventName": "MEM_SCHEDULER_BLOCK.RSV", 156 "PEBScounters": "0,1,2,3,4,5", 157 "SampleAfterValue": "20003", 158 "UMask": "0x4", 159 "Unit": "cpu_atom" 160 }, 161 { 162 "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.", 163 "CollectPEBSRecord": "2", 164 "Counter": "0,1,2,3,4,5", 165 "EventCode": "0x04", 166 "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", 167 "PEBScounters": "0,1,2,3,4,5", 168 "SampleAfterValue": "20003", 169 "UMask": "0x1", 170 "Unit": "cpu_atom" 171 }, 172 { 173 "BriefDescription": "Counts the number of load uops retired.", 174 "CollectPEBSRecord": "2", 175 "Counter": "0,1,2,3,4,5", 176 "Data_LA": "1", 177 "EventCode": "0xd0", 178 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 179 "PEBS": "1", 180 "PEBScounters": "0,1,2,3,4,5", 181 "SampleAfterValue": "200003", 182 "UMask": "0x81", 183 "Unit": "cpu_atom" 184 }, 185 { 186 "BriefDescription": "Counts the number of store uops retired.", 187 "CollectPEBSRecord": "2", 188 "Counter": "0,1,2,3,4,5", 189 "Data_LA": "1", 190 "EventCode": "0xd0", 191 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 192 "PEBS": "1", 193 "PEBScounters": "0,1,2,3,4,5", 194 "SampleAfterValue": "200003", 195 "UMask": "0x82", 196 "Unit": "cpu_atom" 197 }, 198 { 199 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 200 "CollectPEBSRecord": "3", 201 "Counter": "0,1,2,3,4,5", 202 "Data_LA": "1", 203 "EventCode": "0xd0", 204 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", 205 "MSRIndex": "0x3F6", 206 "MSRValue": "0x80", 207 "PEBS": "2", 208 "PEBScounters": "0,1,2,3,4,5", 209 "SampleAfterValue": "1000003", 210 "TakenAlone": "1", 211 "UMask": "0x5", 212 "Unit": "cpu_atom" 213 }, 214 { 215 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 216 "CollectPEBSRecord": "3", 217 "Counter": "0,1,2,3,4,5", 218 "Data_LA": "1", 219 "EventCode": "0xd0", 220 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", 221 "MSRIndex": "0x3F6", 222 "MSRValue": "0x10", 223 "PEBS": "2", 224 "PEBScounters": "0,1,2,3,4,5", 225 "SampleAfterValue": "1000003", 226 "TakenAlone": "1", 227 "UMask": "0x5", 228 "Unit": "cpu_atom" 229 }, 230 { 231 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 232 "CollectPEBSRecord": "3", 233 "Counter": "0,1,2,3,4,5", 234 "Data_LA": "1", 235 "EventCode": "0xd0", 236 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", 237 "MSRIndex": "0x3F6", 238 "MSRValue": "0x100", 239 "PEBS": "2", 240 "PEBScounters": "0,1,2,3,4,5", 241 "SampleAfterValue": "1000003", 242 "TakenAlone": "1", 243 "UMask": "0x5", 244 "Unit": "cpu_atom" 245 }, 246 { 247 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 248 "CollectPEBSRecord": "3", 249 "Counter": "0,1,2,3,4,5", 250 "Data_LA": "1", 251 "EventCode": "0xd0", 252 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", 253 "MSRIndex": "0x3F6", 254 "MSRValue": "0x20", 255 "PEBS": "2", 256 "PEBScounters": "0,1,2,3,4,5", 257 "SampleAfterValue": "1000003", 258 "TakenAlone": "1", 259 "UMask": "0x5", 260 "Unit": "cpu_atom" 261 }, 262 { 263 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 264 "CollectPEBSRecord": "3", 265 "Counter": "0,1,2,3,4,5", 266 "Data_LA": "1", 267 "EventCode": "0xd0", 268 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", 269 "MSRIndex": "0x3F6", 270 "MSRValue": "0x4", 271 "PEBS": "2", 272 "PEBScounters": "0,1,2,3,4,5", 273 "SampleAfterValue": "1000003", 274 "TakenAlone": "1", 275 "UMask": "0x5", 276 "Unit": "cpu_atom" 277 }, 278 { 279 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 280 "CollectPEBSRecord": "3", 281 "Counter": "0,1,2,3,4,5", 282 "Data_LA": "1", 283 "EventCode": "0xd0", 284 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", 285 "MSRIndex": "0x3F6", 286 "MSRValue": "0x200", 287 "PEBS": "2", 288 "PEBScounters": "0,1,2,3,4,5", 289 "SampleAfterValue": "1000003", 290 "TakenAlone": "1", 291 "UMask": "0x5", 292 "Unit": "cpu_atom" 293 }, 294 { 295 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 296 "CollectPEBSRecord": "3", 297 "Counter": "0,1,2,3,4,5", 298 "Data_LA": "1", 299 "EventCode": "0xd0", 300 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", 301 "MSRIndex": "0x3F6", 302 "MSRValue": "0x40", 303 "PEBS": "2", 304 "PEBScounters": "0,1,2,3,4,5", 305 "SampleAfterValue": "1000003", 306 "TakenAlone": "1", 307 "UMask": "0x5", 308 "Unit": "cpu_atom" 309 }, 310 { 311 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 312 "CollectPEBSRecord": "3", 313 "Counter": "0,1,2,3,4,5", 314 "Data_LA": "1", 315 "EventCode": "0xd0", 316 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", 317 "MSRIndex": "0x3F6", 318 "MSRValue": "0x8", 319 "PEBS": "2", 320 "PEBScounters": "0,1,2,3,4,5", 321 "SampleAfterValue": "1000003", 322 "TakenAlone": "1", 323 "UMask": "0x5", 324 "Unit": "cpu_atom" 325 }, 326 { 327 "BriefDescription": "Counts all the retired split loads.", 328 "CollectPEBSRecord": "2", 329 "Counter": "0,1,2,3,4,5", 330 "Data_LA": "1", 331 "EventCode": "0xd0", 332 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 333 "PEBS": "1", 334 "PEBScounters": "0,1,2,3,4,5", 335 "SampleAfterValue": "200003", 336 "UMask": "0x41", 337 "Unit": "cpu_atom" 338 }, 339 { 340 "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.", 341 "CollectPEBSRecord": "2", 342 "Counter": "0,1,2,3,4,5", 343 "EventCode": "0xd0", 344 "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", 345 "PEBS": "1", 346 "PEBScounters": "0,1,2,3,4,5", 347 "SampleAfterValue": "1000003", 348 "UMask": "0x6", 349 "Unit": "cpu_atom" 350 }, 351 { 352 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 353 "Counter": "0,1,2,3", 354 "EventCode": "0xB7", 355 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", 356 "MSRIndex": "0x1a6,0x1a7", 357 "MSRValue": "0x10003C0002", 358 "SampleAfterValue": "100003", 359 "UMask": "0x1", 360 "Unit": "cpu_atom" 361 }, 362 { 363 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.", 364 "CollectPEBSRecord": "2", 365 "Counter": "0,1,2,3,4,5", 366 "EventCode": "0x71", 367 "EventName": "TOPDOWN_FE_BOUND.ICACHE", 368 "PEBScounters": "0,1,2,3,4,5", 369 "SampleAfterValue": "1000003", 370 "UMask": "0x20", 371 "Unit": "cpu_atom" 372 }, 373 { 374 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", 375 "CollectPEBSRecord": "2", 376 "Counter": "0,1,2,3", 377 "EventCode": "0x51", 378 "EventName": "L1D.REPLACEMENT", 379 "PEBScounters": "0,1,2,3", 380 "SampleAfterValue": "100003", 381 "UMask": "0x1", 382 "Unit": "cpu_core" 383 }, 384 { 385 "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", 386 "CollectPEBSRecord": "2", 387 "Counter": "0,1,2,3", 388 "EventCode": "0x48", 389 "EventName": "L1D_PEND_MISS.FB_FULL", 390 "PEBScounters": "0,1,2,3", 391 "SampleAfterValue": "1000003", 392 "UMask": "0x2", 393 "Unit": "cpu_core" 394 }, 395 { 396 "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.", 397 "CollectPEBSRecord": "2", 398 "Counter": "0,1,2,3", 399 "CounterMask": "1", 400 "EdgeDetect": "1", 401 "EventCode": "0x48", 402 "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", 403 "PEBScounters": "0,1,2,3", 404 "SampleAfterValue": "1000003", 405 "UMask": "0x2", 406 "Unit": "cpu_core" 407 }, 408 { 409 "BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS", 410 "CollectPEBSRecord": "2", 411 "Counter": "0,1,2,3", 412 "EventCode": "0x48", 413 "EventName": "L1D_PEND_MISS.L2_STALL", 414 "PEBScounters": "0,1,2,3", 415 "SampleAfterValue": "1000003", 416 "UMask": "0x4", 417 "Unit": "cpu_core" 418 }, 419 { 420 "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 421 "CollectPEBSRecord": "2", 422 "Counter": "0,1,2,3", 423 "EventCode": "0x48", 424 "EventName": "L1D_PEND_MISS.L2_STALLS", 425 "PEBScounters": "0,1,2,3", 426 "SampleAfterValue": "1000003", 427 "UMask": "0x4", 428 "Unit": "cpu_core" 429 }, 430 { 431 "BriefDescription": "Number of L1D misses that are outstanding", 432 "CollectPEBSRecord": "2", 433 "Counter": "0,1,2,3", 434 "EventCode": "0x48", 435 "EventName": "L1D_PEND_MISS.PENDING", 436 "PEBScounters": "0,1,2,3", 437 "SampleAfterValue": "1000003", 438 "UMask": "0x1", 439 "Unit": "cpu_core" 440 }, 441 { 442 "BriefDescription": "Cycles with L1D load Misses outstanding.", 443 "CollectPEBSRecord": "2", 444 "Counter": "0,1,2,3", 445 "CounterMask": "1", 446 "EventCode": "0x48", 447 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 448 "PEBScounters": "0,1,2,3", 449 "SampleAfterValue": "1000003", 450 "UMask": "0x1", 451 "Unit": "cpu_core" 452 }, 453 { 454 "BriefDescription": "L2 cache lines filling L2", 455 "CollectPEBSRecord": "2", 456 "Counter": "0,1,2,3", 457 "EventCode": "0x25", 458 "EventName": "L2_LINES_IN.ALL", 459 "PEBScounters": "0,1,2,3", 460 "SampleAfterValue": "100003", 461 "UMask": "0x1f", 462 "Unit": "cpu_core" 463 }, 464 { 465 "BriefDescription": "All L2 requests.[This event is alias to L2_RQSTS.REFERENCES]", 466 "CollectPEBSRecord": "2", 467 "Counter": "0,1,2,3", 468 "EventCode": "0x24", 469 "EventName": "L2_REQUEST.ALL", 470 "PEBScounters": "0,1,2,3", 471 "SampleAfterValue": "200003", 472 "UMask": "0xff", 473 "Unit": "cpu_core" 474 }, 475 { 476 "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]", 477 "CollectPEBSRecord": "2", 478 "Counter": "0,1,2,3", 479 "EventCode": "0x24", 480 "EventName": "L2_REQUEST.MISS", 481 "PEBScounters": "0,1,2,3", 482 "SampleAfterValue": "200003", 483 "UMask": "0x3f", 484 "Unit": "cpu_core" 485 }, 486 { 487 "BriefDescription": "L2 code requests", 488 "CollectPEBSRecord": "2", 489 "Counter": "0,1,2,3", 490 "EventCode": "0x24", 491 "EventName": "L2_RQSTS.ALL_CODE_RD", 492 "PEBScounters": "0,1,2,3", 493 "SampleAfterValue": "200003", 494 "UMask": "0xe4", 495 "Unit": "cpu_core" 496 }, 497 { 498 "BriefDescription": "Demand Data Read requests", 499 "CollectPEBSRecord": "2", 500 "Counter": "0,1,2,3", 501 "EventCode": "0x24", 502 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 503 "PEBScounters": "0,1,2,3", 504 "SampleAfterValue": "200003", 505 "UMask": "0xe1", 506 "Unit": "cpu_core" 507 }, 508 { 509 "BriefDescription": "Demand requests that miss L2 cache", 510 "CollectPEBSRecord": "2", 511 "Counter": "0,1,2,3", 512 "EventCode": "0x24", 513 "EventName": "L2_RQSTS.ALL_DEMAND_MISS", 514 "PEBScounters": "0,1,2,3", 515 "SampleAfterValue": "200003", 516 "UMask": "0x27", 517 "Unit": "cpu_core" 518 }, 519 { 520 "BriefDescription": "RFO requests to L2 cache.", 521 "CollectPEBSRecord": "2", 522 "Counter": "0,1,2,3", 523 "EventCode": "0x24", 524 "EventName": "L2_RQSTS.ALL_RFO", 525 "PEBScounters": "0,1,2,3", 526 "SampleAfterValue": "200003", 527 "UMask": "0xe2", 528 "Unit": "cpu_core" 529 }, 530 { 531 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 532 "CollectPEBSRecord": "2", 533 "Counter": "0,1,2,3", 534 "EventCode": "0x24", 535 "EventName": "L2_RQSTS.CODE_RD_HIT", 536 "PEBScounters": "0,1,2,3", 537 "SampleAfterValue": "200003", 538 "UMask": "0xc4", 539 "Unit": "cpu_core" 540 }, 541 { 542 "BriefDescription": "L2 cache misses when fetching instructions", 543 "CollectPEBSRecord": "2", 544 "Counter": "0,1,2,3", 545 "EventCode": "0x24", 546 "EventName": "L2_RQSTS.CODE_RD_MISS", 547 "PEBScounters": "0,1,2,3", 548 "SampleAfterValue": "200003", 549 "UMask": "0x24", 550 "Unit": "cpu_core" 551 }, 552 { 553 "BriefDescription": "Demand Data Read requests that hit L2 cache", 554 "CollectPEBSRecord": "2", 555 "Counter": "0,1,2,3", 556 "EventCode": "0x24", 557 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 558 "PEBScounters": "0,1,2,3", 559 "SampleAfterValue": "200003", 560 "UMask": "0xc1", 561 "Unit": "cpu_core" 562 }, 563 { 564 "BriefDescription": "Demand Data Read miss L2, no rejects", 565 "CollectPEBSRecord": "2", 566 "Counter": "0,1,2,3", 567 "EventCode": "0x24", 568 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", 569 "PEBScounters": "0,1,2,3", 570 "SampleAfterValue": "200003", 571 "UMask": "0x21", 572 "Unit": "cpu_core" 573 }, 574 { 575 "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]", 576 "CollectPEBSRecord": "2", 577 "Counter": "0,1,2,3", 578 "EventCode": "0x24", 579 "EventName": "L2_RQSTS.MISS", 580 "PEBScounters": "0,1,2,3", 581 "SampleAfterValue": "200003", 582 "UMask": "0x3f", 583 "Unit": "cpu_core" 584 }, 585 { 586 "BriefDescription": "All L2 requests.[This event is alias to L2_REQUEST.ALL]", 587 "CollectPEBSRecord": "2", 588 "Counter": "0,1,2,3", 589 "EventCode": "0x24", 590 "EventName": "L2_RQSTS.REFERENCES", 591 "PEBScounters": "0,1,2,3", 592 "SampleAfterValue": "200003", 593 "UMask": "0xff", 594 "Unit": "cpu_core" 595 }, 596 { 597 "BriefDescription": "RFO requests that hit L2 cache.", 598 "CollectPEBSRecord": "2", 599 "Counter": "0,1,2,3", 600 "EventCode": "0x24", 601 "EventName": "L2_RQSTS.RFO_HIT", 602 "PEBScounters": "0,1,2,3", 603 "SampleAfterValue": "200003", 604 "UMask": "0xc2", 605 "Unit": "cpu_core" 606 }, 607 { 608 "BriefDescription": "RFO requests that miss L2 cache", 609 "CollectPEBSRecord": "2", 610 "Counter": "0,1,2,3", 611 "EventCode": "0x24", 612 "EventName": "L2_RQSTS.RFO_MISS", 613 "PEBScounters": "0,1,2,3", 614 "SampleAfterValue": "200003", 615 "UMask": "0x22", 616 "Unit": "cpu_core" 617 }, 618 { 619 "BriefDescription": "SW prefetch requests that hit L2 cache.", 620 "CollectPEBSRecord": "2", 621 "Counter": "0,1,2,3", 622 "EventCode": "0x24", 623 "EventName": "L2_RQSTS.SWPF_HIT", 624 "PEBScounters": "0,1,2,3", 625 "SampleAfterValue": "200003", 626 "UMask": "0xc8", 627 "Unit": "cpu_core" 628 }, 629 { 630 "BriefDescription": "SW prefetch requests that miss L2 cache.", 631 "CollectPEBSRecord": "2", 632 "Counter": "0,1,2,3", 633 "EventCode": "0x24", 634 "EventName": "L2_RQSTS.SWPF_MISS", 635 "PEBScounters": "0,1,2,3", 636 "SampleAfterValue": "200003", 637 "UMask": "0x28", 638 "Unit": "cpu_core" 639 }, 640 { 641 "BriefDescription": "TBD", 642 "CollectPEBSRecord": "2", 643 "Counter": "0,1,2,3,4,5,6,7", 644 "EventCode": "0x2e", 645 "EventName": "LONGEST_LAT_CACHE.MISS", 646 "PEBScounters": "0,1,2,3,4,5,6,7", 647 "SampleAfterValue": "100003", 648 "UMask": "0x41", 649 "Unit": "cpu_core" 650 }, 651 { 652 "BriefDescription": "All retired load instructions.", 653 "CollectPEBSRecord": "2", 654 "Counter": "0,1,2,3", 655 "Data_LA": "1", 656 "EventCode": "0xd0", 657 "EventName": "MEM_INST_RETIRED.ALL_LOADS", 658 "PEBS": "1", 659 "PEBScounters": "0,1,2,3", 660 "SampleAfterValue": "1000003", 661 "UMask": "0x81", 662 "Unit": "cpu_core" 663 }, 664 { 665 "BriefDescription": "All retired store instructions.", 666 "CollectPEBSRecord": "2", 667 "Counter": "0,1,2,3", 668 "Data_LA": "1", 669 "EventCode": "0xd0", 670 "EventName": "MEM_INST_RETIRED.ALL_STORES", 671 "L1_Hit_Indication": "1", 672 "PEBS": "1", 673 "PEBScounters": "0,1,2,3", 674 "SampleAfterValue": "1000003", 675 "UMask": "0x82", 676 "Unit": "cpu_core" 677 }, 678 { 679 "BriefDescription": "All retired memory instructions.", 680 "CollectPEBSRecord": "2", 681 "Counter": "0,1,2,3", 682 "Data_LA": "1", 683 "EventCode": "0xd0", 684 "EventName": "MEM_INST_RETIRED.ANY", 685 "L1_Hit_Indication": "1", 686 "PEBS": "1", 687 "PEBScounters": "0,1,2,3", 688 "SampleAfterValue": "1000003", 689 "UMask": "0x83", 690 "Unit": "cpu_core" 691 }, 692 { 693 "BriefDescription": "Retired load instructions with locked access.", 694 "CollectPEBSRecord": "2", 695 "Counter": "0,1,2,3", 696 "Data_LA": "1", 697 "EventCode": "0xd0", 698 "EventName": "MEM_INST_RETIRED.LOCK_LOADS", 699 "PEBS": "1", 700 "PEBScounters": "0,1,2,3", 701 "SampleAfterValue": "100007", 702 "UMask": "0x21", 703 "Unit": "cpu_core" 704 }, 705 { 706 "BriefDescription": "Retired load instructions that split across a cacheline boundary.", 707 "CollectPEBSRecord": "2", 708 "Counter": "0,1,2,3", 709 "Data_LA": "1", 710 "EventCode": "0xd0", 711 "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", 712 "PEBS": "1", 713 "PEBScounters": "0,1,2,3", 714 "SampleAfterValue": "100003", 715 "UMask": "0x41", 716 "Unit": "cpu_core" 717 }, 718 { 719 "BriefDescription": "Retired store instructions that split across a cacheline boundary.", 720 "CollectPEBSRecord": "2", 721 "Counter": "0,1,2,3", 722 "Data_LA": "1", 723 "EventCode": "0xd0", 724 "EventName": "MEM_INST_RETIRED.SPLIT_STORES", 725 "L1_Hit_Indication": "1", 726 "PEBS": "1", 727 "PEBScounters": "0,1,2,3", 728 "SampleAfterValue": "100003", 729 "UMask": "0x42", 730 "Unit": "cpu_core" 731 }, 732 { 733 "BriefDescription": "Retired load instructions that miss the STLB.", 734 "CollectPEBSRecord": "2", 735 "Counter": "0,1,2,3", 736 "Data_LA": "1", 737 "EventCode": "0xd0", 738 "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", 739 "PEBS": "1", 740 "PEBScounters": "0,1,2,3", 741 "SampleAfterValue": "100003", 742 "UMask": "0x11", 743 "Unit": "cpu_core" 744 }, 745 { 746 "BriefDescription": "Retired store instructions that miss the STLB.", 747 "CollectPEBSRecord": "2", 748 "Counter": "0,1,2,3", 749 "Data_LA": "1", 750 "EventCode": "0xd0", 751 "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", 752 "L1_Hit_Indication": "1", 753 "PEBS": "1", 754 "PEBScounters": "0,1,2,3", 755 "SampleAfterValue": "100003", 756 "UMask": "0x12", 757 "Unit": "cpu_core" 758 }, 759 { 760 "BriefDescription": "Completed demand load uops that miss the L1 d-cache.", 761 "CollectPEBSRecord": "2", 762 "Counter": "0,1,2,3", 763 "EventCode": "0x43", 764 "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", 765 "PEBScounters": "0,1,2,3", 766 "SampleAfterValue": "1000003", 767 "UMask": "0xfd", 768 "Unit": "cpu_core" 769 }, 770 { 771 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 772 "CollectPEBSRecord": "2", 773 "Counter": "0,1,2,3", 774 "Data_LA": "1", 775 "EventCode": "0xd2", 776 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", 777 "PEBS": "1", 778 "PEBScounters": "0,1,2,3", 779 "SampleAfterValue": "20011", 780 "UMask": "0x4", 781 "Unit": "cpu_core" 782 }, 783 { 784 "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", 785 "CollectPEBSRecord": "2", 786 "Counter": "0,1,2,3", 787 "Data_LA": "1", 788 "EventCode": "0xd2", 789 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", 790 "PEBS": "1", 791 "PEBScounters": "0,1,2,3", 792 "SampleAfterValue": "20011", 793 "UMask": "0x2", 794 "Unit": "cpu_core" 795 }, 796 { 797 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 798 "CollectPEBSRecord": "2", 799 "Counter": "0,1,2,3", 800 "Data_LA": "1", 801 "EventCode": "0xd2", 802 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", 803 "PEBS": "1", 804 "PEBScounters": "0,1,2,3", 805 "SampleAfterValue": "20011", 806 "UMask": "0x4", 807 "Unit": "cpu_core" 808 }, 809 { 810 "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", 811 "CollectPEBSRecord": "2", 812 "Counter": "0,1,2,3", 813 "Data_LA": "1", 814 "EventCode": "0xd2", 815 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", 816 "PEBS": "1", 817 "PEBScounters": "0,1,2,3", 818 "SampleAfterValue": "20011", 819 "UMask": "0x1", 820 "Unit": "cpu_core" 821 }, 822 { 823 "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", 824 "CollectPEBSRecord": "2", 825 "Counter": "0,1,2,3", 826 "Data_LA": "1", 827 "EventCode": "0xd2", 828 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", 829 "PEBS": "1", 830 "PEBScounters": "0,1,2,3", 831 "SampleAfterValue": "100003", 832 "UMask": "0x8", 833 "Unit": "cpu_core" 834 }, 835 { 836 "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", 837 "CollectPEBSRecord": "2", 838 "Counter": "0,1,2,3", 839 "Data_LA": "1", 840 "EventCode": "0xd2", 841 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", 842 "PEBS": "1", 843 "PEBScounters": "0,1,2,3", 844 "SampleAfterValue": "20011", 845 "UMask": "0x2", 846 "Unit": "cpu_core" 847 }, 848 { 849 "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", 850 "Counter": "0,1,2,3", 851 "Data_LA": "1", 852 "EventCode": "0xd3", 853 "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", 854 "PEBScounters": "0,1,2,3", 855 "SampleAfterValue": "100007", 856 "UMask": "0x1", 857 "Unit": "cpu_core" 858 }, 859 { 860 "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.", 861 "CollectPEBSRecord": "2", 862 "Counter": "0,1,2,3", 863 "Data_LA": "1", 864 "EventCode": "0xd4", 865 "EventName": "MEM_LOAD_MISC_RETIRED.UC", 866 "PEBS": "1", 867 "PEBScounters": "0,1,2,3", 868 "SampleAfterValue": "100007", 869 "UMask": "0x4", 870 "Unit": "cpu_core" 871 }, 872 { 873 "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", 874 "CollectPEBSRecord": "2", 875 "Counter": "0,1,2,3", 876 "Data_LA": "1", 877 "EventCode": "0xd1", 878 "EventName": "MEM_LOAD_RETIRED.FB_HIT", 879 "PEBS": "1", 880 "PEBScounters": "0,1,2,3", 881 "SampleAfterValue": "100007", 882 "UMask": "0x40", 883 "Unit": "cpu_core" 884 }, 885 { 886 "BriefDescription": "Retired load instructions with L1 cache hits as data sources", 887 "CollectPEBSRecord": "2", 888 "Counter": "0,1,2,3", 889 "Data_LA": "1", 890 "EventCode": "0xd1", 891 "EventName": "MEM_LOAD_RETIRED.L1_HIT", 892 "PEBS": "1", 893 "PEBScounters": "0,1,2,3", 894 "SampleAfterValue": "1000003", 895 "UMask": "0x1", 896 "Unit": "cpu_core" 897 }, 898 { 899 "BriefDescription": "Retired load instructions missed L1 cache as data sources", 900 "CollectPEBSRecord": "2", 901 "Counter": "0,1,2,3", 902 "Data_LA": "1", 903 "EventCode": "0xd1", 904 "EventName": "MEM_LOAD_RETIRED.L1_MISS", 905 "PEBS": "1", 906 "PEBScounters": "0,1,2,3", 907 "SampleAfterValue": "200003", 908 "UMask": "0x8", 909 "Unit": "cpu_core" 910 }, 911 { 912 "BriefDescription": "Retired load instructions with L2 cache hits as data sources", 913 "CollectPEBSRecord": "2", 914 "Counter": "0,1,2,3", 915 "Data_LA": "1", 916 "EventCode": "0xd1", 917 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 918 "PEBS": "1", 919 "PEBScounters": "0,1,2,3", 920 "SampleAfterValue": "200003", 921 "UMask": "0x2", 922 "Unit": "cpu_core" 923 }, 924 { 925 "BriefDescription": "Retired load instructions missed L2 cache as data sources", 926 "CollectPEBSRecord": "2", 927 "Counter": "0,1,2,3", 928 "Data_LA": "1", 929 "EventCode": "0xd1", 930 "EventName": "MEM_LOAD_RETIRED.L2_MISS", 931 "PEBS": "1", 932 "PEBScounters": "0,1,2,3", 933 "SampleAfterValue": "100021", 934 "UMask": "0x10", 935 "Unit": "cpu_core" 936 }, 937 { 938 "BriefDescription": "Retired load instructions with L3 cache hits as data sources", 939 "CollectPEBSRecord": "2", 940 "Counter": "0,1,2,3", 941 "Data_LA": "1", 942 "EventCode": "0xd1", 943 "EventName": "MEM_LOAD_RETIRED.L3_HIT", 944 "PEBS": "1", 945 "PEBScounters": "0,1,2,3", 946 "SampleAfterValue": "100021", 947 "UMask": "0x4", 948 "Unit": "cpu_core" 949 }, 950 { 951 "BriefDescription": "Retired load instructions missed L3 cache as data sources", 952 "CollectPEBSRecord": "2", 953 "Counter": "0,1,2,3", 954 "Data_LA": "1", 955 "EventCode": "0xd1", 956 "EventName": "MEM_LOAD_RETIRED.L3_MISS", 957 "PEBS": "1", 958 "PEBScounters": "0,1,2,3", 959 "SampleAfterValue": "50021", 960 "UMask": "0x20", 961 "Unit": "cpu_core" 962 }, 963 { 964 "BriefDescription": "TBD", 965 "CollectPEBSRecord": "2", 966 "Counter": "0,1,2,3", 967 "EventCode": "0x44", 968 "EventName": "MEM_STORE_RETIRED.L2_HIT", 969 "PEBScounters": "0,1,2,3", 970 "SampleAfterValue": "200003", 971 "UMask": "0x1", 972 "Unit": "cpu_core" 973 }, 974 { 975 "BriefDescription": "Retired memory uops for any access", 976 "Counter": "0,1,2,3,4,5,6,7", 977 "EventCode": "0xe5", 978 "EventName": "MEM_UOP_RETIRED.ANY", 979 "PEBScounters": "0,1,2,3,4,5,6,7", 980 "SampleAfterValue": "1000003", 981 "UMask": "0x3", 982 "Unit": "cpu_core" 983 }, 984 { 985 "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.", 986 "Counter": "0,1,2,3", 987 "EventCode": "0x2A,0x2B", 988 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", 989 "MSRIndex": "0x1a6,0x1a7", 990 "MSRValue": "0x10003C0001", 991 "SampleAfterValue": "100003", 992 "UMask": "0x1", 993 "Unit": "cpu_core" 994 }, 995 { 996 "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_HIT_WITH_FWD", 997 "Counter": "0,1,2,3", 998 "EventCode": "0x2A,0x2B", 999 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 1000 "MSRIndex": "0x1a6,0x1a7", 1001 "MSRValue": "0x8003C0001", 1002 "SampleAfterValue": "100003", 1003 "UMask": "0x1", 1004 "Unit": "cpu_core" 1005 }, 1006 { 1007 "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.", 1008 "Counter": "0,1,2,3", 1009 "EventCode": "0x2A,0x2B", 1010 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", 1011 "MSRIndex": "0x1a6,0x1a7", 1012 "MSRValue": "0x10003C0002", 1013 "SampleAfterValue": "100003", 1014 "UMask": "0x1", 1015 "Unit": "cpu_core" 1016 }, 1017 { 1018 "BriefDescription": "TBD", 1019 "CollectPEBSRecord": "2", 1020 "Counter": "0,1,2,3", 1021 "EventCode": "0x21", 1022 "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", 1023 "PEBScounters": "0,1,2,3", 1024 "SampleAfterValue": "100003", 1025 "UMask": "0x80", 1026 "Unit": "cpu_core" 1027 }, 1028 { 1029 "BriefDescription": "Demand and prefetch data reads", 1030 "CollectPEBSRecord": "2", 1031 "Counter": "0,1,2,3", 1032 "EventCode": "0x21", 1033 "EventName": "OFFCORE_REQUESTS.DATA_RD", 1034 "PEBScounters": "0,1,2,3", 1035 "SampleAfterValue": "100003", 1036 "UMask": "0x8", 1037 "Unit": "cpu_core" 1038 }, 1039 { 1040 "BriefDescription": "Demand Data Read requests sent to uncore", 1041 "CollectPEBSRecord": "2", 1042 "Counter": "0,1,2,3", 1043 "EventCode": "0x21", 1044 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 1045 "PEBScounters": "0,1,2,3", 1046 "SampleAfterValue": "100003", 1047 "UMask": "0x1", 1048 "Unit": "cpu_core" 1049 }, 1050 { 1051 "BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", 1052 "CollectPEBSRecord": "2", 1053 "Counter": "0,1,2,3", 1054 "EventCode": "0x20", 1055 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 1056 "PEBScounters": "0,1,2,3", 1057 "SampleAfterValue": "1000003", 1058 "UMask": "0x8", 1059 "Unit": "cpu_core" 1060 }, 1061 { 1062 "BriefDescription": "TBD", 1063 "CollectPEBSRecord": "2", 1064 "Counter": "0,1,2,3", 1065 "CounterMask": "1", 1066 "EventCode": "0x20", 1067 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 1068 "PEBScounters": "0,1,2,3", 1069 "SampleAfterValue": "1000003", 1070 "UMask": "0x8", 1071 "Unit": "cpu_core" 1072 }, 1073 { 1074 "BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.", 1075 "CollectPEBSRecord": "2", 1076 "Counter": "0,1,2,3", 1077 "CounterMask": "1", 1078 "EventCode": "0x20", 1079 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 1080 "PEBScounters": "0,1,2,3", 1081 "SampleAfterValue": "1000003", 1082 "UMask": "0x4", 1083 "Unit": "cpu_core" 1084 }, 1085 { 1086 "BriefDescription": "TBD", 1087 "CollectPEBSRecord": "2", 1088 "Counter": "0,1,2,3", 1089 "EventCode": "0x20", 1090 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", 1091 "PEBScounters": "0,1,2,3", 1092 "SampleAfterValue": "1000003", 1093 "UMask": "0x8", 1094 "Unit": "cpu_core" 1095 }, 1096 { 1097 "BriefDescription": "Number of PREFETCHNTA instructions executed.", 1098 "CollectPEBSRecord": "2", 1099 "Counter": "0,1,2,3", 1100 "EventCode": "0x40", 1101 "EventName": "SW_PREFETCH_ACCESS.NTA", 1102 "PEBScounters": "0,1,2,3", 1103 "SampleAfterValue": "100003", 1104 "UMask": "0x1", 1105 "Unit": "cpu_core" 1106 }, 1107 { 1108 "BriefDescription": "Number of PREFETCHW instructions executed.", 1109 "CollectPEBSRecord": "2", 1110 "Counter": "0,1,2,3", 1111 "EventCode": "0x40", 1112 "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", 1113 "PEBScounters": "0,1,2,3", 1114 "SampleAfterValue": "100003", 1115 "UMask": "0x8", 1116 "Unit": "cpu_core" 1117 }, 1118 { 1119 "BriefDescription": "Number of PREFETCHT0 instructions executed.", 1120 "CollectPEBSRecord": "2", 1121 "Counter": "0,1,2,3", 1122 "EventCode": "0x40", 1123 "EventName": "SW_PREFETCH_ACCESS.T0", 1124 "PEBScounters": "0,1,2,3", 1125 "SampleAfterValue": "100003", 1126 "UMask": "0x2", 1127 "Unit": "cpu_core" 1128 }, 1129 { 1130 "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", 1131 "CollectPEBSRecord": "2", 1132 "Counter": "0,1,2,3", 1133 "EventCode": "0x40", 1134 "EventName": "SW_PREFETCH_ACCESS.T1_T2", 1135 "PEBScounters": "0,1,2,3", 1136 "SampleAfterValue": "100003", 1137 "UMask": "0x4", 1138 "Unit": "cpu_core" 1139 } 1140]