cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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memory.json (12491B)

      1[
      2  {
      3    "EventName": "ls_bad_status2.stli_other",
      4    "EventCode": "0x24",
      5    "BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason.",
      6    "PublicDescription" : "Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores.",
      7    "UMask": "0x02"
      8  },
      9  {
     10    "EventName": "ls_locks.spec_lock_hi_spec",
     11    "EventCode": "0x25",
     12    "BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succeeded.",
     13    "UMask": "0x08"
     14  },
     15  {
     16    "EventName": "ls_locks.spec_lock_lo_spec",
     17    "EventCode": "0x25",
     18    "BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeeded.",
     19    "UMask": "0x04"
     20  },
     21  {
     22    "EventName": "ls_locks.non_spec_lock",
     23    "EventCode": "0x25",
     24    "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.",
     25    "UMask": "0x02"
     26  },
     27  {
     28    "EventName": "ls_locks.bus_lock",
     29    "EventCode": "0x25",
     30    "BriefDescription": "Retired lock instructions. Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type. Comparable to legacy bus lock.",
     31    "UMask": "0x01"
     32  },
     33  {
     34    "EventName": "ls_ret_cl_flush",
     35    "EventCode": "0x26",
     36    "BriefDescription": "Number of retired CLFLUSH instructions."
     37  },
     38  {
     39    "EventName": "ls_ret_cpuid",
     40    "EventCode": "0x27",
     41    "BriefDescription": "Number of retired CPUID instructions."
     42  },
     43  {
     44    "EventName": "ls_dispatch.ld_st_dispatch",
     45    "EventCode": "0x29",
     46    "BriefDescription": "Dispatch of a single op that performs a load from and store to the same memory address. Number of single ops that do load/store to an address.",
     47    "UMask": "0x04"
     48  },
     49  {
     50    "EventName": "ls_dispatch.store_dispatch",
     51    "EventCode": "0x29",
     52    "BriefDescription": "Number of stores dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
     53    "UMask": "0x02"
     54  },
     55  {
     56    "EventName": "ls_dispatch.ld_dispatch",
     57    "EventCode": "0x29",
     58    "BriefDescription": "Number of loads dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
     59    "UMask": "0x01"
     60  },
     61  {
     62    "EventName": "ls_smi_rx",
     63    "EventCode": "0x2b",
     64    "BriefDescription": "Number of SMIs received."
     65  },
     66  {
     67    "EventName": "ls_int_taken",
     68    "EventCode": "0x2c",
     69    "BriefDescription": "Number of interrupts taken."
     70  },
     71  {
     72    "EventName": "ls_rdtsc",
     73    "EventCode": "0x2d",
     74    "BriefDescription": "Number of reads of the TSC (RDTSC instructions). The count is speculative."
     75  },
     76  {
     77    "EventName": "ls_stlf",
     78    "EventCode": "0x35",
     79    "BriefDescription": "Number of STLF hits."
     80  },
     81  {
     82    "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
     83    "EventCode": "0x37",
     84    "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full."
     85  },
     86  {
     87    "EventName": "ls_dc_accesses",
     88    "EventCode": "0x40",
     89    "BriefDescription": "Number of accesses to the dcache for load/store references.",
     90    "PublicDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event."
     91  },
     92  {
     93    "EventName": "ls_mab_alloc.dc_prefetcher",
     94    "EventCode": "0x41",
     95    "BriefDescription": "LS MAB Allocates by Type. DC prefetcher.",
     96    "UMask": "0x08"
     97  },
     98  {
     99    "EventName": "ls_mab_alloc.stores",
    100    "EventCode": "0x41",
    101    "BriefDescription": "LS MAB Allocates by Type. Stores.",
    102    "UMask": "0x02"
    103  },
    104  {
    105    "EventName": "ls_mab_alloc.loads",
    106    "EventCode": "0x41",
    107    "BriefDescription": "LS MAB Allocates by Type. Loads.",
    108    "UMask": "0x01"
    109  },
    110  {
    111    "EventName": "ls_refills_from_sys.ls_mabresp_rmt_dram",
    112    "EventCode": "0x43",
    113    "BriefDescription": "Demand Data Cache Fills by Data Source. DRAM or IO from different die.",
    114    "UMask": "0x40"
    115  },
    116  {
    117    "EventName": "ls_refills_from_sys.ls_mabresp_rmt_cache",
    118    "EventCode": "0x43",
    119    "BriefDescription": "Demand Data Cache Fills by Data Source. Hit in cache; Remote CCX and the address's Home Node is on a different die.",
    120    "UMask": "0x10"
    121  },
    122  {
    123    "EventName": "ls_refills_from_sys.ls_mabresp_lcl_dram",
    124    "EventCode": "0x43",
    125    "BriefDescription": "Demand Data Cache Fills by Data Source. DRAM or IO from this thread's die.",
    126    "UMask": "0x08"
    127  },
    128  {
    129    "EventName": "ls_refills_from_sys.ls_mabresp_lcl_cache",
    130    "EventCode": "0x43",
    131    "BriefDescription": "Demand Data Cache Fills by Data Source. Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die.",
    132    "UMask": "0x02"
    133  },
    134  {
    135    "EventName": "ls_refills_from_sys.ls_mabresp_lcl_l2",
    136    "EventCode": "0x43",
    137    "BriefDescription": "Demand Data Cache Fills by Data Source. Local L2 hit.",
    138    "UMask": "0x01"
    139  },
    140  {
    141    "EventName": "ls_l1_d_tlb_miss.all",
    142    "EventCode": "0x45",
    143    "BriefDescription": "All L1 DTLB Misses or Reloads.",
    144    "UMask": "0xff"
    145  },
    146  {
    147    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
    148    "EventCode": "0x45",
    149    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLB.",
    150    "UMask": "0x80"
    151  },
    152  {
    153    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
    154    "EventCode": "0x45",
    155    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLB.",
    156    "UMask": "0x40"
    157  },
    158  {
    159    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
    160    "EventCode": "0x45",
    161    "BriefDescription": "L1 DTLB Miss. DTLB reload coalesced page miss.",
    162    "UMask": "0x20"
    163  },
    164  {
    165    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
    166    "EventCode": "0x45",
    167    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that miss the L2 TLB.",
    168    "UMask": "0x10"
    169  },
    170  {
    171    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
    172    "EventCode": "0x45",
    173    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB.",
    174    "UMask": "0x08"
    175  },
    176  {
    177    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
    178    "EventCode": "0x45",
    179    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB.",
    180    "UMask": "0x04"
    181  },
    182  {
    183    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
    184    "EventCode": "0x45",
    185    "BriefDescription": "L1 DTLB Miss. DTLB reload hit a coalesced page.",
    186    "UMask": "0x02"
    187  },
    188  {
    189    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
    190    "EventCode": "0x45",
    191    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB.",
    192    "UMask": "0x01"
    193  },
    194  {
    195    "EventName": "ls_tablewalker.iside",
    196    "EventCode": "0x46",
    197    "BriefDescription": "Total Page Table Walks on I-side.",
    198    "UMask": "0x0c"
    199  },
    200  {
    201    "EventName": "ls_tablewalker.ic_type1",
    202    "EventCode": "0x46",
    203    "BriefDescription": "Total Page Table Walks IC Type 1.",
    204    "UMask": "0x08"
    205  },
    206  {
    207    "EventName": "ls_tablewalker.ic_type0",
    208    "EventCode": "0x46",
    209    "BriefDescription": "Total Page Table Walks IC Type 0.",
    210    "UMask": "0x04"
    211  },
    212  {
    213    "EventName": "ls_tablewalker.dside",
    214    "EventCode": "0x46",
    215    "BriefDescription": "Total Page Table Walks on D-side.",
    216    "UMask": "0x03"
    217  },
    218  {
    219    "EventName": "ls_tablewalker.dc_type1",
    220    "EventCode": "0x46",
    221    "BriefDescription": "Total Page Table Walks DC Type 1.",
    222    "UMask": "0x02"
    223  },
    224  {
    225    "EventName": "ls_tablewalker.dc_type0",
    226    "EventCode": "0x46",
    227    "BriefDescription": "Total Page Table Walks DC Type 0.",
    228    "UMask": "0x01"
    229  },
    230  {
    231    "EventName": "ls_misal_accesses",
    232    "EventCode": "0x47",
    233    "BriefDescription": "Misaligned loads."
    234  },
    235  {
    236    "EventName": "ls_pref_instr_disp",
    237    "EventCode": "0x4b",
    238    "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative).",
    239    "UMask": "0xff"
    240  },
    241  {
    242    "EventName": "ls_pref_instr_disp.prefetch_nta",
    243    "EventCode": "0x4b",
    244    "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel.",
    245    "UMask": "0x04"
    246  },
    247  {
    248    "EventName": "ls_pref_instr_disp.prefetch_w",
    249    "EventCode": "0x4b",
    250    "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCHW.",
    251    "UMask": "0x02"
    252  },
    253  {
    254    "EventName": "ls_pref_instr_disp.prefetch",
    255    "EventCode": "0x4b",
    256    "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). Prefetch_T0_T1_T2. PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel.",
    257    "UMask": "0x01"
    258  },
    259  {
    260    "EventName": "ls_inef_sw_pref.mab_mch_cnt",
    261    "EventCode": "0x52",
    262    "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer.",
    263    "UMask": "0x02"
    264  },
    265  {
    266    "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
    267    "EventCode": "0x52",
    268    "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit.",
    269    "UMask": "0x01"
    270  },
    271  {
    272    "EventName": "ls_sw_pf_dc_fill.ls_mabresp_rmt_dram",
    273    "EventCode": "0x59",
    274    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From DRAM (home node remote).",
    275    "UMask": "0x40"
    276  },
    277  {
    278    "EventName": "ls_sw_pf_dc_fill.ls_mabresp_rmt_cache",
    279    "EventCode": "0x59",
    280    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From another cache (home node remote).",
    281    "UMask": "0x10"
    282  },
    283  {
    284    "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_dram",
    285    "EventCode": "0x59",
    286    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. DRAM or IO from this thread's die.  From DRAM (home node local).",
    287    "UMask": "0x08"
    288  },
    289  {
    290    "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_cache",
    291    "EventCode": "0x59",
    292    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From another cache (home node local).",
    293    "UMask": "0x02"
    294  },
    295  {
    296    "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_l2",
    297    "EventCode": "0x59",
    298    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. Local L2 hit.",
    299    "UMask": "0x01"
    300  },
    301  {
    302    "EventName": "ls_hw_pf_dc_fill.ls_mabresp_rmt_dram",
    303    "EventCode": "0x5a",
    304    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote).",
    305    "UMask": "0x40"
    306  },
    307  {
    308    "EventName": "ls_hw_pf_dc_fill.ls_mabresp_rmt_cache",
    309    "EventCode": "0x5a",
    310    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote).",
    311    "UMask": "0x10"
    312  },
    313  {
    314    "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_dram",
    315    "EventCode": "0x5a",
    316    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local).",
    317    "UMask": "0x08"
    318  },
    319  {
    320    "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_cache",
    321    "EventCode": "0x5a",
    322    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node local).",
    323    "UMask": "0x02"
    324  },
    325  {
    326    "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_l2",
    327    "EventCode": "0x5a",
    328    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. Local L2 hit.",
    329    "UMask": "0x01"
    330  },
    331  {
    332    "EventName": "ls_not_halted_cyc",
    333    "EventCode": "0x76",
    334    "BriefDescription": "Cycles not in Halt."
    335  },
    336  {
    337    "EventName": "ls_tlb_flush",
    338    "EventCode": "0x78",
    339    "BriefDescription": "All TLB Flushes"
    340  }
    341]