cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

memory.json (8239B)

      1[
      2    {
      3        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
      4        "Counter": "0,1,2,3",
      5        "CounterHTOff": "0,1,2,3,4,5,6,7",
      6        "EventCode": "0xC3",
      7        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
      8        "SampleAfterValue": "100003",
      9        "UMask": "0x2"
     10    },
     11    {
     12        "BriefDescription": "Loads with latency value being above 128",
     13        "Counter": "3",
     14        "CounterHTOff": "3",
     15        "EventCode": "0xCD",
     16        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
     17        "MSRIndex": "0x3F6",
     18        "MSRValue": "0x80",
     19        "PEBS": "2",
     20        "PublicDescription": "Loads with latency value being above 128.",
     21        "SampleAfterValue": "1009",
     22        "TakenAlone": "1",
     23        "UMask": "0x1"
     24    },
     25    {
     26        "BriefDescription": "Loads with latency value being above 16",
     27        "Counter": "3",
     28        "CounterHTOff": "3",
     29        "EventCode": "0xCD",
     30        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
     31        "MSRIndex": "0x3F6",
     32        "MSRValue": "0x10",
     33        "PEBS": "2",
     34        "PublicDescription": "Loads with latency value being above 16.",
     35        "SampleAfterValue": "20011",
     36        "TakenAlone": "1",
     37        "UMask": "0x1"
     38    },
     39    {
     40        "BriefDescription": "Loads with latency value being above 256",
     41        "Counter": "3",
     42        "CounterHTOff": "3",
     43        "EventCode": "0xCD",
     44        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
     45        "MSRIndex": "0x3F6",
     46        "MSRValue": "0x100",
     47        "PEBS": "2",
     48        "PublicDescription": "Loads with latency value being above 256.",
     49        "SampleAfterValue": "503",
     50        "TakenAlone": "1",
     51        "UMask": "0x1"
     52    },
     53    {
     54        "BriefDescription": "Loads with latency value being above 32",
     55        "Counter": "3",
     56        "CounterHTOff": "3",
     57        "EventCode": "0xCD",
     58        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
     59        "MSRIndex": "0x3F6",
     60        "MSRValue": "0x20",
     61        "PEBS": "2",
     62        "PublicDescription": "Loads with latency value being above 32.",
     63        "SampleAfterValue": "100007",
     64        "TakenAlone": "1",
     65        "UMask": "0x1"
     66    },
     67    {
     68        "BriefDescription": "Loads with latency value being above 4",
     69        "Counter": "3",
     70        "CounterHTOff": "3",
     71        "EventCode": "0xCD",
     72        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
     73        "MSRIndex": "0x3F6",
     74        "MSRValue": "0x4",
     75        "PEBS": "2",
     76        "PublicDescription": "Loads with latency value being above 4.",
     77        "SampleAfterValue": "100003",
     78        "TakenAlone": "1",
     79        "UMask": "0x1"
     80    },
     81    {
     82        "BriefDescription": "Loads with latency value being above 512",
     83        "Counter": "3",
     84        "CounterHTOff": "3",
     85        "EventCode": "0xCD",
     86        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
     87        "MSRIndex": "0x3F6",
     88        "MSRValue": "0x200",
     89        "PEBS": "2",
     90        "PublicDescription": "Loads with latency value being above 512.",
     91        "SampleAfterValue": "101",
     92        "TakenAlone": "1",
     93        "UMask": "0x1"
     94    },
     95    {
     96        "BriefDescription": "Loads with latency value being above 64",
     97        "Counter": "3",
     98        "CounterHTOff": "3",
     99        "EventCode": "0xCD",
    100        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
    101        "MSRIndex": "0x3F6",
    102        "MSRValue": "0x40",
    103        "PEBS": "2",
    104        "PublicDescription": "Loads with latency value being above 64.",
    105        "SampleAfterValue": "2003",
    106        "TakenAlone": "1",
    107        "UMask": "0x1"
    108    },
    109    {
    110        "BriefDescription": "Loads with latency value being above 8",
    111        "Counter": "3",
    112        "CounterHTOff": "3",
    113        "EventCode": "0xCD",
    114        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
    115        "MSRIndex": "0x3F6",
    116        "MSRValue": "0x8",
    117        "PEBS": "2",
    118        "PublicDescription": "Loads with latency value being above 8.",
    119        "SampleAfterValue": "50021",
    120        "TakenAlone": "1",
    121        "UMask": "0x1"
    122    },
    123    {
    124        "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.",
    125        "Counter": "3",
    126        "CounterHTOff": "3",
    127        "EventCode": "0xCD",
    128        "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
    129        "PEBS": "2",
    130        "PRECISE_STORE": "1",
    131        "SampleAfterValue": "2000003",
    132        "TakenAlone": "1",
    133        "UMask": "0x2"
    134    },
    135    {
    136        "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
    137        "Counter": "0,1,2,3",
    138        "CounterHTOff": "0,1,2,3,4,5,6,7",
    139        "EventCode": "0x05",
    140        "EventName": "MISALIGN_MEM_REF.LOADS",
    141        "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
    142        "SampleAfterValue": "2000003",
    143        "UMask": "0x1"
    144    },
    145    {
    146        "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
    147        "Counter": "0,1,2,3",
    148        "CounterHTOff": "0,1,2,3,4,5,6,7",
    149        "EventCode": "0x05",
    150        "EventName": "MISALIGN_MEM_REF.STORES",
    151        "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.",
    152        "SampleAfterValue": "2000003",
    153        "UMask": "0x2"
    154    },
    155    {
    156        "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram",
    157        "Counter": "0,1,2,3",
    158        "CounterHTOff": "0,1,2,3",
    159        "EventCode": "0xB7, 0xBB",
    160        "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
    161        "MSRIndex": "0x1a6,0x1a7",
    162        "MSRValue": "0x300400244",
    163        "Offcore": "1",
    164        "SampleAfterValue": "100003",
    165        "UMask": "0x1"
    166    },
    167    {
    168        "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram",
    169        "Counter": "0,1,2,3",
    170        "CounterHTOff": "0,1,2,3",
    171        "EventCode": "0xB7, 0xBB",
    172        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
    173        "MSRIndex": "0x1a6,0x1a7",
    174        "MSRValue": "0x300400091",
    175        "Offcore": "1",
    176        "SampleAfterValue": "100003",
    177        "UMask": "0x1"
    178    },
    179    {
    180        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram",
    181        "Counter": "0,1,2,3",
    182        "CounterHTOff": "0,1,2,3",
    183        "EventCode": "0xB7, 0xBB",
    184        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
    185        "MSRIndex": "0x1a6,0x1a7",
    186        "MSRValue": "0x3004003f7",
    187        "Offcore": "1",
    188        "SampleAfterValue": "100003",
    189        "UMask": "0x1"
    190    },
    191    {
    192        "BriefDescription": "Counts LLC replacements",
    193        "Counter": "0,1,2,3",
    194        "CounterHTOff": "0,1,2,3",
    195        "EventCode": "0xB7, 0xBB",
    196        "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
    197        "MSRIndex": "0x1a6,0x1a7",
    198        "MSRValue": "0x6004001b3",
    199        "Offcore": "1",
    200        "SampleAfterValue": "100003",
    201        "UMask": "0x1"
    202    },
    203    {
    204        "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram",
    205        "Counter": "0,1,2,3",
    206        "CounterHTOff": "0,1,2,3",
    207        "EventCode": "0xB7, 0xBB",
    208        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
    209        "MSRIndex": "0x1a6,0x1a7",
    210        "MSRValue": "0x300400004",
    211        "Offcore": "1",
    212        "SampleAfterValue": "100003",
    213        "UMask": "0x1"
    214    },
    215    {
    216        "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram",
    217        "Counter": "0,1,2,3",
    218        "CounterHTOff": "0,1,2,3",
    219        "EventCode": "0xB7, 0xBB",
    220        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
    221        "MSRIndex": "0x1a6,0x1a7",
    222        "MSRValue": "0x300400001",
    223        "Offcore": "1",
    224        "SampleAfterValue": "100003",
    225        "UMask": "0x1"
    226    },
    227    {
    228        "BriefDescription": "Number of any page walk that had a miss in LLC.",
    229        "Counter": "0,1,2,3",
    230        "CounterHTOff": "0,1,2,3,4,5,6,7",
    231        "EventCode": "0xBE",
    232        "EventName": "PAGE_WALKS.LLC_MISS",
    233        "SampleAfterValue": "100003",
    234        "UMask": "0x1"
    235    }
    236]