frontend.json (13782B)
1[ 2 { 3 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0xE6", 7 "EventName": "BACLEARS.ANY", 8 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 9 "SampleAfterValue": "100003", 10 "UMask": "0x1f" 11 }, 12 { 13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 14 "Counter": "0,1,2,3", 15 "CounterHTOff": "0,1,2,3,4,5,6,7", 16 "EventCode": "0xAB", 17 "EventName": "DSB2MITE_SWITCHES.COUNT", 18 "PublicDescription": "Number of DSB to MITE switches.", 19 "SampleAfterValue": "2000003", 20 "UMask": "0x1" 21 }, 22 { 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 24 "Counter": "0,1,2,3", 25 "CounterHTOff": "0,1,2,3,4,5,6,7", 26 "EventCode": "0xAB", 27 "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", 28 "PublicDescription": "Cycles DSB to MITE switches caused delay.", 29 "SampleAfterValue": "2000003", 30 "UMask": "0x2" 31 }, 32 { 33 "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines", 34 "Counter": "0,1,2,3", 35 "CounterHTOff": "0,1,2,3,4,5,6,7", 36 "EventCode": "0xAC", 37 "EventName": "DSB_FILL.EXCEED_DSB_LINES", 38 "PublicDescription": "DSB Fill encountered > 3 DSB lines.", 39 "SampleAfterValue": "2000003", 40 "UMask": "0x8" 41 }, 42 { 43 "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", 44 "Counter": "0,1,2,3", 45 "CounterHTOff": "0,1,2,3,4,5,6,7", 46 "EventCode": "0x80", 47 "EventName": "ICACHE.HIT", 48 "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", 49 "SampleAfterValue": "2000003", 50 "UMask": "0x1" 51 }, 52 { 53 "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss", 54 "Counter": "0,1,2,3", 55 "CounterHTOff": "0,1,2,3,4,5,6,7", 56 "EventCode": "0x80", 57 "EventName": "ICACHE.IFETCH_STALL", 58 "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.", 59 "SampleAfterValue": "2000003", 60 "UMask": "0x4" 61 }, 62 { 63 "BriefDescription": "Instruction cache, streaming buffer and victim cache misses", 64 "Counter": "0,1,2,3", 65 "CounterHTOff": "0,1,2,3,4,5,6,7", 66 "EventCode": "0x80", 67 "EventName": "ICACHE.MISSES", 68 "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.", 69 "SampleAfterValue": "200003", 70 "UMask": "0x2" 71 }, 72 { 73 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 74 "Counter": "0,1,2,3", 75 "CounterHTOff": "0,1,2,3,4,5,6,7", 76 "CounterMask": "4", 77 "EventCode": "0x79", 78 "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", 79 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 80 "SampleAfterValue": "2000003", 81 "UMask": "0x18" 82 }, 83 { 84 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 85 "Counter": "0,1,2,3", 86 "CounterHTOff": "0,1,2,3,4,5,6,7", 87 "CounterMask": "1", 88 "EventCode": "0x79", 89 "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", 90 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", 91 "SampleAfterValue": "2000003", 92 "UMask": "0x18" 93 }, 94 { 95 "BriefDescription": "Cycles MITE is delivering 4 Uops", 96 "Counter": "0,1,2,3", 97 "CounterHTOff": "0,1,2,3,4,5,6,7", 98 "CounterMask": "4", 99 "EventCode": "0x79", 100 "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", 101 "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", 102 "SampleAfterValue": "2000003", 103 "UMask": "0x24" 104 }, 105 { 106 "BriefDescription": "Cycles MITE is delivering any Uop", 107 "Counter": "0,1,2,3", 108 "CounterHTOff": "0,1,2,3,4,5,6,7", 109 "CounterMask": "1", 110 "EventCode": "0x79", 111 "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", 112 "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.", 113 "SampleAfterValue": "2000003", 114 "UMask": "0x24" 115 }, 116 { 117 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 118 "Counter": "0,1,2,3", 119 "CounterHTOff": "0,1,2,3,4,5,6,7", 120 "CounterMask": "1", 121 "EventCode": "0x79", 122 "EventName": "IDQ.DSB_CYCLES", 123 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 124 "SampleAfterValue": "2000003", 125 "UMask": "0x8" 126 }, 127 { 128 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 129 "Counter": "0,1,2,3", 130 "CounterHTOff": "0,1,2,3,4,5,6,7", 131 "EventCode": "0x79", 132 "EventName": "IDQ.DSB_UOPS", 133 "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", 134 "SampleAfterValue": "2000003", 135 "UMask": "0x8" 136 }, 137 { 138 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", 139 "Counter": "0,1,2,3", 140 "CounterHTOff": "0,1,2,3", 141 "EventCode": "0x79", 142 "EventName": "IDQ.EMPTY", 143 "PublicDescription": "Counts cycles the IDQ is empty.", 144 "SampleAfterValue": "2000003", 145 "UMask": "0x2" 146 }, 147 { 148 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 149 "Counter": "0,1,2,3", 150 "CounterHTOff": "0,1,2,3,4,5,6,7", 151 "EventCode": "0x79", 152 "EventName": "IDQ.MITE_ALL_UOPS", 153 "PublicDescription": "Number of uops delivered to IDQ from any path.", 154 "SampleAfterValue": "2000003", 155 "UMask": "0x3c" 156 }, 157 { 158 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", 159 "Counter": "0,1,2,3", 160 "CounterHTOff": "0,1,2,3,4,5,6,7", 161 "CounterMask": "1", 162 "EventCode": "0x79", 163 "EventName": "IDQ.MITE_CYCLES", 164 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", 165 "SampleAfterValue": "2000003", 166 "UMask": "0x4" 167 }, 168 { 169 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 170 "Counter": "0,1,2,3", 171 "CounterHTOff": "0,1,2,3,4,5,6,7", 172 "EventCode": "0x79", 173 "EventName": "IDQ.MITE_UOPS", 174 "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", 175 "SampleAfterValue": "2000003", 176 "UMask": "0x4" 177 }, 178 { 179 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 180 "Counter": "0,1,2,3", 181 "CounterHTOff": "0,1,2,3,4,5,6,7", 182 "CounterMask": "1", 183 "EventCode": "0x79", 184 "EventName": "IDQ.MS_CYCLES", 185 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", 186 "SampleAfterValue": "2000003", 187 "UMask": "0x30" 188 }, 189 { 190 "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 191 "Counter": "0,1,2,3", 192 "CounterHTOff": "0,1,2,3,4,5,6,7", 193 "CounterMask": "1", 194 "EventCode": "0x79", 195 "EventName": "IDQ.MS_DSB_CYCLES", 196 "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", 197 "SampleAfterValue": "2000003", 198 "UMask": "0x10" 199 }, 200 { 201 "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", 202 "Counter": "0,1,2,3", 203 "CounterHTOff": "0,1,2,3,4,5,6,7", 204 "CounterMask": "1", 205 "EdgeDetect": "1", 206 "EventCode": "0x79", 207 "EventName": "IDQ.MS_DSB_OCCUR", 208 "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", 209 "SampleAfterValue": "2000003", 210 "UMask": "0x10" 211 }, 212 { 213 "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 214 "Counter": "0,1,2,3", 215 "CounterHTOff": "0,1,2,3,4,5,6,7", 216 "EventCode": "0x79", 217 "EventName": "IDQ.MS_DSB_UOPS", 218 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", 219 "SampleAfterValue": "2000003", 220 "UMask": "0x10" 221 }, 222 { 223 "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 224 "Counter": "0,1,2,3", 225 "CounterHTOff": "0,1,2,3,4,5,6,7", 226 "EventCode": "0x79", 227 "EventName": "IDQ.MS_MITE_UOPS", 228 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", 229 "SampleAfterValue": "2000003", 230 "UMask": "0x20" 231 }, 232 { 233 "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", 234 "Counter": "0,1,2,3", 235 "CounterHTOff": "0,1,2,3,4,5,6,7", 236 "CounterMask": "1", 237 "EdgeDetect": "1", 238 "EventCode": "0x79", 239 "EventName": "IDQ.MS_SWITCHES", 240 "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", 241 "SampleAfterValue": "2000003", 242 "UMask": "0x30" 243 }, 244 { 245 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 246 "Counter": "0,1,2,3", 247 "CounterHTOff": "0,1,2,3,4,5,6,7", 248 "EventCode": "0x79", 249 "EventName": "IDQ.MS_UOPS", 250 "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.", 251 "SampleAfterValue": "2000003", 252 "UMask": "0x30" 253 }, 254 { 255 "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", 256 "Counter": "0,1,2,3", 257 "CounterHTOff": "0,1,2,3", 258 "EventCode": "0x9C", 259 "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", 260 "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.", 261 "SampleAfterValue": "2000003", 262 "UMask": "0x1" 263 }, 264 { 265 "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", 266 "Counter": "0,1,2,3", 267 "CounterHTOff": "0,1,2,3", 268 "CounterMask": "4", 269 "EventCode": "0x9C", 270 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", 271 "SampleAfterValue": "2000003", 272 "UMask": "0x1" 273 }, 274 { 275 "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", 276 "Counter": "0,1,2,3", 277 "CounterHTOff": "0,1,2,3", 278 "CounterMask": "1", 279 "EventCode": "0x9C", 280 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", 281 "Invert": "1", 282 "SampleAfterValue": "2000003", 283 "UMask": "0x1" 284 }, 285 { 286 "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", 287 "Counter": "0,1,2,3", 288 "CounterHTOff": "0,1,2,3", 289 "CounterMask": "3", 290 "EventCode": "0x9C", 291 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", 292 "SampleAfterValue": "2000003", 293 "UMask": "0x1" 294 }, 295 { 296 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", 297 "Counter": "0,1,2,3", 298 "CounterHTOff": "0,1,2,3", 299 "CounterMask": "2", 300 "EventCode": "0x9C", 301 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", 302 "SampleAfterValue": "2000003", 303 "UMask": "0x1" 304 }, 305 { 306 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", 307 "Counter": "0,1,2,3", 308 "CounterHTOff": "0,1,2,3", 309 "CounterMask": "1", 310 "EventCode": "0x9C", 311 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", 312 "SampleAfterValue": "2000003", 313 "UMask": "0x1" 314 } 315]