cache.json (48092B)
1[ 2 { 3 "BriefDescription": "Allocated L1D data cache lines in M state.", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0x51", 7 "EventName": "L1D.ALLOCATED_IN_M", 8 "SampleAfterValue": "2000003", 9 "UMask": "0x2" 10 }, 11 { 12 "BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.", 13 "Counter": "0,1,2,3", 14 "CounterHTOff": "0,1,2,3,4,5,6,7", 15 "EventCode": "0x51", 16 "EventName": "L1D.ALL_M_REPLACEMENT", 17 "SampleAfterValue": "2000003", 18 "UMask": "0x8" 19 }, 20 { 21 "BriefDescription": "L1D data cache lines in M state evicted due to replacement.", 22 "Counter": "0,1,2,3", 23 "CounterHTOff": "0,1,2,3,4,5,6,7", 24 "EventCode": "0x51", 25 "EventName": "L1D.EVICTION", 26 "SampleAfterValue": "2000003", 27 "UMask": "0x4" 28 }, 29 { 30 "BriefDescription": "L1D data line replacements.", 31 "Counter": "0,1,2,3", 32 "CounterHTOff": "0,1,2,3,4,5,6,7", 33 "EventCode": "0x51", 34 "EventName": "L1D.REPLACEMENT", 35 "PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.", 36 "SampleAfterValue": "2000003", 37 "UMask": "0x1" 38 }, 39 { 40 "BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.", 41 "Counter": "0,1,2,3", 42 "CounterHTOff": "0,1,2,3,4,5,6,7", 43 "CounterMask": "1", 44 "EventCode": "0xBF", 45 "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES", 46 "SampleAfterValue": "100003", 47 "UMask": "0x5" 48 }, 49 { 50 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", 51 "Counter": "0,1,2,3", 52 "CounterHTOff": "0,1,2,3,4,5,6,7", 53 "CounterMask": "1", 54 "EventCode": "0x48", 55 "EventName": "L1D_PEND_MISS.FB_FULL", 56 "SampleAfterValue": "2000003", 57 "UMask": "0x2" 58 }, 59 { 60 "BriefDescription": "L1D miss oustandings duration in cycles.", 61 "Counter": "2", 62 "CounterHTOff": "2", 63 "EventCode": "0x48", 64 "EventName": "L1D_PEND_MISS.PENDING", 65 "SampleAfterValue": "2000003", 66 "UMask": "0x1" 67 }, 68 { 69 "BriefDescription": "Cycles with L1D load Misses outstanding.", 70 "Counter": "2", 71 "CounterHTOff": "2", 72 "CounterMask": "1", 73 "EventCode": "0x48", 74 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 75 "SampleAfterValue": "2000003", 76 "UMask": "0x1" 77 }, 78 { 79 "AnyThread": "1", 80 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 81 "Counter": "2", 82 "CounterHTOff": "2", 83 "CounterMask": "1", 84 "EventCode": "0x48", 85 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", 86 "SampleAfterValue": "2000003", 87 "UMask": "0x1" 88 }, 89 { 90 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", 91 "Counter": "0,1,2,3", 92 "CounterHTOff": "0,1,2,3,4,5,6,7", 93 "EventCode": "0x28", 94 "EventName": "L2_L1D_WB_RQSTS.ALL", 95 "SampleAfterValue": "200003", 96 "UMask": "0xf" 97 }, 98 { 99 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", 100 "Counter": "0,1,2,3", 101 "CounterHTOff": "0,1,2,3,4,5,6,7", 102 "EventCode": "0x28", 103 "EventName": "L2_L1D_WB_RQSTS.HIT_E", 104 "SampleAfterValue": "200003", 105 "UMask": "0x4" 106 }, 107 { 108 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", 109 "Counter": "0,1,2,3", 110 "CounterHTOff": "0,1,2,3,4,5,6,7", 111 "EventCode": "0x28", 112 "EventName": "L2_L1D_WB_RQSTS.HIT_M", 113 "SampleAfterValue": "200003", 114 "UMask": "0x8" 115 }, 116 { 117 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.", 118 "Counter": "0,1,2,3", 119 "CounterHTOff": "0,1,2,3,4,5,6,7", 120 "EventCode": "0x28", 121 "EventName": "L2_L1D_WB_RQSTS.HIT_S", 122 "SampleAfterValue": "200003", 123 "UMask": "0x2" 124 }, 125 { 126 "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).", 127 "Counter": "0,1,2,3", 128 "CounterHTOff": "0,1,2,3,4,5,6,7", 129 "EventCode": "0x28", 130 "EventName": "L2_L1D_WB_RQSTS.MISS", 131 "SampleAfterValue": "200003", 132 "UMask": "0x1" 133 }, 134 { 135 "BriefDescription": "L2 cache lines filling L2.", 136 "Counter": "0,1,2,3", 137 "CounterHTOff": "0,1,2,3,4,5,6,7", 138 "EventCode": "0xF1", 139 "EventName": "L2_LINES_IN.ALL", 140 "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", 141 "SampleAfterValue": "100003", 142 "UMask": "0x7" 143 }, 144 { 145 "BriefDescription": "L2 cache lines in E state filling L2.", 146 "Counter": "0,1,2,3", 147 "CounterHTOff": "0,1,2,3,4,5,6,7", 148 "EventCode": "0xF1", 149 "EventName": "L2_LINES_IN.E", 150 "SampleAfterValue": "100003", 151 "UMask": "0x4" 152 }, 153 { 154 "BriefDescription": "L2 cache lines in I state filling L2.", 155 "Counter": "0,1,2,3", 156 "CounterHTOff": "0,1,2,3,4,5,6,7", 157 "EventCode": "0xF1", 158 "EventName": "L2_LINES_IN.I", 159 "SampleAfterValue": "100003", 160 "UMask": "0x1" 161 }, 162 { 163 "BriefDescription": "L2 cache lines in S state filling L2.", 164 "Counter": "0,1,2,3", 165 "CounterHTOff": "0,1,2,3,4,5,6,7", 166 "EventCode": "0xF1", 167 "EventName": "L2_LINES_IN.S", 168 "SampleAfterValue": "100003", 169 "UMask": "0x2" 170 }, 171 { 172 "BriefDescription": "Clean L2 cache lines evicted by demand.", 173 "Counter": "0,1,2,3", 174 "CounterHTOff": "0,1,2,3,4,5,6,7", 175 "EventCode": "0xF2", 176 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 177 "SampleAfterValue": "100003", 178 "UMask": "0x1" 179 }, 180 { 181 "BriefDescription": "Dirty L2 cache lines evicted by demand.", 182 "Counter": "0,1,2,3", 183 "CounterHTOff": "0,1,2,3,4,5,6,7", 184 "EventCode": "0xF2", 185 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 186 "SampleAfterValue": "100003", 187 "UMask": "0x2" 188 }, 189 { 190 "BriefDescription": "Dirty L2 cache lines filling the L2.", 191 "Counter": "0,1,2,3", 192 "CounterHTOff": "0,1,2,3,4,5,6,7", 193 "EventCode": "0xF2", 194 "EventName": "L2_LINES_OUT.DIRTY_ALL", 195 "SampleAfterValue": "100003", 196 "UMask": "0xa" 197 }, 198 { 199 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", 200 "Counter": "0,1,2,3", 201 "CounterHTOff": "0,1,2,3,4,5,6,7", 202 "EventCode": "0xF2", 203 "EventName": "L2_LINES_OUT.PF_CLEAN", 204 "SampleAfterValue": "100003", 205 "UMask": "0x4" 206 }, 207 { 208 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", 209 "Counter": "0,1,2,3", 210 "CounterHTOff": "0,1,2,3,4,5,6,7", 211 "EventCode": "0xF2", 212 "EventName": "L2_LINES_OUT.PF_DIRTY", 213 "SampleAfterValue": "100003", 214 "UMask": "0x8" 215 }, 216 { 217 "BriefDescription": "L2 code requests.", 218 "Counter": "0,1,2,3", 219 "CounterHTOff": "0,1,2,3,4,5,6,7", 220 "EventCode": "0x24", 221 "EventName": "L2_RQSTS.ALL_CODE_RD", 222 "SampleAfterValue": "200003", 223 "UMask": "0x30" 224 }, 225 { 226 "BriefDescription": "Demand Data Read requests.", 227 "Counter": "0,1,2,3", 228 "CounterHTOff": "0,1,2,3,4,5,6,7", 229 "EventCode": "0x24", 230 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 231 "SampleAfterValue": "200003", 232 "UMask": "0x3" 233 }, 234 { 235 "BriefDescription": "Requests from L2 hardware prefetchers.", 236 "Counter": "0,1,2,3", 237 "CounterHTOff": "0,1,2,3,4,5,6,7", 238 "EventCode": "0x24", 239 "EventName": "L2_RQSTS.ALL_PF", 240 "SampleAfterValue": "200003", 241 "UMask": "0xc0" 242 }, 243 { 244 "BriefDescription": "RFO requests to L2 cache.", 245 "Counter": "0,1,2,3", 246 "CounterHTOff": "0,1,2,3,4,5,6,7", 247 "EventCode": "0x24", 248 "EventName": "L2_RQSTS.ALL_RFO", 249 "SampleAfterValue": "200003", 250 "UMask": "0xc" 251 }, 252 { 253 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 254 "Counter": "0,1,2,3", 255 "CounterHTOff": "0,1,2,3,4,5,6,7", 256 "EventCode": "0x24", 257 "EventName": "L2_RQSTS.CODE_RD_HIT", 258 "SampleAfterValue": "200003", 259 "UMask": "0x10" 260 }, 261 { 262 "BriefDescription": "L2 cache misses when fetching instructions.", 263 "Counter": "0,1,2,3", 264 "CounterHTOff": "0,1,2,3,4,5,6,7", 265 "EventCode": "0x24", 266 "EventName": "L2_RQSTS.CODE_RD_MISS", 267 "SampleAfterValue": "200003", 268 "UMask": "0x20" 269 }, 270 { 271 "BriefDescription": "Demand Data Read requests that hit L2 cache.", 272 "Counter": "0,1,2,3", 273 "CounterHTOff": "0,1,2,3,4,5,6,7", 274 "EventCode": "0x24", 275 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 276 "SampleAfterValue": "200003", 277 "UMask": "0x1" 278 }, 279 { 280 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", 281 "Counter": "0,1,2,3", 282 "CounterHTOff": "0,1,2,3,4,5,6,7", 283 "EventCode": "0x24", 284 "EventName": "L2_RQSTS.PF_HIT", 285 "SampleAfterValue": "200003", 286 "UMask": "0x40" 287 }, 288 { 289 "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache.", 290 "Counter": "0,1,2,3", 291 "CounterHTOff": "0,1,2,3,4,5,6,7", 292 "EventCode": "0x24", 293 "EventName": "L2_RQSTS.PF_MISS", 294 "SampleAfterValue": "200003", 295 "UMask": "0x80" 296 }, 297 { 298 "BriefDescription": "RFO requests that hit L2 cache.", 299 "Counter": "0,1,2,3", 300 "CounterHTOff": "0,1,2,3,4,5,6,7", 301 "EventCode": "0x24", 302 "EventName": "L2_RQSTS.RFO_HIT", 303 "SampleAfterValue": "200003", 304 "UMask": "0x4" 305 }, 306 { 307 "BriefDescription": "RFO requests that miss L2 cache.", 308 "Counter": "0,1,2,3", 309 "CounterHTOff": "0,1,2,3,4,5,6,7", 310 "EventCode": "0x24", 311 "EventName": "L2_RQSTS.RFO_MISS", 312 "SampleAfterValue": "200003", 313 "UMask": "0x8" 314 }, 315 { 316 "BriefDescription": "RFOs that access cache lines in any state.", 317 "Counter": "0,1,2,3", 318 "CounterHTOff": "0,1,2,3,4,5,6,7", 319 "EventCode": "0x27", 320 "EventName": "L2_STORE_LOCK_RQSTS.ALL", 321 "SampleAfterValue": "200003", 322 "UMask": "0xf" 323 }, 324 { 325 "BriefDescription": "RFOs that hit cache lines in E state.", 326 "Counter": "0,1,2,3", 327 "CounterHTOff": "0,1,2,3,4,5,6,7", 328 "EventCode": "0x27", 329 "EventName": "L2_STORE_LOCK_RQSTS.HIT_E", 330 "SampleAfterValue": "200003", 331 "UMask": "0x4" 332 }, 333 { 334 "BriefDescription": "RFOs that hit cache lines in M state.", 335 "Counter": "0,1,2,3", 336 "CounterHTOff": "0,1,2,3,4,5,6,7", 337 "EventCode": "0x27", 338 "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", 339 "SampleAfterValue": "200003", 340 "UMask": "0x8" 341 }, 342 { 343 "BriefDescription": "RFOs that miss cache lines.", 344 "Counter": "0,1,2,3", 345 "CounterHTOff": "0,1,2,3,4,5,6,7", 346 "EventCode": "0x27", 347 "EventName": "L2_STORE_LOCK_RQSTS.MISS", 348 "SampleAfterValue": "200003", 349 "UMask": "0x1" 350 }, 351 { 352 "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.", 353 "Counter": "0,1,2,3", 354 "CounterHTOff": "0,1,2,3,4,5,6,7", 355 "EventCode": "0xF0", 356 "EventName": "L2_TRANS.ALL_PF", 357 "SampleAfterValue": "200003", 358 "UMask": "0x8" 359 }, 360 { 361 "BriefDescription": "Transactions accessing L2 pipe.", 362 "Counter": "0,1,2,3", 363 "CounterHTOff": "0,1,2,3,4,5,6,7", 364 "EventCode": "0xF0", 365 "EventName": "L2_TRANS.ALL_REQUESTS", 366 "SampleAfterValue": "200003", 367 "UMask": "0x80" 368 }, 369 { 370 "BriefDescription": "L2 cache accesses when fetching instructions.", 371 "Counter": "0,1,2,3", 372 "CounterHTOff": "0,1,2,3,4,5,6,7", 373 "EventCode": "0xF0", 374 "EventName": "L2_TRANS.CODE_RD", 375 "SampleAfterValue": "200003", 376 "UMask": "0x4" 377 }, 378 { 379 "BriefDescription": "Demand Data Read requests that access L2 cache.", 380 "Counter": "0,1,2,3", 381 "CounterHTOff": "0,1,2,3,4,5,6,7", 382 "EventCode": "0xF0", 383 "EventName": "L2_TRANS.DEMAND_DATA_RD", 384 "SampleAfterValue": "200003", 385 "UMask": "0x1" 386 }, 387 { 388 "BriefDescription": "L1D writebacks that access L2 cache.", 389 "Counter": "0,1,2,3", 390 "CounterHTOff": "0,1,2,3,4,5,6,7", 391 "EventCode": "0xF0", 392 "EventName": "L2_TRANS.L1D_WB", 393 "SampleAfterValue": "200003", 394 "UMask": "0x10" 395 }, 396 { 397 "BriefDescription": "L2 fill requests that access L2 cache.", 398 "Counter": "0,1,2,3", 399 "CounterHTOff": "0,1,2,3,4,5,6,7", 400 "EventCode": "0xF0", 401 "EventName": "L2_TRANS.L2_FILL", 402 "SampleAfterValue": "200003", 403 "UMask": "0x20" 404 }, 405 { 406 "BriefDescription": "L2 writebacks that access L2 cache.", 407 "Counter": "0,1,2,3", 408 "CounterHTOff": "0,1,2,3,4,5,6,7", 409 "EventCode": "0xF0", 410 "EventName": "L2_TRANS.L2_WB", 411 "SampleAfterValue": "200003", 412 "UMask": "0x40" 413 }, 414 { 415 "BriefDescription": "RFO requests that access L2 cache.", 416 "Counter": "0,1,2,3", 417 "CounterHTOff": "0,1,2,3,4,5,6,7", 418 "EventCode": "0xF0", 419 "EventName": "L2_TRANS.RFO", 420 "SampleAfterValue": "200003", 421 "UMask": "0x2" 422 }, 423 { 424 "BriefDescription": "Cycles when L1D is locked.", 425 "Counter": "0,1,2,3", 426 "CounterHTOff": "0,1,2,3,4,5,6,7", 427 "EventCode": "0x63", 428 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", 429 "SampleAfterValue": "2000003", 430 "UMask": "0x2" 431 }, 432 { 433 "BriefDescription": "Core-originated cacheable demand requests missed LLC.", 434 "Counter": "0,1,2,3", 435 "CounterHTOff": "0,1,2,3,4,5,6,7", 436 "EventCode": "0x2E", 437 "EventName": "LONGEST_LAT_CACHE.MISS", 438 "SampleAfterValue": "100003", 439 "UMask": "0x41" 440 }, 441 { 442 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.", 443 "Counter": "0,1,2,3", 444 "CounterHTOff": "0,1,2,3,4,5,6,7", 445 "EventCode": "0x2E", 446 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 447 "SampleAfterValue": "100003", 448 "UMask": "0x4f" 449 }, 450 { 451 "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.", 452 "Counter": "0,1,2,3", 453 "CounterHTOff": "0,1,2,3", 454 "EventCode": "0xD2", 455 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", 456 "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state.", 457 "SampleAfterValue": "20011", 458 "UMask": "0x2" 459 }, 460 { 461 "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.", 462 "Counter": "0,1,2,3", 463 "CounterHTOff": "0,1,2,3", 464 "EventCode": "0xD2", 465 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", 466 "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2.", 467 "SampleAfterValue": "20011", 468 "UMask": "0x4" 469 }, 470 { 471 "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", 472 "Counter": "0,1,2,3", 473 "CounterHTOff": "0,1,2,3", 474 "EventCode": "0xD2", 475 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", 476 "SampleAfterValue": "20011", 477 "UMask": "0x1" 478 }, 479 { 480 "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", 481 "Counter": "0,1,2,3", 482 "CounterHTOff": "0,1,2,3", 483 "EventCode": "0xD2", 484 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", 485 "SampleAfterValue": "100003", 486 "UMask": "0x8" 487 }, 488 { 489 "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", 490 "Counter": "0,1,2,3", 491 "CounterHTOff": "0,1,2,3", 492 "EventCode": "0xD3", 493 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", 494 "SampleAfterValue": "100007", 495 "UMask": "0x1" 496 }, 497 { 498 "BriefDescription": "Data from remote DRAM either Snoop not needed or Snoop Miss (RspI)", 499 "Counter": "0,1,2,3", 500 "CounterHTOff": "0,1,2,3", 501 "EventCode": "0xD3", 502 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", 503 "SampleAfterValue": "100007", 504 "UMask": "0x4" 505 }, 506 { 507 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", 508 "Counter": "0,1,2,3", 509 "CounterHTOff": "0,1,2,3", 510 "EventCode": "0xD1", 511 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", 512 "PEBS": "1", 513 "SampleAfterValue": "100003", 514 "UMask": "0x40" 515 }, 516 { 517 "BriefDescription": "Retired load uops with L1 cache hits as data sources.", 518 "Counter": "0,1,2,3", 519 "CounterHTOff": "0,1,2,3", 520 "EventCode": "0xD1", 521 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 522 "PEBS": "1", 523 "SampleAfterValue": "2000003", 524 "UMask": "0x1" 525 }, 526 { 527 "BriefDescription": "Retired load uops with L2 cache hits as data sources.", 528 "Counter": "0,1,2,3", 529 "CounterHTOff": "0,1,2,3", 530 "EventCode": "0xD1", 531 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 532 "PEBS": "1", 533 "SampleAfterValue": "100003", 534 "UMask": "0x2" 535 }, 536 { 537 "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", 538 "Counter": "0,1,2,3", 539 "CounterHTOff": "0,1,2,3", 540 "EventCode": "0xD1", 541 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", 542 "PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache without snoops required.", 543 "SampleAfterValue": "50021", 544 "UMask": "0x4" 545 }, 546 { 547 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", 548 "Counter": "0,1,2,3", 549 "CounterHTOff": "0,1,2,3", 550 "EventCode": "0xD1", 551 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", 552 "SampleAfterValue": "100007", 553 "UMask": "0x20" 554 }, 555 { 556 "BriefDescription": "All retired load uops.", 557 "Counter": "0,1,2,3", 558 "CounterHTOff": "0,1,2,3", 559 "EventCode": "0xD0", 560 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 561 "PEBS": "1", 562 "PublicDescription": "This event counts the number of load uops retired", 563 "SampleAfterValue": "2000003", 564 "UMask": "0x81" 565 }, 566 { 567 "BriefDescription": "All retired store uops.", 568 "Counter": "0,1,2,3", 569 "CounterHTOff": "0,1,2,3", 570 "EventCode": "0xD0", 571 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 572 "PEBS": "1", 573 "PublicDescription": "This event counts the number of store uops retired.", 574 "SampleAfterValue": "2000003", 575 "UMask": "0x82" 576 }, 577 { 578 "BriefDescription": "Retired load uops with locked access.", 579 "Counter": "0,1,2,3", 580 "CounterHTOff": "0,1,2,3", 581 "EventCode": "0xD0", 582 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 583 "PEBS": "1", 584 "SampleAfterValue": "100007", 585 "UMask": "0x21" 586 }, 587 { 588 "BriefDescription": "Retired load uops that split across a cacheline boundary.", 589 "Counter": "0,1,2,3", 590 "CounterHTOff": "0,1,2,3", 591 "EventCode": "0xD0", 592 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 593 "PEBS": "1", 594 "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", 595 "SampleAfterValue": "100003", 596 "UMask": "0x41" 597 }, 598 { 599 "BriefDescription": "Retired store uops that split across a cacheline boundary.", 600 "Counter": "0,1,2,3", 601 "CounterHTOff": "0,1,2,3", 602 "EventCode": "0xD0", 603 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 604 "PEBS": "1", 605 "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", 606 "SampleAfterValue": "100003", 607 "UMask": "0x42" 608 }, 609 { 610 "BriefDescription": "Retired load uops that miss the STLB.", 611 "Counter": "0,1,2,3", 612 "CounterHTOff": "0,1,2,3", 613 "EventCode": "0xD0", 614 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", 615 "PEBS": "1", 616 "SampleAfterValue": "100003", 617 "UMask": "0x11" 618 }, 619 { 620 "BriefDescription": "Retired store uops that miss the STLB.", 621 "Counter": "0,1,2,3", 622 "CounterHTOff": "0,1,2,3", 623 "EventCode": "0xD0", 624 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", 625 "PEBS": "1", 626 "SampleAfterValue": "100003", 627 "UMask": "0x12" 628 }, 629 { 630 "BriefDescription": "Demand and prefetch data reads.", 631 "Counter": "0,1,2,3", 632 "CounterHTOff": "0,1,2,3,4,5,6,7", 633 "EventCode": "0xB0", 634 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", 635 "SampleAfterValue": "100003", 636 "UMask": "0x8" 637 }, 638 { 639 "BriefDescription": "Cacheable and noncachaeble code read requests.", 640 "Counter": "0,1,2,3", 641 "CounterHTOff": "0,1,2,3,4,5,6,7", 642 "EventCode": "0xB0", 643 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", 644 "SampleAfterValue": "100003", 645 "UMask": "0x2" 646 }, 647 { 648 "BriefDescription": "Demand Data Read requests sent to uncore.", 649 "Counter": "0,1,2,3", 650 "CounterHTOff": "0,1,2,3,4,5,6,7", 651 "EventCode": "0xB0", 652 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 653 "SampleAfterValue": "100003", 654 "UMask": "0x1" 655 }, 656 { 657 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM.", 658 "Counter": "0,1,2,3", 659 "CounterHTOff": "0,1,2,3,4,5,6,7", 660 "EventCode": "0xB0", 661 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", 662 "SampleAfterValue": "100003", 663 "UMask": "0x4" 664 }, 665 { 666 "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core.", 667 "Counter": "0,1,2,3", 668 "CounterHTOff": "0,1,2,3,4,5,6,7", 669 "EventCode": "0xB2", 670 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 671 "SampleAfterValue": "2000003", 672 "UMask": "0x1" 673 }, 674 { 675 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.", 676 "Counter": "0,1,2,3", 677 "CounterHTOff": "0,1,2,3,4,5,6,7", 678 "EventCode": "0x60", 679 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 680 "SampleAfterValue": "2000003", 681 "UMask": "0x8" 682 }, 683 { 684 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 685 "Counter": "0,1,2,3", 686 "CounterHTOff": "0,1,2,3,4,5,6,7", 687 "CounterMask": "1", 688 "EventCode": "0x60", 689 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 690 "SampleAfterValue": "2000003", 691 "UMask": "0x8" 692 }, 693 { 694 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 695 "Counter": "0,1,2,3", 696 "CounterHTOff": "0,1,2,3,4,5,6,7", 697 "CounterMask": "1", 698 "EventCode": "0x60", 699 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", 700 "SampleAfterValue": "2000003", 701 "UMask": "0x1" 702 }, 703 { 704 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 705 "Counter": "0,1,2,3", 706 "CounterHTOff": "0,1,2,3,4,5,6,7", 707 "CounterMask": "1", 708 "EventCode": "0x60", 709 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 710 "SampleAfterValue": "2000003", 711 "UMask": "0x4" 712 }, 713 { 714 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", 715 "Counter": "0,1,2,3", 716 "CounterHTOff": "0,1,2,3,4,5,6,7", 717 "EventCode": "0x60", 718 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 719 "SampleAfterValue": "2000003", 720 "UMask": "0x1" 721 }, 722 { 723 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", 724 "Counter": "0,1,2,3", 725 "CounterHTOff": "0,1,2,3,4,5,6,7", 726 "CounterMask": "6", 727 "EventCode": "0x60", 728 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6", 729 "SampleAfterValue": "2000003", 730 "UMask": "0x1" 731 }, 732 { 733 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.", 734 "Counter": "0,1,2,3", 735 "CounterHTOff": "0,1,2,3,4,5,6,7", 736 "EventCode": "0x60", 737 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 738 "SampleAfterValue": "2000003", 739 "UMask": "0x4" 740 }, 741 { 742 "BriefDescription": "Counts all demand & prefetch data reads", 743 "Counter": "0,1,2,3", 744 "CounterHTOff": "0,1,2,3", 745 "EventCode": "0xB7, 0xBB", 746 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", 747 "MSRIndex": "0x1a6,0x1a7", 748 "MSRValue": "0x000105B3", 749 "Offcore": "1", 750 "SampleAfterValue": "100003", 751 "UMask": "0x1" 752 }, 753 { 754 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 755 "Counter": "0,1,2,3", 756 "CounterHTOff": "0,1,2,3", 757 "EventCode": "0xB7, 0xBB", 758 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 759 "MSRIndex": "0x1a6,0x1a7", 760 "MSRValue": "0x10003c0091", 761 "Offcore": "1", 762 "SampleAfterValue": "100003", 763 "UMask": "0x1" 764 }, 765 { 766 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 767 "Counter": "0,1,2,3", 768 "CounterHTOff": "0,1,2,3", 769 "EventCode": "0xB7, 0xBB", 770 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 771 "MSRIndex": "0x1a6,0x1a7", 772 "MSRValue": "0x4003c0091", 773 "Offcore": "1", 774 "SampleAfterValue": "100003", 775 "UMask": "0x1" 776 }, 777 { 778 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 779 "Counter": "0,1,2,3", 780 "CounterHTOff": "0,1,2,3", 781 "EventCode": "0xB7, 0xBB", 782 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 783 "MSRIndex": "0x1a6,0x1a7", 784 "MSRValue": "0x1003c0091", 785 "Offcore": "1", 786 "SampleAfterValue": "100003", 787 "UMask": "0x1" 788 }, 789 { 790 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", 791 "Counter": "0,1,2,3", 792 "CounterHTOff": "0,1,2,3", 793 "EventCode": "0xB7, 0xBB", 794 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", 795 "MSRIndex": "0x1a6,0x1a7", 796 "MSRValue": "0x2003c0091", 797 "Offcore": "1", 798 "SampleAfterValue": "100003", 799 "UMask": "0x1" 800 }, 801 { 802 "BriefDescription": "Counts all prefetch data reads that hit the LLC", 803 "Counter": "0,1,2,3", 804 "CounterHTOff": "0,1,2,3", 805 "EventCode": "0xB7, 0xBB", 806 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE", 807 "MSRIndex": "0x1a6,0x1a7", 808 "MSRValue": "0x3f803c0090", 809 "Offcore": "1", 810 "SampleAfterValue": "100003", 811 "UMask": "0x1" 812 }, 813 { 814 "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 815 "Counter": "0,1,2,3", 816 "CounterHTOff": "0,1,2,3", 817 "EventCode": "0xB7, 0xBB", 818 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 819 "MSRIndex": "0x1a6,0x1a7", 820 "MSRValue": "0x10003c0090", 821 "Offcore": "1", 822 "SampleAfterValue": "100003", 823 "UMask": "0x1" 824 }, 825 { 826 "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 827 "Counter": "0,1,2,3", 828 "CounterHTOff": "0,1,2,3", 829 "EventCode": "0xB7, 0xBB", 830 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 831 "MSRIndex": "0x1a6,0x1a7", 832 "MSRValue": "0x4003c0090", 833 "Offcore": "1", 834 "SampleAfterValue": "100003", 835 "UMask": "0x1" 836 }, 837 { 838 "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 839 "Counter": "0,1,2,3", 840 "CounterHTOff": "0,1,2,3", 841 "EventCode": "0xB7, 0xBB", 842 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 843 "MSRIndex": "0x1a6,0x1a7", 844 "MSRValue": "0x1003c0090", 845 "Offcore": "1", 846 "SampleAfterValue": "100003", 847 "UMask": "0x1" 848 }, 849 { 850 "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", 851 "Counter": "0,1,2,3", 852 "CounterHTOff": "0,1,2,3", 853 "EventCode": "0xB7, 0xBB", 854 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", 855 "MSRIndex": "0x1a6,0x1a7", 856 "MSRValue": "0x2003c0090", 857 "Offcore": "1", 858 "SampleAfterValue": "100003", 859 "UMask": "0x1" 860 }, 861 { 862 "BriefDescription": "Counts all data/code/rfo references (demand & prefetch)", 863 "Counter": "0,1,2,3", 864 "CounterHTOff": "0,1,2,3", 865 "EventCode": "0xB7, 0xBB", 866 "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", 867 "MSRIndex": "0x1a6,0x1a7", 868 "MSRValue": "0x000107F7", 869 "Offcore": "1", 870 "SampleAfterValue": "100003", 871 "UMask": "0x1" 872 }, 873 { 874 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC", 875 "Counter": "0,1,2,3", 876 "CounterHTOff": "0,1,2,3", 877 "EventCode": "0xB7, 0xBB", 878 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", 879 "MSRIndex": "0x1a6,0x1a7", 880 "MSRValue": "0x3f803c03f7", 881 "Offcore": "1", 882 "SampleAfterValue": "100003", 883 "UMask": "0x1" 884 }, 885 { 886 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 887 "Counter": "0,1,2,3", 888 "CounterHTOff": "0,1,2,3", 889 "EventCode": "0xB7, 0xBB", 890 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", 891 "MSRIndex": "0x1a6,0x1a7", 892 "MSRValue": "0x10003c03f7", 893 "Offcore": "1", 894 "SampleAfterValue": "100003", 895 "UMask": "0x1" 896 }, 897 { 898 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 899 "Counter": "0,1,2,3", 900 "CounterHTOff": "0,1,2,3", 901 "EventCode": "0xB7, 0xBB", 902 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 903 "MSRIndex": "0x1a6,0x1a7", 904 "MSRValue": "0x4003c03f7", 905 "Offcore": "1", 906 "SampleAfterValue": "100003", 907 "UMask": "0x1" 908 }, 909 { 910 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 911 "Counter": "0,1,2,3", 912 "CounterHTOff": "0,1,2,3", 913 "EventCode": "0xB7, 0xBB", 914 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", 915 "MSRIndex": "0x1a6,0x1a7", 916 "MSRValue": "0x1003c03f7", 917 "Offcore": "1", 918 "SampleAfterValue": "100003", 919 "UMask": "0x1" 920 }, 921 { 922 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response", 923 "Counter": "0,1,2,3", 924 "CounterHTOff": "0,1,2,3", 925 "EventCode": "0xB7, 0xBB", 926 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", 927 "MSRIndex": "0x1a6,0x1a7", 928 "MSRValue": "0x2003c03f7", 929 "Offcore": "1", 930 "SampleAfterValue": "100003", 931 "UMask": "0x1" 932 }, 933 { 934 "BriefDescription": "Counts all demand & prefetch prefetch RFOs", 935 "Counter": "0,1,2,3", 936 "CounterHTOff": "0,1,2,3", 937 "EventCode": "0xB7, 0xBB", 938 "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", 939 "MSRIndex": "0x1a6,0x1a7", 940 "MSRValue": "0x00010122", 941 "Offcore": "1", 942 "SampleAfterValue": "100003", 943 "UMask": "0x1" 944 }, 945 { 946 "BriefDescription": "Counts all writebacks from the core to the LLC", 947 "Counter": "0,1,2,3", 948 "CounterHTOff": "0,1,2,3", 949 "EventCode": "0xB7, 0xBB", 950 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", 951 "MSRIndex": "0x1a6,0x1a7", 952 "MSRValue": "0x10008", 953 "Offcore": "1", 954 "SampleAfterValue": "100003", 955 "UMask": "0x1" 956 }, 957 { 958 "BriefDescription": "Counts all demand code reads", 959 "Counter": "0,1,2,3", 960 "CounterHTOff": "0,1,2,3", 961 "EventCode": "0xB7, 0xBB", 962 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", 963 "MSRIndex": "0x1a6,0x1a7", 964 "MSRValue": "0x00010004", 965 "Offcore": "1", 966 "SampleAfterValue": "100003", 967 "UMask": "0x1" 968 }, 969 { 970 "BriefDescription": "Counts all demand code reads that hit in the LLC", 971 "Counter": "0,1,2,3", 972 "CounterHTOff": "0,1,2,3", 973 "EventCode": "0xB7, 0xBB", 974 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", 975 "MSRIndex": "0x1a6,0x1a7", 976 "MSRValue": "0x3f803c0004", 977 "Offcore": "1", 978 "SampleAfterValue": "100003", 979 "UMask": "0x1" 980 }, 981 { 982 "BriefDescription": "Counts all demand data reads", 983 "Counter": "0,1,2,3", 984 "CounterHTOff": "0,1,2,3", 985 "EventCode": "0xB7, 0xBB", 986 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", 987 "MSRIndex": "0x1a6,0x1a7", 988 "MSRValue": "0x00010001", 989 "Offcore": "1", 990 "SampleAfterValue": "100003", 991 "UMask": "0x1" 992 }, 993 { 994 "BriefDescription": "Counts all demand data reads that hit in the LLC", 995 "Counter": "0,1,2,3", 996 "CounterHTOff": "0,1,2,3", 997 "EventCode": "0xB7, 0xBB", 998 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", 999 "MSRIndex": "0x1a6,0x1a7", 1000 "MSRValue": "0x3f803c0001", 1001 "Offcore": "1", 1002 "SampleAfterValue": "100003", 1003 "UMask": "0x1" 1004 }, 1005 { 1006 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1007 "Counter": "0,1,2,3", 1008 "CounterHTOff": "0,1,2,3", 1009 "EventCode": "0xB7, 0xBB", 1010 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 1011 "MSRIndex": "0x1a6,0x1a7", 1012 "MSRValue": "0x10003c0001", 1013 "Offcore": "1", 1014 "SampleAfterValue": "100003", 1015 "UMask": "0x1" 1016 }, 1017 { 1018 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 1019 "Counter": "0,1,2,3", 1020 "CounterHTOff": "0,1,2,3", 1021 "EventCode": "0xB7, 0xBB", 1022 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 1023 "MSRIndex": "0x1a6,0x1a7", 1024 "MSRValue": "0x4003c0001", 1025 "Offcore": "1", 1026 "SampleAfterValue": "100003", 1027 "UMask": "0x1" 1028 }, 1029 { 1030 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 1031 "Counter": "0,1,2,3", 1032 "CounterHTOff": "0,1,2,3", 1033 "EventCode": "0xB7, 0xBB", 1034 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 1035 "MSRIndex": "0x1a6,0x1a7", 1036 "MSRValue": "0x1003c0001", 1037 "Offcore": "1", 1038 "SampleAfterValue": "100003", 1039 "UMask": "0x1" 1040 }, 1041 { 1042 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response", 1043 "Counter": "0,1,2,3", 1044 "CounterHTOff": "0,1,2,3", 1045 "EventCode": "0xB7, 0xBB", 1046 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", 1047 "MSRIndex": "0x1a6,0x1a7", 1048 "MSRValue": "0x2003c0001", 1049 "Offcore": "1", 1050 "SampleAfterValue": "100003", 1051 "UMask": "0x1" 1052 }, 1053 { 1054 "BriefDescription": "Counts all demand rfo's", 1055 "Counter": "0,1,2,3", 1056 "CounterHTOff": "0,1,2,3", 1057 "EventCode": "0xB7, 0xBB", 1058 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", 1059 "MSRIndex": "0x1a6,0x1a7", 1060 "MSRValue": "0x00010002", 1061 "Offcore": "1", 1062 "SampleAfterValue": "100003", 1063 "UMask": "0x1" 1064 }, 1065 { 1066 "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches", 1067 "Counter": "0,1,2,3", 1068 "CounterHTOff": "0,1,2,3", 1069 "EventCode": "0xB7, 0xBB", 1070 "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", 1071 "MSRIndex": "0x1a6,0x1a7", 1072 "MSRValue": "0x803c8000", 1073 "Offcore": "1", 1074 "SampleAfterValue": "100003", 1075 "UMask": "0x1" 1076 }, 1077 { 1078 "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses", 1079 "Counter": "0,1,2,3", 1080 "CounterHTOff": "0,1,2,3", 1081 "EventCode": "0xB7, 0xBB", 1082 "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", 1083 "MSRIndex": "0x1a6,0x1a7", 1084 "MSRValue": "0x23ffc08000", 1085 "Offcore": "1", 1086 "SampleAfterValue": "100003", 1087 "UMask": "0x1" 1088 }, 1089 { 1090 "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC", 1091 "Counter": "0,1,2,3", 1092 "CounterHTOff": "0,1,2,3", 1093 "EventCode": "0xB7, 0xBB", 1094 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", 1095 "MSRIndex": "0x1a6,0x1a7", 1096 "MSRValue": "0x3f803c0040", 1097 "Offcore": "1", 1098 "SampleAfterValue": "100003", 1099 "UMask": "0x1" 1100 }, 1101 { 1102 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC", 1103 "Counter": "0,1,2,3", 1104 "CounterHTOff": "0,1,2,3", 1105 "EventCode": "0xB7, 0xBB", 1106 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", 1107 "MSRIndex": "0x1a6,0x1a7", 1108 "MSRValue": "0x3f803c0010", 1109 "Offcore": "1", 1110 "SampleAfterValue": "100003", 1111 "UMask": "0x1" 1112 }, 1113 { 1114 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1115 "Counter": "0,1,2,3", 1116 "CounterHTOff": "0,1,2,3", 1117 "EventCode": "0xB7, 0xBB", 1118 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 1119 "MSRIndex": "0x1a6,0x1a7", 1120 "MSRValue": "0x10003c0010", 1121 "Offcore": "1", 1122 "SampleAfterValue": "100003", 1123 "UMask": "0x1" 1124 }, 1125 { 1126 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 1127 "Counter": "0,1,2,3", 1128 "CounterHTOff": "0,1,2,3", 1129 "EventCode": "0xB7, 0xBB", 1130 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 1131 "MSRIndex": "0x1a6,0x1a7", 1132 "MSRValue": "0x4003c0010", 1133 "Offcore": "1", 1134 "SampleAfterValue": "100003", 1135 "UMask": "0x1" 1136 }, 1137 { 1138 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 1139 "Counter": "0,1,2,3", 1140 "CounterHTOff": "0,1,2,3", 1141 "EventCode": "0xB7, 0xBB", 1142 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 1143 "MSRIndex": "0x1a6,0x1a7", 1144 "MSRValue": "0x1003c0010", 1145 "Offcore": "1", 1146 "SampleAfterValue": "100003", 1147 "UMask": "0x1" 1148 }, 1149 { 1150 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", 1151 "Counter": "0,1,2,3", 1152 "CounterHTOff": "0,1,2,3", 1153 "EventCode": "0xB7, 0xBB", 1154 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", 1155 "MSRIndex": "0x1a6,0x1a7", 1156 "MSRValue": "0x2003c0010", 1157 "Offcore": "1", 1158 "SampleAfterValue": "100003", 1159 "UMask": "0x1" 1160 }, 1161 { 1162 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC", 1163 "Counter": "0,1,2,3", 1164 "CounterHTOff": "0,1,2,3", 1165 "EventCode": "0xB7, 0xBB", 1166 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", 1167 "MSRIndex": "0x1a6,0x1a7", 1168 "MSRValue": "0x3f803c0200", 1169 "Offcore": "1", 1170 "SampleAfterValue": "100003", 1171 "UMask": "0x1" 1172 }, 1173 { 1174 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC", 1175 "Counter": "0,1,2,3", 1176 "CounterHTOff": "0,1,2,3", 1177 "EventCode": "0xB7, 0xBB", 1178 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", 1179 "MSRIndex": "0x1a6,0x1a7", 1180 "MSRValue": "0x3f803c0080", 1181 "Offcore": "1", 1182 "SampleAfterValue": "100003", 1183 "UMask": "0x1" 1184 }, 1185 { 1186 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1187 "Counter": "0,1,2,3", 1188 "CounterHTOff": "0,1,2,3", 1189 "EventCode": "0xB7, 0xBB", 1190 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 1191 "MSRIndex": "0x1a6,0x1a7", 1192 "MSRValue": "0x10003c0080", 1193 "Offcore": "1", 1194 "SampleAfterValue": "100003", 1195 "UMask": "0x1" 1196 }, 1197 { 1198 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 1199 "Counter": "0,1,2,3", 1200 "CounterHTOff": "0,1,2,3", 1201 "EventCode": "0xB7, 0xBB", 1202 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 1203 "MSRIndex": "0x1a6,0x1a7", 1204 "MSRValue": "0x4003c0080", 1205 "Offcore": "1", 1206 "SampleAfterValue": "100003", 1207 "UMask": "0x1" 1208 }, 1209 { 1210 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 1211 "Counter": "0,1,2,3", 1212 "CounterHTOff": "0,1,2,3", 1213 "EventCode": "0xB7, 0xBB", 1214 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 1215 "MSRIndex": "0x1a6,0x1a7", 1216 "MSRValue": "0x1003c0080", 1217 "Offcore": "1", 1218 "SampleAfterValue": "100003", 1219 "UMask": "0x1" 1220 }, 1221 { 1222 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", 1223 "Counter": "0,1,2,3", 1224 "CounterHTOff": "0,1,2,3", 1225 "EventCode": "0xB7, 0xBB", 1226 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", 1227 "MSRIndex": "0x1a6,0x1a7", 1228 "MSRValue": "0x2003c0080", 1229 "Offcore": "1", 1230 "SampleAfterValue": "100003", 1231 "UMask": "0x1" 1232 }, 1233 { 1234 "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address", 1235 "Counter": "0,1,2,3", 1236 "CounterHTOff": "0,1,2,3", 1237 "EventCode": "0xB7, 0xBB", 1238 "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", 1239 "MSRIndex": "0x1a6,0x1a7", 1240 "MSRValue": "0x10400", 1241 "Offcore": "1", 1242 "SampleAfterValue": "100003", 1243 "UMask": "0x1" 1244 }, 1245 { 1246 "BriefDescription": "Counts non-temporal stores", 1247 "Counter": "0,1,2,3", 1248 "CounterHTOff": "0,1,2,3", 1249 "EventCode": "0xB7, 0xBB", 1250 "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", 1251 "MSRIndex": "0x1a6,0x1a7", 1252 "MSRValue": "0x10800", 1253 "Offcore": "1", 1254 "SampleAfterValue": "100003", 1255 "UMask": "0x1" 1256 }, 1257 { 1258 "BriefDescription": "Split locks in SQ.", 1259 "Counter": "0,1,2,3", 1260 "CounterHTOff": "0,1,2,3,4,5,6,7", 1261 "EventCode": "0xF4", 1262 "EventName": "SQ_MISC.SPLIT_LOCK", 1263 "SampleAfterValue": "100003", 1264 "UMask": "0x10" 1265 } 1266]