cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

other.json (2131B)

      1[
      2    {
      3        "BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
      4        "Counter": "0,1,2,3",
      5        "CounterHTOff": "0,1,2,3,4,5,6,7",
      6        "EventCode": "0x5C",
      7        "EventName": "CPL_CYCLES.RING0",
      8        "SampleAfterValue": "2000003",
      9        "UMask": "0x1"
     10    },
     11    {
     12        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
     13        "Counter": "0,1,2,3",
     14        "CounterHTOff": "0,1,2,3,4,5,6,7",
     15        "CounterMask": "1",
     16        "EdgeDetect": "1",
     17        "EventCode": "0x5C",
     18        "EventName": "CPL_CYCLES.RING0_TRANS",
     19        "SampleAfterValue": "100007",
     20        "UMask": "0x1"
     21    },
     22    {
     23        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
     24        "Counter": "0,1,2,3",
     25        "CounterHTOff": "0,1,2,3,4,5,6,7",
     26        "EventCode": "0x5C",
     27        "EventName": "CPL_CYCLES.RING123",
     28        "SampleAfterValue": "2000003",
     29        "UMask": "0x2"
     30    },
     31    {
     32        "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
     33        "Counter": "0,1,2,3",
     34        "CounterHTOff": "0,1,2,3,4,5,6,7",
     35        "EventCode": "0x4E",
     36        "EventName": "HW_PRE_REQ.DL1_MISS",
     37        "SampleAfterValue": "2000003",
     38        "UMask": "0x2"
     39    },
     40    {
     41        "BriefDescription": "Valid instructions written to IQ per cycle.",
     42        "Counter": "0,1,2,3",
     43        "CounterHTOff": "0,1,2,3,4,5,6,7",
     44        "EventCode": "0x17",
     45        "EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
     46        "SampleAfterValue": "2000003",
     47        "UMask": "0x1"
     48    },
     49    {
     50        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
     51        "Counter": "0,1,2,3",
     52        "CounterHTOff": "0,1,2,3,4,5,6,7",
     53        "EventCode": "0x63",
     54        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
     55        "SampleAfterValue": "2000003",
     56        "UMask": "0x1"
     57    }
     58]