memory.json (42314B)
1[ 2 { 3 "BriefDescription": "Counts the number of times the machine clears due to memory ordering hazards", 4 "Counter": "0,1", 5 "EventCode": "0xC3", 6 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 7 "SampleAfterValue": "200003", 8 "UMask": "0x2" 9 }, 10 { 11 "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far)", 12 "Counter": "0,1", 13 "EventCode": "0xB7", 14 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR", 15 "MSRIndex": "0x1a6,0x1a7", 16 "MSRValue": "0x0181800044", 17 "Offcore": "1", 18 "SampleAfterValue": "100007", 19 "UMask": "0x1" 20 }, 21 { 22 "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far.", 23 "Counter": "0,1", 24 "EventCode": "0xB7", 25 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR", 26 "MSRIndex": "0x1a6,0x1a7", 27 "MSRValue": "0x0101000044", 28 "Offcore": "1", 29 "SampleAfterValue": "100007", 30 "UMask": "0x1" 31 }, 32 { 33 "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local.", 34 "Counter": "0,1", 35 "EventCode": "0xB7", 36 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR", 37 "MSRIndex": "0x1a6,0x1a7", 38 "MSRValue": "0x0080800044", 39 "Offcore": "1", 40 "SampleAfterValue": "100007", 41 "UMask": "0x1" 42 }, 43 { 44 "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far)", 45 "Counter": "0,1", 46 "EventCode": "0xB7", 47 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM", 48 "MSRIndex": "0x1a6,0x1a7", 49 "MSRValue": "0x0180600044", 50 "Offcore": "1", 51 "SampleAfterValue": "100007", 52 "UMask": "0x1" 53 }, 54 { 55 "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 56 "Counter": "0,1", 57 "EventCode": "0xB7", 58 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR", 59 "MSRIndex": "0x1a6,0x1a7", 60 "MSRValue": "0x0100400044", 61 "Offcore": "1", 62 "SampleAfterValue": "100007", 63 "UMask": "0x1" 64 }, 65 { 66 "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local.", 67 "Counter": "0,1", 68 "EventCode": "0xB7", 69 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR", 70 "MSRIndex": "0x1a6,0x1a7", 71 "MSRValue": "0x0080200044", 72 "Offcore": "1", 73 "SampleAfterValue": "100007", 74 "UMask": "0x1" 75 }, 76 { 77 "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far)", 78 "Counter": "0,1", 79 "EventCode": "0xB7", 80 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR", 81 "MSRIndex": "0x1a6,0x1a7", 82 "MSRValue": "0x0181803091", 83 "Offcore": "1", 84 "SampleAfterValue": "100007", 85 "UMask": "0x1" 86 }, 87 { 88 "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far.", 89 "Counter": "0,1", 90 "EventCode": "0xB7", 91 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR", 92 "MSRIndex": "0x1a6,0x1a7", 93 "MSRValue": "0x0101003091", 94 "Offcore": "1", 95 "SampleAfterValue": "100007", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local.", 100 "Counter": "0,1", 101 "EventCode": "0xB7", 102 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR", 103 "MSRIndex": "0x1a6,0x1a7", 104 "MSRValue": "0x0080803091", 105 "Offcore": "1", 106 "SampleAfterValue": "100007", 107 "UMask": "0x1" 108 }, 109 { 110 "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far)", 111 "Counter": "0,1", 112 "EventCode": "0xB7", 113 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM", 114 "MSRIndex": "0x1a6,0x1a7", 115 "MSRValue": "0x0180603091", 116 "Offcore": "1", 117 "SampleAfterValue": "100007", 118 "UMask": "0x1" 119 }, 120 { 121 "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 122 "Counter": "0,1", 123 "EventCode": "0xB7", 124 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR", 125 "MSRIndex": "0x1a6,0x1a7", 126 "MSRValue": "0x0100403091", 127 "Offcore": "1", 128 "SampleAfterValue": "100007", 129 "UMask": "0x1" 130 }, 131 { 132 "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local.", 133 "Counter": "0,1", 134 "EventCode": "0xB7", 135 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR", 136 "MSRIndex": "0x1a6,0x1a7", 137 "MSRValue": "0x0080203091", 138 "Offcore": "1", 139 "SampleAfterValue": "100007", 140 "UMask": "0x1" 141 }, 142 { 143 "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.", 144 "Counter": "0,1", 145 "EventCode": "0xB7", 146 "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR", 147 "MSRIndex": "0x1a6,0x1a7", 148 "MSRValue": "0x0101000070", 149 "Offcore": "1", 150 "SampleAfterValue": "100007", 151 "UMask": "0x1" 152 }, 153 { 154 "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.", 155 "Counter": "0,1", 156 "EventCode": "0xB7", 157 "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR", 158 "MSRIndex": "0x1a6,0x1a7", 159 "MSRValue": "0x0080800070", 160 "Offcore": "1", 161 "SampleAfterValue": "100007", 162 "UMask": "0x1" 163 }, 164 { 165 "BriefDescription": "Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)", 166 "Counter": "0,1", 167 "EventCode": "0xB7", 168 "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM", 169 "MSRIndex": "0x1a6,0x1a7", 170 "MSRValue": "0x0180600070", 171 "Offcore": "1", 172 "SampleAfterValue": "100007", 173 "UMask": "0x1" 174 }, 175 { 176 "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 177 "Counter": "0,1", 178 "EventCode": "0xB7", 179 "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR", 180 "MSRIndex": "0x1a6,0x1a7", 181 "MSRValue": "0x0100400070", 182 "Offcore": "1", 183 "SampleAfterValue": "100007", 184 "UMask": "0x1" 185 }, 186 { 187 "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Local.", 188 "Counter": "0,1", 189 "EventCode": "0xB7", 190 "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR", 191 "MSRIndex": "0x1a6,0x1a7", 192 "MSRValue": "0x0080200070", 193 "Offcore": "1", 194 "SampleAfterValue": "100007", 195 "UMask": "0x1" 196 }, 197 { 198 "BriefDescription": "Counts any Read request that accounts for responses from DDR (local and far)", 199 "Counter": "0,1", 200 "EventCode": "0xB7", 201 "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR", 202 "MSRIndex": "0x1a6,0x1a7", 203 "MSRValue": "0x01818032f7", 204 "Offcore": "1", 205 "SampleAfterValue": "100007", 206 "UMask": "0x1" 207 }, 208 { 209 "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Far.", 210 "Counter": "0,1", 211 "EventCode": "0xB7", 212 "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR", 213 "MSRIndex": "0x1a6,0x1a7", 214 "MSRValue": "0x01010032f7", 215 "Offcore": "1", 216 "SampleAfterValue": "100007", 217 "UMask": "0x1" 218 }, 219 { 220 "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Local.", 221 "Counter": "0,1", 222 "EventCode": "0xB7", 223 "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR", 224 "MSRIndex": "0x1a6,0x1a7", 225 "MSRValue": "0x00808032f7", 226 "Offcore": "1", 227 "SampleAfterValue": "100007", 228 "UMask": "0x1" 229 }, 230 { 231 "BriefDescription": "Counts any Read request that accounts for responses from MCDRAM (local and far)", 232 "Counter": "0,1", 233 "EventCode": "0xB7", 234 "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM", 235 "MSRIndex": "0x1a6,0x1a7", 236 "MSRValue": "0x01806032f7", 237 "Offcore": "1", 238 "SampleAfterValue": "100007", 239 "UMask": "0x1" 240 }, 241 { 242 "BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 243 "Counter": "0,1", 244 "EventCode": "0xB7", 245 "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR", 246 "MSRIndex": "0x1a6,0x1a7", 247 "MSRValue": "0x01004032f7", 248 "Offcore": "1", 249 "SampleAfterValue": "100007", 250 "UMask": "0x1" 251 }, 252 { 253 "BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Local.", 254 "Counter": "0,1", 255 "EventCode": "0xB7", 256 "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR", 257 "MSRIndex": "0x1a6,0x1a7", 258 "MSRValue": "0x00802032f7", 259 "Offcore": "1", 260 "SampleAfterValue": "100007", 261 "UMask": "0x1" 262 }, 263 { 264 "BriefDescription": "Counts any request that accounts for responses from DDR (local and far)", 265 "Counter": "0,1", 266 "EventCode": "0xB7", 267 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR", 268 "MSRIndex": "0x1a6,0x1a7", 269 "MSRValue": "0x0181808000", 270 "Offcore": "1", 271 "SampleAfterValue": "100007", 272 "UMask": "0x1" 273 }, 274 { 275 "BriefDescription": "Counts any request that accounts for data responses from DRAM Far.", 276 "Counter": "0,1", 277 "EventCode": "0xB7", 278 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR", 279 "MSRIndex": "0x1a6,0x1a7", 280 "MSRValue": "0x0101008000", 281 "Offcore": "1", 282 "SampleAfterValue": "100007", 283 "UMask": "0x1" 284 }, 285 { 286 "BriefDescription": "Counts any request that accounts for data responses from DRAM Local.", 287 "Counter": "0,1", 288 "EventCode": "0xB7", 289 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR", 290 "MSRIndex": "0x1a6,0x1a7", 291 "MSRValue": "0x0080808000", 292 "Offcore": "1", 293 "SampleAfterValue": "100007", 294 "UMask": "0x1" 295 }, 296 { 297 "BriefDescription": "Counts any request that accounts for responses from MCDRAM (local and far)", 298 "Counter": "0,1", 299 "EventCode": "0xB7", 300 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM", 301 "MSRIndex": "0x1a6,0x1a7", 302 "MSRValue": "0x0180608000", 303 "Offcore": "1", 304 "SampleAfterValue": "100007", 305 "UMask": "0x1" 306 }, 307 { 308 "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 309 "Counter": "0,1", 310 "EventCode": "0xB7", 311 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR", 312 "MSRIndex": "0x1a6,0x1a7", 313 "MSRValue": "0x0100408000", 314 "Offcore": "1", 315 "SampleAfterValue": "100007", 316 "UMask": "0x1" 317 }, 318 { 319 "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Local.", 320 "Counter": "0,1", 321 "EventCode": "0xB7", 322 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR", 323 "MSRIndex": "0x1a6,0x1a7", 324 "MSRValue": "0x0080208000", 325 "Offcore": "1", 326 "SampleAfterValue": "100007", 327 "UMask": "0x1" 328 }, 329 { 330 "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from DDR (local and far)", 331 "Counter": "0,1", 332 "EventCode": "0xB7", 333 "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR", 334 "MSRIndex": "0x1a6,0x1a7", 335 "MSRValue": "0x0181800022", 336 "Offcore": "1", 337 "SampleAfterValue": "100007", 338 "UMask": "0x1" 339 }, 340 { 341 "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Far.", 342 "Counter": "0,1", 343 "EventCode": "0xB7", 344 "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR", 345 "MSRIndex": "0x1a6,0x1a7", 346 "MSRValue": "0x0101000022", 347 "Offcore": "1", 348 "SampleAfterValue": "100007", 349 "UMask": "0x1" 350 }, 351 { 352 "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Local.", 353 "Counter": "0,1", 354 "EventCode": "0xB7", 355 "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR", 356 "MSRIndex": "0x1a6,0x1a7", 357 "MSRValue": "0x0080800022", 358 "Offcore": "1", 359 "SampleAfterValue": "100007", 360 "UMask": "0x1" 361 }, 362 { 363 "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far)", 364 "Counter": "0,1", 365 "EventCode": "0xB7", 366 "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM", 367 "MSRIndex": "0x1a6,0x1a7", 368 "MSRValue": "0x0180600022", 369 "Offcore": "1", 370 "SampleAfterValue": "100007", 371 "UMask": "0x1" 372 }, 373 { 374 "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 375 "Counter": "0,1", 376 "EventCode": "0xB7", 377 "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR", 378 "MSRIndex": "0x1a6,0x1a7", 379 "MSRValue": "0x0100400022", 380 "Offcore": "1", 381 "SampleAfterValue": "100007", 382 "UMask": "0x1" 383 }, 384 { 385 "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local.", 386 "Counter": "0,1", 387 "EventCode": "0xB7", 388 "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR", 389 "MSRIndex": "0x1a6,0x1a7", 390 "MSRValue": "0x0080200022", 391 "Offcore": "1", 392 "SampleAfterValue": "100007", 393 "UMask": "0x1" 394 }, 395 { 396 "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)", 397 "Counter": "0,1", 398 "EventCode": "0xB7", 399 "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR", 400 "MSRIndex": "0x1a6,0x1a7", 401 "MSRValue": "0x0181800400", 402 "Offcore": "1", 403 "SampleAfterValue": "100007", 404 "UMask": "0x1" 405 }, 406 { 407 "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far.", 408 "Counter": "0,1", 409 "EventCode": "0xB7", 410 "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR", 411 "MSRIndex": "0x1a6,0x1a7", 412 "MSRValue": "0x0101000400", 413 "Offcore": "1", 414 "SampleAfterValue": "100007", 415 "UMask": "0x1" 416 }, 417 { 418 "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Local.", 419 "Counter": "0,1", 420 "EventCode": "0xB7", 421 "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR", 422 "MSRIndex": "0x1a6,0x1a7", 423 "MSRValue": "0x0080800400", 424 "Offcore": "1", 425 "SampleAfterValue": "100007", 426 "UMask": "0x1" 427 }, 428 { 429 "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)", 430 "Counter": "0,1", 431 "EventCode": "0xB7", 432 "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM", 433 "MSRIndex": "0x1a6,0x1a7", 434 "MSRValue": "0x0180600400", 435 "Offcore": "1", 436 "SampleAfterValue": "100007", 437 "UMask": "0x1" 438 }, 439 { 440 "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 441 "Counter": "0,1", 442 "EventCode": "0xB7", 443 "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR", 444 "MSRIndex": "0x1a6,0x1a7", 445 "MSRValue": "0x0100400400", 446 "Offcore": "1", 447 "SampleAfterValue": "100007", 448 "UMask": "0x1" 449 }, 450 { 451 "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local.", 452 "Counter": "0,1", 453 "EventCode": "0xB7", 454 "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR", 455 "MSRIndex": "0x1a6,0x1a7", 456 "MSRValue": "0x0080200400", 457 "Offcore": "1", 458 "SampleAfterValue": "100007", 459 "UMask": "0x1" 460 }, 461 { 462 "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)", 463 "Counter": "0,1", 464 "EventCode": "0xB7", 465 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR", 466 "MSRIndex": "0x1a6,0x1a7", 467 "MSRValue": "0x0181800004", 468 "Offcore": "1", 469 "SampleAfterValue": "100007", 470 "UMask": "0x1" 471 }, 472 { 473 "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far.", 474 "Counter": "0,1", 475 "EventCode": "0xB7", 476 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR", 477 "MSRIndex": "0x1a6,0x1a7", 478 "MSRValue": "0x0101000004", 479 "Offcore": "1", 480 "SampleAfterValue": "100007", 481 "UMask": "0x1" 482 }, 483 { 484 "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local.", 485 "Counter": "0,1", 486 "EventCode": "0xB7", 487 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR", 488 "MSRIndex": "0x1a6,0x1a7", 489 "MSRValue": "0x0080800004", 490 "Offcore": "1", 491 "SampleAfterValue": "100007", 492 "UMask": "0x1" 493 }, 494 { 495 "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)", 496 "Counter": "0,1", 497 "EventCode": "0xB7", 498 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM", 499 "MSRIndex": "0x1a6,0x1a7", 500 "MSRValue": "0x0180600004", 501 "Offcore": "1", 502 "SampleAfterValue": "100007", 503 "UMask": "0x1" 504 }, 505 { 506 "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 507 "Counter": "0,1", 508 "EventCode": "0xB7", 509 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR", 510 "MSRIndex": "0x1a6,0x1a7", 511 "MSRValue": "0x0100400004", 512 "Offcore": "1", 513 "SampleAfterValue": "100007", 514 "UMask": "0x1" 515 }, 516 { 517 "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local.", 518 "Counter": "0,1", 519 "EventCode": "0xB7", 520 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR", 521 "MSRIndex": "0x1a6,0x1a7", 522 "MSRValue": "0x0080200004", 523 "Offcore": "1", 524 "SampleAfterValue": "100007", 525 "UMask": "0x1" 526 }, 527 { 528 "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)", 529 "Counter": "0,1", 530 "EventCode": "0xB7", 531 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR", 532 "MSRIndex": "0x1a6,0x1a7", 533 "MSRValue": "0x0181800001", 534 "Offcore": "1", 535 "SampleAfterValue": "100007", 536 "UMask": "0x1" 537 }, 538 { 539 "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far.", 540 "Counter": "0,1", 541 "EventCode": "0xB7", 542 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR", 543 "MSRIndex": "0x1a6,0x1a7", 544 "MSRValue": "0x0101000001", 545 "Offcore": "1", 546 "SampleAfterValue": "100007", 547 "UMask": "0x1" 548 }, 549 { 550 "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local.", 551 "Counter": "0,1", 552 "EventCode": "0xB7", 553 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR", 554 "MSRIndex": "0x1a6,0x1a7", 555 "MSRValue": "0x0080800001", 556 "Offcore": "1", 557 "SampleAfterValue": "100007", 558 "UMask": "0x1" 559 }, 560 { 561 "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)", 562 "Counter": "0,1", 563 "EventCode": "0xB7", 564 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM", 565 "MSRIndex": "0x1a6,0x1a7", 566 "MSRValue": "0x0180600001", 567 "Offcore": "1", 568 "SampleAfterValue": "100007", 569 "UMask": "0x1" 570 }, 571 { 572 "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 573 "Counter": "0,1", 574 "EventCode": "0xB7", 575 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR", 576 "MSRIndex": "0x1a6,0x1a7", 577 "MSRValue": "0x0100400001", 578 "Offcore": "1", 579 "SampleAfterValue": "100007", 580 "UMask": "0x1" 581 }, 582 { 583 "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local.", 584 "Counter": "0,1", 585 "EventCode": "0xB7", 586 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR", 587 "MSRIndex": "0x1a6,0x1a7", 588 "MSRValue": "0x0080200001", 589 "Offcore": "1", 590 "SampleAfterValue": "100007", 591 "UMask": "0x1" 592 }, 593 { 594 "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from DDR (local and far)", 595 "Counter": "0,1", 596 "EventCode": "0xB7", 597 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR", 598 "MSRIndex": "0x1a6,0x1a7", 599 "MSRValue": "0x0181800002", 600 "Offcore": "1", 601 "SampleAfterValue": "100007", 602 "UMask": "0x1" 603 }, 604 { 605 "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far.", 606 "Counter": "0,1", 607 "EventCode": "0xB7", 608 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR", 609 "MSRIndex": "0x1a6,0x1a7", 610 "MSRValue": "0x0101000002", 611 "Offcore": "1", 612 "SampleAfterValue": "100007", 613 "UMask": "0x1" 614 }, 615 { 616 "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Local.", 617 "Counter": "0,1", 618 "EventCode": "0xB7", 619 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR", 620 "MSRIndex": "0x1a6,0x1a7", 621 "MSRValue": "0x0080800002", 622 "Offcore": "1", 623 "SampleAfterValue": "100007", 624 "UMask": "0x1" 625 }, 626 { 627 "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)", 628 "Counter": "0,1", 629 "EventCode": "0xB7", 630 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM", 631 "MSRIndex": "0x1a6,0x1a7", 632 "MSRValue": "0x0180600002", 633 "Offcore": "1", 634 "SampleAfterValue": "100007", 635 "UMask": "0x1" 636 }, 637 { 638 "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 639 "Counter": "0,1", 640 "EventCode": "0xB7", 641 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR", 642 "MSRIndex": "0x1a6,0x1a7", 643 "MSRValue": "0x0100400002", 644 "Offcore": "1", 645 "SampleAfterValue": "100007", 646 "UMask": "0x1" 647 }, 648 { 649 "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local.", 650 "Counter": "0,1", 651 "EventCode": "0xB7", 652 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR", 653 "MSRIndex": "0x1a6,0x1a7", 654 "MSRValue": "0x0080200002", 655 "Offcore": "1", 656 "SampleAfterValue": "100007", 657 "UMask": "0x1" 658 }, 659 { 660 "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far)", 661 "Counter": "0,1", 662 "EventCode": "0xB7", 663 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR", 664 "MSRIndex": "0x1a6,0x1a7", 665 "MSRValue": "0x0181800080", 666 "Offcore": "1", 667 "SampleAfterValue": "100007", 668 "UMask": "0x1" 669 }, 670 { 671 "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far.", 672 "Counter": "0,1", 673 "EventCode": "0xB7", 674 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR", 675 "MSRIndex": "0x1a6,0x1a7", 676 "MSRValue": "0x0101000080", 677 "Offcore": "1", 678 "SampleAfterValue": "100007", 679 "UMask": "0x1" 680 }, 681 { 682 "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local.", 683 "Counter": "0,1", 684 "EventCode": "0xB7", 685 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR", 686 "MSRIndex": "0x1a6,0x1a7", 687 "MSRValue": "0x0080800080", 688 "Offcore": "1", 689 "SampleAfterValue": "100007", 690 "UMask": "0x1" 691 }, 692 { 693 "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far)", 694 "Counter": "0,1", 695 "EventCode": "0xB7", 696 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM", 697 "MSRIndex": "0x1a6,0x1a7", 698 "MSRValue": "0x0180600080", 699 "Offcore": "1", 700 "SampleAfterValue": "100007", 701 "UMask": "0x1" 702 }, 703 { 704 "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 705 "Counter": "0,1", 706 "EventCode": "0xB7", 707 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR", 708 "MSRIndex": "0x1a6,0x1a7", 709 "MSRValue": "0x0100400080", 710 "Offcore": "1", 711 "SampleAfterValue": "100007", 712 "UMask": "0x1" 713 }, 714 { 715 "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local.", 716 "Counter": "0,1", 717 "EventCode": "0xB7", 718 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR", 719 "MSRIndex": "0x1a6,0x1a7", 720 "MSRValue": "0x0080200080", 721 "Offcore": "1", 722 "SampleAfterValue": "100007", 723 "UMask": "0x1" 724 }, 725 { 726 "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions", 727 "Counter": "0,1", 728 "EventCode": "0xB7", 729 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM", 730 "MSRIndex": "0x1a6,0x1a7", 731 "MSRValue": "0x2000020080", 732 "Offcore": "1", 733 "SampleAfterValue": "100007", 734 "UMask": "0x1" 735 }, 736 { 737 "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far.", 738 "Counter": "0,1", 739 "EventCode": "0xB7", 740 "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR", 741 "MSRIndex": "0x1a7", 742 "MSRValue": "0x0101000100", 743 "Offcore": "1", 744 "SampleAfterValue": "100007", 745 "UMask": "0x1" 746 }, 747 { 748 "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local.", 749 "Counter": "0,1", 750 "EventCode": "0xB7", 751 "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR", 752 "MSRIndex": "0x1a7", 753 "MSRValue": "0x0080800100", 754 "Offcore": "1", 755 "SampleAfterValue": "100007", 756 "UMask": "0x1" 757 }, 758 { 759 "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)", 760 "Counter": "0,1", 761 "EventCode": "0xB7", 762 "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM", 763 "MSRIndex": "0x1a7", 764 "MSRValue": "0x0180600100", 765 "Offcore": "1", 766 "SampleAfterValue": "100007", 767 "UMask": "0x1" 768 }, 769 { 770 "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 771 "Counter": "0,1", 772 "EventCode": "0xB7", 773 "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR", 774 "MSRIndex": "0x1a7", 775 "MSRValue": "0x0100400100", 776 "Offcore": "1", 777 "SampleAfterValue": "100007", 778 "UMask": "0x1" 779 }, 780 { 781 "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local.", 782 "Counter": "0,1", 783 "EventCode": "0xB7", 784 "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR", 785 "MSRIndex": "0x1a7", 786 "MSRValue": "0x0080200100", 787 "Offcore": "1", 788 "SampleAfterValue": "100007", 789 "UMask": "0x1" 790 }, 791 { 792 "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from DDR (local and far)", 793 "Counter": "0,1", 794 "EventCode": "0xB7", 795 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR", 796 "MSRIndex": "0x1a6,0x1a7", 797 "MSRValue": "0x0181802000", 798 "Offcore": "1", 799 "SampleAfterValue": "100007", 800 "UMask": "0x1" 801 }, 802 { 803 "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far.", 804 "Counter": "0,1", 805 "EventCode": "0xB7", 806 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR", 807 "MSRIndex": "0x1a6,0x1a7", 808 "MSRValue": "0x0101002000", 809 "Offcore": "1", 810 "SampleAfterValue": "100007", 811 "UMask": "0x1" 812 }, 813 { 814 "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Local.", 815 "Counter": "0,1", 816 "EventCode": "0xB7", 817 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR", 818 "MSRIndex": "0x1a6,0x1a7", 819 "MSRValue": "0x0080802000", 820 "Offcore": "1", 821 "SampleAfterValue": "100007", 822 "UMask": "0x1" 823 }, 824 { 825 "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 826 "Counter": "0,1", 827 "EventCode": "0xB7", 828 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR", 829 "MSRIndex": "0x1a6,0x1a7", 830 "MSRValue": "0x0100402000", 831 "Offcore": "1", 832 "SampleAfterValue": "100007", 833 "UMask": "0x1" 834 }, 835 { 836 "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local.", 837 "Counter": "0,1", 838 "EventCode": "0xB7", 839 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR", 840 "MSRIndex": "0x1a6,0x1a7", 841 "MSRValue": "0x0080202000", 842 "Offcore": "1", 843 "SampleAfterValue": "100007", 844 "UMask": "0x1" 845 }, 846 { 847 "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from DDR (local and far)", 848 "Counter": "0,1", 849 "EventCode": "0xB7", 850 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR", 851 "MSRIndex": "0x1a6,0x1a7", 852 "MSRValue": "0x0181800040", 853 "Offcore": "1", 854 "SampleAfterValue": "100007", 855 "UMask": "0x1" 856 }, 857 { 858 "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far.", 859 "Counter": "0,1", 860 "EventCode": "0xB7", 861 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR", 862 "MSRIndex": "0x1a6,0x1a7", 863 "MSRValue": "0x0101000040", 864 "Offcore": "1", 865 "SampleAfterValue": "100007", 866 "UMask": "0x1" 867 }, 868 { 869 "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Local.", 870 "Counter": "0,1", 871 "EventCode": "0xB7", 872 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR", 873 "MSRIndex": "0x1a6,0x1a7", 874 "MSRValue": "0x0080800040", 875 "Offcore": "1", 876 "SampleAfterValue": "100007", 877 "UMask": "0x1" 878 }, 879 { 880 "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 881 "Counter": "0,1", 882 "EventCode": "0xB7", 883 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR", 884 "MSRIndex": "0x1a6,0x1a7", 885 "MSRValue": "0x0100400040", 886 "Offcore": "1", 887 "SampleAfterValue": "100007", 888 "UMask": "0x1" 889 }, 890 { 891 "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local.", 892 "Counter": "0,1", 893 "EventCode": "0xB7", 894 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR", 895 "MSRIndex": "0x1a6,0x1a7", 896 "MSRValue": "0x0080200040", 897 "Offcore": "1", 898 "SampleAfterValue": "100007", 899 "UMask": "0x1" 900 }, 901 { 902 "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)", 903 "Counter": "0,1", 904 "EventCode": "0xB7", 905 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR", 906 "MSRIndex": "0x1a6,0x1a7", 907 "MSRValue": "0x0181800020", 908 "Offcore": "1", 909 "SampleAfterValue": "100007", 910 "UMask": "0x1" 911 }, 912 { 913 "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far.", 914 "Counter": "0,1", 915 "EventCode": "0xB7", 916 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR", 917 "MSRIndex": "0x1a6,0x1a7", 918 "MSRValue": "0x0101000020", 919 "Offcore": "1", 920 "SampleAfterValue": "100007", 921 "UMask": "0x1" 922 }, 923 { 924 "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local.", 925 "Counter": "0,1", 926 "EventCode": "0xB7", 927 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR", 928 "MSRIndex": "0x1a6,0x1a7", 929 "MSRValue": "0x0080800020", 930 "Offcore": "1", 931 "SampleAfterValue": "100007", 932 "UMask": "0x1" 933 }, 934 { 935 "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)", 936 "Counter": "0,1", 937 "EventCode": "0xB7", 938 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM", 939 "MSRIndex": "0x1a6,0x1a7", 940 "MSRValue": "0x0180600020", 941 "Offcore": "1", 942 "SampleAfterValue": "100007", 943 "UMask": "0x1" 944 }, 945 { 946 "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 947 "Counter": "0,1", 948 "EventCode": "0xB7", 949 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR", 950 "MSRIndex": "0x1a6,0x1a7", 951 "MSRValue": "0x0100400020", 952 "Offcore": "1", 953 "SampleAfterValue": "100007", 954 "UMask": "0x1" 955 }, 956 { 957 "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local.", 958 "Counter": "0,1", 959 "EventCode": "0xB7", 960 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR", 961 "MSRIndex": "0x1a6,0x1a7", 962 "MSRValue": "0x0080200020", 963 "Offcore": "1", 964 "SampleAfterValue": "100007", 965 "UMask": "0x1" 966 }, 967 { 968 "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions", 969 "Counter": "0,1", 970 "EventCode": "0xB7", 971 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM", 972 "MSRIndex": "0x1a6,0x1a7", 973 "MSRValue": "0x2000020020", 974 "Offcore": "1", 975 "SampleAfterValue": "100007", 976 "UMask": "0x1" 977 }, 978 { 979 "BriefDescription": "Counts Software Prefetches that accounts for responses from DDR (local and far)", 980 "Counter": "0,1", 981 "EventCode": "0xB7", 982 "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR", 983 "MSRIndex": "0x1a6,0x1a7", 984 "MSRValue": "0x0181801000", 985 "Offcore": "1", 986 "SampleAfterValue": "100007", 987 "UMask": "0x1" 988 }, 989 { 990 "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far.", 991 "Counter": "0,1", 992 "EventCode": "0xB7", 993 "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR", 994 "MSRIndex": "0x1a6,0x1a7", 995 "MSRValue": "0x0101001000", 996 "Offcore": "1", 997 "SampleAfterValue": "100007", 998 "UMask": "0x1" 999 }, 1000 { 1001 "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Local.", 1002 "Counter": "0,1", 1003 "EventCode": "0xB7", 1004 "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR", 1005 "MSRIndex": "0x1a6,0x1a7", 1006 "MSRValue": "0x0080801000", 1007 "Offcore": "1", 1008 "SampleAfterValue": "100007", 1009 "UMask": "0x1" 1010 }, 1011 { 1012 "BriefDescription": "Counts Software Prefetches that accounts for responses from MCDRAM (local and far)", 1013 "Counter": "0,1", 1014 "EventCode": "0xB7", 1015 "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM", 1016 "MSRIndex": "0x1a6,0x1a7", 1017 "MSRValue": "0x0180601000", 1018 "Offcore": "1", 1019 "SampleAfterValue": "100007", 1020 "UMask": "0x1" 1021 }, 1022 { 1023 "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 1024 "Counter": "0,1", 1025 "EventCode": "0xB7", 1026 "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR", 1027 "MSRIndex": "0x1a6,0x1a7", 1028 "MSRValue": "0x0100401000", 1029 "Offcore": "1", 1030 "SampleAfterValue": "100007", 1031 "UMask": "0x1" 1032 }, 1033 { 1034 "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Local.", 1035 "Counter": "0,1", 1036 "EventCode": "0xB7", 1037 "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR", 1038 "MSRIndex": "0x1a6,0x1a7", 1039 "MSRValue": "0x0080201000", 1040 "Offcore": "1", 1041 "SampleAfterValue": "100007", 1042 "UMask": "0x1" 1043 }, 1044 { 1045 "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far)", 1046 "Counter": "0,1", 1047 "EventCode": "0xB7", 1048 "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR", 1049 "MSRIndex": "0x1a6,0x1a7", 1050 "MSRValue": "0x0181800200", 1051 "Offcore": "1", 1052 "SampleAfterValue": "100007", 1053 "UMask": "0x1" 1054 }, 1055 { 1056 "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far.", 1057 "Counter": "0,1", 1058 "EventCode": "0xB7", 1059 "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR", 1060 "MSRIndex": "0x1a6,0x1a7", 1061 "MSRValue": "0x0101000200", 1062 "Offcore": "1", 1063 "SampleAfterValue": "100007", 1064 "UMask": "0x1" 1065 }, 1066 { 1067 "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local.", 1068 "Counter": "0,1", 1069 "EventCode": "0xB7", 1070 "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR", 1071 "MSRIndex": "0x1a6,0x1a7", 1072 "MSRValue": "0x0080800200", 1073 "Offcore": "1", 1074 "SampleAfterValue": "100007", 1075 "UMask": "0x1" 1076 }, 1077 { 1078 "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far)", 1079 "Counter": "0,1", 1080 "EventCode": "0xB7", 1081 "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM", 1082 "MSRIndex": "0x1a6,0x1a7", 1083 "MSRValue": "0x0180600200", 1084 "Offcore": "1", 1085 "SampleAfterValue": "100007", 1086 "UMask": "0x1" 1087 }, 1088 { 1089 "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", 1090 "Counter": "0,1", 1091 "EventCode": "0xB7", 1092 "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR", 1093 "MSRIndex": "0x1a6,0x1a7", 1094 "MSRValue": "0x0100400200", 1095 "Offcore": "1", 1096 "SampleAfterValue": "100007", 1097 "UMask": "0x1" 1098 }, 1099 { 1100 "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local.", 1101 "Counter": "0,1", 1102 "EventCode": "0xB7", 1103 "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR", 1104 "MSRIndex": "0x1a6,0x1a7", 1105 "MSRValue": "0x0080200200", 1106 "Offcore": "1", 1107 "SampleAfterValue": "100007", 1108 "UMask": "0x1" 1109 } 1110]