cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

other.json (4220B)

      1[
      2    {
      3        "BriefDescription": "ES segment renames",
      4        "Counter": "0,1,2,3",
      5        "EventCode": "0xD5",
      6        "EventName": "ES_REG_RENAMES",
      7        "SampleAfterValue": "2000000",
      8        "UMask": "0x1"
      9    },
     10    {
     11        "BriefDescription": "I/O transactions",
     12        "Counter": "0,1,2,3",
     13        "EventCode": "0x6C",
     14        "EventName": "IO_TRANSACTIONS",
     15        "SampleAfterValue": "2000000",
     16        "UMask": "0x1"
     17    },
     18    {
     19        "BriefDescription": "L1I instruction fetch stall cycles",
     20        "Counter": "0,1,2,3",
     21        "EventCode": "0x80",
     22        "EventName": "L1I.CYCLES_STALLED",
     23        "SampleAfterValue": "2000000",
     24        "UMask": "0x4"
     25    },
     26    {
     27        "BriefDescription": "L1I instruction fetch hits",
     28        "Counter": "0,1,2,3",
     29        "EventCode": "0x80",
     30        "EventName": "L1I.HITS",
     31        "SampleAfterValue": "2000000",
     32        "UMask": "0x1"
     33    },
     34    {
     35        "BriefDescription": "L1I instruction fetch misses",
     36        "Counter": "0,1,2,3",
     37        "EventCode": "0x80",
     38        "EventName": "L1I.MISSES",
     39        "SampleAfterValue": "2000000",
     40        "UMask": "0x2"
     41    },
     42    {
     43        "BriefDescription": "L1I Instruction fetches",
     44        "Counter": "0,1,2,3",
     45        "EventCode": "0x80",
     46        "EventName": "L1I.READS",
     47        "SampleAfterValue": "2000000",
     48        "UMask": "0x3"
     49    },
     50    {
     51        "BriefDescription": "Large ITLB hit",
     52        "Counter": "0,1,2,3",
     53        "EventCode": "0x82",
     54        "EventName": "LARGE_ITLB.HIT",
     55        "SampleAfterValue": "200000",
     56        "UMask": "0x1"
     57    },
     58    {
     59        "BriefDescription": "All loads dispatched",
     60        "Counter": "0,1,2,3",
     61        "EventCode": "0x13",
     62        "EventName": "LOAD_DISPATCH.ANY",
     63        "SampleAfterValue": "2000000",
     64        "UMask": "0x7"
     65    },
     66    {
     67        "BriefDescription": "Loads dispatched from the MOB",
     68        "Counter": "0,1,2,3",
     69        "EventCode": "0x13",
     70        "EventName": "LOAD_DISPATCH.MOB",
     71        "SampleAfterValue": "2000000",
     72        "UMask": "0x4"
     73    },
     74    {
     75        "BriefDescription": "Loads dispatched that bypass the MOB",
     76        "Counter": "0,1,2,3",
     77        "EventCode": "0x13",
     78        "EventName": "LOAD_DISPATCH.RS",
     79        "SampleAfterValue": "2000000",
     80        "UMask": "0x1"
     81    },
     82    {
     83        "BriefDescription": "Loads dispatched from stage 305",
     84        "Counter": "0,1,2,3",
     85        "EventCode": "0x13",
     86        "EventName": "LOAD_DISPATCH.RS_DELAYED",
     87        "SampleAfterValue": "2000000",
     88        "UMask": "0x2"
     89    },
     90    {
     91        "BriefDescription": "False dependencies due to partial address aliasing",
     92        "Counter": "0,1,2,3",
     93        "EventCode": "0x7",
     94        "EventName": "PARTIAL_ADDRESS_ALIAS",
     95        "SampleAfterValue": "200000",
     96        "UMask": "0x1"
     97    },
     98    {
     99        "BriefDescription": "All Store buffer stall cycles",
    100        "Counter": "0,1,2,3",
    101        "EventCode": "0x4",
    102        "EventName": "SB_DRAIN.ANY",
    103        "SampleAfterValue": "200000",
    104        "UMask": "0x7"
    105    },
    106    {
    107        "BriefDescription": "Segment rename stall cycles",
    108        "Counter": "0,1,2,3",
    109        "EventCode": "0xD4",
    110        "EventName": "SEG_RENAME_STALLS",
    111        "SampleAfterValue": "2000000",
    112        "UMask": "0x1"
    113    },
    114    {
    115        "BriefDescription": "Thread responded HIT to snoop",
    116        "Counter": "0,1,2,3",
    117        "EventCode": "0xB8",
    118        "EventName": "SNOOP_RESPONSE.HIT",
    119        "SampleAfterValue": "100000",
    120        "UMask": "0x1"
    121    },
    122    {
    123        "BriefDescription": "Thread responded HITE to snoop",
    124        "Counter": "0,1,2,3",
    125        "EventCode": "0xB8",
    126        "EventName": "SNOOP_RESPONSE.HITE",
    127        "SampleAfterValue": "100000",
    128        "UMask": "0x2"
    129    },
    130    {
    131        "BriefDescription": "Thread responded HITM to snoop",
    132        "Counter": "0,1,2,3",
    133        "EventCode": "0xB8",
    134        "EventName": "SNOOP_RESPONSE.HITM",
    135        "SampleAfterValue": "100000",
    136        "UMask": "0x4"
    137    },
    138    {
    139        "BriefDescription": "Super Queue full stall cycles",
    140        "Counter": "0,1,2,3",
    141        "EventCode": "0xF6",
    142        "EventName": "SQ_FULL_STALL_CYCLES",
    143        "SampleAfterValue": "2000000",
    144        "UMask": "0x1"
    145    }
    146]