frontend.json (13200B)
1[ 2 { 3 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0xE6", 7 "EventName": "BACLEARS.ANY", 8 "SampleAfterValue": "100003", 9 "UMask": "0x1f" 10 }, 11 { 12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 13 "Counter": "0,1,2,3", 14 "CounterHTOff": "0,1,2,3,4,5,6,7", 15 "EventCode": "0xAB", 16 "EventName": "DSB2MITE_SWITCHES.COUNT", 17 "SampleAfterValue": "2000003", 18 "UMask": "0x1" 19 }, 20 { 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 22 "Counter": "0,1,2,3", 23 "CounterHTOff": "0,1,2,3,4,5,6,7", 24 "EventCode": "0xAB", 25 "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", 26 "PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.", 27 "SampleAfterValue": "2000003", 28 "UMask": "0x2" 29 }, 30 { 31 "BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.", 32 "Counter": "0,1,2,3", 33 "CounterHTOff": "0,1,2,3,4,5,6,7", 34 "EventCode": "0xAC", 35 "EventName": "DSB_FILL.ALL_CANCEL", 36 "SampleAfterValue": "2000003", 37 "UMask": "0xa" 38 }, 39 { 40 "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.", 41 "Counter": "0,1,2,3", 42 "CounterHTOff": "0,1,2,3,4,5,6,7", 43 "EventCode": "0xAC", 44 "EventName": "DSB_FILL.EXCEED_DSB_LINES", 45 "SampleAfterValue": "2000003", 46 "UMask": "0x8" 47 }, 48 { 49 "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.", 50 "Counter": "0,1,2,3", 51 "CounterHTOff": "0,1,2,3,4,5,6,7", 52 "EventCode": "0xAC", 53 "EventName": "DSB_FILL.OTHER_CANCEL", 54 "SampleAfterValue": "2000003", 55 "UMask": "0x2" 56 }, 57 { 58 "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", 59 "Counter": "0,1,2,3", 60 "CounterHTOff": "0,1,2,3,4,5,6,7", 61 "EventCode": "0x80", 62 "EventName": "ICACHE.HIT", 63 "SampleAfterValue": "2000003", 64 "UMask": "0x1" 65 }, 66 { 67 "BriefDescription": "Instruction cache, streaming buffer and victim cache misses.", 68 "Counter": "0,1,2,3", 69 "CounterHTOff": "0,1,2,3,4,5,6,7", 70 "EventCode": "0x80", 71 "EventName": "ICACHE.MISSES", 72 "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.", 73 "SampleAfterValue": "200003", 74 "UMask": "0x2" 75 }, 76 { 77 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", 78 "Counter": "0,1,2,3", 79 "CounterHTOff": "0,1,2,3,4,5,6,7", 80 "CounterMask": "4", 81 "EventCode": "0x79", 82 "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", 83 "SampleAfterValue": "2000003", 84 "UMask": "0x18" 85 }, 86 { 87 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", 88 "Counter": "0,1,2,3", 89 "CounterHTOff": "0,1,2,3,4,5,6,7", 90 "CounterMask": "1", 91 "EventCode": "0x79", 92 "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", 93 "SampleAfterValue": "2000003", 94 "UMask": "0x18" 95 }, 96 { 97 "BriefDescription": "Cycles MITE is delivering 4 Uops.", 98 "Counter": "0,1,2,3", 99 "CounterHTOff": "0,1,2,3,4,5,6,7", 100 "CounterMask": "4", 101 "EventCode": "0x79", 102 "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", 103 "SampleAfterValue": "2000003", 104 "UMask": "0x24" 105 }, 106 { 107 "BriefDescription": "Cycles MITE is delivering any Uop.", 108 "Counter": "0,1,2,3", 109 "CounterHTOff": "0,1,2,3,4,5,6,7", 110 "CounterMask": "1", 111 "EventCode": "0x79", 112 "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", 113 "SampleAfterValue": "2000003", 114 "UMask": "0x24" 115 }, 116 { 117 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 118 "Counter": "0,1,2,3", 119 "CounterHTOff": "0,1,2,3,4,5,6,7", 120 "CounterMask": "1", 121 "EventCode": "0x79", 122 "EventName": "IDQ.DSB_CYCLES", 123 "SampleAfterValue": "2000003", 124 "UMask": "0x8" 125 }, 126 { 127 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", 128 "Counter": "0,1,2,3", 129 "CounterHTOff": "0,1,2,3,4,5,6,7", 130 "EventCode": "0x79", 131 "EventName": "IDQ.DSB_UOPS", 132 "SampleAfterValue": "2000003", 133 "UMask": "0x8" 134 }, 135 { 136 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", 137 "Counter": "0,1,2,3", 138 "CounterHTOff": "0,1,2,3", 139 "EventCode": "0x79", 140 "EventName": "IDQ.EMPTY", 141 "SampleAfterValue": "2000003", 142 "UMask": "0x2" 143 }, 144 { 145 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", 146 "Counter": "0,1,2,3", 147 "CounterHTOff": "0,1,2,3,4,5,6,7", 148 "EventCode": "0x79", 149 "EventName": "IDQ.MITE_ALL_UOPS", 150 "SampleAfterValue": "2000003", 151 "UMask": "0x3c" 152 }, 153 { 154 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", 155 "Counter": "0,1,2,3", 156 "CounterHTOff": "0,1,2,3,4,5,6,7", 157 "CounterMask": "1", 158 "EventCode": "0x79", 159 "EventName": "IDQ.MITE_CYCLES", 160 "SampleAfterValue": "2000003", 161 "UMask": "0x4" 162 }, 163 { 164 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", 165 "Counter": "0,1,2,3", 166 "CounterHTOff": "0,1,2,3,4,5,6,7", 167 "EventCode": "0x79", 168 "EventName": "IDQ.MITE_UOPS", 169 "SampleAfterValue": "2000003", 170 "UMask": "0x4" 171 }, 172 { 173 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", 174 "Counter": "0,1,2,3", 175 "CounterHTOff": "0,1,2,3,4,5,6,7", 176 "CounterMask": "1", 177 "EventCode": "0x79", 178 "EventName": "IDQ.MS_CYCLES", 179 "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel 64 and IA-32 Architectures Optimization Reference Manual for more information.", 180 "SampleAfterValue": "2000003", 181 "UMask": "0x30" 182 }, 183 { 184 "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", 185 "Counter": "0,1,2,3", 186 "CounterHTOff": "0,1,2,3,4,5,6,7", 187 "CounterMask": "1", 188 "EventCode": "0x79", 189 "EventName": "IDQ.MS_DSB_CYCLES", 190 "SampleAfterValue": "2000003", 191 "UMask": "0x10" 192 }, 193 { 194 "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", 195 "Counter": "0,1,2,3", 196 "CounterHTOff": "0,1,2,3,4,5,6,7", 197 "CounterMask": "1", 198 "EdgeDetect": "1", 199 "EventCode": "0x79", 200 "EventName": "IDQ.MS_DSB_OCCUR", 201 "SampleAfterValue": "2000003", 202 "UMask": "0x10" 203 }, 204 { 205 "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", 206 "Counter": "0,1,2,3", 207 "CounterHTOff": "0,1,2,3,4,5,6,7", 208 "EventCode": "0x79", 209 "EventName": "IDQ.MS_DSB_UOPS", 210 "SampleAfterValue": "2000003", 211 "UMask": "0x10" 212 }, 213 { 214 "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", 215 "Counter": "0,1,2,3", 216 "CounterHTOff": "0,1,2,3,4,5,6,7", 217 "EventCode": "0x79", 218 "EventName": "IDQ.MS_MITE_UOPS", 219 "SampleAfterValue": "2000003", 220 "UMask": "0x20" 221 }, 222 { 223 "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", 224 "Counter": "0,1,2,3", 225 "CounterHTOff": "0,1,2,3,4,5,6,7", 226 "CounterMask": "1", 227 "EdgeDetect": "1", 228 "EventCode": "0x79", 229 "EventName": "IDQ.MS_SWITCHES", 230 "SampleAfterValue": "2000003", 231 "UMask": "0x30" 232 }, 233 { 234 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", 235 "Counter": "0,1,2,3", 236 "CounterHTOff": "0,1,2,3,4,5,6,7", 237 "EventCode": "0x79", 238 "EventName": "IDQ.MS_UOPS", 239 "SampleAfterValue": "2000003", 240 "UMask": "0x30" 241 }, 242 { 243 "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .", 244 "Counter": "0,1,2,3", 245 "CounterHTOff": "0,1,2,3", 246 "EventCode": "0x9C", 247 "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", 248 "PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.", 249 "SampleAfterValue": "2000003", 250 "UMask": "0x1" 251 }, 252 { 253 "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", 254 "Counter": "0,1,2,3", 255 "CounterHTOff": "0,1,2,3", 256 "CounterMask": "4", 257 "EventCode": "0x9C", 258 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", 259 "SampleAfterValue": "2000003", 260 "UMask": "0x1" 261 }, 262 { 263 "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", 264 "Counter": "0,1,2,3", 265 "CounterHTOff": "0,1,2,3", 266 "CounterMask": "1", 267 "EventCode": "0x9C", 268 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", 269 "Invert": "1", 270 "SampleAfterValue": "2000003", 271 "UMask": "0x1" 272 }, 273 { 274 "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.", 275 "Counter": "0,1,2,3", 276 "CounterHTOff": "0,1,2,3", 277 "CounterMask": "4", 278 "EventCode": "0x9C", 279 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE", 280 "Invert": "1", 281 "SampleAfterValue": "2000003", 282 "UMask": "0x1" 283 }, 284 { 285 "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", 286 "Counter": "0,1,2,3", 287 "CounterHTOff": "0,1,2,3", 288 "CounterMask": "3", 289 "EventCode": "0x9C", 290 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", 291 "SampleAfterValue": "2000003", 292 "UMask": "0x1" 293 }, 294 { 295 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", 296 "Counter": "0,1,2,3", 297 "CounterHTOff": "0,1,2,3", 298 "CounterMask": "2", 299 "EventCode": "0x9C", 300 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", 301 "SampleAfterValue": "2000003", 302 "UMask": "0x1" 303 }, 304 { 305 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", 306 "Counter": "0,1,2,3", 307 "CounterHTOff": "0,1,2,3", 308 "CounterMask": "1", 309 "EventCode": "0x9C", 310 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", 311 "SampleAfterValue": "2000003", 312 "UMask": "0x1" 313 } 314]