memory.json (16403B)
1[ 2 { 3 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0xC3", 7 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 8 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", 9 "SampleAfterValue": "100003", 10 "UMask": "0x2" 11 }, 12 { 13 "BriefDescription": "Loads with latency value being above 128.", 14 "Counter": "3", 15 "CounterHTOff": "3", 16 "EventCode": "0xCD", 17 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 18 "MSRIndex": "0x3F6", 19 "MSRValue": "0x80", 20 "PEBS": "2", 21 "SampleAfterValue": "1009", 22 "TakenAlone": "1", 23 "UMask": "0x1" 24 }, 25 { 26 "BriefDescription": "Loads with latency value being above 16.", 27 "Counter": "3", 28 "CounterHTOff": "3", 29 "EventCode": "0xCD", 30 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 31 "MSRIndex": "0x3F6", 32 "MSRValue": "0x10", 33 "PEBS": "2", 34 "SampleAfterValue": "20011", 35 "TakenAlone": "1", 36 "UMask": "0x1" 37 }, 38 { 39 "BriefDescription": "Loads with latency value being above 256.", 40 "Counter": "3", 41 "CounterHTOff": "3", 42 "EventCode": "0xCD", 43 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 44 "MSRIndex": "0x3F6", 45 "MSRValue": "0x100", 46 "PEBS": "2", 47 "SampleAfterValue": "503", 48 "TakenAlone": "1", 49 "UMask": "0x1" 50 }, 51 { 52 "BriefDescription": "Loads with latency value being above 32.", 53 "Counter": "3", 54 "CounterHTOff": "3", 55 "EventCode": "0xCD", 56 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 57 "MSRIndex": "0x3F6", 58 "MSRValue": "0x20", 59 "PEBS": "2", 60 "SampleAfterValue": "100007", 61 "TakenAlone": "1", 62 "UMask": "0x1" 63 }, 64 { 65 "BriefDescription": "Loads with latency value being above 4 .", 66 "Counter": "3", 67 "CounterHTOff": "3", 68 "EventCode": "0xCD", 69 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 70 "MSRIndex": "0x3F6", 71 "MSRValue": "0x4", 72 "PEBS": "2", 73 "SampleAfterValue": "100003", 74 "TakenAlone": "1", 75 "UMask": "0x1" 76 }, 77 { 78 "BriefDescription": "Loads with latency value being above 512.", 79 "Counter": "3", 80 "CounterHTOff": "3", 81 "EventCode": "0xCD", 82 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 83 "MSRIndex": "0x3F6", 84 "MSRValue": "0x200", 85 "PEBS": "2", 86 "SampleAfterValue": "101", 87 "TakenAlone": "1", 88 "UMask": "0x1" 89 }, 90 { 91 "BriefDescription": "Loads with latency value being above 64.", 92 "Counter": "3", 93 "CounterHTOff": "3", 94 "EventCode": "0xCD", 95 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 96 "MSRIndex": "0x3F6", 97 "MSRValue": "0x40", 98 "PEBS": "2", 99 "SampleAfterValue": "2003", 100 "TakenAlone": "1", 101 "UMask": "0x1" 102 }, 103 { 104 "BriefDescription": "Loads with latency value being above 8.", 105 "Counter": "3", 106 "CounterHTOff": "3", 107 "EventCode": "0xCD", 108 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 109 "MSRIndex": "0x3F6", 110 "MSRValue": "0x8", 111 "PEBS": "2", 112 "SampleAfterValue": "50021", 113 "TakenAlone": "1", 114 "UMask": "0x1" 115 }, 116 { 117 "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", 118 "Counter": "3", 119 "CounterHTOff": "3", 120 "EventCode": "0xCD", 121 "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", 122 "PEBS": "2", 123 "PRECISE_STORE": "1", 124 "SampleAfterValue": "2000003", 125 "TakenAlone": "1", 126 "UMask": "0x2" 127 }, 128 { 129 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", 130 "Counter": "0,1,2,3", 131 "CounterHTOff": "0,1,2,3,4,5,6,7", 132 "EventCode": "0x05", 133 "EventName": "MISALIGN_MEM_REF.LOADS", 134 "SampleAfterValue": "2000003", 135 "UMask": "0x1" 136 }, 137 { 138 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", 139 "Counter": "0,1,2,3", 140 "CounterHTOff": "0,1,2,3,4,5,6,7", 141 "EventCode": "0x05", 142 "EventName": "MISALIGN_MEM_REF.STORES", 143 "SampleAfterValue": "2000003", 144 "UMask": "0x2" 145 }, 146 { 147 "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.", 148 "Counter": "0,1,2,3", 149 "CounterHTOff": "0,1,2,3", 150 "EventCode": "0xB7, 0xBB", 151 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", 152 "MSRIndex": "0x1a6,0x1a7", 153 "MSRValue": "0x300400244", 154 "Offcore": "1", 155 "SampleAfterValue": "100003", 156 "UMask": "0x1" 157 }, 158 { 159 "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.", 160 "Counter": "0,1,2,3", 161 "CounterHTOff": "0,1,2,3", 162 "EventCode": "0xB7, 0xBB", 163 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", 164 "MSRIndex": "0x1a6,0x1a7", 165 "MSRValue": "0x300400091", 166 "Offcore": "1", 167 "SampleAfterValue": "100003", 168 "UMask": "0x1" 169 }, 170 { 171 "BriefDescription": "Counts all prefetch code reads that miss the LLC and the data returned from dram.", 172 "Counter": "0,1,2,3", 173 "CounterHTOff": "0,1,2,3", 174 "EventCode": "0xB7, 0xBB", 175 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM", 176 "MSRIndex": "0x1a6,0x1a7", 177 "MSRValue": "0x300400240", 178 "Offcore": "1", 179 "SampleAfterValue": "100003", 180 "UMask": "0x1" 181 }, 182 { 183 "BriefDescription": "Counts all prefetch data reads that miss the LLC and the data returned from dram.", 184 "Counter": "0,1,2,3", 185 "CounterHTOff": "0,1,2,3", 186 "EventCode": "0xB7, 0xBB", 187 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM", 188 "MSRIndex": "0x1a6,0x1a7", 189 "MSRValue": "0x300400090", 190 "Offcore": "1", 191 "SampleAfterValue": "100003", 192 "UMask": "0x1" 193 }, 194 { 195 "BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.", 196 "Counter": "0,1,2,3", 197 "CounterHTOff": "0,1,2,3", 198 "EventCode": "0xB7, 0xBB", 199 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM", 200 "MSRIndex": "0x1a6,0x1a7", 201 "MSRValue": "0x300400120", 202 "Offcore": "1", 203 "SampleAfterValue": "100003", 204 "UMask": "0x1" 205 }, 206 { 207 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram.", 208 "Counter": "0,1,2,3", 209 "CounterHTOff": "0,1,2,3", 210 "EventCode": "0xB7, 0xBB", 211 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", 212 "MSRIndex": "0x1a6,0x1a7", 213 "MSRValue": "0x3004003f7", 214 "Offcore": "1", 215 "SampleAfterValue": "100003", 216 "UMask": "0x1" 217 }, 218 { 219 "BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram.", 220 "Counter": "0,1,2,3", 221 "CounterHTOff": "0,1,2,3", 222 "EventCode": "0xB7, 0xBB", 223 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM", 224 "MSRIndex": "0x1a6,0x1a7", 225 "MSRValue": "0x300400122", 226 "Offcore": "1", 227 "SampleAfterValue": "100003", 228 "UMask": "0x1" 229 }, 230 { 231 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 232 "Counter": "0,1,2,3", 233 "CounterHTOff": "0,1,2,3", 234 "EventCode": "0xB7, 0xBB", 235 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM", 236 "MSRIndex": "0x1a6,0x1a7", 237 "MSRValue": "0x1f80408fff", 238 "Offcore": "1", 239 "PublicDescription": "This event counts any requests that miss the LLC where the data was returned from local DRAM", 240 "SampleAfterValue": "100003", 241 "UMask": "0x1" 242 }, 243 { 244 "BriefDescription": "Counts LLC replacements.", 245 "Counter": "0,1,2,3", 246 "CounterHTOff": "0,1,2,3", 247 "EventCode": "0xB7, 0xBB", 248 "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", 249 "MSRIndex": "0x1a6,0x1a7", 250 "MSRValue": "0x6004001b3", 251 "Offcore": "1", 252 "PublicDescription": "This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM", 253 "SampleAfterValue": "100003", 254 "UMask": "0x1" 255 }, 256 { 257 "BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT", 258 "Counter": "0,1,2,3", 259 "CounterHTOff": "0,1,2,3", 260 "EventCode": "0xB7, 0xBB", 261 "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT", 262 "MSRIndex": "0x1a6,0x1a7", 263 "MSRValue": "0x17004001b3", 264 "Offcore": "1", 265 "SampleAfterValue": "100003", 266 "UMask": "0x1" 267 }, 268 { 269 "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.", 270 "Counter": "0,1,2,3", 271 "CounterHTOff": "0,1,2,3", 272 "EventCode": "0xB7, 0xBB", 273 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", 274 "MSRIndex": "0x1a6,0x1a7", 275 "MSRValue": "0x300400004", 276 "Offcore": "1", 277 "SampleAfterValue": "100003", 278 "UMask": "0x1" 279 }, 280 { 281 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.", 282 "Counter": "0,1,2,3", 283 "CounterHTOff": "0,1,2,3", 284 "EventCode": "0xB7, 0xBB", 285 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", 286 "MSRIndex": "0x1a6,0x1a7", 287 "MSRValue": "0x300400001", 288 "Offcore": "1", 289 "SampleAfterValue": "100003", 290 "UMask": "0x1" 291 }, 292 { 293 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 294 "Counter": "0,1,2,3", 295 "CounterHTOff": "0,1,2,3", 296 "EventCode": "0xB7, 0xBB", 297 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM", 298 "MSRIndex": "0x1a6,0x1a7", 299 "MSRValue": "0x1f80400004", 300 "Offcore": "1", 301 "SampleAfterValue": "100003", 302 "UMask": "0x1" 303 }, 304 { 305 "BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.", 306 "Counter": "0,1,2,3", 307 "CounterHTOff": "0,1,2,3", 308 "EventCode": "0xB7, 0xBB", 309 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM", 310 "MSRIndex": "0x1a6,0x1a7", 311 "MSRValue": "0x300400002", 312 "Offcore": "1", 313 "SampleAfterValue": "100003", 314 "UMask": "0x1" 315 }, 316 { 317 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 318 "Counter": "0,1,2,3", 319 "CounterHTOff": "0,1,2,3", 320 "EventCode": "0xB7, 0xBB", 321 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM", 322 "MSRIndex": "0x1a6,0x1a7", 323 "MSRValue": "0x1f80400010", 324 "Offcore": "1", 325 "SampleAfterValue": "100003", 326 "UMask": "0x1" 327 }, 328 { 329 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 330 "Counter": "0,1,2,3", 331 "CounterHTOff": "0,1,2,3", 332 "EventCode": "0xB7, 0xBB", 333 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM", 334 "MSRIndex": "0x1a6,0x1a7", 335 "MSRValue": "0x1f80400040", 336 "Offcore": "1", 337 "SampleAfterValue": "100003", 338 "UMask": "0x1" 339 }, 340 { 341 "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram.", 342 "Counter": "0,1,2,3", 343 "CounterHTOff": "0,1,2,3", 344 "EventCode": "0xB7, 0xBB", 345 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM", 346 "MSRIndex": "0x1a6,0x1a7", 347 "MSRValue": "0x300400040", 348 "Offcore": "1", 349 "SampleAfterValue": "100003", 350 "UMask": "0x1" 351 }, 352 { 353 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.", 354 "Counter": "0,1,2,3", 355 "CounterHTOff": "0,1,2,3", 356 "EventCode": "0xB7, 0xBB", 357 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM", 358 "MSRIndex": "0x1a6,0x1a7", 359 "MSRValue": "0x300400010", 360 "Offcore": "1", 361 "SampleAfterValue": "100003", 362 "UMask": "0x1" 363 }, 364 { 365 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram.", 366 "Counter": "0,1,2,3", 367 "CounterHTOff": "0,1,2,3", 368 "EventCode": "0xB7, 0xBB", 369 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM", 370 "MSRIndex": "0x1a6,0x1a7", 371 "MSRValue": "0x300400020", 372 "Offcore": "1", 373 "SampleAfterValue": "100003", 374 "UMask": "0x1" 375 }, 376 { 377 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram.", 378 "Counter": "0,1,2,3", 379 "CounterHTOff": "0,1,2,3", 380 "EventCode": "0xB7, 0xBB", 381 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM", 382 "MSRIndex": "0x1a6,0x1a7", 383 "MSRValue": "0x300400200", 384 "Offcore": "1", 385 "SampleAfterValue": "100003", 386 "UMask": "0x1" 387 }, 388 { 389 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram.", 390 "Counter": "0,1,2,3", 391 "CounterHTOff": "0,1,2,3", 392 "EventCode": "0xB7, 0xBB", 393 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM", 394 "MSRIndex": "0x1a6,0x1a7", 395 "MSRValue": "0x300400080", 396 "Offcore": "1", 397 "SampleAfterValue": "100003", 398 "UMask": "0x1" 399 }, 400 { 401 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram.", 402 "Counter": "0,1,2,3", 403 "CounterHTOff": "0,1,2,3", 404 "EventCode": "0xB7, 0xBB", 405 "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM", 406 "MSRIndex": "0x1a6,0x1a7", 407 "MSRValue": "0x300400100", 408 "Offcore": "1", 409 "SampleAfterValue": "100003", 410 "UMask": "0x1" 411 }, 412 { 413 "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 414 "Counter": "0,1,2,3", 415 "CounterHTOff": "0,1,2,3", 416 "EventCode": "0xB7, 0xBB", 417 "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM", 418 "MSRIndex": "0x1a6,0x1a7", 419 "MSRValue": "0x1f80400080", 420 "Offcore": "1", 421 "SampleAfterValue": "100003", 422 "UMask": "0x1" 423 }, 424 { 425 "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 426 "Counter": "0,1,2,3", 427 "CounterHTOff": "0,1,2,3", 428 "EventCode": "0xB7, 0xBB", 429 "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM", 430 "MSRIndex": "0x1a6,0x1a7", 431 "MSRValue": "0x1f80400200", 432 "Offcore": "1", 433 "SampleAfterValue": "100003", 434 "UMask": "0x1" 435 }, 436 { 437 "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.", 438 "Counter": "0,1,2,3", 439 "CounterHTOff": "0,1,2,3,4,5,6,7", 440 "EventCode": "0xBE", 441 "EventName": "PAGE_WALKS.LLC_MISS", 442 "SampleAfterValue": "100003", 443 "UMask": "0x1" 444 } 445]