frontend.json (26236B)
1[ 2 { 3 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0xE6", 7 "EventName": "BACLEARS.ANY", 8 "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", 9 "SampleAfterValue": "100003", 10 "UMask": "0x1" 11 }, 12 { 13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 14 "Counter": "0,1,2,3", 15 "CounterHTOff": "0,1,2,3,4,5,6,7", 16 "EventCode": "0xAB", 17 "EventName": "DSB2MITE_SWITCHES.COUNT", 18 "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.", 19 "SampleAfterValue": "2000003", 20 "UMask": "0x1" 21 }, 22 { 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 24 "Counter": "0,1,2,3", 25 "CounterHTOff": "0,1,2,3,4,5,6,7", 26 "EventCode": "0xAB", 27 "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", 28 "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", 29 "SampleAfterValue": "2000003", 30 "UMask": "0x2" 31 }, 32 { 33 "BriefDescription": "Retired Instructions who experienced DSB miss.", 34 "Counter": "0,1,2,3", 35 "CounterHTOff": "0,1,2,3", 36 "EventCode": "0xC6", 37 "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", 38 "MSRIndex": "0x3F7", 39 "MSRValue": "0x1", 40 "PEBS": "1", 41 "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 42 "SampleAfterValue": "100007", 43 "TakenAlone": "1", 44 "UMask": "0x1" 45 }, 46 { 47 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 48 "Counter": "0,1,2,3", 49 "CounterHTOff": "0,1,2,3", 50 "EventCode": "0xC6", 51 "EventName": "FRONTEND_RETIRED.DSB_MISS", 52 "MSRIndex": "0x3F7", 53 "MSRValue": "0x11", 54 "PEBS": "1", 55 "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.", 56 "SampleAfterValue": "100007", 57 "TakenAlone": "1", 58 "UMask": "0x1" 59 }, 60 { 61 "BriefDescription": "Retired Instructions who experienced iTLB true miss.", 62 "Counter": "0,1,2,3", 63 "CounterHTOff": "0,1,2,3", 64 "EventCode": "0xC6", 65 "EventName": "FRONTEND_RETIRED.ITLB_MISS", 66 "MSRIndex": "0x3F7", 67 "MSRValue": "0x14", 68 "PEBS": "1", 69 "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", 70 "SampleAfterValue": "100007", 71 "TakenAlone": "1", 72 "UMask": "0x1" 73 }, 74 { 75 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 76 "Counter": "0,1,2,3", 77 "CounterHTOff": "0,1,2,3", 78 "EventCode": "0xC6", 79 "EventName": "FRONTEND_RETIRED.L1I_MISS", 80 "MSRIndex": "0x3F7", 81 "MSRValue": "0x12", 82 "PEBS": "1", 83 "SampleAfterValue": "100007", 84 "TakenAlone": "1", 85 "UMask": "0x1" 86 }, 87 { 88 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", 89 "Counter": "0,1,2,3", 90 "CounterHTOff": "0,1,2,3", 91 "EventCode": "0xC6", 92 "EventName": "FRONTEND_RETIRED.L2_MISS", 93 "MSRIndex": "0x3F7", 94 "MSRValue": "0x13", 95 "PEBS": "1", 96 "SampleAfterValue": "100007", 97 "TakenAlone": "1", 98 "UMask": "0x1" 99 }, 100 { 101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 102 "Counter": "0,1,2,3", 103 "CounterHTOff": "0,1,2,3", 104 "EventCode": "0xc6", 105 "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", 106 "MSRIndex": "0x3F7", 107 "MSRValue": "0x400106", 108 "PEBS": "2", 109 "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.", 110 "SampleAfterValue": "100007", 111 "TakenAlone": "1", 112 "UMask": "0x1" 113 }, 114 { 115 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", 116 "Counter": "0,1,2,3", 117 "CounterHTOff": "0,1,2,3", 118 "EventCode": "0xC6", 119 "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", 120 "MSRIndex": "0x3F7", 121 "MSRValue": "0x408006", 122 "PEBS": "1", 123 "SampleAfterValue": "100007", 124 "TakenAlone": "1", 125 "UMask": "0x1" 126 }, 127 { 128 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", 129 "Counter": "0,1,2,3", 130 "CounterHTOff": "0,1,2,3", 131 "EventCode": "0xC6", 132 "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", 133 "MSRIndex": "0x3F7", 134 "MSRValue": "0x401006", 135 "PEBS": "1", 136 "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", 137 "SampleAfterValue": "100007", 138 "TakenAlone": "1", 139 "UMask": "0x1" 140 }, 141 { 142 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.", 143 "Counter": "0,1,2,3", 144 "CounterHTOff": "0,1,2,3", 145 "EventCode": "0xC6", 146 "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", 147 "MSRIndex": "0x3F7", 148 "MSRValue": "0x400206", 149 "PEBS": "1", 150 "SampleAfterValue": "100007", 151 "TakenAlone": "1", 152 "UMask": "0x1" 153 }, 154 { 155 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", 156 "Counter": "0,1,2,3", 157 "CounterHTOff": "0,1,2,3", 158 "EventCode": "0xC6", 159 "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", 160 "MSRIndex": "0x3F7", 161 "MSRValue": "0x410006", 162 "PEBS": "1", 163 "SampleAfterValue": "100007", 164 "TakenAlone": "1", 165 "UMask": "0x1" 166 }, 167 { 168 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", 169 "Counter": "0,1,2,3", 170 "CounterHTOff": "0,1,2,3", 171 "EventCode": "0xC6", 172 "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", 173 "MSRIndex": "0x3F7", 174 "MSRValue": "0x100206", 175 "PEBS": "1", 176 "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", 177 "SampleAfterValue": "100007", 178 "TakenAlone": "1", 179 "UMask": "0x1" 180 }, 181 { 182 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", 183 "Counter": "0,1,2,3", 184 "CounterHTOff": "0,1,2,3", 185 "EventCode": "0xC6", 186 "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2", 187 "MSRIndex": "0x3F7", 188 "MSRValue": "0x200206", 189 "PEBS": "1", 190 "SampleAfterValue": "100007", 191 "TakenAlone": "1", 192 "UMask": "0x1" 193 }, 194 { 195 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", 196 "Counter": "0,1,2,3", 197 "CounterHTOff": "0,1,2,3", 198 "EventCode": "0xC6", 199 "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3", 200 "MSRIndex": "0x3F7", 201 "MSRValue": "0x300206", 202 "PEBS": "1", 203 "SampleAfterValue": "100007", 204 "TakenAlone": "1", 205 "UMask": "0x1" 206 }, 207 { 208 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", 209 "Counter": "0,1,2,3", 210 "CounterHTOff": "0,1,2,3", 211 "EventCode": "0xC6", 212 "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", 213 "MSRIndex": "0x3F7", 214 "MSRValue": "0x402006", 215 "PEBS": "1", 216 "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", 217 "SampleAfterValue": "100007", 218 "TakenAlone": "1", 219 "UMask": "0x1" 220 }, 221 { 222 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", 223 "Counter": "0,1,2,3", 224 "CounterHTOff": "0,1,2,3", 225 "EventCode": "0xC6", 226 "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", 227 "MSRIndex": "0x3F7", 228 "MSRValue": "0x400406", 229 "PEBS": "1", 230 "SampleAfterValue": "100007", 231 "TakenAlone": "1", 232 "UMask": "0x1" 233 }, 234 { 235 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", 236 "Counter": "0,1,2,3", 237 "CounterHTOff": "0,1,2,3", 238 "EventCode": "0xC6", 239 "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", 240 "MSRIndex": "0x3F7", 241 "MSRValue": "0x420006", 242 "PEBS": "1", 243 "SampleAfterValue": "100007", 244 "TakenAlone": "1", 245 "UMask": "0x1" 246 }, 247 { 248 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", 249 "Counter": "0,1,2,3", 250 "CounterHTOff": "0,1,2,3", 251 "EventCode": "0xC6", 252 "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", 253 "MSRIndex": "0x3F7", 254 "MSRValue": "0x404006", 255 "PEBS": "1", 256 "SampleAfterValue": "100007", 257 "TakenAlone": "1", 258 "UMask": "0x1" 259 }, 260 { 261 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", 262 "Counter": "0,1,2,3", 263 "CounterHTOff": "0,1,2,3", 264 "EventCode": "0xC6", 265 "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", 266 "MSRIndex": "0x3F7", 267 "MSRValue": "0x400806", 268 "PEBS": "1", 269 "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", 270 "SampleAfterValue": "100007", 271 "TakenAlone": "1", 272 "UMask": "0x1" 273 }, 274 { 275 "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", 276 "Counter": "0,1,2,3", 277 "CounterHTOff": "0,1,2,3", 278 "EventCode": "0xC6", 279 "EventName": "FRONTEND_RETIRED.STLB_MISS", 280 "MSRIndex": "0x3F7", 281 "MSRValue": "0x15", 282 "PEBS": "1", 283 "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", 284 "SampleAfterValue": "100007", 285 "TakenAlone": "1", 286 "UMask": "0x1" 287 }, 288 { 289 "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", 290 "Counter": "0,1,2,3", 291 "CounterHTOff": "0,1,2,3,4,5,6,7", 292 "EventCode": "0x80", 293 "EventName": "ICACHE_16B.IFDATA_STALL", 294 "PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.", 295 "SampleAfterValue": "2000003", 296 "UMask": "0x4" 297 }, 298 { 299 "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", 300 "Counter": "0,1,2,3", 301 "CounterHTOff": "0,1,2,3,4,5,6,7", 302 "EventCode": "0x83", 303 "EventName": "ICACHE_64B.IFTAG_HIT", 304 "SampleAfterValue": "200003", 305 "UMask": "0x1" 306 }, 307 { 308 "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", 309 "Counter": "0,1,2,3", 310 "CounterHTOff": "0,1,2,3,4,5,6,7", 311 "EventCode": "0x83", 312 "EventName": "ICACHE_64B.IFTAG_MISS", 313 "SampleAfterValue": "200003", 314 "UMask": "0x2" 315 }, 316 { 317 "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", 318 "Counter": "0,1,2,3", 319 "CounterHTOff": "0,1,2,3,4,5,6,7", 320 "EventCode": "0x83", 321 "EventName": "ICACHE_64B.IFTAG_STALL", 322 "SampleAfterValue": "200003", 323 "UMask": "0x4" 324 }, 325 { 326 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 327 "Counter": "0,1,2,3", 328 "CounterHTOff": "0,1,2,3,4,5,6,7", 329 "CounterMask": "4", 330 "EventCode": "0x79", 331 "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", 332 "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.", 333 "SampleAfterValue": "2000003", 334 "UMask": "0x18" 335 }, 336 { 337 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 338 "Counter": "0,1,2,3", 339 "CounterHTOff": "0,1,2,3,4,5,6,7", 340 "CounterMask": "1", 341 "EventCode": "0x79", 342 "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", 343 "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.", 344 "SampleAfterValue": "2000003", 345 "UMask": "0x18" 346 }, 347 { 348 "BriefDescription": "Cycles MITE is delivering 4 Uops", 349 "Counter": "0,1,2,3", 350 "CounterHTOff": "0,1,2,3,4,5,6,7", 351 "CounterMask": "4", 352 "EventCode": "0x79", 353 "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", 354 "PublicDescription": "Counts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", 355 "SampleAfterValue": "2000003", 356 "UMask": "0x24" 357 }, 358 { 359 "BriefDescription": "Cycles MITE is delivering any Uop", 360 "Counter": "0,1,2,3", 361 "CounterHTOff": "0,1,2,3,4,5,6,7", 362 "CounterMask": "1", 363 "EventCode": "0x79", 364 "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", 365 "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", 366 "SampleAfterValue": "2000003", 367 "UMask": "0x24" 368 }, 369 { 370 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 371 "Counter": "0,1,2,3", 372 "CounterHTOff": "0,1,2,3,4,5,6,7", 373 "CounterMask": "1", 374 "EventCode": "0x79", 375 "EventName": "IDQ.DSB_CYCLES", 376 "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.", 377 "SampleAfterValue": "2000003", 378 "UMask": "0x8" 379 }, 380 { 381 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 382 "Counter": "0,1,2,3", 383 "CounterHTOff": "0,1,2,3,4,5,6,7", 384 "EventCode": "0x79", 385 "EventName": "IDQ.DSB_UOPS", 386 "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.", 387 "SampleAfterValue": "2000003", 388 "UMask": "0x8" 389 }, 390 { 391 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", 392 "Counter": "0,1,2,3", 393 "CounterHTOff": "0,1,2,3,4,5,6,7", 394 "CounterMask": "1", 395 "EventCode": "0x79", 396 "EventName": "IDQ.MITE_CYCLES", 397 "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ.", 398 "SampleAfterValue": "2000003", 399 "UMask": "0x4" 400 }, 401 { 402 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 403 "Counter": "0,1,2,3", 404 "CounterHTOff": "0,1,2,3,4,5,6,7", 405 "EventCode": "0x79", 406 "EventName": "IDQ.MITE_UOPS", 407 "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 408 "SampleAfterValue": "2000003", 409 "UMask": "0x4" 410 }, 411 { 412 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 413 "Counter": "0,1,2,3", 414 "CounterHTOff": "0,1,2,3,4,5,6,7", 415 "CounterMask": "1", 416 "EventCode": "0x79", 417 "EventName": "IDQ.MS_CYCLES", 418 "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", 419 "SampleAfterValue": "2000003", 420 "UMask": "0x30" 421 }, 422 { 423 "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 424 "Counter": "0,1,2,3", 425 "CounterHTOff": "0,1,2,3,4,5,6,7", 426 "CounterMask": "1", 427 "EventCode": "0x79", 428 "EventName": "IDQ.MS_DSB_CYCLES", 429 "PublicDescription": "Counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", 430 "SampleAfterValue": "2000003", 431 "UMask": "0x10" 432 }, 433 { 434 "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 435 "Counter": "0,1,2,3", 436 "CounterHTOff": "0,1,2,3,4,5,6,7", 437 "EventCode": "0x79", 438 "EventName": "IDQ.MS_MITE_UOPS", 439 "PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", 440 "SampleAfterValue": "2000003", 441 "UMask": "0x20" 442 }, 443 { 444 "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", 445 "Counter": "0,1,2,3", 446 "CounterHTOff": "0,1,2,3,4,5,6,7", 447 "CounterMask": "1", 448 "EdgeDetect": "1", 449 "EventCode": "0x79", 450 "EventName": "IDQ.MS_SWITCHES", 451 "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", 452 "SampleAfterValue": "2000003", 453 "UMask": "0x30" 454 }, 455 { 456 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 457 "Counter": "0,1,2,3", 458 "CounterHTOff": "0,1,2,3,4,5,6,7", 459 "EventCode": "0x79", 460 "EventName": "IDQ.MS_UOPS", 461 "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.", 462 "SampleAfterValue": "2000003", 463 "UMask": "0x30" 464 }, 465 { 466 "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", 467 "Counter": "0,1,2,3", 468 "CounterHTOff": "0,1,2,3,4,5,6,7", 469 "EventCode": "0x9C", 470 "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", 471 "PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.", 472 "SampleAfterValue": "2000003", 473 "UMask": "0x1" 474 }, 475 { 476 "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", 477 "Counter": "0,1,2,3", 478 "CounterHTOff": "0,1,2,3,4,5,6,7", 479 "CounterMask": "4", 480 "EventCode": "0x9C", 481 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", 482 "PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", 483 "SampleAfterValue": "2000003", 484 "UMask": "0x1" 485 }, 486 { 487 "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", 488 "Counter": "0,1,2,3", 489 "CounterHTOff": "0,1,2,3,4,5,6,7", 490 "CounterMask": "1", 491 "EventCode": "0x9C", 492 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", 493 "Invert": "1", 494 "SampleAfterValue": "2000003", 495 "UMask": "0x1" 496 }, 497 { 498 "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", 499 "Counter": "0,1,2,3", 500 "CounterHTOff": "0,1,2,3,4,5,6,7", 501 "CounterMask": "3", 502 "EventCode": "0x9C", 503 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", 504 "PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3.", 505 "SampleAfterValue": "2000003", 506 "UMask": "0x1" 507 }, 508 { 509 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", 510 "Counter": "0,1,2,3", 511 "CounterHTOff": "0,1,2,3,4,5,6,7", 512 "CounterMask": "2", 513 "EventCode": "0x9C", 514 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", 515 "PublicDescription": "Cycles with less than 2 uops delivered by the front-end.", 516 "SampleAfterValue": "2000003", 517 "UMask": "0x1" 518 }, 519 { 520 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", 521 "Counter": "0,1,2,3", 522 "CounterHTOff": "0,1,2,3,4,5,6,7", 523 "CounterMask": "1", 524 "EventCode": "0x9C", 525 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", 526 "PublicDescription": "Cycles with less than 3 uops delivered by the front-end.", 527 "SampleAfterValue": "2000003", 528 "UMask": "0x1" 529 } 530]