cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

other.json (3942B)

      1[
      2    {
      3        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
      4        "Counter": "0,1,2,3",
      5        "CounterHTOff": "0,1,2,3,4,5,6,7",
      6        "EventCode": "0x28",
      7        "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
      8        "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
      9        "SampleAfterValue": "200003",
     10        "UMask": "0x7"
     11    },
     12    {
     13        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
     14        "Counter": "0,1,2,3",
     15        "CounterHTOff": "0,1,2,3,4,5,6,7",
     16        "EventCode": "0x28",
     17        "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
     18        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
     19        "SampleAfterValue": "200003",
     20        "UMask": "0x18"
     21    },
     22    {
     23        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
     24        "Counter": "0,1,2,3",
     25        "CounterHTOff": "0,1,2,3,4,5,6,7",
     26        "EventCode": "0x28",
     27        "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
     28        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture).  This includes high current AVX 512-bit instructions.",
     29        "SampleAfterValue": "200003",
     30        "UMask": "0x20"
     31    },
     32    {
     33        "BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
     34        "Counter": "0,1,2,3",
     35        "CounterHTOff": "0,1,2,3,4,5,6,7",
     36        "EventCode": "0x28",
     37        "EventName": "CORE_POWER.THROTTLE",
     38        "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
     39        "SampleAfterValue": "200003",
     40        "UMask": "0x40"
     41    },
     42    {
     43        "BriefDescription": "Number of hardware interrupts received by the processor.",
     44        "Counter": "0,1,2,3",
     45        "CounterHTOff": "0,1,2,3,4,5,6,7",
     46        "EventCode": "0xCB",
     47        "EventName": "HW_INTERRUPTS.RECEIVED",
     48        "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
     49        "SampleAfterValue": "203",
     50        "UMask": "0x1"
     51    },
     52    {
     53        "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
     54        "Counter": "0,1,2,3",
     55        "CounterHTOff": "0,1,2,3,4,5,6,7",
     56        "EventCode": "0xFE",
     57        "EventName": "IDI_MISC.WB_DOWNGRADE",
     58        "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
     59        "SampleAfterValue": "100003",
     60        "UMask": "0x4"
     61    },
     62    {
     63        "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",
     64        "Counter": "0,1,2,3",
     65        "CounterHTOff": "0,1,2,3,4,5,6,7",
     66        "EventCode": "0xFE",
     67        "EventName": "IDI_MISC.WB_UPGRADE",
     68        "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",
     69        "SampleAfterValue": "100003",
     70        "UMask": "0x2"
     71    },
     72    {
     73        "Counter": "0,1,2,3",
     74        "CounterHTOff": "0,1,2,3,4,5,6,7",
     75        "EventCode": "0x09",
     76        "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
     77        "SampleAfterValue": "2000003",
     78        "UMask": "0x1"
     79    }
     80]