tgl-metrics.json (10909B)
1[ 2 { 3 "BriefDescription": "Instructions Per Cycle (per Logical Processor)", 4 "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", 5 "MetricGroup": "Summary", 6 "MetricName": "IPC" 7 }, 8 { 9 "BriefDescription": "Instruction per taken branch", 10 "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", 11 "MetricGroup": "Branches;FetchBW;PGO", 12 "MetricName": "IpTB" 13 }, 14 { 15 "BriefDescription": "Cycles Per Instruction (per Logical Processor)", 16 "MetricExpr": "1 / IPC", 17 "MetricGroup": "Pipeline", 18 "MetricName": "CPI" 19 }, 20 { 21 "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", 22 "MetricExpr": "CPU_CLK_UNHALTED.THREAD", 23 "MetricGroup": "Pipeline", 24 "MetricName": "CLKS" 25 }, 26 { 27 "BriefDescription": "Instructions Per Cycle (per physical core)", 28 "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.DISTRIBUTED", 29 "MetricGroup": "SMT;TmaL1", 30 "MetricName": "CoreIPC" 31 }, 32 { 33 "BriefDescription": "Floating Point Operations Per Cycle", 34 "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED", 35 "MetricGroup": "Flops", 36 "MetricName": "FLOPc" 37 }, 38 { 39 "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", 40 "MetricExpr": "UOPS_EXECUTED.THREAD / ( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 )", 41 "MetricGroup": "Pipeline;PortsUtil", 42 "MetricName": "ILP" 43 }, 44 { 45 "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", 46 "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", 47 "MetricGroup": "BrMispredicts", 48 "MetricName": "IpMispredict" 49 }, 50 { 51 "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", 52 "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", 53 "MetricGroup": "SMT", 54 "MetricName": "CORE_CLKS" 55 }, 56 { 57 "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", 58 "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", 59 "MetricGroup": "InsType", 60 "MetricName": "IpLoad" 61 }, 62 { 63 "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", 64 "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", 65 "MetricGroup": "InsType", 66 "MetricName": "IpStore" 67 }, 68 { 69 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", 70 "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", 71 "MetricGroup": "Branches;InsType", 72 "MetricName": "IpBranch" 73 }, 74 { 75 "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", 76 "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", 77 "MetricGroup": "Branches", 78 "MetricName": "IpCall" 79 }, 80 { 81 "BriefDescription": "Branch instructions per taken branch. ", 82 "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", 83 "MetricGroup": "Branches;PGO", 84 "MetricName": "BpTkBranch" 85 }, 86 { 87 "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", 88 "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", 89 "MetricGroup": "Flops;FpArith;InsType", 90 "MetricName": "IpFLOP" 91 }, 92 { 93 "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", 94 "MetricExpr": "INST_RETIRED.ANY", 95 "MetricGroup": "Summary;TmaL1", 96 "MetricName": "Instructions" 97 }, 98 { 99 "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)", 100 "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", 101 "MetricGroup": "LSD", 102 "MetricName": "LSD_Coverage" 103 }, 104 { 105 "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", 106 "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", 107 "MetricGroup": "DSB;FetchBW", 108 "MetricName": "DSB_Coverage" 109 }, 110 { 111 "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", 112 "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )", 113 "MetricGroup": "MemoryBound;MemoryLat", 114 "MetricName": "Load_Miss_Real_Latency" 115 }, 116 { 117 "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", 118 "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", 119 "MetricGroup": "MemoryBound;MemoryBW", 120 "MetricName": "MLP" 121 }, 122 { 123 "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", 124 "MetricConstraint": "NO_NMI_WATCHDOG", 125 "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CORE_CLKS )", 126 "MetricGroup": "MemoryTLB", 127 "MetricName": "Page_Walks_Utilization" 128 }, 129 { 130 "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", 131 "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", 132 "MetricGroup": "MemoryBW", 133 "MetricName": "L1D_Cache_Fill_BW" 134 }, 135 { 136 "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", 137 "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", 138 "MetricGroup": "MemoryBW", 139 "MetricName": "L2_Cache_Fill_BW" 140 }, 141 { 142 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", 143 "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time", 144 "MetricGroup": "MemoryBW;Offcore", 145 "MetricName": "L3_Cache_Access_BW" 146 }, 147 { 148 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", 149 "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", 150 "MetricGroup": "CacheMisses", 151 "MetricName": "L1MPKI" 152 }, 153 { 154 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", 155 "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", 156 "MetricGroup": "CacheMisses", 157 "MetricName": "L2MPKI" 158 }, 159 { 160 "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", 161 "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", 162 "MetricGroup": "CacheMisses", 163 "MetricName": "L3MPKI" 164 }, 165 { 166 "BriefDescription": "Average CPU Utilization", 167 "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", 168 "MetricGroup": "HPC;Summary", 169 "MetricName": "CPU_Utilization" 170 }, 171 { 172 "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", 173 "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", 174 "MetricGroup": "Summary;Power", 175 "MetricName": "Average_Frequency" 176 }, 177 { 178 "BriefDescription": "Giga Floating Point Operations Per Second", 179 "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / 1000000000 ) / duration_time", 180 "MetricGroup": "Flops;HPC", 181 "MetricName": "GFLOPs" 182 }, 183 { 184 "BriefDescription": "Average Frequency Utilization relative nominal frequency", 185 "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", 186 "MetricGroup": "Power", 187 "MetricName": "Turbo_Utilization" 188 }, 189 { 190 "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", 191 "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED", 192 "MetricGroup": "SMT", 193 "MetricName": "SMT_2T_Utilization" 194 }, 195 { 196 "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", 197 "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", 198 "MetricGroup": "OS", 199 "MetricName": "Kernel_Utilization" 200 }, 201 { 202 "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", 203 "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", 204 "MetricGroup": "Branches;OS", 205 "MetricName": "IpFarBranch" 206 }, 207 { 208 "BriefDescription": "C6 residency percent per core", 209 "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", 210 "MetricGroup": "Power", 211 "MetricName": "C6_Core_Residency" 212 }, 213 { 214 "BriefDescription": "C7 residency percent per core", 215 "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", 216 "MetricGroup": "Power", 217 "MetricName": "C7_Core_Residency" 218 }, 219 { 220 "BriefDescription": "C6 residency percent per package", 221 "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", 222 "MetricGroup": "Power", 223 "MetricName": "C6_Pkg_Residency" 224 }, 225 { 226 "BriefDescription": "C7 residency percent per package", 227 "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", 228 "MetricGroup": "Power", 229 "MetricName": "C7_Pkg_Residency" 230 } 231]