cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

cache.json (109438B)

      1[
      2    {
      3        "BriefDescription": "Cycles L1D locked",
      4        "Counter": "0,1",
      5        "EventCode": "0x63",
      6        "EventName": "CACHE_LOCK_CYCLES.L1D",
      7        "SampleAfterValue": "2000000",
      8        "UMask": "0x2"
      9    },
     10    {
     11        "BriefDescription": "Cycles L1D and L2 locked",
     12        "Counter": "0,1",
     13        "EventCode": "0x63",
     14        "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
     15        "SampleAfterValue": "2000000",
     16        "UMask": "0x1"
     17    },
     18    {
     19        "BriefDescription": "L1D cache lines replaced in M state",
     20        "Counter": "0,1",
     21        "EventCode": "0x51",
     22        "EventName": "L1D.M_EVICT",
     23        "SampleAfterValue": "2000000",
     24        "UMask": "0x4"
     25    },
     26    {
     27        "BriefDescription": "L1D cache lines allocated in the M state",
     28        "Counter": "0,1",
     29        "EventCode": "0x51",
     30        "EventName": "L1D.M_REPL",
     31        "SampleAfterValue": "2000000",
     32        "UMask": "0x2"
     33    },
     34    {
     35        "BriefDescription": "L1D snoop eviction of cache lines in M state",
     36        "Counter": "0,1",
     37        "EventCode": "0x51",
     38        "EventName": "L1D.M_SNOOP_EVICT",
     39        "SampleAfterValue": "2000000",
     40        "UMask": "0x8"
     41    },
     42    {
     43        "BriefDescription": "L1 data cache lines allocated",
     44        "Counter": "0,1",
     45        "EventCode": "0x51",
     46        "EventName": "L1D.REPL",
     47        "SampleAfterValue": "2000000",
     48        "UMask": "0x1"
     49    },
     50    {
     51        "BriefDescription": "L1D prefetch load lock accepted in fill buffer",
     52        "Counter": "0,1",
     53        "EventCode": "0x52",
     54        "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
     55        "SampleAfterValue": "2000000",
     56        "UMask": "0x1"
     57    },
     58    {
     59        "BriefDescription": "L1D hardware prefetch misses",
     60        "Counter": "0,1",
     61        "EventCode": "0x4E",
     62        "EventName": "L1D_PREFETCH.MISS",
     63        "SampleAfterValue": "200000",
     64        "UMask": "0x2"
     65    },
     66    {
     67        "BriefDescription": "L1D hardware prefetch requests",
     68        "Counter": "0,1",
     69        "EventCode": "0x4E",
     70        "EventName": "L1D_PREFETCH.REQUESTS",
     71        "SampleAfterValue": "200000",
     72        "UMask": "0x1"
     73    },
     74    {
     75        "BriefDescription": "L1D hardware prefetch requests triggered",
     76        "Counter": "0,1",
     77        "EventCode": "0x4E",
     78        "EventName": "L1D_PREFETCH.TRIGGERS",
     79        "SampleAfterValue": "200000",
     80        "UMask": "0x4"
     81    },
     82    {
     83        "BriefDescription": "L1 writebacks to L2 in E state",
     84        "Counter": "0,1,2,3",
     85        "EventCode": "0x28",
     86        "EventName": "L1D_WB_L2.E_STATE",
     87        "SampleAfterValue": "100000",
     88        "UMask": "0x4"
     89    },
     90    {
     91        "BriefDescription": "L1 writebacks to L2 in I state (misses)",
     92        "Counter": "0,1,2,3",
     93        "EventCode": "0x28",
     94        "EventName": "L1D_WB_L2.I_STATE",
     95        "SampleAfterValue": "100000",
     96        "UMask": "0x1"
     97    },
     98    {
     99        "BriefDescription": "All L1 writebacks to L2",
    100        "Counter": "0,1,2,3",
    101        "EventCode": "0x28",
    102        "EventName": "L1D_WB_L2.MESI",
    103        "SampleAfterValue": "100000",
    104        "UMask": "0xf"
    105    },
    106    {
    107        "BriefDescription": "L1 writebacks to L2 in M state",
    108        "Counter": "0,1,2,3",
    109        "EventCode": "0x28",
    110        "EventName": "L1D_WB_L2.M_STATE",
    111        "SampleAfterValue": "100000",
    112        "UMask": "0x8"
    113    },
    114    {
    115        "BriefDescription": "L1 writebacks to L2 in S state",
    116        "Counter": "0,1,2,3",
    117        "EventCode": "0x28",
    118        "EventName": "L1D_WB_L2.S_STATE",
    119        "SampleAfterValue": "100000",
    120        "UMask": "0x2"
    121    },
    122    {
    123        "BriefDescription": "All L2 data requests",
    124        "Counter": "0,1,2,3",
    125        "EventCode": "0x26",
    126        "EventName": "L2_DATA_RQSTS.ANY",
    127        "SampleAfterValue": "200000",
    128        "UMask": "0xff"
    129    },
    130    {
    131        "BriefDescription": "L2 data demand loads in E state",
    132        "Counter": "0,1,2,3",
    133        "EventCode": "0x26",
    134        "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
    135        "SampleAfterValue": "200000",
    136        "UMask": "0x4"
    137    },
    138    {
    139        "BriefDescription": "L2 data demand loads in I state (misses)",
    140        "Counter": "0,1,2,3",
    141        "EventCode": "0x26",
    142        "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
    143        "SampleAfterValue": "200000",
    144        "UMask": "0x1"
    145    },
    146    {
    147        "BriefDescription": "L2 data demand requests",
    148        "Counter": "0,1,2,3",
    149        "EventCode": "0x26",
    150        "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
    151        "SampleAfterValue": "200000",
    152        "UMask": "0xf"
    153    },
    154    {
    155        "BriefDescription": "L2 data demand loads in M state",
    156        "Counter": "0,1,2,3",
    157        "EventCode": "0x26",
    158        "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
    159        "SampleAfterValue": "200000",
    160        "UMask": "0x8"
    161    },
    162    {
    163        "BriefDescription": "L2 data demand loads in S state",
    164        "Counter": "0,1,2,3",
    165        "EventCode": "0x26",
    166        "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
    167        "SampleAfterValue": "200000",
    168        "UMask": "0x2"
    169    },
    170    {
    171        "BriefDescription": "L2 data prefetches in E state",
    172        "Counter": "0,1,2,3",
    173        "EventCode": "0x26",
    174        "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
    175        "SampleAfterValue": "200000",
    176        "UMask": "0x40"
    177    },
    178    {
    179        "BriefDescription": "L2 data prefetches in the I state (misses)",
    180        "Counter": "0,1,2,3",
    181        "EventCode": "0x26",
    182        "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
    183        "SampleAfterValue": "200000",
    184        "UMask": "0x10"
    185    },
    186    {
    187        "BriefDescription": "All L2 data prefetches",
    188        "Counter": "0,1,2,3",
    189        "EventCode": "0x26",
    190        "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
    191        "SampleAfterValue": "200000",
    192        "UMask": "0xf0"
    193    },
    194    {
    195        "BriefDescription": "L2 data prefetches in M state",
    196        "Counter": "0,1,2,3",
    197        "EventCode": "0x26",
    198        "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
    199        "SampleAfterValue": "200000",
    200        "UMask": "0x80"
    201    },
    202    {
    203        "BriefDescription": "L2 data prefetches in the S state",
    204        "Counter": "0,1,2,3",
    205        "EventCode": "0x26",
    206        "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
    207        "SampleAfterValue": "200000",
    208        "UMask": "0x20"
    209    },
    210    {
    211        "BriefDescription": "L2 lines alloacated",
    212        "Counter": "0,1,2,3",
    213        "EventCode": "0xF1",
    214        "EventName": "L2_LINES_IN.ANY",
    215        "SampleAfterValue": "100000",
    216        "UMask": "0x7"
    217    },
    218    {
    219        "BriefDescription": "L2 lines allocated in the E state",
    220        "Counter": "0,1,2,3",
    221        "EventCode": "0xF1",
    222        "EventName": "L2_LINES_IN.E_STATE",
    223        "SampleAfterValue": "100000",
    224        "UMask": "0x4"
    225    },
    226    {
    227        "BriefDescription": "L2 lines allocated in the S state",
    228        "Counter": "0,1,2,3",
    229        "EventCode": "0xF1",
    230        "EventName": "L2_LINES_IN.S_STATE",
    231        "SampleAfterValue": "100000",
    232        "UMask": "0x2"
    233    },
    234    {
    235        "BriefDescription": "L2 lines evicted",
    236        "Counter": "0,1,2,3",
    237        "EventCode": "0xF2",
    238        "EventName": "L2_LINES_OUT.ANY",
    239        "SampleAfterValue": "100000",
    240        "UMask": "0xf"
    241    },
    242    {
    243        "BriefDescription": "L2 lines evicted by a demand request",
    244        "Counter": "0,1,2,3",
    245        "EventCode": "0xF2",
    246        "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
    247        "SampleAfterValue": "100000",
    248        "UMask": "0x1"
    249    },
    250    {
    251        "BriefDescription": "L2 modified lines evicted by a demand request",
    252        "Counter": "0,1,2,3",
    253        "EventCode": "0xF2",
    254        "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
    255        "SampleAfterValue": "100000",
    256        "UMask": "0x2"
    257    },
    258    {
    259        "BriefDescription": "L2 lines evicted by a prefetch request",
    260        "Counter": "0,1,2,3",
    261        "EventCode": "0xF2",
    262        "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
    263        "SampleAfterValue": "100000",
    264        "UMask": "0x4"
    265    },
    266    {
    267        "BriefDescription": "L2 modified lines evicted by a prefetch request",
    268        "Counter": "0,1,2,3",
    269        "EventCode": "0xF2",
    270        "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
    271        "SampleAfterValue": "100000",
    272        "UMask": "0x8"
    273    },
    274    {
    275        "BriefDescription": "L2 instruction fetches",
    276        "Counter": "0,1,2,3",
    277        "EventCode": "0x24",
    278        "EventName": "L2_RQSTS.IFETCHES",
    279        "SampleAfterValue": "200000",
    280        "UMask": "0x30"
    281    },
    282    {
    283        "BriefDescription": "L2 instruction fetch hits",
    284        "Counter": "0,1,2,3",
    285        "EventCode": "0x24",
    286        "EventName": "L2_RQSTS.IFETCH_HIT",
    287        "SampleAfterValue": "200000",
    288        "UMask": "0x10"
    289    },
    290    {
    291        "BriefDescription": "L2 instruction fetch misses",
    292        "Counter": "0,1,2,3",
    293        "EventCode": "0x24",
    294        "EventName": "L2_RQSTS.IFETCH_MISS",
    295        "SampleAfterValue": "200000",
    296        "UMask": "0x20"
    297    },
    298    {
    299        "BriefDescription": "L2 load hits",
    300        "Counter": "0,1,2,3",
    301        "EventCode": "0x24",
    302        "EventName": "L2_RQSTS.LD_HIT",
    303        "SampleAfterValue": "200000",
    304        "UMask": "0x1"
    305    },
    306    {
    307        "BriefDescription": "L2 load misses",
    308        "Counter": "0,1,2,3",
    309        "EventCode": "0x24",
    310        "EventName": "L2_RQSTS.LD_MISS",
    311        "SampleAfterValue": "200000",
    312        "UMask": "0x2"
    313    },
    314    {
    315        "BriefDescription": "L2 requests",
    316        "Counter": "0,1,2,3",
    317        "EventCode": "0x24",
    318        "EventName": "L2_RQSTS.LOADS",
    319        "SampleAfterValue": "200000",
    320        "UMask": "0x3"
    321    },
    322    {
    323        "BriefDescription": "All L2 misses",
    324        "Counter": "0,1,2,3",
    325        "EventCode": "0x24",
    326        "EventName": "L2_RQSTS.MISS",
    327        "SampleAfterValue": "200000",
    328        "UMask": "0xaa"
    329    },
    330    {
    331        "BriefDescription": "All L2 prefetches",
    332        "Counter": "0,1,2,3",
    333        "EventCode": "0x24",
    334        "EventName": "L2_RQSTS.PREFETCHES",
    335        "SampleAfterValue": "200000",
    336        "UMask": "0xc0"
    337    },
    338    {
    339        "BriefDescription": "L2 prefetch hits",
    340        "Counter": "0,1,2,3",
    341        "EventCode": "0x24",
    342        "EventName": "L2_RQSTS.PREFETCH_HIT",
    343        "SampleAfterValue": "200000",
    344        "UMask": "0x40"
    345    },
    346    {
    347        "BriefDescription": "L2 prefetch misses",
    348        "Counter": "0,1,2,3",
    349        "EventCode": "0x24",
    350        "EventName": "L2_RQSTS.PREFETCH_MISS",
    351        "SampleAfterValue": "200000",
    352        "UMask": "0x80"
    353    },
    354    {
    355        "BriefDescription": "All L2 requests",
    356        "Counter": "0,1,2,3",
    357        "EventCode": "0x24",
    358        "EventName": "L2_RQSTS.REFERENCES",
    359        "SampleAfterValue": "200000",
    360        "UMask": "0xff"
    361    },
    362    {
    363        "BriefDescription": "L2 RFO requests",
    364        "Counter": "0,1,2,3",
    365        "EventCode": "0x24",
    366        "EventName": "L2_RQSTS.RFOS",
    367        "SampleAfterValue": "200000",
    368        "UMask": "0xc"
    369    },
    370    {
    371        "BriefDescription": "L2 RFO hits",
    372        "Counter": "0,1,2,3",
    373        "EventCode": "0x24",
    374        "EventName": "L2_RQSTS.RFO_HIT",
    375        "SampleAfterValue": "200000",
    376        "UMask": "0x4"
    377    },
    378    {
    379        "BriefDescription": "L2 RFO misses",
    380        "Counter": "0,1,2,3",
    381        "EventCode": "0x24",
    382        "EventName": "L2_RQSTS.RFO_MISS",
    383        "SampleAfterValue": "200000",
    384        "UMask": "0x8"
    385    },
    386    {
    387        "BriefDescription": "All L2 transactions",
    388        "Counter": "0,1,2,3",
    389        "EventCode": "0xF0",
    390        "EventName": "L2_TRANSACTIONS.ANY",
    391        "SampleAfterValue": "200000",
    392        "UMask": "0x80"
    393    },
    394    {
    395        "BriefDescription": "L2 fill transactions",
    396        "Counter": "0,1,2,3",
    397        "EventCode": "0xF0",
    398        "EventName": "L2_TRANSACTIONS.FILL",
    399        "SampleAfterValue": "200000",
    400        "UMask": "0x20"
    401    },
    402    {
    403        "BriefDescription": "L2 instruction fetch transactions",
    404        "Counter": "0,1,2,3",
    405        "EventCode": "0xF0",
    406        "EventName": "L2_TRANSACTIONS.IFETCH",
    407        "SampleAfterValue": "200000",
    408        "UMask": "0x4"
    409    },
    410    {
    411        "BriefDescription": "L1D writeback to L2 transactions",
    412        "Counter": "0,1,2,3",
    413        "EventCode": "0xF0",
    414        "EventName": "L2_TRANSACTIONS.L1D_WB",
    415        "SampleAfterValue": "200000",
    416        "UMask": "0x10"
    417    },
    418    {
    419        "BriefDescription": "L2 Load transactions",
    420        "Counter": "0,1,2,3",
    421        "EventCode": "0xF0",
    422        "EventName": "L2_TRANSACTIONS.LOAD",
    423        "SampleAfterValue": "200000",
    424        "UMask": "0x1"
    425    },
    426    {
    427        "BriefDescription": "L2 prefetch transactions",
    428        "Counter": "0,1,2,3",
    429        "EventCode": "0xF0",
    430        "EventName": "L2_TRANSACTIONS.PREFETCH",
    431        "SampleAfterValue": "200000",
    432        "UMask": "0x8"
    433    },
    434    {
    435        "BriefDescription": "L2 RFO transactions",
    436        "Counter": "0,1,2,3",
    437        "EventCode": "0xF0",
    438        "EventName": "L2_TRANSACTIONS.RFO",
    439        "SampleAfterValue": "200000",
    440        "UMask": "0x2"
    441    },
    442    {
    443        "BriefDescription": "L2 writeback to LLC transactions",
    444        "Counter": "0,1,2,3",
    445        "EventCode": "0xF0",
    446        "EventName": "L2_TRANSACTIONS.WB",
    447        "SampleAfterValue": "200000",
    448        "UMask": "0x40"
    449    },
    450    {
    451        "BriefDescription": "L2 demand lock RFOs in E state",
    452        "Counter": "0,1,2,3",
    453        "EventCode": "0x27",
    454        "EventName": "L2_WRITE.LOCK.E_STATE",
    455        "SampleAfterValue": "100000",
    456        "UMask": "0x40"
    457    },
    458    {
    459        "BriefDescription": "All demand L2 lock RFOs that hit the cache",
    460        "Counter": "0,1,2,3",
    461        "EventCode": "0x27",
    462        "EventName": "L2_WRITE.LOCK.HIT",
    463        "SampleAfterValue": "100000",
    464        "UMask": "0xe0"
    465    },
    466    {
    467        "BriefDescription": "L2 demand lock RFOs in I state (misses)",
    468        "Counter": "0,1,2,3",
    469        "EventCode": "0x27",
    470        "EventName": "L2_WRITE.LOCK.I_STATE",
    471        "SampleAfterValue": "100000",
    472        "UMask": "0x10"
    473    },
    474    {
    475        "BriefDescription": "All demand L2 lock RFOs",
    476        "Counter": "0,1,2,3",
    477        "EventCode": "0x27",
    478        "EventName": "L2_WRITE.LOCK.MESI",
    479        "SampleAfterValue": "100000",
    480        "UMask": "0xf0"
    481    },
    482    {
    483        "BriefDescription": "L2 demand lock RFOs in M state",
    484        "Counter": "0,1,2,3",
    485        "EventCode": "0x27",
    486        "EventName": "L2_WRITE.LOCK.M_STATE",
    487        "SampleAfterValue": "100000",
    488        "UMask": "0x80"
    489    },
    490    {
    491        "BriefDescription": "L2 demand lock RFOs in S state",
    492        "Counter": "0,1,2,3",
    493        "EventCode": "0x27",
    494        "EventName": "L2_WRITE.LOCK.S_STATE",
    495        "SampleAfterValue": "100000",
    496        "UMask": "0x20"
    497    },
    498    {
    499        "BriefDescription": "All L2 demand store RFOs that hit the cache",
    500        "Counter": "0,1,2,3",
    501        "EventCode": "0x27",
    502        "EventName": "L2_WRITE.RFO.HIT",
    503        "SampleAfterValue": "100000",
    504        "UMask": "0xe"
    505    },
    506    {
    507        "BriefDescription": "L2 demand store RFOs in I state (misses)",
    508        "Counter": "0,1,2,3",
    509        "EventCode": "0x27",
    510        "EventName": "L2_WRITE.RFO.I_STATE",
    511        "SampleAfterValue": "100000",
    512        "UMask": "0x1"
    513    },
    514    {
    515        "BriefDescription": "All L2 demand store RFOs",
    516        "Counter": "0,1,2,3",
    517        "EventCode": "0x27",
    518        "EventName": "L2_WRITE.RFO.MESI",
    519        "SampleAfterValue": "100000",
    520        "UMask": "0xf"
    521    },
    522    {
    523        "BriefDescription": "L2 demand store RFOs in M state",
    524        "Counter": "0,1,2,3",
    525        "EventCode": "0x27",
    526        "EventName": "L2_WRITE.RFO.M_STATE",
    527        "SampleAfterValue": "100000",
    528        "UMask": "0x8"
    529    },
    530    {
    531        "BriefDescription": "L2 demand store RFOs in S state",
    532        "Counter": "0,1,2,3",
    533        "EventCode": "0x27",
    534        "EventName": "L2_WRITE.RFO.S_STATE",
    535        "SampleAfterValue": "100000",
    536        "UMask": "0x2"
    537    },
    538    {
    539        "BriefDescription": "Longest latency cache miss",
    540        "Counter": "0,1,2,3",
    541        "EventCode": "0x2E",
    542        "EventName": "LONGEST_LAT_CACHE.MISS",
    543        "SampleAfterValue": "100000",
    544        "UMask": "0x41"
    545    },
    546    {
    547        "BriefDescription": "Longest latency cache reference",
    548        "Counter": "0,1,2,3",
    549        "EventCode": "0x2E",
    550        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
    551        "SampleAfterValue": "200000",
    552        "UMask": "0x4f"
    553    },
    554    {
    555        "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
    556        "Counter": "3",
    557        "EventCode": "0xB",
    558        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
    559        "MSRIndex": "0x3F6",
    560        "MSRValue": "0x0",
    561        "PEBS": "2",
    562        "SampleAfterValue": "2000000",
    563        "UMask": "0x10"
    564    },
    565    {
    566        "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
    567        "Counter": "3",
    568        "EventCode": "0xB",
    569        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
    570        "MSRIndex": "0x3F6",
    571        "MSRValue": "0x400",
    572        "PEBS": "2",
    573        "SampleAfterValue": "100",
    574        "UMask": "0x10"
    575    },
    576    {
    577        "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
    578        "Counter": "3",
    579        "EventCode": "0xB",
    580        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
    581        "MSRIndex": "0x3F6",
    582        "MSRValue": "0x80",
    583        "PEBS": "2",
    584        "SampleAfterValue": "1000",
    585        "UMask": "0x10"
    586    },
    587    {
    588        "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
    589        "Counter": "3",
    590        "EventCode": "0xB",
    591        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
    592        "MSRIndex": "0x3F6",
    593        "MSRValue": "0x10",
    594        "PEBS": "2",
    595        "SampleAfterValue": "10000",
    596        "UMask": "0x10"
    597    },
    598    {
    599        "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
    600        "Counter": "3",
    601        "EventCode": "0xB",
    602        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
    603        "MSRIndex": "0x3F6",
    604        "MSRValue": "0x4000",
    605        "PEBS": "2",
    606        "SampleAfterValue": "5",
    607        "UMask": "0x10"
    608    },
    609    {
    610        "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
    611        "Counter": "3",
    612        "EventCode": "0xB",
    613        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
    614        "MSRIndex": "0x3F6",
    615        "MSRValue": "0x800",
    616        "PEBS": "2",
    617        "SampleAfterValue": "50",
    618        "UMask": "0x10"
    619    },
    620    {
    621        "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
    622        "Counter": "3",
    623        "EventCode": "0xB",
    624        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
    625        "MSRIndex": "0x3F6",
    626        "MSRValue": "0x100",
    627        "PEBS": "2",
    628        "SampleAfterValue": "500",
    629        "UMask": "0x10"
    630    },
    631    {
    632        "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
    633        "Counter": "3",
    634        "EventCode": "0xB",
    635        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
    636        "MSRIndex": "0x3F6",
    637        "MSRValue": "0x20",
    638        "PEBS": "2",
    639        "SampleAfterValue": "5000",
    640        "UMask": "0x10"
    641    },
    642    {
    643        "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
    644        "Counter": "3",
    645        "EventCode": "0xB",
    646        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
    647        "MSRIndex": "0x3F6",
    648        "MSRValue": "0x8000",
    649        "PEBS": "2",
    650        "SampleAfterValue": "3",
    651        "UMask": "0x10"
    652    },
    653    {
    654        "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
    655        "Counter": "3",
    656        "EventCode": "0xB",
    657        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
    658        "MSRIndex": "0x3F6",
    659        "MSRValue": "0x4",
    660        "PEBS": "2",
    661        "SampleAfterValue": "50000",
    662        "UMask": "0x10"
    663    },
    664    {
    665        "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
    666        "Counter": "3",
    667        "EventCode": "0xB",
    668        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
    669        "MSRIndex": "0x3F6",
    670        "MSRValue": "0x1000",
    671        "PEBS": "2",
    672        "SampleAfterValue": "20",
    673        "UMask": "0x10"
    674    },
    675    {
    676        "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
    677        "Counter": "3",
    678        "EventCode": "0xB",
    679        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
    680        "MSRIndex": "0x3F6",
    681        "MSRValue": "0x200",
    682        "PEBS": "2",
    683        "SampleAfterValue": "200",
    684        "UMask": "0x10"
    685    },
    686    {
    687        "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
    688        "Counter": "3",
    689        "EventCode": "0xB",
    690        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
    691        "MSRIndex": "0x3F6",
    692        "MSRValue": "0x40",
    693        "PEBS": "2",
    694        "SampleAfterValue": "2000",
    695        "UMask": "0x10"
    696    },
    697    {
    698        "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
    699        "Counter": "3",
    700        "EventCode": "0xB",
    701        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
    702        "MSRIndex": "0x3F6",
    703        "MSRValue": "0x8",
    704        "PEBS": "2",
    705        "SampleAfterValue": "20000",
    706        "UMask": "0x10"
    707    },
    708    {
    709        "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
    710        "Counter": "3",
    711        "EventCode": "0xB",
    712        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
    713        "MSRIndex": "0x3F6",
    714        "MSRValue": "0x2000",
    715        "PEBS": "2",
    716        "SampleAfterValue": "10",
    717        "UMask": "0x10"
    718    },
    719    {
    720        "BriefDescription": "Instructions retired which contains a load (Precise Event)",
    721        "Counter": "0,1,2,3",
    722        "EventCode": "0xB",
    723        "EventName": "MEM_INST_RETIRED.LOADS",
    724        "PEBS": "1",
    725        "SampleAfterValue": "2000000",
    726        "UMask": "0x1"
    727    },
    728    {
    729        "BriefDescription": "Instructions retired which contains a store (Precise Event)",
    730        "Counter": "0,1,2,3",
    731        "EventCode": "0xB",
    732        "EventName": "MEM_INST_RETIRED.STORES",
    733        "PEBS": "1",
    734        "SampleAfterValue": "2000000",
    735        "UMask": "0x2"
    736    },
    737    {
    738        "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
    739        "Counter": "0,1,2,3",
    740        "EventCode": "0xCB",
    741        "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
    742        "PEBS": "1",
    743        "SampleAfterValue": "200000",
    744        "UMask": "0x40"
    745    },
    746    {
    747        "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
    748        "Counter": "0,1,2,3",
    749        "EventCode": "0xCB",
    750        "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
    751        "PEBS": "1",
    752        "SampleAfterValue": "2000000",
    753        "UMask": "0x1"
    754    },
    755    {
    756        "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
    757        "Counter": "0,1,2,3",
    758        "EventCode": "0xCB",
    759        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
    760        "PEBS": "1",
    761        "SampleAfterValue": "200000",
    762        "UMask": "0x2"
    763    },
    764    {
    765        "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
    766        "Counter": "0,1,2,3",
    767        "EventCode": "0xCB",
    768        "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
    769        "PEBS": "1",
    770        "SampleAfterValue": "10000",
    771        "UMask": "0x10"
    772    },
    773    {
    774        "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
    775        "Counter": "0,1,2,3",
    776        "EventCode": "0xCB",
    777        "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
    778        "PEBS": "1",
    779        "SampleAfterValue": "40000",
    780        "UMask": "0x4"
    781    },
    782    {
    783        "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
    784        "Counter": "0,1,2,3",
    785        "EventCode": "0xCB",
    786        "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
    787        "PEBS": "1",
    788        "SampleAfterValue": "40000",
    789        "UMask": "0x8"
    790    },
    791    {
    792        "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)",
    793        "Counter": "0,1,2,3",
    794        "EventCode": "0xF",
    795        "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM",
    796        "PEBS": "1",
    797        "SampleAfterValue": "10000",
    798        "UMask": "0x10"
    799    },
    800    {
    801        "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
    802        "Counter": "0,1,2,3",
    803        "EventCode": "0xF",
    804        "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",
    805        "PEBS": "1",
    806        "SampleAfterValue": "40000",
    807        "UMask": "0x2"
    808    },
    809    {
    810        "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)",
    811        "Counter": "0,1,2,3",
    812        "EventCode": "0xF",
    813        "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",
    814        "PEBS": "1",
    815        "SampleAfterValue": "20000",
    816        "UMask": "0x8"
    817    },
    818    {
    819        "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
    820        "Counter": "0,1,2,3",
    821        "EventCode": "0xF",
    822        "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
    823        "PEBS": "1",
    824        "SampleAfterValue": "10000",
    825        "UMask": "0x20"
    826    },
    827    {
    828        "BriefDescription": "Load instructions retired IO (Precise Event)",
    829        "Counter": "0,1,2,3",
    830        "EventCode": "0xF",
    831        "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
    832        "PEBS": "1",
    833        "SampleAfterValue": "4000",
    834        "UMask": "0x80"
    835    },
    836    {
    837        "BriefDescription": "All offcore requests",
    838        "Counter": "0,1,2,3",
    839        "EventCode": "0xB0",
    840        "EventName": "OFFCORE_REQUESTS.ANY",
    841        "SampleAfterValue": "100000",
    842        "UMask": "0x80"
    843    },
    844    {
    845        "BriefDescription": "Offcore read requests",
    846        "Counter": "0,1,2,3",
    847        "EventCode": "0xB0",
    848        "EventName": "OFFCORE_REQUESTS.ANY.READ",
    849        "SampleAfterValue": "100000",
    850        "UMask": "0x8"
    851    },
    852    {
    853        "BriefDescription": "Offcore RFO requests",
    854        "Counter": "0,1,2,3",
    855        "EventCode": "0xB0",
    856        "EventName": "OFFCORE_REQUESTS.ANY.RFO",
    857        "SampleAfterValue": "100000",
    858        "UMask": "0x10"
    859    },
    860    {
    861        "BriefDescription": "Offcore demand code read requests",
    862        "Counter": "0,1,2,3",
    863        "EventCode": "0xB0",
    864        "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
    865        "SampleAfterValue": "100000",
    866        "UMask": "0x2"
    867    },
    868    {
    869        "BriefDescription": "Offcore demand data read requests",
    870        "Counter": "0,1,2,3",
    871        "EventCode": "0xB0",
    872        "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
    873        "SampleAfterValue": "100000",
    874        "UMask": "0x1"
    875    },
    876    {
    877        "BriefDescription": "Offcore demand RFO requests",
    878        "Counter": "0,1,2,3",
    879        "EventCode": "0xB0",
    880        "EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
    881        "SampleAfterValue": "100000",
    882        "UMask": "0x4"
    883    },
    884    {
    885        "BriefDescription": "Offcore L1 data cache writebacks",
    886        "Counter": "0,1,2,3",
    887        "EventCode": "0xB0",
    888        "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
    889        "SampleAfterValue": "100000",
    890        "UMask": "0x40"
    891    },
    892    {
    893        "BriefDescription": "Offcore uncached memory accesses",
    894        "Counter": "0,1,2,3",
    895        "EventCode": "0xB0",
    896        "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM",
    897        "SampleAfterValue": "100000",
    898        "UMask": "0x20"
    899    },
    900    {
    901        "BriefDescription": "Outstanding offcore reads",
    902        "EventCode": "0x60",
    903        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",
    904        "SampleAfterValue": "2000000",
    905        "UMask": "0x8"
    906    },
    907    {
    908        "BriefDescription": "Cycles offcore reads busy",
    909        "CounterMask": "1",
    910        "EventCode": "0x60",
    911        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",
    912        "SampleAfterValue": "2000000",
    913        "UMask": "0x8"
    914    },
    915    {
    916        "BriefDescription": "Outstanding offcore demand code reads",
    917        "EventCode": "0x60",
    918        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",
    919        "SampleAfterValue": "2000000",
    920        "UMask": "0x2"
    921    },
    922    {
    923        "BriefDescription": "Cycles offcore demand code read busy",
    924        "CounterMask": "1",
    925        "EventCode": "0x60",
    926        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",
    927        "SampleAfterValue": "2000000",
    928        "UMask": "0x2"
    929    },
    930    {
    931        "BriefDescription": "Outstanding offcore demand data reads",
    932        "EventCode": "0x60",
    933        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",
    934        "SampleAfterValue": "2000000",
    935        "UMask": "0x1"
    936    },
    937    {
    938        "BriefDescription": "Cycles offcore demand data read busy",
    939        "CounterMask": "1",
    940        "EventCode": "0x60",
    941        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",
    942        "SampleAfterValue": "2000000",
    943        "UMask": "0x1"
    944    },
    945    {
    946        "BriefDescription": "Outstanding offcore demand RFOs",
    947        "EventCode": "0x60",
    948        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",
    949        "SampleAfterValue": "2000000",
    950        "UMask": "0x4"
    951    },
    952    {
    953        "BriefDescription": "Cycles offcore demand RFOs busy",
    954        "CounterMask": "1",
    955        "EventCode": "0x60",
    956        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",
    957        "SampleAfterValue": "2000000",
    958        "UMask": "0x4"
    959    },
    960    {
    961        "BriefDescription": "Offcore requests blocked due to Super Queue full",
    962        "Counter": "0,1,2,3",
    963        "EventCode": "0xB2",
    964        "EventName": "OFFCORE_REQUESTS_SQ_FULL",
    965        "SampleAfterValue": "100000",
    966        "UMask": "0x1"
    967    },
    968    {
    969        "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
    970        "Counter": "0,1,2,3",
    971        "EventCode": "0xB7, 0xBB",
    972        "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
    973        "MSRIndex": "0x1a6,0x1a7",
    974        "MSRValue": "0x7F11",
    975        "Offcore": "1",
    976        "SampleAfterValue": "100000",
    977        "UMask": "0x1"
    978    },
    979    {
    980        "BriefDescription": "All offcore data reads",
    981        "Counter": "0,1,2,3",
    982        "EventCode": "0xB7, 0xBB",
    983        "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
    984        "MSRIndex": "0x1a6,0x1a7",
    985        "MSRValue": "0xFF11",
    986        "Offcore": "1",
    987        "SampleAfterValue": "100000",
    988        "UMask": "0x1"
    989    },
    990    {
    991        "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
    992        "Counter": "0,1,2,3",
    993        "EventCode": "0xB7, 0xBB",
    994        "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
    995        "MSRIndex": "0x1a6,0x1a7",
    996        "MSRValue": "0x8011",
    997        "Offcore": "1",
    998        "SampleAfterValue": "100000",
    999        "UMask": "0x1"
   1000    },
   1001    {
   1002        "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
   1003        "Counter": "0,1,2,3",
   1004        "EventCode": "0xB7, 0xBB",
   1005        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
   1006        "MSRIndex": "0x1a6,0x1a7",
   1007        "MSRValue": "0x111",
   1008        "Offcore": "1",
   1009        "SampleAfterValue": "100000",
   1010        "UMask": "0x1"
   1011    },
   1012    {
   1013        "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
   1014        "Counter": "0,1,2,3",
   1015        "EventCode": "0xB7, 0xBB",
   1016        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
   1017        "MSRIndex": "0x1a6,0x1a7",
   1018        "MSRValue": "0x211",
   1019        "Offcore": "1",
   1020        "SampleAfterValue": "100000",
   1021        "UMask": "0x1"
   1022    },
   1023    {
   1024        "BriefDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",
   1025        "Counter": "0,1,2,3",
   1026        "EventCode": "0xB7, 0xBB",
   1027        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
   1028        "MSRIndex": "0x1a6,0x1a7",
   1029        "MSRValue": "0x411",
   1030        "Offcore": "1",
   1031        "SampleAfterValue": "100000",
   1032        "UMask": "0x1"
   1033    },
   1034    {
   1035        "BriefDescription": "Offcore data reads satisfied by the LLC",
   1036        "Counter": "0,1,2,3",
   1037        "EventCode": "0xB7, 0xBB",
   1038        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
   1039        "MSRIndex": "0x1a6,0x1a7",
   1040        "MSRValue": "0x711",
   1041        "Offcore": "1",
   1042        "SampleAfterValue": "100000",
   1043        "UMask": "0x1"
   1044    },
   1045    {
   1046        "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
   1047        "Counter": "0,1,2,3",
   1048        "EventCode": "0xB7, 0xBB",
   1049        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
   1050        "MSRIndex": "0x1a6,0x1a7",
   1051        "MSRValue": "0x2711",
   1052        "Offcore": "1",
   1053        "SampleAfterValue": "100000",
   1054        "UMask": "0x1"
   1055    },
   1056    {
   1057        "BriefDescription": "Offcore data reads satisfied by a remote cache",
   1058        "Counter": "0,1,2,3",
   1059        "EventCode": "0xB7, 0xBB",
   1060        "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
   1061        "MSRIndex": "0x1a6,0x1a7",
   1062        "MSRValue": "0x1811",
   1063        "Offcore": "1",
   1064        "SampleAfterValue": "100000",
   1065        "UMask": "0x1"
   1066    },
   1067    {
   1068        "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
   1069        "Counter": "0,1,2,3",
   1070        "EventCode": "0xB7, 0xBB",
   1071        "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
   1072        "MSRIndex": "0x1a6,0x1a7",
   1073        "MSRValue": "0x5811",
   1074        "Offcore": "1",
   1075        "SampleAfterValue": "100000",
   1076        "UMask": "0x1"
   1077    },
   1078    {
   1079        "BriefDescription": "Offcore data reads that HIT in a remote cache",
   1080        "Counter": "0,1,2,3",
   1081        "EventCode": "0xB7, 0xBB",
   1082        "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
   1083        "MSRIndex": "0x1a6,0x1a7",
   1084        "MSRValue": "0x1011",
   1085        "Offcore": "1",
   1086        "SampleAfterValue": "100000",
   1087        "UMask": "0x1"
   1088    },
   1089    {
   1090        "BriefDescription": "Offcore data reads that HITM in a remote cache",
   1091        "Counter": "0,1,2,3",
   1092        "EventCode": "0xB7, 0xBB",
   1093        "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
   1094        "MSRIndex": "0x1a6,0x1a7",
   1095        "MSRValue": "0x811",
   1096        "Offcore": "1",
   1097        "SampleAfterValue": "100000",
   1098        "UMask": "0x1"
   1099    },
   1100    {
   1101        "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
   1102        "Counter": "0,1,2,3",
   1103        "EventCode": "0xB7, 0xBB",
   1104        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
   1105        "MSRIndex": "0x1a6,0x1a7",
   1106        "MSRValue": "0x7F44",
   1107        "Offcore": "1",
   1108        "SampleAfterValue": "100000",
   1109        "UMask": "0x1"
   1110    },
   1111    {
   1112        "BriefDescription": "All offcore code reads",
   1113        "Counter": "0,1,2,3",
   1114        "EventCode": "0xB7, 0xBB",
   1115        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
   1116        "MSRIndex": "0x1a6,0x1a7",
   1117        "MSRValue": "0xFF44",
   1118        "Offcore": "1",
   1119        "SampleAfterValue": "100000",
   1120        "UMask": "0x1"
   1121    },
   1122    {
   1123        "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
   1124        "Counter": "0,1,2,3",
   1125        "EventCode": "0xB7, 0xBB",
   1126        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
   1127        "MSRIndex": "0x1a6,0x1a7",
   1128        "MSRValue": "0x8044",
   1129        "Offcore": "1",
   1130        "SampleAfterValue": "100000",
   1131        "UMask": "0x1"
   1132    },
   1133    {
   1134        "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
   1135        "Counter": "0,1,2,3",
   1136        "EventCode": "0xB7, 0xBB",
   1137        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
   1138        "MSRIndex": "0x1a6,0x1a7",
   1139        "MSRValue": "0x144",
   1140        "Offcore": "1",
   1141        "SampleAfterValue": "100000",
   1142        "UMask": "0x1"
   1143    },
   1144    {
   1145        "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
   1146        "Counter": "0,1,2,3",
   1147        "EventCode": "0xB7, 0xBB",
   1148        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
   1149        "MSRIndex": "0x1a6,0x1a7",
   1150        "MSRValue": "0x244",
   1151        "Offcore": "1",
   1152        "SampleAfterValue": "100000",
   1153        "UMask": "0x1"
   1154    },
   1155    {
   1156        "BriefDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",
   1157        "Counter": "0,1,2,3",
   1158        "EventCode": "0xB7, 0xBB",
   1159        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
   1160        "MSRIndex": "0x1a6,0x1a7",
   1161        "MSRValue": "0x444",
   1162        "Offcore": "1",
   1163        "SampleAfterValue": "100000",
   1164        "UMask": "0x1"
   1165    },
   1166    {
   1167        "BriefDescription": "Offcore code reads satisfied by the LLC",
   1168        "Counter": "0,1,2,3",
   1169        "EventCode": "0xB7, 0xBB",
   1170        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
   1171        "MSRIndex": "0x1a6,0x1a7",
   1172        "MSRValue": "0x744",
   1173        "Offcore": "1",
   1174        "SampleAfterValue": "100000",
   1175        "UMask": "0x1"
   1176    },
   1177    {
   1178        "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
   1179        "Counter": "0,1,2,3",
   1180        "EventCode": "0xB7, 0xBB",
   1181        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
   1182        "MSRIndex": "0x1a6,0x1a7",
   1183        "MSRValue": "0x2744",
   1184        "Offcore": "1",
   1185        "SampleAfterValue": "100000",
   1186        "UMask": "0x1"
   1187    },
   1188    {
   1189        "BriefDescription": "Offcore code reads satisfied by a remote cache",
   1190        "Counter": "0,1,2,3",
   1191        "EventCode": "0xB7, 0xBB",
   1192        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
   1193        "MSRIndex": "0x1a6,0x1a7",
   1194        "MSRValue": "0x1844",
   1195        "Offcore": "1",
   1196        "SampleAfterValue": "100000",
   1197        "UMask": "0x1"
   1198    },
   1199    {
   1200        "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
   1201        "Counter": "0,1,2,3",
   1202        "EventCode": "0xB7, 0xBB",
   1203        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
   1204        "MSRIndex": "0x1a6,0x1a7",
   1205        "MSRValue": "0x5844",
   1206        "Offcore": "1",
   1207        "SampleAfterValue": "100000",
   1208        "UMask": "0x1"
   1209    },
   1210    {
   1211        "BriefDescription": "Offcore code reads that HIT in a remote cache",
   1212        "Counter": "0,1,2,3",
   1213        "EventCode": "0xB7, 0xBB",
   1214        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
   1215        "MSRIndex": "0x1a6,0x1a7",
   1216        "MSRValue": "0x1044",
   1217        "Offcore": "1",
   1218        "SampleAfterValue": "100000",
   1219        "UMask": "0x1"
   1220    },
   1221    {
   1222        "BriefDescription": "Offcore code reads that HITM in a remote cache",
   1223        "Counter": "0,1,2,3",
   1224        "EventCode": "0xB7, 0xBB",
   1225        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
   1226        "MSRIndex": "0x1a6,0x1a7",
   1227        "MSRValue": "0x844",
   1228        "Offcore": "1",
   1229        "SampleAfterValue": "100000",
   1230        "UMask": "0x1"
   1231    },
   1232    {
   1233        "BriefDescription": "Offcore requests satisfied by any cache or DRAM",
   1234        "Counter": "0,1,2,3",
   1235        "EventCode": "0xB7, 0xBB",
   1236        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
   1237        "MSRIndex": "0x1a6,0x1a7",
   1238        "MSRValue": "0x7FFF",
   1239        "Offcore": "1",
   1240        "SampleAfterValue": "100000",
   1241        "UMask": "0x1"
   1242    },
   1243    {
   1244        "BriefDescription": "All offcore requests",
   1245        "Counter": "0,1,2,3",
   1246        "EventCode": "0xB7, 0xBB",
   1247        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
   1248        "MSRIndex": "0x1a6,0x1a7",
   1249        "MSRValue": "0xFFFF",
   1250        "Offcore": "1",
   1251        "SampleAfterValue": "100000",
   1252        "UMask": "0x1"
   1253    },
   1254    {
   1255        "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
   1256        "Counter": "0,1,2,3",
   1257        "EventCode": "0xB7, 0xBB",
   1258        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
   1259        "MSRIndex": "0x1a6,0x1a7",
   1260        "MSRValue": "0x80FF",
   1261        "Offcore": "1",
   1262        "SampleAfterValue": "100000",
   1263        "UMask": "0x1"
   1264    },
   1265    {
   1266        "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
   1267        "Counter": "0,1,2,3",
   1268        "EventCode": "0xB7, 0xBB",
   1269        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
   1270        "MSRIndex": "0x1a6,0x1a7",
   1271        "MSRValue": "0x1FF",
   1272        "Offcore": "1",
   1273        "SampleAfterValue": "100000",
   1274        "UMask": "0x1"
   1275    },
   1276    {
   1277        "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
   1278        "Counter": "0,1,2,3",
   1279        "EventCode": "0xB7, 0xBB",
   1280        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
   1281        "MSRIndex": "0x1a6,0x1a7",
   1282        "MSRValue": "0x2FF",
   1283        "Offcore": "1",
   1284        "SampleAfterValue": "100000",
   1285        "UMask": "0x1"
   1286    },
   1287    {
   1288        "BriefDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",
   1289        "Counter": "0,1,2,3",
   1290        "EventCode": "0xB7, 0xBB",
   1291        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
   1292        "MSRIndex": "0x1a6,0x1a7",
   1293        "MSRValue": "0x4FF",
   1294        "Offcore": "1",
   1295        "SampleAfterValue": "100000",
   1296        "UMask": "0x1"
   1297    },
   1298    {
   1299        "BriefDescription": "Offcore requests satisfied by the LLC",
   1300        "Counter": "0,1,2,3",
   1301        "EventCode": "0xB7, 0xBB",
   1302        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
   1303        "MSRIndex": "0x1a6,0x1a7",
   1304        "MSRValue": "0x7FF",
   1305        "Offcore": "1",
   1306        "SampleAfterValue": "100000",
   1307        "UMask": "0x1"
   1308    },
   1309    {
   1310        "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
   1311        "Counter": "0,1,2,3",
   1312        "EventCode": "0xB7, 0xBB",
   1313        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
   1314        "MSRIndex": "0x1a6,0x1a7",
   1315        "MSRValue": "0x27FF",
   1316        "Offcore": "1",
   1317        "SampleAfterValue": "100000",
   1318        "UMask": "0x1"
   1319    },
   1320    {
   1321        "BriefDescription": "Offcore requests satisfied by a remote cache",
   1322        "Counter": "0,1,2,3",
   1323        "EventCode": "0xB7, 0xBB",
   1324        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
   1325        "MSRIndex": "0x1a6,0x1a7",
   1326        "MSRValue": "0x18FF",
   1327        "Offcore": "1",
   1328        "SampleAfterValue": "100000",
   1329        "UMask": "0x1"
   1330    },
   1331    {
   1332        "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
   1333        "Counter": "0,1,2,3",
   1334        "EventCode": "0xB7, 0xBB",
   1335        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
   1336        "MSRIndex": "0x1a6,0x1a7",
   1337        "MSRValue": "0x58FF",
   1338        "Offcore": "1",
   1339        "SampleAfterValue": "100000",
   1340        "UMask": "0x1"
   1341    },
   1342    {
   1343        "BriefDescription": "Offcore requests that HIT in a remote cache",
   1344        "Counter": "0,1,2,3",
   1345        "EventCode": "0xB7, 0xBB",
   1346        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
   1347        "MSRIndex": "0x1a6,0x1a7",
   1348        "MSRValue": "0x10FF",
   1349        "Offcore": "1",
   1350        "SampleAfterValue": "100000",
   1351        "UMask": "0x1"
   1352    },
   1353    {
   1354        "BriefDescription": "Offcore requests that HITM in a remote cache",
   1355        "Counter": "0,1,2,3",
   1356        "EventCode": "0xB7, 0xBB",
   1357        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
   1358        "MSRIndex": "0x1a6,0x1a7",
   1359        "MSRValue": "0x8FF",
   1360        "Offcore": "1",
   1361        "SampleAfterValue": "100000",
   1362        "UMask": "0x1"
   1363    },
   1364    {
   1365        "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
   1366        "Counter": "0,1,2,3",
   1367        "EventCode": "0xB7, 0xBB",
   1368        "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
   1369        "MSRIndex": "0x1a6,0x1a7",
   1370        "MSRValue": "0x7F22",
   1371        "Offcore": "1",
   1372        "SampleAfterValue": "100000",
   1373        "UMask": "0x1"
   1374    },
   1375    {
   1376        "BriefDescription": "All offcore RFO requests",
   1377        "Counter": "0,1,2,3",
   1378        "EventCode": "0xB7, 0xBB",
   1379        "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
   1380        "MSRIndex": "0x1a6,0x1a7",
   1381        "MSRValue": "0xFF22",
   1382        "Offcore": "1",
   1383        "SampleAfterValue": "100000",
   1384        "UMask": "0x1"
   1385    },
   1386    {
   1387        "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
   1388        "Counter": "0,1,2,3",
   1389        "EventCode": "0xB7, 0xBB",
   1390        "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
   1391        "MSRIndex": "0x1a6,0x1a7",
   1392        "MSRValue": "0x8022",
   1393        "Offcore": "1",
   1394        "SampleAfterValue": "100000",
   1395        "UMask": "0x1"
   1396    },
   1397    {
   1398        "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
   1399        "Counter": "0,1,2,3",
   1400        "EventCode": "0xB7, 0xBB",
   1401        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
   1402        "MSRIndex": "0x1a6,0x1a7",
   1403        "MSRValue": "0x122",
   1404        "Offcore": "1",
   1405        "SampleAfterValue": "100000",
   1406        "UMask": "0x1"
   1407    },
   1408    {
   1409        "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
   1410        "Counter": "0,1,2,3",
   1411        "EventCode": "0xB7, 0xBB",
   1412        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
   1413        "MSRIndex": "0x1a6,0x1a7",
   1414        "MSRValue": "0x222",
   1415        "Offcore": "1",
   1416        "SampleAfterValue": "100000",
   1417        "UMask": "0x1"
   1418    },
   1419    {
   1420        "BriefDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",
   1421        "Counter": "0,1,2,3",
   1422        "EventCode": "0xB7, 0xBB",
   1423        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
   1424        "MSRIndex": "0x1a6,0x1a7",
   1425        "MSRValue": "0x422",
   1426        "Offcore": "1",
   1427        "SampleAfterValue": "100000",
   1428        "UMask": "0x1"
   1429    },
   1430    {
   1431        "BriefDescription": "Offcore RFO requests satisfied by the LLC",
   1432        "Counter": "0,1,2,3",
   1433        "EventCode": "0xB7, 0xBB",
   1434        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
   1435        "MSRIndex": "0x1a6,0x1a7",
   1436        "MSRValue": "0x722",
   1437        "Offcore": "1",
   1438        "SampleAfterValue": "100000",
   1439        "UMask": "0x1"
   1440    },
   1441    {
   1442        "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
   1443        "Counter": "0,1,2,3",
   1444        "EventCode": "0xB7, 0xBB",
   1445        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
   1446        "MSRIndex": "0x1a6,0x1a7",
   1447        "MSRValue": "0x2722",
   1448        "Offcore": "1",
   1449        "SampleAfterValue": "100000",
   1450        "UMask": "0x1"
   1451    },
   1452    {
   1453        "BriefDescription": "Offcore RFO requests satisfied by a remote cache",
   1454        "Counter": "0,1,2,3",
   1455        "EventCode": "0xB7, 0xBB",
   1456        "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
   1457        "MSRIndex": "0x1a6,0x1a7",
   1458        "MSRValue": "0x1822",
   1459        "Offcore": "1",
   1460        "SampleAfterValue": "100000",
   1461        "UMask": "0x1"
   1462    },
   1463    {
   1464        "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
   1465        "Counter": "0,1,2,3",
   1466        "EventCode": "0xB7, 0xBB",
   1467        "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
   1468        "MSRIndex": "0x1a6,0x1a7",
   1469        "MSRValue": "0x5822",
   1470        "Offcore": "1",
   1471        "SampleAfterValue": "100000",
   1472        "UMask": "0x1"
   1473    },
   1474    {
   1475        "BriefDescription": "Offcore RFO requests that HIT in a remote cache",
   1476        "Counter": "0,1,2,3",
   1477        "EventCode": "0xB7, 0xBB",
   1478        "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
   1479        "MSRIndex": "0x1a6,0x1a7",
   1480        "MSRValue": "0x1022",
   1481        "Offcore": "1",
   1482        "SampleAfterValue": "100000",
   1483        "UMask": "0x1"
   1484    },
   1485    {
   1486        "BriefDescription": "Offcore RFO requests that HITM in a remote cache",
   1487        "Counter": "0,1,2,3",
   1488        "EventCode": "0xB7, 0xBB",
   1489        "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
   1490        "MSRIndex": "0x1a6,0x1a7",
   1491        "MSRValue": "0x822",
   1492        "Offcore": "1",
   1493        "SampleAfterValue": "100000",
   1494        "UMask": "0x1"
   1495    },
   1496    {
   1497        "BriefDescription": "Offcore writebacks to any cache or DRAM.",
   1498        "Counter": "0,1,2,3",
   1499        "EventCode": "0xB7, 0xBB",
   1500        "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
   1501        "MSRIndex": "0x1a6,0x1a7",
   1502        "MSRValue": "0x7F08",
   1503        "Offcore": "1",
   1504        "SampleAfterValue": "100000",
   1505        "UMask": "0x1"
   1506    },
   1507    {
   1508        "BriefDescription": "All offcore writebacks",
   1509        "Counter": "0,1,2,3",
   1510        "EventCode": "0xB7, 0xBB",
   1511        "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
   1512        "MSRIndex": "0x1a6,0x1a7",
   1513        "MSRValue": "0xFF08",
   1514        "Offcore": "1",
   1515        "SampleAfterValue": "100000",
   1516        "UMask": "0x1"
   1517    },
   1518    {
   1519        "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
   1520        "Counter": "0,1,2,3",
   1521        "EventCode": "0xB7, 0xBB",
   1522        "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
   1523        "MSRIndex": "0x1a6,0x1a7",
   1524        "MSRValue": "0x8008",
   1525        "Offcore": "1",
   1526        "SampleAfterValue": "100000",
   1527        "UMask": "0x1"
   1528    },
   1529    {
   1530        "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
   1531        "Counter": "0,1,2,3",
   1532        "EventCode": "0xB7, 0xBB",
   1533        "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
   1534        "MSRIndex": "0x1a6,0x1a7",
   1535        "MSRValue": "0x108",
   1536        "Offcore": "1",
   1537        "SampleAfterValue": "100000",
   1538        "UMask": "0x1"
   1539    },
   1540    {
   1541        "BriefDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",
   1542        "Counter": "0,1,2,3",
   1543        "EventCode": "0xB7, 0xBB",
   1544        "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
   1545        "MSRIndex": "0x1a6,0x1a7",
   1546        "MSRValue": "0x408",
   1547        "Offcore": "1",
   1548        "SampleAfterValue": "100000",
   1549        "UMask": "0x1"
   1550    },
   1551    {
   1552        "BriefDescription": "Offcore writebacks to the LLC",
   1553        "Counter": "0,1,2,3",
   1554        "EventCode": "0xB7, 0xBB",
   1555        "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
   1556        "MSRIndex": "0x1a6,0x1a7",
   1557        "MSRValue": "0x708",
   1558        "Offcore": "1",
   1559        "SampleAfterValue": "100000",
   1560        "UMask": "0x1"
   1561    },
   1562    {
   1563        "BriefDescription": "Offcore writebacks to the LLC or local DRAM",
   1564        "Counter": "0,1,2,3",
   1565        "EventCode": "0xB7, 0xBB",
   1566        "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
   1567        "MSRIndex": "0x1a6,0x1a7",
   1568        "MSRValue": "0x2708",
   1569        "Offcore": "1",
   1570        "SampleAfterValue": "100000",
   1571        "UMask": "0x1"
   1572    },
   1573    {
   1574        "BriefDescription": "Offcore writebacks to a remote cache",
   1575        "Counter": "0,1,2,3",
   1576        "EventCode": "0xB7, 0xBB",
   1577        "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
   1578        "MSRIndex": "0x1a6,0x1a7",
   1579        "MSRValue": "0x1808",
   1580        "Offcore": "1",
   1581        "SampleAfterValue": "100000",
   1582        "UMask": "0x1"
   1583    },
   1584    {
   1585        "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
   1586        "Counter": "0,1,2,3",
   1587        "EventCode": "0xB7, 0xBB",
   1588        "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
   1589        "MSRIndex": "0x1a6,0x1a7",
   1590        "MSRValue": "0x5808",
   1591        "Offcore": "1",
   1592        "SampleAfterValue": "100000",
   1593        "UMask": "0x1"
   1594    },
   1595    {
   1596        "BriefDescription": "Offcore writebacks that HIT in a remote cache",
   1597        "Counter": "0,1,2,3",
   1598        "EventCode": "0xB7, 0xBB",
   1599        "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
   1600        "MSRIndex": "0x1a6,0x1a7",
   1601        "MSRValue": "0x1008",
   1602        "Offcore": "1",
   1603        "SampleAfterValue": "100000",
   1604        "UMask": "0x1"
   1605    },
   1606    {
   1607        "BriefDescription": "Offcore writebacks that HITM in a remote cache",
   1608        "Counter": "0,1,2,3",
   1609        "EventCode": "0xB7, 0xBB",
   1610        "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
   1611        "MSRIndex": "0x1a6,0x1a7",
   1612        "MSRValue": "0x808",
   1613        "Offcore": "1",
   1614        "SampleAfterValue": "100000",
   1615        "UMask": "0x1"
   1616    },
   1617    {
   1618        "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
   1619        "Counter": "0,1,2,3",
   1620        "EventCode": "0xB7, 0xBB",
   1621        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
   1622        "MSRIndex": "0x1a6,0x1a7",
   1623        "MSRValue": "0x7F77",
   1624        "Offcore": "1",
   1625        "SampleAfterValue": "100000",
   1626        "UMask": "0x1"
   1627    },
   1628    {
   1629        "BriefDescription": "All offcore code or data read requests",
   1630        "Counter": "0,1,2,3",
   1631        "EventCode": "0xB7, 0xBB",
   1632        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
   1633        "MSRIndex": "0x1a6,0x1a7",
   1634        "MSRValue": "0xFF77",
   1635        "Offcore": "1",
   1636        "SampleAfterValue": "100000",
   1637        "UMask": "0x1"
   1638    },
   1639    {
   1640        "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
   1641        "Counter": "0,1,2,3",
   1642        "EventCode": "0xB7, 0xBB",
   1643        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
   1644        "MSRIndex": "0x1a6,0x1a7",
   1645        "MSRValue": "0x8077",
   1646        "Offcore": "1",
   1647        "SampleAfterValue": "100000",
   1648        "UMask": "0x1"
   1649    },
   1650    {
   1651        "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
   1652        "Counter": "0,1,2,3",
   1653        "EventCode": "0xB7, 0xBB",
   1654        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
   1655        "MSRIndex": "0x1a6,0x1a7",
   1656        "MSRValue": "0x177",
   1657        "Offcore": "1",
   1658        "SampleAfterValue": "100000",
   1659        "UMask": "0x1"
   1660    },
   1661    {
   1662        "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
   1663        "Counter": "0,1,2,3",
   1664        "EventCode": "0xB7, 0xBB",
   1665        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
   1666        "MSRIndex": "0x1a6,0x1a7",
   1667        "MSRValue": "0x277",
   1668        "Offcore": "1",
   1669        "SampleAfterValue": "100000",
   1670        "UMask": "0x1"
   1671    },
   1672    {
   1673        "BriefDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",
   1674        "Counter": "0,1,2,3",
   1675        "EventCode": "0xB7, 0xBB",
   1676        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
   1677        "MSRIndex": "0x1a6,0x1a7",
   1678        "MSRValue": "0x477",
   1679        "Offcore": "1",
   1680        "SampleAfterValue": "100000",
   1681        "UMask": "0x1"
   1682    },
   1683    {
   1684        "BriefDescription": "Offcore code or data read requests satisfied by the LLC",
   1685        "Counter": "0,1,2,3",
   1686        "EventCode": "0xB7, 0xBB",
   1687        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
   1688        "MSRIndex": "0x1a6,0x1a7",
   1689        "MSRValue": "0x777",
   1690        "Offcore": "1",
   1691        "SampleAfterValue": "100000",
   1692        "UMask": "0x1"
   1693    },
   1694    {
   1695        "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
   1696        "Counter": "0,1,2,3",
   1697        "EventCode": "0xB7, 0xBB",
   1698        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
   1699        "MSRIndex": "0x1a6,0x1a7",
   1700        "MSRValue": "0x2777",
   1701        "Offcore": "1",
   1702        "SampleAfterValue": "100000",
   1703        "UMask": "0x1"
   1704    },
   1705    {
   1706        "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
   1707        "Counter": "0,1,2,3",
   1708        "EventCode": "0xB7, 0xBB",
   1709        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
   1710        "MSRIndex": "0x1a6,0x1a7",
   1711        "MSRValue": "0x1877",
   1712        "Offcore": "1",
   1713        "SampleAfterValue": "100000",
   1714        "UMask": "0x1"
   1715    },
   1716    {
   1717        "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
   1718        "Counter": "0,1,2,3",
   1719        "EventCode": "0xB7, 0xBB",
   1720        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
   1721        "MSRIndex": "0x1a6,0x1a7",
   1722        "MSRValue": "0x5877",
   1723        "Offcore": "1",
   1724        "SampleAfterValue": "100000",
   1725        "UMask": "0x1"
   1726    },
   1727    {
   1728        "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
   1729        "Counter": "0,1,2,3",
   1730        "EventCode": "0xB7, 0xBB",
   1731        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
   1732        "MSRIndex": "0x1a6,0x1a7",
   1733        "MSRValue": "0x1077",
   1734        "Offcore": "1",
   1735        "SampleAfterValue": "100000",
   1736        "UMask": "0x1"
   1737    },
   1738    {
   1739        "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
   1740        "Counter": "0,1,2,3",
   1741        "EventCode": "0xB7, 0xBB",
   1742        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
   1743        "MSRIndex": "0x1a6,0x1a7",
   1744        "MSRValue": "0x877",
   1745        "Offcore": "1",
   1746        "SampleAfterValue": "100000",
   1747        "UMask": "0x1"
   1748    },
   1749    {
   1750        "BriefDescription": "Offcore request = all data, response = any cache_dram",
   1751        "Counter": "0,1,2,3",
   1752        "EventCode": "0xB7, 0xBB",
   1753        "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
   1754        "MSRIndex": "0x1a6,0x1a7",
   1755        "MSRValue": "0x7F33",
   1756        "Offcore": "1",
   1757        "SampleAfterValue": "100000",
   1758        "UMask": "0x1"
   1759    },
   1760    {
   1761        "BriefDescription": "Offcore request = all data, response = any location",
   1762        "Counter": "0,1,2,3",
   1763        "EventCode": "0xB7, 0xBB",
   1764        "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
   1765        "MSRIndex": "0x1a6,0x1a7",
   1766        "MSRValue": "0xFF33",
   1767        "Offcore": "1",
   1768        "SampleAfterValue": "100000",
   1769        "UMask": "0x1"
   1770    },
   1771    {
   1772        "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
   1773        "Counter": "0,1,2,3",
   1774        "EventCode": "0xB7, 0xBB",
   1775        "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
   1776        "MSRIndex": "0x1a6,0x1a7",
   1777        "MSRValue": "0x8033",
   1778        "Offcore": "1",
   1779        "SampleAfterValue": "100000",
   1780        "UMask": "0x1"
   1781    },
   1782    {
   1783        "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
   1784        "Counter": "0,1,2,3",
   1785        "EventCode": "0xB7, 0xBB",
   1786        "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
   1787        "MSRIndex": "0x1a6,0x1a7",
   1788        "MSRValue": "0x133",
   1789        "Offcore": "1",
   1790        "SampleAfterValue": "100000",
   1791        "UMask": "0x1"
   1792    },
   1793    {
   1794        "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
   1795        "Counter": "0,1,2,3",
   1796        "EventCode": "0xB7, 0xBB",
   1797        "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
   1798        "MSRIndex": "0x1a6,0x1a7",
   1799        "MSRValue": "0x233",
   1800        "Offcore": "1",
   1801        "SampleAfterValue": "100000",
   1802        "UMask": "0x1"
   1803    },
   1804    {
   1805        "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC  and HITM in a sibling core",
   1806        "Counter": "0,1,2,3",
   1807        "EventCode": "0xB7, 0xBB",
   1808        "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
   1809        "MSRIndex": "0x1a6,0x1a7",
   1810        "MSRValue": "0x433",
   1811        "Offcore": "1",
   1812        "SampleAfterValue": "100000",
   1813        "UMask": "0x1"
   1814    },
   1815    {
   1816        "BriefDescription": "Offcore request = all data, response = local cache",
   1817        "Counter": "0,1,2,3",
   1818        "EventCode": "0xB7, 0xBB",
   1819        "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
   1820        "MSRIndex": "0x1a6,0x1a7",
   1821        "MSRValue": "0x733",
   1822        "Offcore": "1",
   1823        "SampleAfterValue": "100000",
   1824        "UMask": "0x1"
   1825    },
   1826    {
   1827        "BriefDescription": "Offcore request = all data, response = local cache or dram",
   1828        "Counter": "0,1,2,3",
   1829        "EventCode": "0xB7, 0xBB",
   1830        "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
   1831        "MSRIndex": "0x1a6,0x1a7",
   1832        "MSRValue": "0x2733",
   1833        "Offcore": "1",
   1834        "SampleAfterValue": "100000",
   1835        "UMask": "0x1"
   1836    },
   1837    {
   1838        "BriefDescription": "Offcore request = all data, response = remote cache",
   1839        "Counter": "0,1,2,3",
   1840        "EventCode": "0xB7, 0xBB",
   1841        "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
   1842        "MSRIndex": "0x1a6,0x1a7",
   1843        "MSRValue": "0x1833",
   1844        "Offcore": "1",
   1845        "SampleAfterValue": "100000",
   1846        "UMask": "0x1"
   1847    },
   1848    {
   1849        "BriefDescription": "Offcore request = all data, response = remote cache or dram",
   1850        "Counter": "0,1,2,3",
   1851        "EventCode": "0xB7, 0xBB",
   1852        "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
   1853        "MSRIndex": "0x1a6,0x1a7",
   1854        "MSRValue": "0x5833",
   1855        "Offcore": "1",
   1856        "SampleAfterValue": "100000",
   1857        "UMask": "0x1"
   1858    },
   1859    {
   1860        "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
   1861        "Counter": "0,1,2,3",
   1862        "EventCode": "0xB7, 0xBB",
   1863        "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
   1864        "MSRIndex": "0x1a6,0x1a7",
   1865        "MSRValue": "0x1033",
   1866        "Offcore": "1",
   1867        "SampleAfterValue": "100000",
   1868        "UMask": "0x1"
   1869    },
   1870    {
   1871        "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
   1872        "Counter": "0,1,2,3",
   1873        "EventCode": "0xB7, 0xBB",
   1874        "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
   1875        "MSRIndex": "0x1a6,0x1a7",
   1876        "MSRValue": "0x833",
   1877        "Offcore": "1",
   1878        "SampleAfterValue": "100000",
   1879        "UMask": "0x1"
   1880    },
   1881    {
   1882        "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
   1883        "Counter": "0,1,2,3",
   1884        "EventCode": "0xB7, 0xBB",
   1885        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
   1886        "MSRIndex": "0x1a6,0x1a7",
   1887        "MSRValue": "0x7F03",
   1888        "Offcore": "1",
   1889        "SampleAfterValue": "100000",
   1890        "UMask": "0x1"
   1891    },
   1892    {
   1893        "BriefDescription": "All offcore demand data requests",
   1894        "Counter": "0,1,2,3",
   1895        "EventCode": "0xB7, 0xBB",
   1896        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
   1897        "MSRIndex": "0x1a6,0x1a7",
   1898        "MSRValue": "0xFF03",
   1899        "Offcore": "1",
   1900        "SampleAfterValue": "100000",
   1901        "UMask": "0x1"
   1902    },
   1903    {
   1904        "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
   1905        "Counter": "0,1,2,3",
   1906        "EventCode": "0xB7, 0xBB",
   1907        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
   1908        "MSRIndex": "0x1a6,0x1a7",
   1909        "MSRValue": "0x8003",
   1910        "Offcore": "1",
   1911        "SampleAfterValue": "100000",
   1912        "UMask": "0x1"
   1913    },
   1914    {
   1915        "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
   1916        "Counter": "0,1,2,3",
   1917        "EventCode": "0xB7, 0xBB",
   1918        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
   1919        "MSRIndex": "0x1a6,0x1a7",
   1920        "MSRValue": "0x103",
   1921        "Offcore": "1",
   1922        "SampleAfterValue": "100000",
   1923        "UMask": "0x1"
   1924    },
   1925    {
   1926        "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
   1927        "Counter": "0,1,2,3",
   1928        "EventCode": "0xB7, 0xBB",
   1929        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
   1930        "MSRIndex": "0x1a6,0x1a7",
   1931        "MSRValue": "0x203",
   1932        "Offcore": "1",
   1933        "SampleAfterValue": "100000",
   1934        "UMask": "0x1"
   1935    },
   1936    {
   1937        "BriefDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",
   1938        "Counter": "0,1,2,3",
   1939        "EventCode": "0xB7, 0xBB",
   1940        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
   1941        "MSRIndex": "0x1a6,0x1a7",
   1942        "MSRValue": "0x403",
   1943        "Offcore": "1",
   1944        "SampleAfterValue": "100000",
   1945        "UMask": "0x1"
   1946    },
   1947    {
   1948        "BriefDescription": "Offcore demand data requests satisfied by the LLC",
   1949        "Counter": "0,1,2,3",
   1950        "EventCode": "0xB7, 0xBB",
   1951        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
   1952        "MSRIndex": "0x1a6,0x1a7",
   1953        "MSRValue": "0x703",
   1954        "Offcore": "1",
   1955        "SampleAfterValue": "100000",
   1956        "UMask": "0x1"
   1957    },
   1958    {
   1959        "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
   1960        "Counter": "0,1,2,3",
   1961        "EventCode": "0xB7, 0xBB",
   1962        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
   1963        "MSRIndex": "0x1a6,0x1a7",
   1964        "MSRValue": "0x2703",
   1965        "Offcore": "1",
   1966        "SampleAfterValue": "100000",
   1967        "UMask": "0x1"
   1968    },
   1969    {
   1970        "BriefDescription": "Offcore demand data requests satisfied by a remote cache",
   1971        "Counter": "0,1,2,3",
   1972        "EventCode": "0xB7, 0xBB",
   1973        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
   1974        "MSRIndex": "0x1a6,0x1a7",
   1975        "MSRValue": "0x1803",
   1976        "Offcore": "1",
   1977        "SampleAfterValue": "100000",
   1978        "UMask": "0x1"
   1979    },
   1980    {
   1981        "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
   1982        "Counter": "0,1,2,3",
   1983        "EventCode": "0xB7, 0xBB",
   1984        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
   1985        "MSRIndex": "0x1a6,0x1a7",
   1986        "MSRValue": "0x5803",
   1987        "Offcore": "1",
   1988        "SampleAfterValue": "100000",
   1989        "UMask": "0x1"
   1990    },
   1991    {
   1992        "BriefDescription": "Offcore demand data requests that HIT in a remote cache",
   1993        "Counter": "0,1,2,3",
   1994        "EventCode": "0xB7, 0xBB",
   1995        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
   1996        "MSRIndex": "0x1a6,0x1a7",
   1997        "MSRValue": "0x1003",
   1998        "Offcore": "1",
   1999        "SampleAfterValue": "100000",
   2000        "UMask": "0x1"
   2001    },
   2002    {
   2003        "BriefDescription": "Offcore demand data requests that HITM in a remote cache",
   2004        "Counter": "0,1,2,3",
   2005        "EventCode": "0xB7, 0xBB",
   2006        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
   2007        "MSRIndex": "0x1a6,0x1a7",
   2008        "MSRValue": "0x803",
   2009        "Offcore": "1",
   2010        "SampleAfterValue": "100000",
   2011        "UMask": "0x1"
   2012    },
   2013    {
   2014        "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
   2015        "Counter": "0,1,2,3",
   2016        "EventCode": "0xB7, 0xBB",
   2017        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
   2018        "MSRIndex": "0x1a6,0x1a7",
   2019        "MSRValue": "0x7F01",
   2020        "Offcore": "1",
   2021        "SampleAfterValue": "100000",
   2022        "UMask": "0x1"
   2023    },
   2024    {
   2025        "BriefDescription": "All offcore demand data reads",
   2026        "Counter": "0,1,2,3",
   2027        "EventCode": "0xB7, 0xBB",
   2028        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
   2029        "MSRIndex": "0x1a6,0x1a7",
   2030        "MSRValue": "0xFF01",
   2031        "Offcore": "1",
   2032        "SampleAfterValue": "100000",
   2033        "UMask": "0x1"
   2034    },
   2035    {
   2036        "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
   2037        "Counter": "0,1,2,3",
   2038        "EventCode": "0xB7, 0xBB",
   2039        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
   2040        "MSRIndex": "0x1a6,0x1a7",
   2041        "MSRValue": "0x8001",
   2042        "Offcore": "1",
   2043        "SampleAfterValue": "100000",
   2044        "UMask": "0x1"
   2045    },
   2046    {
   2047        "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
   2048        "Counter": "0,1,2,3",
   2049        "EventCode": "0xB7, 0xBB",
   2050        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
   2051        "MSRIndex": "0x1a6,0x1a7",
   2052        "MSRValue": "0x101",
   2053        "Offcore": "1",
   2054        "SampleAfterValue": "100000",
   2055        "UMask": "0x1"
   2056    },
   2057    {
   2058        "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
   2059        "Counter": "0,1,2,3",
   2060        "EventCode": "0xB7, 0xBB",
   2061        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
   2062        "MSRIndex": "0x1a6,0x1a7",
   2063        "MSRValue": "0x201",
   2064        "Offcore": "1",
   2065        "SampleAfterValue": "100000",
   2066        "UMask": "0x1"
   2067    },
   2068    {
   2069        "BriefDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",
   2070        "Counter": "0,1,2,3",
   2071        "EventCode": "0xB7, 0xBB",
   2072        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
   2073        "MSRIndex": "0x1a6,0x1a7",
   2074        "MSRValue": "0x401",
   2075        "Offcore": "1",
   2076        "SampleAfterValue": "100000",
   2077        "UMask": "0x1"
   2078    },
   2079    {
   2080        "BriefDescription": "Offcore demand data reads satisfied by the LLC",
   2081        "Counter": "0,1,2,3",
   2082        "EventCode": "0xB7, 0xBB",
   2083        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
   2084        "MSRIndex": "0x1a6,0x1a7",
   2085        "MSRValue": "0x701",
   2086        "Offcore": "1",
   2087        "SampleAfterValue": "100000",
   2088        "UMask": "0x1"
   2089    },
   2090    {
   2091        "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
   2092        "Counter": "0,1,2,3",
   2093        "EventCode": "0xB7, 0xBB",
   2094        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
   2095        "MSRIndex": "0x1a6,0x1a7",
   2096        "MSRValue": "0x2701",
   2097        "Offcore": "1",
   2098        "SampleAfterValue": "100000",
   2099        "UMask": "0x1"
   2100    },
   2101    {
   2102        "BriefDescription": "Offcore demand data reads satisfied by a remote cache",
   2103        "Counter": "0,1,2,3",
   2104        "EventCode": "0xB7, 0xBB",
   2105        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
   2106        "MSRIndex": "0x1a6,0x1a7",
   2107        "MSRValue": "0x1801",
   2108        "Offcore": "1",
   2109        "SampleAfterValue": "100000",
   2110        "UMask": "0x1"
   2111    },
   2112    {
   2113        "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
   2114        "Counter": "0,1,2,3",
   2115        "EventCode": "0xB7, 0xBB",
   2116        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
   2117        "MSRIndex": "0x1a6,0x1a7",
   2118        "MSRValue": "0x5801",
   2119        "Offcore": "1",
   2120        "SampleAfterValue": "100000",
   2121        "UMask": "0x1"
   2122    },
   2123    {
   2124        "BriefDescription": "Offcore demand data reads that HIT in a remote cache",
   2125        "Counter": "0,1,2,3",
   2126        "EventCode": "0xB7, 0xBB",
   2127        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
   2128        "MSRIndex": "0x1a6,0x1a7",
   2129        "MSRValue": "0x1001",
   2130        "Offcore": "1",
   2131        "SampleAfterValue": "100000",
   2132        "UMask": "0x1"
   2133    },
   2134    {
   2135        "BriefDescription": "Offcore demand data reads that HITM in a remote cache",
   2136        "Counter": "0,1,2,3",
   2137        "EventCode": "0xB7, 0xBB",
   2138        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
   2139        "MSRIndex": "0x1a6,0x1a7",
   2140        "MSRValue": "0x801",
   2141        "Offcore": "1",
   2142        "SampleAfterValue": "100000",
   2143        "UMask": "0x1"
   2144    },
   2145    {
   2146        "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
   2147        "Counter": "0,1,2,3",
   2148        "EventCode": "0xB7, 0xBB",
   2149        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
   2150        "MSRIndex": "0x1a6,0x1a7",
   2151        "MSRValue": "0x7F04",
   2152        "Offcore": "1",
   2153        "SampleAfterValue": "100000",
   2154        "UMask": "0x1"
   2155    },
   2156    {
   2157        "BriefDescription": "All offcore demand code reads",
   2158        "Counter": "0,1,2,3",
   2159        "EventCode": "0xB7, 0xBB",
   2160        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
   2161        "MSRIndex": "0x1a6,0x1a7",
   2162        "MSRValue": "0xFF04",
   2163        "Offcore": "1",
   2164        "SampleAfterValue": "100000",
   2165        "UMask": "0x1"
   2166    },
   2167    {
   2168        "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
   2169        "Counter": "0,1,2,3",
   2170        "EventCode": "0xB7, 0xBB",
   2171        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
   2172        "MSRIndex": "0x1a6,0x1a7",
   2173        "MSRValue": "0x8004",
   2174        "Offcore": "1",
   2175        "SampleAfterValue": "100000",
   2176        "UMask": "0x1"
   2177    },
   2178    {
   2179        "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
   2180        "Counter": "0,1,2,3",
   2181        "EventCode": "0xB7, 0xBB",
   2182        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
   2183        "MSRIndex": "0x1a6,0x1a7",
   2184        "MSRValue": "0x104",
   2185        "Offcore": "1",
   2186        "SampleAfterValue": "100000",
   2187        "UMask": "0x1"
   2188    },
   2189    {
   2190        "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
   2191        "Counter": "0,1,2,3",
   2192        "EventCode": "0xB7, 0xBB",
   2193        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
   2194        "MSRIndex": "0x1a6,0x1a7",
   2195        "MSRValue": "0x204",
   2196        "Offcore": "1",
   2197        "SampleAfterValue": "100000",
   2198        "UMask": "0x1"
   2199    },
   2200    {
   2201        "BriefDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",
   2202        "Counter": "0,1,2,3",
   2203        "EventCode": "0xB7, 0xBB",
   2204        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
   2205        "MSRIndex": "0x1a6,0x1a7",
   2206        "MSRValue": "0x404",
   2207        "Offcore": "1",
   2208        "SampleAfterValue": "100000",
   2209        "UMask": "0x1"
   2210    },
   2211    {
   2212        "BriefDescription": "Offcore demand code reads satisfied by the LLC",
   2213        "Counter": "0,1,2,3",
   2214        "EventCode": "0xB7, 0xBB",
   2215        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
   2216        "MSRIndex": "0x1a6,0x1a7",
   2217        "MSRValue": "0x704",
   2218        "Offcore": "1",
   2219        "SampleAfterValue": "100000",
   2220        "UMask": "0x1"
   2221    },
   2222    {
   2223        "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
   2224        "Counter": "0,1,2,3",
   2225        "EventCode": "0xB7, 0xBB",
   2226        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
   2227        "MSRIndex": "0x1a6,0x1a7",
   2228        "MSRValue": "0x2704",
   2229        "Offcore": "1",
   2230        "SampleAfterValue": "100000",
   2231        "UMask": "0x1"
   2232    },
   2233    {
   2234        "BriefDescription": "Offcore demand code reads satisfied by a remote cache",
   2235        "Counter": "0,1,2,3",
   2236        "EventCode": "0xB7, 0xBB",
   2237        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
   2238        "MSRIndex": "0x1a6,0x1a7",
   2239        "MSRValue": "0x1804",
   2240        "Offcore": "1",
   2241        "SampleAfterValue": "100000",
   2242        "UMask": "0x1"
   2243    },
   2244    {
   2245        "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
   2246        "Counter": "0,1,2,3",
   2247        "EventCode": "0xB7, 0xBB",
   2248        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
   2249        "MSRIndex": "0x1a6,0x1a7",
   2250        "MSRValue": "0x5804",
   2251        "Offcore": "1",
   2252        "SampleAfterValue": "100000",
   2253        "UMask": "0x1"
   2254    },
   2255    {
   2256        "BriefDescription": "Offcore demand code reads that HIT in a remote cache",
   2257        "Counter": "0,1,2,3",
   2258        "EventCode": "0xB7, 0xBB",
   2259        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
   2260        "MSRIndex": "0x1a6,0x1a7",
   2261        "MSRValue": "0x1004",
   2262        "Offcore": "1",
   2263        "SampleAfterValue": "100000",
   2264        "UMask": "0x1"
   2265    },
   2266    {
   2267        "BriefDescription": "Offcore demand code reads that HITM in a remote cache",
   2268        "Counter": "0,1,2,3",
   2269        "EventCode": "0xB7, 0xBB",
   2270        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
   2271        "MSRIndex": "0x1a6,0x1a7",
   2272        "MSRValue": "0x804",
   2273        "Offcore": "1",
   2274        "SampleAfterValue": "100000",
   2275        "UMask": "0x1"
   2276    },
   2277    {
   2278        "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
   2279        "Counter": "0,1,2,3",
   2280        "EventCode": "0xB7, 0xBB",
   2281        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
   2282        "MSRIndex": "0x1a6,0x1a7",
   2283        "MSRValue": "0x7F02",
   2284        "Offcore": "1",
   2285        "SampleAfterValue": "100000",
   2286        "UMask": "0x1"
   2287    },
   2288    {
   2289        "BriefDescription": "All offcore demand RFO requests",
   2290        "Counter": "0,1,2,3",
   2291        "EventCode": "0xB7, 0xBB",
   2292        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
   2293        "MSRIndex": "0x1a6,0x1a7",
   2294        "MSRValue": "0xFF02",
   2295        "Offcore": "1",
   2296        "SampleAfterValue": "100000",
   2297        "UMask": "0x1"
   2298    },
   2299    {
   2300        "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
   2301        "Counter": "0,1,2,3",
   2302        "EventCode": "0xB7, 0xBB",
   2303        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
   2304        "MSRIndex": "0x1a6,0x1a7",
   2305        "MSRValue": "0x8002",
   2306        "Offcore": "1",
   2307        "SampleAfterValue": "100000",
   2308        "UMask": "0x1"
   2309    },
   2310    {
   2311        "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
   2312        "Counter": "0,1,2,3",
   2313        "EventCode": "0xB7, 0xBB",
   2314        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
   2315        "MSRIndex": "0x1a6,0x1a7",
   2316        "MSRValue": "0x102",
   2317        "Offcore": "1",
   2318        "SampleAfterValue": "100000",
   2319        "UMask": "0x1"
   2320    },
   2321    {
   2322        "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
   2323        "Counter": "0,1,2,3",
   2324        "EventCode": "0xB7, 0xBB",
   2325        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
   2326        "MSRIndex": "0x1a6,0x1a7",
   2327        "MSRValue": "0x202",
   2328        "Offcore": "1",
   2329        "SampleAfterValue": "100000",
   2330        "UMask": "0x1"
   2331    },
   2332    {
   2333        "BriefDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",
   2334        "Counter": "0,1,2,3",
   2335        "EventCode": "0xB7, 0xBB",
   2336        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
   2337        "MSRIndex": "0x1a6,0x1a7",
   2338        "MSRValue": "0x402",
   2339        "Offcore": "1",
   2340        "SampleAfterValue": "100000",
   2341        "UMask": "0x1"
   2342    },
   2343    {
   2344        "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
   2345        "Counter": "0,1,2,3",
   2346        "EventCode": "0xB7, 0xBB",
   2347        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
   2348        "MSRIndex": "0x1a6,0x1a7",
   2349        "MSRValue": "0x702",
   2350        "Offcore": "1",
   2351        "SampleAfterValue": "100000",
   2352        "UMask": "0x1"
   2353    },
   2354    {
   2355        "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
   2356        "Counter": "0,1,2,3",
   2357        "EventCode": "0xB7, 0xBB",
   2358        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
   2359        "MSRIndex": "0x1a6,0x1a7",
   2360        "MSRValue": "0x2702",
   2361        "Offcore": "1",
   2362        "SampleAfterValue": "100000",
   2363        "UMask": "0x1"
   2364    },
   2365    {
   2366        "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
   2367        "Counter": "0,1,2,3",
   2368        "EventCode": "0xB7, 0xBB",
   2369        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
   2370        "MSRIndex": "0x1a6,0x1a7",
   2371        "MSRValue": "0x1802",
   2372        "Offcore": "1",
   2373        "SampleAfterValue": "100000",
   2374        "UMask": "0x1"
   2375    },
   2376    {
   2377        "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
   2378        "Counter": "0,1,2,3",
   2379        "EventCode": "0xB7, 0xBB",
   2380        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
   2381        "MSRIndex": "0x1a6,0x1a7",
   2382        "MSRValue": "0x5802",
   2383        "Offcore": "1",
   2384        "SampleAfterValue": "100000",
   2385        "UMask": "0x1"
   2386    },
   2387    {
   2388        "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
   2389        "Counter": "0,1,2,3",
   2390        "EventCode": "0xB7, 0xBB",
   2391        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
   2392        "MSRIndex": "0x1a6,0x1a7",
   2393        "MSRValue": "0x1002",
   2394        "Offcore": "1",
   2395        "SampleAfterValue": "100000",
   2396        "UMask": "0x1"
   2397    },
   2398    {
   2399        "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
   2400        "Counter": "0,1,2,3",
   2401        "EventCode": "0xB7, 0xBB",
   2402        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
   2403        "MSRIndex": "0x1a6,0x1a7",
   2404        "MSRValue": "0x802",
   2405        "Offcore": "1",
   2406        "SampleAfterValue": "100000",
   2407        "UMask": "0x1"
   2408    },
   2409    {
   2410        "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
   2411        "Counter": "0,1,2,3",
   2412        "EventCode": "0xB7, 0xBB",
   2413        "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
   2414        "MSRIndex": "0x1a6,0x1a7",
   2415        "MSRValue": "0x7F80",
   2416        "Offcore": "1",
   2417        "SampleAfterValue": "100000",
   2418        "UMask": "0x1"
   2419    },
   2420    {
   2421        "BriefDescription": "All offcore other requests",
   2422        "Counter": "0,1,2,3",
   2423        "EventCode": "0xB7, 0xBB",
   2424        "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
   2425        "MSRIndex": "0x1a6,0x1a7",
   2426        "MSRValue": "0xFF80",
   2427        "Offcore": "1",
   2428        "SampleAfterValue": "100000",
   2429        "UMask": "0x1"
   2430    },
   2431    {
   2432        "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
   2433        "Counter": "0,1,2,3",
   2434        "EventCode": "0xB7, 0xBB",
   2435        "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
   2436        "MSRIndex": "0x1a6,0x1a7",
   2437        "MSRValue": "0x8080",
   2438        "Offcore": "1",
   2439        "SampleAfterValue": "100000",
   2440        "UMask": "0x1"
   2441    },
   2442    {
   2443        "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
   2444        "Counter": "0,1,2,3",
   2445        "EventCode": "0xB7, 0xBB",
   2446        "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
   2447        "MSRIndex": "0x1a6,0x1a7",
   2448        "MSRValue": "0x180",
   2449        "Offcore": "1",
   2450        "SampleAfterValue": "100000",
   2451        "UMask": "0x1"
   2452    },
   2453    {
   2454        "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
   2455        "Counter": "0,1,2,3",
   2456        "EventCode": "0xB7, 0xBB",
   2457        "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
   2458        "MSRIndex": "0x1a6,0x1a7",
   2459        "MSRValue": "0x280",
   2460        "Offcore": "1",
   2461        "SampleAfterValue": "100000",
   2462        "UMask": "0x1"
   2463    },
   2464    {
   2465        "BriefDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",
   2466        "Counter": "0,1,2,3",
   2467        "EventCode": "0xB7, 0xBB",
   2468        "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
   2469        "MSRIndex": "0x1a6,0x1a7",
   2470        "MSRValue": "0x480",
   2471        "Offcore": "1",
   2472        "SampleAfterValue": "100000",
   2473        "UMask": "0x1"
   2474    },
   2475    {
   2476        "BriefDescription": "Offcore other requests satisfied by the LLC",
   2477        "Counter": "0,1,2,3",
   2478        "EventCode": "0xB7, 0xBB",
   2479        "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
   2480        "MSRIndex": "0x1a6,0x1a7",
   2481        "MSRValue": "0x780",
   2482        "Offcore": "1",
   2483        "SampleAfterValue": "100000",
   2484        "UMask": "0x1"
   2485    },
   2486    {
   2487        "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
   2488        "Counter": "0,1,2,3",
   2489        "EventCode": "0xB7, 0xBB",
   2490        "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
   2491        "MSRIndex": "0x1a6,0x1a7",
   2492        "MSRValue": "0x2780",
   2493        "Offcore": "1",
   2494        "SampleAfterValue": "100000",
   2495        "UMask": "0x1"
   2496    },
   2497    {
   2498        "BriefDescription": "Offcore other requests satisfied by a remote cache",
   2499        "Counter": "0,1,2,3",
   2500        "EventCode": "0xB7, 0xBB",
   2501        "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
   2502        "MSRIndex": "0x1a6,0x1a7",
   2503        "MSRValue": "0x1880",
   2504        "Offcore": "1",
   2505        "SampleAfterValue": "100000",
   2506        "UMask": "0x1"
   2507    },
   2508    {
   2509        "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
   2510        "Counter": "0,1,2,3",
   2511        "EventCode": "0xB7, 0xBB",
   2512        "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
   2513        "MSRIndex": "0x1a6,0x1a7",
   2514        "MSRValue": "0x5880",
   2515        "Offcore": "1",
   2516        "SampleAfterValue": "100000",
   2517        "UMask": "0x1"
   2518    },
   2519    {
   2520        "BriefDescription": "Offcore other requests that HIT in a remote cache",
   2521        "Counter": "0,1,2,3",
   2522        "EventCode": "0xB7, 0xBB",
   2523        "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
   2524        "MSRIndex": "0x1a6,0x1a7",
   2525        "MSRValue": "0x1080",
   2526        "Offcore": "1",
   2527        "SampleAfterValue": "100000",
   2528        "UMask": "0x1"
   2529    },
   2530    {
   2531        "BriefDescription": "Offcore other requests that HITM in a remote cache",
   2532        "Counter": "0,1,2,3",
   2533        "EventCode": "0xB7, 0xBB",
   2534        "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
   2535        "MSRIndex": "0x1a6,0x1a7",
   2536        "MSRValue": "0x880",
   2537        "Offcore": "1",
   2538        "SampleAfterValue": "100000",
   2539        "UMask": "0x1"
   2540    },
   2541    {
   2542        "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
   2543        "Counter": "0,1,2,3",
   2544        "EventCode": "0xB7, 0xBB",
   2545        "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
   2546        "MSRIndex": "0x1a6,0x1a7",
   2547        "MSRValue": "0x7F50",
   2548        "Offcore": "1",
   2549        "SampleAfterValue": "100000",
   2550        "UMask": "0x1"
   2551    },
   2552    {
   2553        "BriefDescription": "All offcore prefetch data requests",
   2554        "Counter": "0,1,2,3",
   2555        "EventCode": "0xB7, 0xBB",
   2556        "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
   2557        "MSRIndex": "0x1a6,0x1a7",
   2558        "MSRValue": "0xFF50",
   2559        "Offcore": "1",
   2560        "SampleAfterValue": "100000",
   2561        "UMask": "0x1"
   2562    },
   2563    {
   2564        "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
   2565        "Counter": "0,1,2,3",
   2566        "EventCode": "0xB7, 0xBB",
   2567        "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
   2568        "MSRIndex": "0x1a6,0x1a7",
   2569        "MSRValue": "0x8050",
   2570        "Offcore": "1",
   2571        "SampleAfterValue": "100000",
   2572        "UMask": "0x1"
   2573    },
   2574    {
   2575        "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
   2576        "Counter": "0,1,2,3",
   2577        "EventCode": "0xB7, 0xBB",
   2578        "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
   2579        "MSRIndex": "0x1a6,0x1a7",
   2580        "MSRValue": "0x150",
   2581        "Offcore": "1",
   2582        "SampleAfterValue": "100000",
   2583        "UMask": "0x1"
   2584    },
   2585    {
   2586        "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
   2587        "Counter": "0,1,2,3",
   2588        "EventCode": "0xB7, 0xBB",
   2589        "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
   2590        "MSRIndex": "0x1a6,0x1a7",
   2591        "MSRValue": "0x250",
   2592        "Offcore": "1",
   2593        "SampleAfterValue": "100000",
   2594        "UMask": "0x1"
   2595    },
   2596    {
   2597        "BriefDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",
   2598        "Counter": "0,1,2,3",
   2599        "EventCode": "0xB7, 0xBB",
   2600        "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
   2601        "MSRIndex": "0x1a6,0x1a7",
   2602        "MSRValue": "0x450",
   2603        "Offcore": "1",
   2604        "SampleAfterValue": "100000",
   2605        "UMask": "0x1"
   2606    },
   2607    {
   2608        "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
   2609        "Counter": "0,1,2,3",
   2610        "EventCode": "0xB7, 0xBB",
   2611        "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
   2612        "MSRIndex": "0x1a6,0x1a7",
   2613        "MSRValue": "0x750",
   2614        "Offcore": "1",
   2615        "SampleAfterValue": "100000",
   2616        "UMask": "0x1"
   2617    },
   2618    {
   2619        "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
   2620        "Counter": "0,1,2,3",
   2621        "EventCode": "0xB7, 0xBB",
   2622        "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
   2623        "MSRIndex": "0x1a6,0x1a7",
   2624        "MSRValue": "0x2750",
   2625        "Offcore": "1",
   2626        "SampleAfterValue": "100000",
   2627        "UMask": "0x1"
   2628    },
   2629    {
   2630        "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
   2631        "Counter": "0,1,2,3",
   2632        "EventCode": "0xB7, 0xBB",
   2633        "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
   2634        "MSRIndex": "0x1a6,0x1a7",
   2635        "MSRValue": "0x1850",
   2636        "Offcore": "1",
   2637        "SampleAfterValue": "100000",
   2638        "UMask": "0x1"
   2639    },
   2640    {
   2641        "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
   2642        "Counter": "0,1,2,3",
   2643        "EventCode": "0xB7, 0xBB",
   2644        "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
   2645        "MSRIndex": "0x1a6,0x1a7",
   2646        "MSRValue": "0x5850",
   2647        "Offcore": "1",
   2648        "SampleAfterValue": "100000",
   2649        "UMask": "0x1"
   2650    },
   2651    {
   2652        "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
   2653        "Counter": "0,1,2,3",
   2654        "EventCode": "0xB7, 0xBB",
   2655        "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
   2656        "MSRIndex": "0x1a6,0x1a7",
   2657        "MSRValue": "0x1050",
   2658        "Offcore": "1",
   2659        "SampleAfterValue": "100000",
   2660        "UMask": "0x1"
   2661    },
   2662    {
   2663        "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
   2664        "Counter": "0,1,2,3",
   2665        "EventCode": "0xB7, 0xBB",
   2666        "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
   2667        "MSRIndex": "0x1a6,0x1a7",
   2668        "MSRValue": "0x850",
   2669        "Offcore": "1",
   2670        "SampleAfterValue": "100000",
   2671        "UMask": "0x1"
   2672    },
   2673    {
   2674        "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
   2675        "Counter": "0,1,2,3",
   2676        "EventCode": "0xB7, 0xBB",
   2677        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
   2678        "MSRIndex": "0x1a6,0x1a7",
   2679        "MSRValue": "0x7F10",
   2680        "Offcore": "1",
   2681        "SampleAfterValue": "100000",
   2682        "UMask": "0x1"
   2683    },
   2684    {
   2685        "BriefDescription": "All offcore prefetch data reads",
   2686        "Counter": "0,1,2,3",
   2687        "EventCode": "0xB7, 0xBB",
   2688        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
   2689        "MSRIndex": "0x1a6,0x1a7",
   2690        "MSRValue": "0xFF10",
   2691        "Offcore": "1",
   2692        "SampleAfterValue": "100000",
   2693        "UMask": "0x1"
   2694    },
   2695    {
   2696        "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
   2697        "Counter": "0,1,2,3",
   2698        "EventCode": "0xB7, 0xBB",
   2699        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
   2700        "MSRIndex": "0x1a6,0x1a7",
   2701        "MSRValue": "0x8010",
   2702        "Offcore": "1",
   2703        "SampleAfterValue": "100000",
   2704        "UMask": "0x1"
   2705    },
   2706    {
   2707        "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
   2708        "Counter": "0,1,2,3",
   2709        "EventCode": "0xB7, 0xBB",
   2710        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
   2711        "MSRIndex": "0x1a6,0x1a7",
   2712        "MSRValue": "0x110",
   2713        "Offcore": "1",
   2714        "SampleAfterValue": "100000",
   2715        "UMask": "0x1"
   2716    },
   2717    {
   2718        "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
   2719        "Counter": "0,1,2,3",
   2720        "EventCode": "0xB7, 0xBB",
   2721        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
   2722        "MSRIndex": "0x1a6,0x1a7",
   2723        "MSRValue": "0x210",
   2724        "Offcore": "1",
   2725        "SampleAfterValue": "100000",
   2726        "UMask": "0x1"
   2727    },
   2728    {
   2729        "BriefDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",
   2730        "Counter": "0,1,2,3",
   2731        "EventCode": "0xB7, 0xBB",
   2732        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
   2733        "MSRIndex": "0x1a6,0x1a7",
   2734        "MSRValue": "0x410",
   2735        "Offcore": "1",
   2736        "SampleAfterValue": "100000",
   2737        "UMask": "0x1"
   2738    },
   2739    {
   2740        "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
   2741        "Counter": "0,1,2,3",
   2742        "EventCode": "0xB7, 0xBB",
   2743        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
   2744        "MSRIndex": "0x1a6,0x1a7",
   2745        "MSRValue": "0x710",
   2746        "Offcore": "1",
   2747        "SampleAfterValue": "100000",
   2748        "UMask": "0x1"
   2749    },
   2750    {
   2751        "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
   2752        "Counter": "0,1,2,3",
   2753        "EventCode": "0xB7, 0xBB",
   2754        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
   2755        "MSRIndex": "0x1a6,0x1a7",
   2756        "MSRValue": "0x2710",
   2757        "Offcore": "1",
   2758        "SampleAfterValue": "100000",
   2759        "UMask": "0x1"
   2760    },
   2761    {
   2762        "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
   2763        "Counter": "0,1,2,3",
   2764        "EventCode": "0xB7, 0xBB",
   2765        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
   2766        "MSRIndex": "0x1a6,0x1a7",
   2767        "MSRValue": "0x1810",
   2768        "Offcore": "1",
   2769        "SampleAfterValue": "100000",
   2770        "UMask": "0x1"
   2771    },
   2772    {
   2773        "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
   2774        "Counter": "0,1,2,3",
   2775        "EventCode": "0xB7, 0xBB",
   2776        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
   2777        "MSRIndex": "0x1a6,0x1a7",
   2778        "MSRValue": "0x5810",
   2779        "Offcore": "1",
   2780        "SampleAfterValue": "100000",
   2781        "UMask": "0x1"
   2782    },
   2783    {
   2784        "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
   2785        "Counter": "0,1,2,3",
   2786        "EventCode": "0xB7, 0xBB",
   2787        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
   2788        "MSRIndex": "0x1a6,0x1a7",
   2789        "MSRValue": "0x1010",
   2790        "Offcore": "1",
   2791        "SampleAfterValue": "100000",
   2792        "UMask": "0x1"
   2793    },
   2794    {
   2795        "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
   2796        "Counter": "0,1,2,3",
   2797        "EventCode": "0xB7, 0xBB",
   2798        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
   2799        "MSRIndex": "0x1a6,0x1a7",
   2800        "MSRValue": "0x810",
   2801        "Offcore": "1",
   2802        "SampleAfterValue": "100000",
   2803        "UMask": "0x1"
   2804    },
   2805    {
   2806        "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
   2807        "Counter": "0,1,2,3",
   2808        "EventCode": "0xB7, 0xBB",
   2809        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
   2810        "MSRIndex": "0x1a6,0x1a7",
   2811        "MSRValue": "0x7F40",
   2812        "Offcore": "1",
   2813        "SampleAfterValue": "100000",
   2814        "UMask": "0x1"
   2815    },
   2816    {
   2817        "BriefDescription": "All offcore prefetch code reads",
   2818        "Counter": "0,1,2,3",
   2819        "EventCode": "0xB7, 0xBB",
   2820        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
   2821        "MSRIndex": "0x1a6,0x1a7",
   2822        "MSRValue": "0xFF40",
   2823        "Offcore": "1",
   2824        "SampleAfterValue": "100000",
   2825        "UMask": "0x1"
   2826    },
   2827    {
   2828        "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
   2829        "Counter": "0,1,2,3",
   2830        "EventCode": "0xB7, 0xBB",
   2831        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
   2832        "MSRIndex": "0x1a6,0x1a7",
   2833        "MSRValue": "0x8040",
   2834        "Offcore": "1",
   2835        "SampleAfterValue": "100000",
   2836        "UMask": "0x1"
   2837    },
   2838    {
   2839        "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
   2840        "Counter": "0,1,2,3",
   2841        "EventCode": "0xB7, 0xBB",
   2842        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
   2843        "MSRIndex": "0x1a6,0x1a7",
   2844        "MSRValue": "0x140",
   2845        "Offcore": "1",
   2846        "SampleAfterValue": "100000",
   2847        "UMask": "0x1"
   2848    },
   2849    {
   2850        "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
   2851        "Counter": "0,1,2,3",
   2852        "EventCode": "0xB7, 0xBB",
   2853        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
   2854        "MSRIndex": "0x1a6,0x1a7",
   2855        "MSRValue": "0x240",
   2856        "Offcore": "1",
   2857        "SampleAfterValue": "100000",
   2858        "UMask": "0x1"
   2859    },
   2860    {
   2861        "BriefDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",
   2862        "Counter": "0,1,2,3",
   2863        "EventCode": "0xB7, 0xBB",
   2864        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
   2865        "MSRIndex": "0x1a6,0x1a7",
   2866        "MSRValue": "0x440",
   2867        "Offcore": "1",
   2868        "SampleAfterValue": "100000",
   2869        "UMask": "0x1"
   2870    },
   2871    {
   2872        "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
   2873        "Counter": "0,1,2,3",
   2874        "EventCode": "0xB7, 0xBB",
   2875        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
   2876        "MSRIndex": "0x1a6,0x1a7",
   2877        "MSRValue": "0x740",
   2878        "Offcore": "1",
   2879        "SampleAfterValue": "100000",
   2880        "UMask": "0x1"
   2881    },
   2882    {
   2883        "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
   2884        "Counter": "0,1,2,3",
   2885        "EventCode": "0xB7, 0xBB",
   2886        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
   2887        "MSRIndex": "0x1a6,0x1a7",
   2888        "MSRValue": "0x2740",
   2889        "Offcore": "1",
   2890        "SampleAfterValue": "100000",
   2891        "UMask": "0x1"
   2892    },
   2893    {
   2894        "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
   2895        "Counter": "0,1,2,3",
   2896        "EventCode": "0xB7, 0xBB",
   2897        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
   2898        "MSRIndex": "0x1a6,0x1a7",
   2899        "MSRValue": "0x1840",
   2900        "Offcore": "1",
   2901        "SampleAfterValue": "100000",
   2902        "UMask": "0x1"
   2903    },
   2904    {
   2905        "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
   2906        "Counter": "0,1,2,3",
   2907        "EventCode": "0xB7, 0xBB",
   2908        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
   2909        "MSRIndex": "0x1a6,0x1a7",
   2910        "MSRValue": "0x5840",
   2911        "Offcore": "1",
   2912        "SampleAfterValue": "100000",
   2913        "UMask": "0x1"
   2914    },
   2915    {
   2916        "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
   2917        "Counter": "0,1,2,3",
   2918        "EventCode": "0xB7, 0xBB",
   2919        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
   2920        "MSRIndex": "0x1a6,0x1a7",
   2921        "MSRValue": "0x1040",
   2922        "Offcore": "1",
   2923        "SampleAfterValue": "100000",
   2924        "UMask": "0x1"
   2925    },
   2926    {
   2927        "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
   2928        "Counter": "0,1,2,3",
   2929        "EventCode": "0xB7, 0xBB",
   2930        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
   2931        "MSRIndex": "0x1a6,0x1a7",
   2932        "MSRValue": "0x840",
   2933        "Offcore": "1",
   2934        "SampleAfterValue": "100000",
   2935        "UMask": "0x1"
   2936    },
   2937    {
   2938        "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
   2939        "Counter": "0,1,2,3",
   2940        "EventCode": "0xB7, 0xBB",
   2941        "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
   2942        "MSRIndex": "0x1a6,0x1a7",
   2943        "MSRValue": "0x7F20",
   2944        "Offcore": "1",
   2945        "SampleAfterValue": "100000",
   2946        "UMask": "0x1"
   2947    },
   2948    {
   2949        "BriefDescription": "All offcore prefetch RFO requests",
   2950        "Counter": "0,1,2,3",
   2951        "EventCode": "0xB7, 0xBB",
   2952        "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
   2953        "MSRIndex": "0x1a6,0x1a7",
   2954        "MSRValue": "0xFF20",
   2955        "Offcore": "1",
   2956        "SampleAfterValue": "100000",
   2957        "UMask": "0x1"
   2958    },
   2959    {
   2960        "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
   2961        "Counter": "0,1,2,3",
   2962        "EventCode": "0xB7, 0xBB",
   2963        "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
   2964        "MSRIndex": "0x1a6,0x1a7",
   2965        "MSRValue": "0x8020",
   2966        "Offcore": "1",
   2967        "SampleAfterValue": "100000",
   2968        "UMask": "0x1"
   2969    },
   2970    {
   2971        "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
   2972        "Counter": "0,1,2,3",
   2973        "EventCode": "0xB7, 0xBB",
   2974        "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
   2975        "MSRIndex": "0x1a6,0x1a7",
   2976        "MSRValue": "0x120",
   2977        "Offcore": "1",
   2978        "SampleAfterValue": "100000",
   2979        "UMask": "0x1"
   2980    },
   2981    {
   2982        "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
   2983        "Counter": "0,1,2,3",
   2984        "EventCode": "0xB7, 0xBB",
   2985        "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
   2986        "MSRIndex": "0x1a6,0x1a7",
   2987        "MSRValue": "0x220",
   2988        "Offcore": "1",
   2989        "SampleAfterValue": "100000",
   2990        "UMask": "0x1"
   2991    },
   2992    {
   2993        "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",
   2994        "Counter": "0,1,2,3",
   2995        "EventCode": "0xB7, 0xBB",
   2996        "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
   2997        "MSRIndex": "0x1a6,0x1a7",
   2998        "MSRValue": "0x420",
   2999        "Offcore": "1",
   3000        "SampleAfterValue": "100000",
   3001        "UMask": "0x1"
   3002    },
   3003    {
   3004        "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
   3005        "Counter": "0,1,2,3",
   3006        "EventCode": "0xB7, 0xBB",
   3007        "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
   3008        "MSRIndex": "0x1a6,0x1a7",
   3009        "MSRValue": "0x720",
   3010        "Offcore": "1",
   3011        "SampleAfterValue": "100000",
   3012        "UMask": "0x1"
   3013    },
   3014    {
   3015        "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
   3016        "Counter": "0,1,2,3",
   3017        "EventCode": "0xB7, 0xBB",
   3018        "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
   3019        "MSRIndex": "0x1a6,0x1a7",
   3020        "MSRValue": "0x2720",
   3021        "Offcore": "1",
   3022        "SampleAfterValue": "100000",
   3023        "UMask": "0x1"
   3024    },
   3025    {
   3026        "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
   3027        "Counter": "0,1,2,3",
   3028        "EventCode": "0xB7, 0xBB",
   3029        "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
   3030        "MSRIndex": "0x1a6,0x1a7",
   3031        "MSRValue": "0x1820",
   3032        "Offcore": "1",
   3033        "SampleAfterValue": "100000",
   3034        "UMask": "0x1"
   3035    },
   3036    {
   3037        "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
   3038        "Counter": "0,1,2,3",
   3039        "EventCode": "0xB7, 0xBB",
   3040        "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
   3041        "MSRIndex": "0x1a6,0x1a7",
   3042        "MSRValue": "0x5820",
   3043        "Offcore": "1",
   3044        "SampleAfterValue": "100000",
   3045        "UMask": "0x1"
   3046    },
   3047    {
   3048        "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
   3049        "Counter": "0,1,2,3",
   3050        "EventCode": "0xB7, 0xBB",
   3051        "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
   3052        "MSRIndex": "0x1a6,0x1a7",
   3053        "MSRValue": "0x1020",
   3054        "Offcore": "1",
   3055        "SampleAfterValue": "100000",
   3056        "UMask": "0x1"
   3057    },
   3058    {
   3059        "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
   3060        "Counter": "0,1,2,3",
   3061        "EventCode": "0xB7, 0xBB",
   3062        "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
   3063        "MSRIndex": "0x1a6,0x1a7",
   3064        "MSRValue": "0x820",
   3065        "Offcore": "1",
   3066        "SampleAfterValue": "100000",
   3067        "UMask": "0x1"
   3068    },
   3069    {
   3070        "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
   3071        "Counter": "0,1,2,3",
   3072        "EventCode": "0xB7, 0xBB",
   3073        "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
   3074        "MSRIndex": "0x1a6,0x1a7",
   3075        "MSRValue": "0x7F70",
   3076        "Offcore": "1",
   3077        "SampleAfterValue": "100000",
   3078        "UMask": "0x1"
   3079    },
   3080    {
   3081        "BriefDescription": "All offcore prefetch requests",
   3082        "Counter": "0,1,2,3",
   3083        "EventCode": "0xB7, 0xBB",
   3084        "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
   3085        "MSRIndex": "0x1a6,0x1a7",
   3086        "MSRValue": "0xFF70",
   3087        "Offcore": "1",
   3088        "SampleAfterValue": "100000",
   3089        "UMask": "0x1"
   3090    },
   3091    {
   3092        "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
   3093        "Counter": "0,1,2,3",
   3094        "EventCode": "0xB7, 0xBB",
   3095        "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
   3096        "MSRIndex": "0x1a6,0x1a7",
   3097        "MSRValue": "0x8070",
   3098        "Offcore": "1",
   3099        "SampleAfterValue": "100000",
   3100        "UMask": "0x1"
   3101    },
   3102    {
   3103        "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
   3104        "Counter": "0,1,2,3",
   3105        "EventCode": "0xB7, 0xBB",
   3106        "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
   3107        "MSRIndex": "0x1a6,0x1a7",
   3108        "MSRValue": "0x170",
   3109        "Offcore": "1",
   3110        "SampleAfterValue": "100000",
   3111        "UMask": "0x1"
   3112    },
   3113    {
   3114        "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
   3115        "Counter": "0,1,2,3",
   3116        "EventCode": "0xB7, 0xBB",
   3117        "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
   3118        "MSRIndex": "0x1a6,0x1a7",
   3119        "MSRValue": "0x270",
   3120        "Offcore": "1",
   3121        "SampleAfterValue": "100000",
   3122        "UMask": "0x1"
   3123    },
   3124    {
   3125        "BriefDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",
   3126        "Counter": "0,1,2,3",
   3127        "EventCode": "0xB7, 0xBB",
   3128        "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
   3129        "MSRIndex": "0x1a6,0x1a7",
   3130        "MSRValue": "0x470",
   3131        "Offcore": "1",
   3132        "SampleAfterValue": "100000",
   3133        "UMask": "0x1"
   3134    },
   3135    {
   3136        "BriefDescription": "Offcore prefetch requests satisfied by the LLC",
   3137        "Counter": "0,1,2,3",
   3138        "EventCode": "0xB7, 0xBB",
   3139        "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
   3140        "MSRIndex": "0x1a6,0x1a7",
   3141        "MSRValue": "0x770",
   3142        "Offcore": "1",
   3143        "SampleAfterValue": "100000",
   3144        "UMask": "0x1"
   3145    },
   3146    {
   3147        "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
   3148        "Counter": "0,1,2,3",
   3149        "EventCode": "0xB7, 0xBB",
   3150        "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
   3151        "MSRIndex": "0x1a6,0x1a7",
   3152        "MSRValue": "0x2770",
   3153        "Offcore": "1",
   3154        "SampleAfterValue": "100000",
   3155        "UMask": "0x1"
   3156    },
   3157    {
   3158        "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
   3159        "Counter": "0,1,2,3",
   3160        "EventCode": "0xB7, 0xBB",
   3161        "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
   3162        "MSRIndex": "0x1a6,0x1a7",
   3163        "MSRValue": "0x1870",
   3164        "Offcore": "1",
   3165        "SampleAfterValue": "100000",
   3166        "UMask": "0x1"
   3167    },
   3168    {
   3169        "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
   3170        "Counter": "0,1,2,3",
   3171        "EventCode": "0xB7, 0xBB",
   3172        "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
   3173        "MSRIndex": "0x1a6,0x1a7",
   3174        "MSRValue": "0x5870",
   3175        "Offcore": "1",
   3176        "SampleAfterValue": "100000",
   3177        "UMask": "0x1"
   3178    },
   3179    {
   3180        "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
   3181        "Counter": "0,1,2,3",
   3182        "EventCode": "0xB7, 0xBB",
   3183        "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
   3184        "MSRIndex": "0x1a6,0x1a7",
   3185        "MSRValue": "0x1070",
   3186        "Offcore": "1",
   3187        "SampleAfterValue": "100000",
   3188        "UMask": "0x1"
   3189    },
   3190    {
   3191        "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
   3192        "Counter": "0,1,2,3",
   3193        "EventCode": "0xB7, 0xBB",
   3194        "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
   3195        "MSRIndex": "0x1a6,0x1a7",
   3196        "MSRValue": "0x870",
   3197        "Offcore": "1",
   3198        "SampleAfterValue": "100000",
   3199        "UMask": "0x1"
   3200    },
   3201    {
   3202        "BriefDescription": "Super Queue LRU hints sent to LLC",
   3203        "Counter": "0,1,2,3",
   3204        "EventCode": "0xF4",
   3205        "EventName": "SQ_MISC.LRU_HINTS",
   3206        "SampleAfterValue": "2000000",
   3207        "UMask": "0x4"
   3208    },
   3209    {
   3210        "BriefDescription": "Super Queue lock splits across a cache line",
   3211        "Counter": "0,1,2,3",
   3212        "EventCode": "0xF4",
   3213        "EventName": "SQ_MISC.SPLIT_LOCK",
   3214        "SampleAfterValue": "2000000",
   3215        "UMask": "0x10"
   3216    },
   3217    {
   3218        "BriefDescription": "Loads delayed with at-Retirement block code",
   3219        "Counter": "0,1,2,3",
   3220        "EventCode": "0x6",
   3221        "EventName": "STORE_BLOCKS.AT_RET",
   3222        "SampleAfterValue": "200000",
   3223        "UMask": "0x4"
   3224    },
   3225    {
   3226        "BriefDescription": "Cacheable loads delayed with L1D block code",
   3227        "Counter": "0,1,2,3",
   3228        "EventCode": "0x6",
   3229        "EventName": "STORE_BLOCKS.L1D_BLOCK",
   3230        "SampleAfterValue": "200000",
   3231        "UMask": "0x8"
   3232    }
   3233]