cs-etm.h (6732B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright(C) 2015 Linaro Limited. All rights reserved. 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5 */ 6 7#ifndef INCLUDE__UTIL_PERF_CS_ETM_H__ 8#define INCLUDE__UTIL_PERF_CS_ETM_H__ 9 10#include "util/event.h" 11#include <linux/bits.h> 12 13struct perf_session; 14 15/* 16 * Versioning header in case things need to change in the future. That way 17 * decoding of old snapshot is still possible. 18 */ 19enum { 20 /* Starting with 0x0 */ 21 CS_HEADER_VERSION, 22 /* PMU->type (32 bit), total # of CPUs (32 bit) */ 23 CS_PMU_TYPE_CPUS, 24 CS_ETM_SNAPSHOT, 25 CS_HEADER_VERSION_MAX, 26}; 27 28/* 29 * Update the version for new format. 30 * 31 * New version 1 format adds a param count to the per cpu metadata. 32 * This allows easy adding of new metadata parameters. 33 * Requires that new params always added after current ones. 34 * Also allows client reader to handle file versions that are different by 35 * checking the number of params in the file vs the number expected. 36 */ 37#define CS_HEADER_CURRENT_VERSION 1 38 39/* Beginning of header common to both ETMv3 and V4 */ 40enum { 41 CS_ETM_MAGIC, 42 CS_ETM_CPU, 43 /* Number of trace config params in following ETM specific block */ 44 CS_ETM_NR_TRC_PARAMS, 45 CS_ETM_COMMON_BLK_MAX_V1, 46}; 47 48/* ETMv3/PTM metadata */ 49enum { 50 /* Dynamic, configurable parameters */ 51 CS_ETM_ETMCR = CS_ETM_COMMON_BLK_MAX_V1, 52 CS_ETM_ETMTRACEIDR, 53 /* RO, taken from sysFS */ 54 CS_ETM_ETMCCER, 55 CS_ETM_ETMIDR, 56 CS_ETM_PRIV_MAX, 57}; 58 59/* define fixed version 0 length - allow new format reader to read old files. */ 60#define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1) 61 62/* ETMv4 metadata */ 63enum { 64 /* Dynamic, configurable parameters */ 65 CS_ETMV4_TRCCONFIGR = CS_ETM_COMMON_BLK_MAX_V1, 66 CS_ETMV4_TRCTRACEIDR, 67 /* RO, taken from sysFS */ 68 CS_ETMV4_TRCIDR0, 69 CS_ETMV4_TRCIDR1, 70 CS_ETMV4_TRCIDR2, 71 CS_ETMV4_TRCIDR8, 72 CS_ETMV4_TRCAUTHSTATUS, 73 CS_ETMV4_PRIV_MAX, 74}; 75 76/* define fixed version 0 length - allow new format reader to read old files. */ 77#define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1) 78 79/* 80 * ETE metadata is ETMv4 plus TRCDEVARCH register and doesn't support header V0 since it was 81 * added in header V1 82 */ 83enum { 84 CS_ETE_TRCDEVARCH = CS_ETMV4_PRIV_MAX, 85 CS_ETE_PRIV_MAX 86}; 87 88/* 89 * ETMv3 exception encoding number: 90 * See Embedded Trace Macrocell specification (ARM IHI 0014Q) 91 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors. 92 */ 93enum { 94 CS_ETMV3_EXC_NONE = 0, 95 CS_ETMV3_EXC_DEBUG_HALT = 1, 96 CS_ETMV3_EXC_SMC = 2, 97 CS_ETMV3_EXC_HYP = 3, 98 CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4, 99 CS_ETMV3_EXC_JAZELLE_THUMBEE = 5, 100 CS_ETMV3_EXC_PE_RESET = 8, 101 CS_ETMV3_EXC_UNDEFINED_INSTR = 9, 102 CS_ETMV3_EXC_SVC = 10, 103 CS_ETMV3_EXC_PREFETCH_ABORT = 11, 104 CS_ETMV3_EXC_DATA_FAULT = 12, 105 CS_ETMV3_EXC_GENERIC = 13, 106 CS_ETMV3_EXC_IRQ = 14, 107 CS_ETMV3_EXC_FIQ = 15, 108}; 109 110/* 111 * ETMv4 exception encoding number: 112 * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D) 113 * table 6-12 Possible values for the TYPE field in an Exception instruction 114 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs. 115 */ 116enum { 117 CS_ETMV4_EXC_RESET = 0, 118 CS_ETMV4_EXC_DEBUG_HALT = 1, 119 CS_ETMV4_EXC_CALL = 2, 120 CS_ETMV4_EXC_TRAP = 3, 121 CS_ETMV4_EXC_SYSTEM_ERROR = 4, 122 CS_ETMV4_EXC_INST_DEBUG = 6, 123 CS_ETMV4_EXC_DATA_DEBUG = 7, 124 CS_ETMV4_EXC_ALIGNMENT = 10, 125 CS_ETMV4_EXC_INST_FAULT = 11, 126 CS_ETMV4_EXC_DATA_FAULT = 12, 127 CS_ETMV4_EXC_IRQ = 14, 128 CS_ETMV4_EXC_FIQ = 15, 129 CS_ETMV4_EXC_END = 31, 130}; 131 132enum cs_etm_sample_type { 133 CS_ETM_EMPTY, 134 CS_ETM_RANGE, 135 CS_ETM_DISCONTINUITY, 136 CS_ETM_EXCEPTION, 137 CS_ETM_EXCEPTION_RET, 138}; 139 140enum cs_etm_isa { 141 CS_ETM_ISA_UNKNOWN, 142 CS_ETM_ISA_A64, 143 CS_ETM_ISA_A32, 144 CS_ETM_ISA_T32, 145}; 146 147struct cs_etm_queue; 148 149struct cs_etm_packet { 150 enum cs_etm_sample_type sample_type; 151 enum cs_etm_isa isa; 152 u64 start_addr; 153 u64 end_addr; 154 u32 instr_count; 155 u32 last_instr_type; 156 u32 last_instr_subtype; 157 u32 flags; 158 u32 exception_number; 159 u8 last_instr_cond; 160 u8 last_instr_taken_branch; 161 u8 last_instr_size; 162 u8 trace_chan_id; 163 int cpu; 164}; 165 166#define CS_ETM_PACKET_MAX_BUFFER 1024 167 168/* 169 * When working with per-thread scenarios the process under trace can 170 * be scheduled on any CPU and as such, more than one traceID may be 171 * associated with the same process. Since a traceID of '0' is illegal 172 * as per the CoreSight architecture, use that specific value to 173 * identify the queue where all packets (with any traceID) are 174 * aggregated. 175 */ 176#define CS_ETM_PER_THREAD_TRACEID 0 177 178struct cs_etm_packet_queue { 179 u32 packet_count; 180 u32 head; 181 u32 tail; 182 u32 instr_count; 183 u64 cs_timestamp; 184 u64 next_cs_timestamp; 185 struct cs_etm_packet packet_buffer[CS_ETM_PACKET_MAX_BUFFER]; 186}; 187 188#define KiB(x) ((x) * 1024) 189#define MiB(x) ((x) * 1024 * 1024) 190 191#define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL 192 193#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) 194 195#define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_MAX * sizeof(u64)) 196 197#define __perf_cs_etmv3_magic 0x3030303030303030ULL 198#define __perf_cs_etmv4_magic 0x4040404040404040ULL 199#define __perf_cs_ete_magic 0x5050505050505050ULL 200#define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64)) 201#define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64)) 202#define CS_ETE_PRIV_SIZE (CS_ETE_PRIV_MAX * sizeof(u64)) 203 204#ifdef HAVE_CSTRACE_SUPPORT 205int cs_etm__process_auxtrace_info(union perf_event *event, 206 struct perf_session *session); 207int cs_etm__get_cpu(u8 trace_chan_id, int *cpu); 208int cs_etm__get_pid_fmt(u8 trace_chan_id, u64 *pid_fmt); 209int cs_etm__etmq_set_tid(struct cs_etm_queue *etmq, 210 pid_t tid, u8 trace_chan_id); 211bool cs_etm__etmq_is_timeless(struct cs_etm_queue *etmq); 212void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, 213 u8 trace_chan_id); 214struct cs_etm_packet_queue 215*cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id); 216#else 217static inline int 218cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused, 219 struct perf_session *session __maybe_unused) 220{ 221 return -1; 222} 223 224static inline int cs_etm__get_cpu(u8 trace_chan_id __maybe_unused, 225 int *cpu __maybe_unused) 226{ 227 return -1; 228} 229 230static inline int cs_etm__etmq_set_tid( 231 struct cs_etm_queue *etmq __maybe_unused, 232 pid_t tid __maybe_unused, 233 u8 trace_chan_id __maybe_unused) 234{ 235 return -1; 236} 237 238static inline bool cs_etm__etmq_is_timeless( 239 struct cs_etm_queue *etmq __maybe_unused) 240{ 241 /* What else to return? */ 242 return true; 243} 244 245static inline void cs_etm__etmq_set_traceid_queue_timestamp( 246 struct cs_etm_queue *etmq __maybe_unused, 247 u8 trace_chan_id __maybe_unused) {} 248 249static inline struct cs_etm_packet_queue *cs_etm__etmq_get_packet_queue( 250 struct cs_etm_queue *etmq __maybe_unused, 251 u8 trace_chan_id __maybe_unused) 252{ 253 return NULL; 254} 255#endif 256 257#endif