gic.h (1483B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * ARM Generic Interrupt Controller (GIC) specific defines 4 */ 5 6#ifndef SELFTEST_KVM_GIC_H 7#define SELFTEST_KVM_GIC_H 8 9enum gic_type { 10 GIC_V3, 11 GIC_TYPE_MAX, 12}; 13 14#define MIN_SGI 0 15#define MIN_PPI 16 16#define MIN_SPI 32 17#define MAX_SPI 1019 18#define IAR_SPURIOUS 1023 19 20#define INTID_IS_SGI(intid) (0 <= (intid) && (intid) < MIN_PPI) 21#define INTID_IS_PPI(intid) (MIN_PPI <= (intid) && (intid) < MIN_SPI) 22#define INTID_IS_SPI(intid) (MIN_SPI <= (intid) && (intid) <= MAX_SPI) 23 24void gic_init(enum gic_type type, unsigned int nr_cpus, 25 void *dist_base, void *redist_base); 26void gic_irq_enable(unsigned int intid); 27void gic_irq_disable(unsigned int intid); 28unsigned int gic_get_and_ack_irq(void); 29void gic_set_eoi(unsigned int intid); 30void gic_set_dir(unsigned int intid); 31 32/* 33 * Sets the EOI mode. When split is false, EOI just drops the priority. When 34 * split is true, EOI drops the priority and deactivates the interrupt. 35 */ 36void gic_set_eoi_split(bool split); 37void gic_set_priority_mask(uint64_t mask); 38void gic_set_priority(uint32_t intid, uint32_t prio); 39void gic_irq_set_active(unsigned int intid); 40void gic_irq_clear_active(unsigned int intid); 41bool gic_irq_get_active(unsigned int intid); 42void gic_irq_set_pending(unsigned int intid); 43void gic_irq_clear_pending(unsigned int intid); 44bool gic_irq_get_pending(unsigned int intid); 45void gic_irq_set_config(unsigned int intid, bool is_edge); 46 47#endif /* SELFTEST_KVM_GIC_H */