gic_v3.h (2230B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * ARM Generic Interrupt Controller (GIC) v3 specific defines 4 */ 5 6#ifndef SELFTEST_KVM_GICV3_H 7#define SELFTEST_KVM_GICV3_H 8 9#include <asm/sysreg.h> 10 11/* 12 * Distributor registers 13 */ 14#define GICD_CTLR 0x0000 15#define GICD_TYPER 0x0004 16#define GICD_IGROUPR 0x0080 17#define GICD_ISENABLER 0x0100 18#define GICD_ICENABLER 0x0180 19#define GICD_ISPENDR 0x0200 20#define GICD_ICPENDR 0x0280 21#define GICD_ICACTIVER 0x0380 22#define GICD_ISACTIVER 0x0300 23#define GICD_IPRIORITYR 0x0400 24#define GICD_ICFGR 0x0C00 25 26/* 27 * The assumption is that the guest runs in a non-secure mode. 28 * The following bits of GICD_CTLR are defined accordingly. 29 */ 30#define GICD_CTLR_RWP (1U << 31) 31#define GICD_CTLR_nASSGIreq (1U << 8) 32#define GICD_CTLR_ARE_NS (1U << 4) 33#define GICD_CTLR_ENABLE_G1A (1U << 1) 34#define GICD_CTLR_ENABLE_G1 (1U << 0) 35 36#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32) 37#define GICD_INT_DEF_PRI_X4 0xa0a0a0a0 38 39/* 40 * Redistributor registers 41 */ 42#define GICR_CTLR 0x000 43#define GICR_WAKER 0x014 44 45#define GICR_CTLR_RWP (1U << 3) 46 47#define GICR_WAKER_ProcessorSleep (1U << 1) 48#define GICR_WAKER_ChildrenAsleep (1U << 2) 49 50/* 51 * Redistributor registers, offsets from SGI base 52 */ 53#define GICR_IGROUPR0 GICD_IGROUPR 54#define GICR_ISENABLER0 GICD_ISENABLER 55#define GICR_ICENABLER0 GICD_ICENABLER 56#define GICR_ISPENDR0 GICD_ISPENDR 57#define GICR_ISACTIVER0 GICD_ISACTIVER 58#define GICR_ICACTIVER0 GICD_ICACTIVER 59#define GICR_ICENABLER GICD_ICENABLER 60#define GICR_ICACTIVER GICD_ICACTIVER 61#define GICR_IPRIORITYR0 GICD_IPRIORITYR 62 63/* CPU interface registers */ 64#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 65#define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 66#define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 67#define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 68#define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 69#define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 70#define SYS_ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 71 72#define SYS_ICV_AP1R0_EL1 sys_reg(3, 0, 12, 9, 0) 73 74#define ICC_PMR_DEF_PRIO 0xf0 75 76#define ICC_SRE_EL1_SRE (1U << 0) 77 78#define ICC_IGRPEN1_EL1_ENABLE (1U << 0) 79 80#define GICV3_MAX_CPUS 512 81 82#endif /* SELFTEST_KVM_GICV3_H */