cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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processor.h (4443B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * RISC-V processor specific defines
      4 *
      5 * Copyright (C) 2021 Western Digital Corporation or its affiliates.
      6 */
      7#ifndef SELFTEST_KVM_PROCESSOR_H
      8#define SELFTEST_KVM_PROCESSOR_H
      9
     10#include "kvm_util.h"
     11#include <linux/stringify.h>
     12
     13static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx,
     14				    uint64_t  size)
     15{
     16	return KVM_REG_RISCV | type | idx | size;
     17}
     18
     19#if __riscv_xlen == 64
     20#define KVM_REG_SIZE_ULONG	KVM_REG_SIZE_U64
     21#else
     22#define KVM_REG_SIZE_ULONG	KVM_REG_SIZE_U32
     23#endif
     24
     25#define RISCV_CONFIG_REG(name)	__kvm_reg_id(KVM_REG_RISCV_CONFIG, \
     26					     KVM_REG_RISCV_CONFIG_REG(name), \
     27					     KVM_REG_SIZE_ULONG)
     28
     29#define RISCV_CORE_REG(name)	__kvm_reg_id(KVM_REG_RISCV_CORE, \
     30					     KVM_REG_RISCV_CORE_REG(name), \
     31					     KVM_REG_SIZE_ULONG)
     32
     33#define RISCV_CSR_REG(name)	__kvm_reg_id(KVM_REG_RISCV_CSR, \
     34					     KVM_REG_RISCV_CSR_REG(name), \
     35					     KVM_REG_SIZE_ULONG)
     36
     37#define RISCV_TIMER_REG(name)	__kvm_reg_id(KVM_REG_RISCV_TIMER, \
     38					     KVM_REG_RISCV_TIMER_REG(name), \
     39					     KVM_REG_SIZE_U64)
     40
     41static inline void get_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id,
     42			   unsigned long *addr)
     43{
     44	struct kvm_one_reg reg;
     45
     46	reg.id = id;
     47	reg.addr = (unsigned long)addr;
     48	vcpu_get_reg(vm, vcpuid, &reg);
     49}
     50
     51static inline void set_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id,
     52			   unsigned long val)
     53{
     54	struct kvm_one_reg reg;
     55
     56	reg.id = id;
     57	reg.addr = (unsigned long)&val;
     58	vcpu_set_reg(vm, vcpuid, &reg);
     59}
     60
     61/* L3 index Bit[47:39] */
     62#define PGTBL_L3_INDEX_MASK			0x0000FF8000000000ULL
     63#define PGTBL_L3_INDEX_SHIFT			39
     64#define PGTBL_L3_BLOCK_SHIFT			39
     65#define PGTBL_L3_BLOCK_SIZE			0x0000008000000000ULL
     66#define PGTBL_L3_MAP_MASK			(~(PGTBL_L3_BLOCK_SIZE - 1))
     67/* L2 index Bit[38:30] */
     68#define PGTBL_L2_INDEX_MASK			0x0000007FC0000000ULL
     69#define PGTBL_L2_INDEX_SHIFT			30
     70#define PGTBL_L2_BLOCK_SHIFT			30
     71#define PGTBL_L2_BLOCK_SIZE			0x0000000040000000ULL
     72#define PGTBL_L2_MAP_MASK			(~(PGTBL_L2_BLOCK_SIZE - 1))
     73/* L1 index Bit[29:21] */
     74#define PGTBL_L1_INDEX_MASK			0x000000003FE00000ULL
     75#define PGTBL_L1_INDEX_SHIFT			21
     76#define PGTBL_L1_BLOCK_SHIFT			21
     77#define PGTBL_L1_BLOCK_SIZE			0x0000000000200000ULL
     78#define PGTBL_L1_MAP_MASK			(~(PGTBL_L1_BLOCK_SIZE - 1))
     79/* L0 index Bit[20:12] */
     80#define PGTBL_L0_INDEX_MASK			0x00000000001FF000ULL
     81#define PGTBL_L0_INDEX_SHIFT			12
     82#define PGTBL_L0_BLOCK_SHIFT			12
     83#define PGTBL_L0_BLOCK_SIZE			0x0000000000001000ULL
     84#define PGTBL_L0_MAP_MASK			(~(PGTBL_L0_BLOCK_SIZE - 1))
     85
     86#define PGTBL_PTE_ADDR_MASK			0x003FFFFFFFFFFC00ULL
     87#define PGTBL_PTE_ADDR_SHIFT			10
     88#define PGTBL_PTE_RSW_MASK			0x0000000000000300ULL
     89#define PGTBL_PTE_RSW_SHIFT			8
     90#define PGTBL_PTE_DIRTY_MASK			0x0000000000000080ULL
     91#define PGTBL_PTE_DIRTY_SHIFT			7
     92#define PGTBL_PTE_ACCESSED_MASK			0x0000000000000040ULL
     93#define PGTBL_PTE_ACCESSED_SHIFT		6
     94#define PGTBL_PTE_GLOBAL_MASK			0x0000000000000020ULL
     95#define PGTBL_PTE_GLOBAL_SHIFT			5
     96#define PGTBL_PTE_USER_MASK			0x0000000000000010ULL
     97#define PGTBL_PTE_USER_SHIFT			4
     98#define PGTBL_PTE_EXECUTE_MASK			0x0000000000000008ULL
     99#define PGTBL_PTE_EXECUTE_SHIFT			3
    100#define PGTBL_PTE_WRITE_MASK			0x0000000000000004ULL
    101#define PGTBL_PTE_WRITE_SHIFT			2
    102#define PGTBL_PTE_READ_MASK			0x0000000000000002ULL
    103#define PGTBL_PTE_READ_SHIFT			1
    104#define PGTBL_PTE_PERM_MASK			(PGTBL_PTE_ACCESSED_MASK | \
    105						 PGTBL_PTE_DIRTY_MASK | \
    106						 PGTBL_PTE_EXECUTE_MASK | \
    107						 PGTBL_PTE_WRITE_MASK | \
    108						 PGTBL_PTE_READ_MASK)
    109#define PGTBL_PTE_VALID_MASK			0x0000000000000001ULL
    110#define PGTBL_PTE_VALID_SHIFT			0
    111
    112#define PGTBL_PAGE_SIZE				PGTBL_L0_BLOCK_SIZE
    113#define PGTBL_PAGE_SIZE_SHIFT			PGTBL_L0_BLOCK_SHIFT
    114
    115#define SATP_PPN				_AC(0x00000FFFFFFFFFFF, UL)
    116#define SATP_MODE_39				_AC(0x8000000000000000, UL)
    117#define SATP_MODE_48				_AC(0x9000000000000000, UL)
    118#define SATP_ASID_BITS				16
    119#define SATP_ASID_SHIFT				44
    120#define SATP_ASID_MASK				_AC(0xFFFF, UL)
    121
    122#define SBI_EXT_EXPERIMENTAL_START		0x08000000
    123#define SBI_EXT_EXPERIMENTAL_END		0x08FFFFFF
    124
    125#define KVM_RISCV_SELFTESTS_SBI_EXT		SBI_EXT_EXPERIMENTAL_END
    126#define KVM_RISCV_SELFTESTS_SBI_UCALL		0
    127#define KVM_RISCV_SELFTESTS_SBI_UNEXP		1
    128
    129struct sbiret {
    130	long error;
    131	long value;
    132};
    133
    134struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
    135			unsigned long arg1, unsigned long arg2,
    136			unsigned long arg3, unsigned long arg4,
    137			unsigned long arg5);
    138
    139#endif /* SELFTEST_KVM_PROCESSOR_H */