svm.h (7306B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * tools/testing/selftests/kvm/include/x86_64/svm.h 4 * This is a copy of arch/x86/include/asm/svm.h 5 * 6 */ 7 8#ifndef SELFTEST_KVM_SVM_H 9#define SELFTEST_KVM_SVM_H 10 11enum { 12 INTERCEPT_INTR, 13 INTERCEPT_NMI, 14 INTERCEPT_SMI, 15 INTERCEPT_INIT, 16 INTERCEPT_VINTR, 17 INTERCEPT_SELECTIVE_CR0, 18 INTERCEPT_STORE_IDTR, 19 INTERCEPT_STORE_GDTR, 20 INTERCEPT_STORE_LDTR, 21 INTERCEPT_STORE_TR, 22 INTERCEPT_LOAD_IDTR, 23 INTERCEPT_LOAD_GDTR, 24 INTERCEPT_LOAD_LDTR, 25 INTERCEPT_LOAD_TR, 26 INTERCEPT_RDTSC, 27 INTERCEPT_RDPMC, 28 INTERCEPT_PUSHF, 29 INTERCEPT_POPF, 30 INTERCEPT_CPUID, 31 INTERCEPT_RSM, 32 INTERCEPT_IRET, 33 INTERCEPT_INTn, 34 INTERCEPT_INVD, 35 INTERCEPT_PAUSE, 36 INTERCEPT_HLT, 37 INTERCEPT_INVLPG, 38 INTERCEPT_INVLPGA, 39 INTERCEPT_IOIO_PROT, 40 INTERCEPT_MSR_PROT, 41 INTERCEPT_TASK_SWITCH, 42 INTERCEPT_FERR_FREEZE, 43 INTERCEPT_SHUTDOWN, 44 INTERCEPT_VMRUN, 45 INTERCEPT_VMMCALL, 46 INTERCEPT_VMLOAD, 47 INTERCEPT_VMSAVE, 48 INTERCEPT_STGI, 49 INTERCEPT_CLGI, 50 INTERCEPT_SKINIT, 51 INTERCEPT_RDTSCP, 52 INTERCEPT_ICEBP, 53 INTERCEPT_WBINVD, 54 INTERCEPT_MONITOR, 55 INTERCEPT_MWAIT, 56 INTERCEPT_MWAIT_COND, 57 INTERCEPT_XSETBV, 58 INTERCEPT_RDPRU, 59}; 60 61 62struct __attribute__ ((__packed__)) vmcb_control_area { 63 u32 intercept_cr; 64 u32 intercept_dr; 65 u32 intercept_exceptions; 66 u64 intercept; 67 u8 reserved_1[40]; 68 u16 pause_filter_thresh; 69 u16 pause_filter_count; 70 u64 iopm_base_pa; 71 u64 msrpm_base_pa; 72 u64 tsc_offset; 73 u32 asid; 74 u8 tlb_ctl; 75 u8 reserved_2[3]; 76 u32 int_ctl; 77 u32 int_vector; 78 u32 int_state; 79 u8 reserved_3[4]; 80 u32 exit_code; 81 u32 exit_code_hi; 82 u64 exit_info_1; 83 u64 exit_info_2; 84 u32 exit_int_info; 85 u32 exit_int_info_err; 86 u64 nested_ctl; 87 u64 avic_vapic_bar; 88 u8 reserved_4[8]; 89 u32 event_inj; 90 u32 event_inj_err; 91 u64 nested_cr3; 92 u64 virt_ext; 93 u32 clean; 94 u32 reserved_5; 95 u64 next_rip; 96 u8 insn_len; 97 u8 insn_bytes[15]; 98 u64 avic_backing_page; /* Offset 0xe0 */ 99 u8 reserved_6[8]; /* Offset 0xe8 */ 100 u64 avic_logical_id; /* Offset 0xf0 */ 101 u64 avic_physical_id; /* Offset 0xf8 */ 102 u8 reserved_7[8]; 103 u64 vmsa_pa; /* Used for an SEV-ES guest */ 104 u8 reserved_8[720]; 105 /* 106 * Offset 0x3e0, 32 bytes reserved 107 * for use by hypervisor/software. 108 */ 109 u8 reserved_sw[32]; 110}; 111 112 113#define TLB_CONTROL_DO_NOTHING 0 114#define TLB_CONTROL_FLUSH_ALL_ASID 1 115#define TLB_CONTROL_FLUSH_ASID 3 116#define TLB_CONTROL_FLUSH_ASID_LOCAL 7 117 118#define V_TPR_MASK 0x0f 119 120#define V_IRQ_SHIFT 8 121#define V_IRQ_MASK (1 << V_IRQ_SHIFT) 122 123#define V_GIF_SHIFT 9 124#define V_GIF_MASK (1 << V_GIF_SHIFT) 125 126#define V_INTR_PRIO_SHIFT 16 127#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) 128 129#define V_IGN_TPR_SHIFT 20 130#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) 131 132#define V_INTR_MASKING_SHIFT 24 133#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) 134 135#define V_GIF_ENABLE_SHIFT 25 136#define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT) 137 138#define AVIC_ENABLE_SHIFT 31 139#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT) 140 141#define LBR_CTL_ENABLE_MASK BIT_ULL(0) 142#define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1) 143 144#define SVM_INTERRUPT_SHADOW_MASK 1 145 146#define SVM_IOIO_STR_SHIFT 2 147#define SVM_IOIO_REP_SHIFT 3 148#define SVM_IOIO_SIZE_SHIFT 4 149#define SVM_IOIO_ASIZE_SHIFT 7 150 151#define SVM_IOIO_TYPE_MASK 1 152#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) 153#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) 154#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) 155#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) 156 157#define SVM_VM_CR_VALID_MASK 0x001fULL 158#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL 159#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL 160 161#define SVM_NESTED_CTL_NP_ENABLE BIT(0) 162#define SVM_NESTED_CTL_SEV_ENABLE BIT(1) 163 164struct __attribute__ ((__packed__)) vmcb_seg { 165 u16 selector; 166 u16 attrib; 167 u32 limit; 168 u64 base; 169}; 170 171struct __attribute__ ((__packed__)) vmcb_save_area { 172 struct vmcb_seg es; 173 struct vmcb_seg cs; 174 struct vmcb_seg ss; 175 struct vmcb_seg ds; 176 struct vmcb_seg fs; 177 struct vmcb_seg gs; 178 struct vmcb_seg gdtr; 179 struct vmcb_seg ldtr; 180 struct vmcb_seg idtr; 181 struct vmcb_seg tr; 182 u8 reserved_1[43]; 183 u8 cpl; 184 u8 reserved_2[4]; 185 u64 efer; 186 u8 reserved_3[112]; 187 u64 cr4; 188 u64 cr3; 189 u64 cr0; 190 u64 dr7; 191 u64 dr6; 192 u64 rflags; 193 u64 rip; 194 u8 reserved_4[88]; 195 u64 rsp; 196 u8 reserved_5[24]; 197 u64 rax; 198 u64 star; 199 u64 lstar; 200 u64 cstar; 201 u64 sfmask; 202 u64 kernel_gs_base; 203 u64 sysenter_cs; 204 u64 sysenter_esp; 205 u64 sysenter_eip; 206 u64 cr2; 207 u8 reserved_6[32]; 208 u64 g_pat; 209 u64 dbgctl; 210 u64 br_from; 211 u64 br_to; 212 u64 last_excp_from; 213 u64 last_excp_to; 214}; 215 216struct __attribute__ ((__packed__)) vmcb { 217 struct vmcb_control_area control; 218 struct vmcb_save_area save; 219}; 220 221#define SVM_CPUID_FUNC 0x8000000a 222 223#define SVM_VM_CR_SVM_DISABLE 4 224 225#define SVM_SELECTOR_S_SHIFT 4 226#define SVM_SELECTOR_DPL_SHIFT 5 227#define SVM_SELECTOR_P_SHIFT 7 228#define SVM_SELECTOR_AVL_SHIFT 8 229#define SVM_SELECTOR_L_SHIFT 9 230#define SVM_SELECTOR_DB_SHIFT 10 231#define SVM_SELECTOR_G_SHIFT 11 232 233#define SVM_SELECTOR_TYPE_MASK (0xf) 234#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT) 235#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT) 236#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT) 237#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT) 238#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT) 239#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT) 240#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT) 241 242#define SVM_SELECTOR_WRITE_MASK (1 << 1) 243#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK 244#define SVM_SELECTOR_CODE_MASK (1 << 3) 245 246#define INTERCEPT_CR0_READ 0 247#define INTERCEPT_CR3_READ 3 248#define INTERCEPT_CR4_READ 4 249#define INTERCEPT_CR8_READ 8 250#define INTERCEPT_CR0_WRITE (16 + 0) 251#define INTERCEPT_CR3_WRITE (16 + 3) 252#define INTERCEPT_CR4_WRITE (16 + 4) 253#define INTERCEPT_CR8_WRITE (16 + 8) 254 255#define INTERCEPT_DR0_READ 0 256#define INTERCEPT_DR1_READ 1 257#define INTERCEPT_DR2_READ 2 258#define INTERCEPT_DR3_READ 3 259#define INTERCEPT_DR4_READ 4 260#define INTERCEPT_DR5_READ 5 261#define INTERCEPT_DR6_READ 6 262#define INTERCEPT_DR7_READ 7 263#define INTERCEPT_DR0_WRITE (16 + 0) 264#define INTERCEPT_DR1_WRITE (16 + 1) 265#define INTERCEPT_DR2_WRITE (16 + 2) 266#define INTERCEPT_DR3_WRITE (16 + 3) 267#define INTERCEPT_DR4_WRITE (16 + 4) 268#define INTERCEPT_DR5_WRITE (16 + 5) 269#define INTERCEPT_DR6_WRITE (16 + 6) 270#define INTERCEPT_DR7_WRITE (16 + 7) 271 272#define SVM_EVTINJ_VEC_MASK 0xff 273 274#define SVM_EVTINJ_TYPE_SHIFT 8 275#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) 276 277#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) 278#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) 279#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) 280#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) 281 282#define SVM_EVTINJ_VALID (1 << 31) 283#define SVM_EVTINJ_VALID_ERR (1 << 11) 284 285#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK 286#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK 287 288#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR 289#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI 290#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT 291#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT 292 293#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID 294#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR 295 296#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36 297#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38 298#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44 299 300#define SVM_EXITINFO_REG_MASK 0x0F 301 302#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP) 303 304#endif /* SELFTEST_KVM_SVM_H */