cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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svm_int_ctl_test.c (3008B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * svm_int_ctl_test
      4 *
      5 * Copyright (C) 2021, Red Hat, Inc.
      6 *
      7 * Nested SVM testing: test simultaneous use of V_IRQ from L1 and L0.
      8 */
      9
     10#include "test_util.h"
     11#include "kvm_util.h"
     12#include "processor.h"
     13#include "svm_util.h"
     14#include "apic.h"
     15
     16#define VCPU_ID		0
     17
     18static struct kvm_vm *vm;
     19
     20bool vintr_irq_called;
     21bool intr_irq_called;
     22
     23#define VINTR_IRQ_NUMBER 0x20
     24#define INTR_IRQ_NUMBER 0x30
     25
     26static void vintr_irq_handler(struct ex_regs *regs)
     27{
     28	vintr_irq_called = true;
     29}
     30
     31static void intr_irq_handler(struct ex_regs *regs)
     32{
     33	x2apic_write_reg(APIC_EOI, 0x00);
     34	intr_irq_called = true;
     35}
     36
     37static void l2_guest_code(struct svm_test_data *svm)
     38{
     39	/* This code raises interrupt INTR_IRQ_NUMBER in the L1's LAPIC,
     40	 * and since L1 didn't enable virtual interrupt masking,
     41	 * L2 should receive it and not L1.
     42	 *
     43	 * L2 also has virtual interrupt 'VINTR_IRQ_NUMBER' pending in V_IRQ
     44	 * so it should also receive it after the following 'sti'.
     45	 */
     46	x2apic_write_reg(APIC_ICR,
     47		APIC_DEST_SELF | APIC_INT_ASSERT | INTR_IRQ_NUMBER);
     48
     49	__asm__ __volatile__(
     50		"sti\n"
     51		"nop\n"
     52	);
     53
     54	GUEST_ASSERT(vintr_irq_called);
     55	GUEST_ASSERT(intr_irq_called);
     56
     57	__asm__ __volatile__(
     58		"vmcall\n"
     59	);
     60}
     61
     62static void l1_guest_code(struct svm_test_data *svm)
     63{
     64	#define L2_GUEST_STACK_SIZE 64
     65	unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];
     66	struct vmcb *vmcb = svm->vmcb;
     67
     68	x2apic_enable();
     69
     70	/* Prepare for L2 execution. */
     71	generic_svm_setup(svm, l2_guest_code,
     72			  &l2_guest_stack[L2_GUEST_STACK_SIZE]);
     73
     74	/* No virtual interrupt masking */
     75	vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
     76
     77	/* No intercepts for real and virtual interrupts */
     78	vmcb->control.intercept &= ~(BIT(INTERCEPT_INTR) | BIT(INTERCEPT_VINTR));
     79
     80	/* Make a virtual interrupt VINTR_IRQ_NUMBER pending */
     81	vmcb->control.int_ctl |= V_IRQ_MASK | (0x1 << V_INTR_PRIO_SHIFT);
     82	vmcb->control.int_vector = VINTR_IRQ_NUMBER;
     83
     84	run_guest(vmcb, svm->vmcb_gpa);
     85	GUEST_ASSERT(vmcb->control.exit_code == SVM_EXIT_VMMCALL);
     86	GUEST_DONE();
     87}
     88
     89int main(int argc, char *argv[])
     90{
     91	vm_vaddr_t svm_gva;
     92
     93	nested_svm_check_supported();
     94
     95	vm = vm_create_default(VCPU_ID, 0, (void *) l1_guest_code);
     96
     97	vm_init_descriptor_tables(vm);
     98	vcpu_init_descriptor_tables(vm, VCPU_ID);
     99
    100	vm_install_exception_handler(vm, VINTR_IRQ_NUMBER, vintr_irq_handler);
    101	vm_install_exception_handler(vm, INTR_IRQ_NUMBER, intr_irq_handler);
    102
    103	vcpu_alloc_svm(vm, &svm_gva);
    104	vcpu_args_set(vm, VCPU_ID, 1, svm_gva);
    105
    106	struct kvm_run *run = vcpu_state(vm, VCPU_ID);
    107	struct ucall uc;
    108
    109	vcpu_run(vm, VCPU_ID);
    110	TEST_ASSERT(run->exit_reason == KVM_EXIT_IO,
    111		    "Got exit_reason other than KVM_EXIT_IO: %u (%s)\n",
    112		    run->exit_reason,
    113		    exit_reason_str(run->exit_reason));
    114
    115	switch (get_ucall(vm, VCPU_ID, &uc)) {
    116	case UCALL_ABORT:
    117		TEST_FAIL("%s", (const char *)uc.args[0]);
    118		break;
    119		/* NOT REACHED */
    120	case UCALL_DONE:
    121		goto done;
    122	default:
    123		TEST_FAIL("Unknown ucall 0x%lx.", uc.cmd);
    124	}
    125done:
    126	kvm_vm_free(vm);
    127	return 0;
    128}