cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dscr_user_test.c (1398B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * POWER Data Stream Control Register (DSCR) SPR test
      4 *
      5 * This test modifies the DSCR value through both the SPR number
      6 * based mtspr instruction and then makes sure that the same is
      7 * reflected through mfspr instruction using either of the SPR
      8 * numbers.
      9 *
     10 * When using the privilege state SPR, the instructions such as
     11 * mfspr or mtspr are priviledged and the kernel emulates them
     12 * for us. Instructions using problem state SPR can be exuecuted
     13 * directly without any emulation if the HW supports them. Else
     14 * they also get emulated by the kernel.
     15 *
     16 * Copyright 2013, Anton Blanchard, IBM Corporation.
     17 * Copyright 2015, Anshuman Khandual, IBM Corporation.
     18 */
     19#include "dscr.h"
     20
     21static int check_dscr(char *str)
     22{
     23	unsigned long cur_dscr, cur_dscr_usr;
     24
     25	cur_dscr = get_dscr();
     26	cur_dscr_usr = get_dscr_usr();
     27	if (cur_dscr != cur_dscr_usr) {
     28		printf("%s set, kernel get %lx != user get %lx\n",
     29					str, cur_dscr, cur_dscr_usr);
     30		return 1;
     31	}
     32	return 0;
     33}
     34
     35int dscr_user(void)
     36{
     37	int i;
     38
     39	SKIP_IF(!have_hwcap2(PPC_FEATURE2_DSCR));
     40
     41	check_dscr("");
     42
     43	for (i = 0; i < COUNT; i++) {
     44		set_dscr(i);
     45		if (check_dscr("kernel"))
     46			return 1;
     47	}
     48
     49	for (i = 0; i < COUNT; i++) {
     50		set_dscr_usr(i);
     51		if (check_dscr("user"))
     52			return 1;
     53	}
     54	return 0;
     55}
     56
     57int main(int argc, char *argv[])
     58{
     59	return test_harness(dscr_user, "dscr_user_test");
     60}