cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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gpr_asm.h (2267B)

      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 * Copyright 2016, Cyril Bur, IBM Corp.
      4 */
      5
      6#ifndef _SELFTESTS_POWERPC_GPR_ASM_H
      7#define _SELFTESTS_POWERPC_GPR_ASM_H
      8
      9#include "basic_asm.h"
     10
     11#define __PUSH_NVREGS(top_pos); \
     12	std r31,(top_pos)(%r1); \
     13	std r30,(top_pos - 8)(%r1); \
     14	std r29,(top_pos - 16)(%r1); \
     15	std r28,(top_pos - 24)(%r1); \
     16	std r27,(top_pos - 32)(%r1); \
     17	std r26,(top_pos - 40)(%r1); \
     18	std r25,(top_pos - 48)(%r1); \
     19	std r24,(top_pos - 56)(%r1); \
     20	std r23,(top_pos - 64)(%r1); \
     21	std r22,(top_pos - 72)(%r1); \
     22	std r21,(top_pos - 80)(%r1); \
     23	std r20,(top_pos - 88)(%r1); \
     24	std r19,(top_pos - 96)(%r1); \
     25	std r18,(top_pos - 104)(%r1); \
     26	std r17,(top_pos - 112)(%r1); \
     27	std r16,(top_pos - 120)(%r1); \
     28	std r15,(top_pos - 128)(%r1); \
     29	std r14,(top_pos - 136)(%r1)
     30
     31#define __POP_NVREGS(top_pos); \
     32	ld r31,(top_pos)(%r1); \
     33	ld r30,(top_pos - 8)(%r1); \
     34	ld r29,(top_pos - 16)(%r1); \
     35	ld r28,(top_pos - 24)(%r1); \
     36	ld r27,(top_pos - 32)(%r1); \
     37	ld r26,(top_pos - 40)(%r1); \
     38	ld r25,(top_pos - 48)(%r1); \
     39	ld r24,(top_pos - 56)(%r1); \
     40	ld r23,(top_pos - 64)(%r1); \
     41	ld r22,(top_pos - 72)(%r1); \
     42	ld r21,(top_pos - 80)(%r1); \
     43	ld r20,(top_pos - 88)(%r1); \
     44	ld r19,(top_pos - 96)(%r1); \
     45	ld r18,(top_pos - 104)(%r1); \
     46	ld r17,(top_pos - 112)(%r1); \
     47	ld r16,(top_pos - 120)(%r1); \
     48	ld r15,(top_pos - 128)(%r1); \
     49	ld r14,(top_pos - 136)(%r1)
     50
     51#define PUSH_NVREGS(stack_size) \
     52	__PUSH_NVREGS(stack_size + STACK_FRAME_MIN_SIZE)
     53
     54/* 18 NV FPU REGS */
     55#define PUSH_NVREGS_BELOW_FPU(stack_size) \
     56	__PUSH_NVREGS(stack_size + STACK_FRAME_MIN_SIZE - (18 * 8))
     57
     58#define POP_NVREGS(stack_size) \
     59	__POP_NVREGS(stack_size + STACK_FRAME_MIN_SIZE)
     60
     61/* 18 NV FPU REGS */
     62#define POP_NVREGS_BELOW_FPU(stack_size) \
     63	__POP_NVREGS(stack_size + STACK_FRAME_MIN_SIZE - (18 * 8))
     64
     65/*
     66 * Careful calling this, it will 'clobber' NVGPRs (by design)
     67 * Don't call this from C
     68 */
     69FUNC_START(load_gpr)
     70	ld	r14,0(r3)
     71	ld	r15,8(r3)
     72	ld	r16,16(r3)
     73	ld	r17,24(r3)
     74	ld	r18,32(r3)
     75	ld	r19,40(r3)
     76	ld	r20,48(r3)
     77	ld	r21,56(r3)
     78	ld	r22,64(r3)
     79	ld	r23,72(r3)
     80	ld	r24,80(r3)
     81	ld	r25,88(r3)
     82	ld	r26,96(r3)
     83	ld	r27,104(r3)
     84	ld	r28,112(r3)
     85	ld	r29,120(r3)
     86	ld	r30,128(r3)
     87	ld	r31,136(r3)
     88	blr
     89FUNC_END(load_gpr)
     90
     91
     92#endif /* _SELFTESTS_POWERPC_GPR_ASM_H */