cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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barrier.h (1128B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2#include <stdlib.h>
      3#if defined(__i386__) || defined(__x86_64__)
      4#define barrier() asm volatile("" ::: "memory")
      5#define virt_mb() __sync_synchronize()
      6#define virt_rmb() barrier()
      7#define virt_wmb() barrier()
      8/* Atomic store should be enough, but gcc generates worse code in that case. */
      9#define virt_store_mb(var, value)  do { \
     10	typeof(var) virt_store_mb_value = (value); \
     11	__atomic_exchange(&(var), &virt_store_mb_value, &virt_store_mb_value, \
     12			  __ATOMIC_SEQ_CST); \
     13	barrier(); \
     14} while (0);
     15/* Weak barriers should be used. If not - it's a bug */
     16# define mb() abort()
     17# define dma_rmb() abort()
     18# define dma_wmb() abort()
     19#elif defined(__aarch64__)
     20#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
     21#define virt_mb() __sync_synchronize()
     22#define virt_rmb() dmb(ishld)
     23#define virt_wmb() dmb(ishst)
     24#define virt_store_mb(var, value)  do { WRITE_ONCE(var, value); dmb(ish); } while (0)
     25/* Weak barriers should be used. If not - it's a bug */
     26# define mb() abort()
     27# define dma_rmb() abort()
     28# define dma_wmb() abort()
     29#else
     30#error Please fill in barrier macros
     31#endif
     32