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| * | | | clk: mmp2: Add HSIC clocksLubomir Rintel2020-01-061-0/+6
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two USB HSIC controllers on MMP2 and MMP3. Link: https://lore.kernel.org/r/20191220065314.237624-3-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* | | | Merge tag 'clk-for-linus' of ↵Linus Torvalds2020-02-075-41/+27
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "A collection of fixes: - Make of_clk.h self contained - Fix new qcom DT bindings that just merged to match the DTS files - Fix qcom clk driver to properly detect DFS clk frequencies - Fix the ls1028a driver to not deref a pointer before assigning it" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: of: clk: Make <linux/of_clk.h> self-contained clk: qcom: Use ARRAY_SIZE in videocc-sc7180 for parent clocks clk: qcom: Get rid of the test clock for videocc-sc7180 dt-bindings: clock: Cleanup qcom,videocc bindings for sdm845/sc7180 clk: qcom: Use ARRAY_SIZE in gpucc-sc7180 for parent clocks clk: qcom: Get rid of the test clock for gpucc-sc7180 dt-bindings: clock: Fix qcom,gpucc bindings for sdm845/sc7180/msm8998 clk: qcom: Use ARRAY_SIZE in dispcc-sc7180 for parent clocks clk: qcom: Get rid of the test clock for dispcc-sc7180 clk: qcom: Get rid of fallback global names for dispcc-sc7180 dt-bindings: clock: Fix qcom,dispcc bindings for sdm845/sc7180 clk: qcom: rcg2: Don't crash if our parent can't be found; return an error clk: ls1028a: fix a dereference of pointer 'parent' before a null check dt-bindings: clk: qcom: Fix self-validation, split, and clean cruft clk: qcom: Don't overwrite 'cfg' in clk_rcg2_dfs_populate_freq()
| * | | | clk: qcom: Use ARRAY_SIZE in videocc-sc7180 for parent clocksDouglas Anderson2020-02-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's nicer to use ARRAY_SIZE instead of hardcoding. Had we always been doing this it would have prevented a previous bug. See commit 74c31ff9c84a ("clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6"). Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lkml.kernel.org/r/20200203103049.v4.13.If37e4b1b5553ac9db5ea51e84a6eec286cdf209e@changeid Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | | clk: qcom: Get rid of the test clock for videocc-sc7180Douglas Anderson2020-02-031-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lkml.kernel.org/r/20200203103049.v4.12.Ifd19a2701a102ec9f04e61a09345198383a9e937@changeid Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | | clk: qcom: Use ARRAY_SIZE in gpucc-sc7180 for parent clocksDouglas Anderson2020-02-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's nicer to use ARRAY_SIZE instead of hardcoding. Had we always been doing this it would have prevented a previous bug. See commit 74c31ff9c84a ("clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6"). Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lkml.kernel.org/r/20200203103049.v4.10.I3bf44e33f4dc7ecca10a50dbccb7dc082894fa59@changeid Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | | clk: qcom: Get rid of the test clock for gpucc-sc7180Douglas Anderson2020-02-031-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lkml.kernel.org/r/20200203103049.v4.9.I6d5276b768f6593053be036a3e70cce298d39f0c@changeid Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | | clk: qcom: Use ARRAY_SIZE in dispcc-sc7180 for parent clocksDouglas Anderson2020-02-031-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's nicer to use ARRAY_SIZE instead of hardcoding. Had we always been doing this it would have prevented a previous bug. See commit 74c31ff9c84a ("clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6"). Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lkml.kernel.org/r/20200203103049.v4.6.If590c468722d2985cea63adf60c0d2b3098f37d9@changeid Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | | clk: qcom: Get rid of the test clock for dispcc-sc7180Douglas Anderson2020-02-031-22/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lkml.kernel.org/r/20200203103049.v4.5.I28ac8f801456f1b950f7da10ed0f74a1344d4a35@changeid Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | | clk: qcom: Get rid of fallback global names for dispcc-sc7180Douglas Anderson2020-02-031-13/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the new world input clocks should be matched by ".fw_name". sc7180 is new enough that no backward compatibility use of global names should be needed. Remove it. With a proper device tree and downstream display patches I have verified booting a sc7180 up and seeing the display after this patch. Fixes: dd3d06622138 ("clk: qcom: Add display clock controller driver for SC7180") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lkml.kernel.org/r/20200203103049.v4.4.Ia3706a5d5add72e88dbff60fd13ec06bf7a2fd48@changeid Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | | clk: qcom: rcg2: Don't crash if our parent can't be found; return an errorDouglas Anderson2020-02-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When I got my clock parenting slightly wrong I ended up with a crash that looked like this: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 ... pc : clk_hw_get_rate+0x14/0x44 ... Call trace: clk_hw_get_rate+0x14/0x44 _freq_tbl_determine_rate+0x94/0xfc clk_rcg2_determine_rate+0x2c/0x38 clk_core_determine_round_nolock+0x4c/0x88 clk_core_round_rate_nolock+0x6c/0xa8 clk_core_round_rate_nolock+0x9c/0xa8 clk_core_set_rate_nolock+0x70/0x180 clk_set_rate+0x3c/0x6c of_clk_set_defaults+0x254/0x360 platform_drv_probe+0x28/0xb0 really_probe+0x120/0x2dc driver_probe_device+0x64/0xfc device_driver_attach+0x4c/0x6c __driver_attach+0xac/0xc0 bus_for_each_dev+0x84/0xcc driver_attach+0x2c/0x38 bus_add_driver+0xfc/0x1d0 driver_register+0x64/0xf8 __platform_driver_register+0x4c/0x58 msm_drm_register+0x5c/0x60 ... It turned out that clk_hw_get_parent_by_index() was returning NULL and we weren't checking. Let's check it so that we don't crash. Fixes: ac269395cdd8 ("clk: qcom: Convert to clk_hw based provider APIs") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lkml.kernel.org/r/20200203103049.v4.1.I7487325fe8e701a68a07d3be8a6a4b571eca9cfa@changeid Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | | clk: ls1028a: fix a dereference of pointer 'parent' before a null checkColin Ian King2020-02-031-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the pointer 'parent' is being dereferenced before it is being null checked. Fix this by performing the null check before it is dereferenced. Addresses-Coverity: ("Dereference before null check") Fixes: d37010a3c162 ("clk: ls1028a: Add clock driver for Display output interface") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lkml.kernel.org/r/20200203223736.99645-1-colin.king@canonical.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | | clk: qcom: Don't overwrite 'cfg' in clk_rcg2_dfs_populate_freq()Stephen Boyd2020-02-031-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DFS frequency table logic overwrites 'cfg' while detecting the parent clk and then later on in clk_rcg2_dfs_populate_freq() we use that same variable to figure out the mode of the clk, either MND or not. Add a new variable to hold the parent clk bit so that 'cfg' is left untouched for use later. This fixes problems in detecting the supported frequencies for any clks in DFS mode. Fixes: cc4f6944d0e3 ("clk: qcom: Add support for RCG to register for DFS") Reported-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20200128193329.45635-1-sboyd@kernel.org Tested-by: Rajendra Nayak <rnayak@codeaurora.org>
* | | | | Merge branch 'akpm' (patches from Andrew)Linus Torvalds2020-02-041-1/+1
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge more updates from Andrew Morton: "The rest of MM and the rest of everything else: hotfixes, ipc, misc, procfs, lib, cleanups, arm" * emailed patches from Andrew Morton <akpm@linux-foundation.org>: (67 commits) ARM: dma-api: fix max_pfn off-by-one error in __dma_supported() treewide: remove redundant IS_ERR() before error code check include/linux/cpumask.h: don't calculate length of the input string lib: new testcases for bitmap_parse{_user} lib: rework bitmap_parse() lib: make bitmap_parse_user a wrapper on bitmap_parse lib: add test for bitmap_parse() bitops: more BITS_TO_* macros lib/string: add strnchrnul() proc: convert everything to "struct proc_ops" proc: decouple proc from VFS with "struct proc_ops" asm-generic/tlb: provide MMU_GATHER_TABLE_FREE asm-generic/tlb: rename HAVE_MMU_GATHER_NO_GATHER asm-generic/tlb: rename HAVE_MMU_GATHER_PAGE_SIZE asm-generic/tlb: rename HAVE_RCU_TABLE_FREE asm-generic/tlb: add missing CONFIG symbol asm-gemeric/tlb: remove stray function declarations asm-generic/tlb: avoid potential double flush mm/mmu_gather: invalidate TLB correctly on batch allocation failure and flush powerpc/mmu_gather: enable RCU_TABLE_FREE even for !SMP case ...
| * | | | | treewide: remove redundant IS_ERR() before error code checkMasahiro Yamada2020-02-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'PTR_ERR(p) == -E*' is a stronger condition than IS_ERR(p). Hence, IS_ERR(p) is unneeded. The semantic patch that generates this commit is as follows: // <smpl> @@ expression ptr; constant error_code; @@ -IS_ERR(ptr) && (PTR_ERR(ptr) == - error_code) +PTR_ERR(ptr) == - error_code // </smpl> Link: http://lkml.kernel.org/r/20200106045833.1725-1-masahiroy@kernel.org Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Cc: Julia Lawall <julia.lawall@lip6.fr> Acked-by: Stephen Boyd <sboyd@kernel.org> [drivers/clk/clk.c] Acked-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> [GPIO] Acked-by: Wolfram Sang <wsa@the-dreams.de> [drivers/i2c] Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [acpi/scan.c] Acked-by: Rob Herring <robh@kernel.org> Cc: Eric Biggers <ebiggers@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | | | | Merge tag 'clk-for-linus' of ↵Linus Torvalds2020-02-0399-1599/+12741
|\ \ \ \ \ \ | |/ / / / / |/| / / / / | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "There are a few changes to the core framework this time around, in addition to the normal collection of driver updates to support new SoCs, fix incorrect data, and convert various drivers to clk_hw based APIs. In the core, we allow clk_ops::init() to return an error code now so that we can fail clk registration if the callback does something like fail to allocate memory. We also add a new "terminate" clk_op so that things done in clk_ops::init() can be undone, e.g. free memory. We also spit out a warning now when critical clks fail to enable and we support changing clk rates and enable/disable state through debugfs when developers compile the kernel themselves. On the driver front, we get support for what seems like a lot of Qualcomm and NXP SoCs given that those vendors dominate the diffstat. There are a couple new drivers for Xilinx and Amlogic SoCs too. The updates are all small things like fixing the way glitch free muxes switch parents, avoiding div-by-zero problems, or fixing data like parent names. See the updates section below for more details. Finally, the "basic" clk types have been converted to support specifying parents with clk_hw pointers. This work includes an overhaul of the fixed-rate clk type to be more modern by using clk_hw APIs. Core: - Let clk_ops::init() return an error code - Add a clk_ops::terminate() callback to undo clk_ops::init() - Warn about critical clks that fail to enable or prepare - Support dangerous debugfs actions on clks with dead code New Drivers: - Support for Xilinx Versal platform clks - Display clk controller on qcom sc7180 - Video clk controller on qcom sc7180 - Graphics clk controller on qcom sc7180 - CPU PLLs for qcom msm8916 - Move qcom msm8974 gfx3d clk to RPM control - Display port clk support on qcom sdm845 SoCs - Global clk controller on qcom ipq6018 - Add a driver for BCLK of Freescale SAI cores - Add cam, vpe and sgx clock support for TI dra7 - Add aess clock support for TI omap5 - Enable clks for CPUfreq on Allwinner A64 SoCs - Add Amlogic meson8b DDR clock controller - Add input clocks to Amlogic meson8b controllers - Add SPIBSC (SPI FLASH) clock on Renesas RZ/A2 - i.MX8MP clk driver support Updates: - Convert gpio, fixed-factor, mux, gate, divider basic clks to hw based APIs - Detect more PRMCU variants in ux500 driver - Adjust the composite clk type to new way of describing clk parents - Fixes for clk controllers on qcom msm8998 SoCs - Fix gmac main clock for TI dra7 - Move TI dra7-atl clock header to correct location - Fix hidden node name dependency on TI clkctrl clocks - Fix Amlogic meson8b mali clock update using the glitch free mux - Fix Amlogic pll driver division by zero at init - Prepare for split of Renesas R-Car H3 ES1.x and ES2.0+ config symbols - Switch more i.MX clk drivers to clk_hw based APIs - Disable non-functional divider between pll4_audio_div and pll4_post_div on imx6q - Fix watchdog2 clock name typo in imx7ulp clock driver - Set CLK_GET_RATE_NOCACHE flag for DRAM related clocks on i.MX8M SoCs - Suppress bind attrs for i.MX8M clock driver - Add a big comment in imx8qxp-lpcg driver to tell why devm_platform_ioremap_resource() shouldn't be used for the driver - A correction on i.MX8MN usb1_ctrl parent clock setting" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (140 commits) dt/bindings: clk: fsl,plldig: Drop 'bindings' from schema id clk: ls1028a: Fix warning on clamp() usage clk: qoriq: add ls1088a hwaccel clocks support clk: ls1028a: Add clock driver for Display output interface dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings clk: fsl-sai: new driver dt-bindings: clock: document the fsl-sai driver clk: composite: add _register_composite_pdata() variants clk: qcom: rpmh: Sort OF match table dt-bindings: fix warnings in validation of qcom,gcc.yaml dt-binding: fix compilation error of the example in qcom,gcc.yaml clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag clk: zynqmp: Fix divider calculation clk: zynqmp: Add support for get max divider clk: zynqmp: Warn user if clock user are more than allowed clk: zynqmp: Extend driver for versal dt-bindings: clock: Add bindings for versal clock driver clk: ti: clkctrl: Fix hidden dependency to node name clk: ti: add clkctrl data dra7 sgx clk: ti: omap5: Add missing AESS clock ...
| * | | | clk: ls1028a: Fix warning on clamp() usageStephen Boyd2020-02-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These constants are used in clamp() with the value being clamped an unsigned long. Make them unsigned long defines so that clamp() doesn't complain about comparing different types. In file included from include/linux/list.h:9, from include/linux/kobject.h:19, from include/linux/of.h:17, from include/linux/clk-provider.h:9, from drivers/clk/clk-plldig.c:8: drivers/clk/clk-plldig.c: In function 'plldig_determine_rate': include/linux/kernel.h:835:29: warning: comparison of distinct pointer types lacks a cast 835 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1))) | Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Wen He <wen.he_1@nxp.com> Fixes: d37010a3c162 ("clk: ls1028a: Add clock driver for Display output interface") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20200203052507.93215-1-sboyd@kernel.org
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| *-----------. \ \ \ Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', ↵Stephen Boyd2020-01-3159-1125/+12120
| |\ \ \ \ \ \ \ \ \ \ | | | | |_|_|_|_|_|_|/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-freescale' and 'clk-qoriq' into clk-next - Support for Xilinx Versal platform clks - Display clk controller on qcom sc7180 - Video clk controller on qcom sc7180 - Graphics clk controller on qcom sc7180 - CPU PLLs for qcom msm8916 - Fixes for clk controllers on qcom msm8998 SoCs - Move qcom msm8974 gfx3d clk to RPM control - Display port clk support on qcom sdm845 SoCs - Global clk controller on qcom ipq6018 - Adjust composite clk to new way of describing clk parents - Add a driver for BCLK of Freescale SAI cores * clk-imx: (32 commits) clk: imx: Add support for i.MX8MP clock driver dt-bindings: imx: Add clock binding doc for i.MX8MP clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based API clk: imx: imx8mq: Switch to clk_hw based API clk: imx: imx8mm: Switch to clk_hw based API clk: imx: imx8mn: Switch to clk_hw based API clk: imx: Remove __init for imx_obtain_fixed_clk_hw() API clk: imx: gate3: Switch to clk_hw based API clk: imx: add hw API imx_clk_hw_mux2_flags clk: imx: add imx_unregister_hw_clocks clk: imx: clk-composite-8m: Switch to clk_hw based API clk: imx: clk-pll14xx: Switch to clk_hw based API clk: imx7up: Rename the clks to hws clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based clk: imx: Rename sccg and frac pll register to suggest clk_hw clk: imx: imx7ulp composite: Rename to show is clk_hw based clk: imx: pllv2: Switch to clk_hw based API clk: imx: pllv1: Switch to clk_hw based API ... * clk-ti: clk: ti: clkctrl: Fix hidden dependency to node name clk: ti: add clkctrl data dra7 sgx clk: ti: omap5: Add missing AESS clock clk: ti: dra7: fix parent for gmac_clkctrl clk: ti: dra7: add vpe clkctrl data clk: ti: dra7: add cam clkctrl data dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock * clk-xilinx: clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag clk: zynqmp: Fix divider calculation clk: zynqmp: Add support for get max divider clk: zynqmp: Warn user if clock user are more than allowed clk: zynqmp: Extend driver for versal dt-bindings: clock: Add bindings for versal clock driver * clk-nvidia: clk: tegra20/30: Explicitly set parent clock for Video Decoder clk: tegra20/30: Don't pre-initialize displays parent clock clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe() clk: tegra: Mark fuse clock as critical * clk-qcom: (35 commits) clk: qcom: rpmh: Sort OF match table dt-bindings: fix warnings in validation of qcom,gcc.yaml dt-binding: fix compilation error of the example in qcom,gcc.yaml clk: qcom: Add ipq6018 Global Clock Controller support clk: qcom: Add DT bindings for ipq6018 gcc clock controller clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks clk: qcom: rpmh: Add IPA clock for SC7180 clk: qcom: rpmh: skip undefined clocks when registering clk: qcom: Add video clock controller driver for SC7180 dt-bindings: clock: Introduce SC7180 QCOM Video clock bindings dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings clk: qcom: Add graphics clock controller driver for SC7180 dt-bindings: clock: Introduce SC7180 QCOM Graphics clock bindings dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings clk: qcom: apcs-msm8916: use clk_parent_data to specify the parent clk: qcom: Add display clock controller driver for SC7180 dt-bindings: clock: Introduce QCOM sc7180 display clock bindings dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration clk: qcom: alpha-pll: Remove useless read from set rate ... * clk-freescale: clk: fsl-sai: new driver dt-bindings: clock: document the fsl-sai driver clk: composite: add _register_composite_pdata() variants * clk-qoriq: clk: qoriq: add ls1088a hwaccel clocks support clk: ls1028a: Add clock driver for Display output interface dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings
| | | | | | | | * | | clk: qoriq: add ls1088a hwaccel clocks supportYangbo Lu2020-01-301-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to add hwaccel clocks information for ls1088a. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Link: https://lkml.kernel.org/r/20191216100111.17122-1-yangbo.lu@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | | | * | | clk: ls1028a: Add clock driver for Display output interfaceWen He2020-01-303-0/+297
| | | | | | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY), as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable integer division and range of the display output pixel clock's 27-594MHz. Signed-off-by: Wen He <wen.he_1@nxp.com> Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lkml.kernel.org/r/20191213083402.35678-2-wen.he_1@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | | * | | clk: fsl-sai: new driverMichael Walle2020-01-283-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this driver it is possible to use the BCLK pin of the SAI module as a generic clock output. This is esp. useful if you want to drive a clock to an audio codec. Because the output only allows integer divider values the audio codec needs an integrated PLL. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lkml.kernel.org/r/20200102231101.11834-3-michael@walle.cc Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | | * | | clk: composite: add _register_composite_pdata() variantsMichael Walle2020-01-281-3/+53
| | | | | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the new way of specifying the clock parents. Add the two new functions clk_hw_register_composite_pdata() clk_register_composite_pdata() to let the driver provide parent_data instead of the parent_names. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lkml.kernel.org/r/20200102231101.11834-1-michael@walle.cc Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | clk: qcom: rpmh: Sort OF match tableBjorn Andersson2020-01-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sc7180 was added to the end of the match table, sort the table. Fixes: eee28109f871 ("clk: qcom: clk-rpmh: Add support for RPMHCC for SC7180") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/20200124175934.3937473-1-bjorn.andersson@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | clk: qcom: Add ipq6018 Global Clock Controller supportSricharan R2020-01-093-0/+4644
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the global clock controller found on the ipq6018 based devices. Also fixed the sparse warnings reported by, Reported-by: kbuild test robot <lkp@intel.com> Co-developed-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Signed-off-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Co-developed-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Co-developed-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Link: https://lkml.kernel.org/r/1578557121-423-3-git-send-email-sricharan@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | clk: qcom: gcc-msm8996: Fix parent for CLKREF clocksBjorn Andersson2020-01-061-7/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the SoC. Update the definition of these clocks to allow this to be wired up to the appropriate clock source. Retain "xo" as the global named parent to make the change a nop in the event that DT doesn't carry the necessary clocks definition. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/20200106080546.3192125-2-bjorn.andersson@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | clk: qcom: rpmh: Add IPA clock for SC7180Taniya Das2020-01-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Qualcomm IP Accelerator (IPA) clock resource that is managed by the BCM is required by the IPA driver in order to scale its core clock. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1578305923-29125-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | clk: qcom: rpmh: skip undefined clocks when registeringTaniya Das2020-01-061-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When iterating over a platform's available clocks in clk_rpmh_probe(), check for undefined (null) entries in the clocks array. Not all clock indexes necessarily have clocks defined. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1578305923-29125-2-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Leave 'name' declaration at beginning of loop] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | clk: qcom: Add video clock controller driver for SC7180Taniya Das2020-01-043-0/+268
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the video clock controller found on SC7180 based devices. This would allow video drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1577428714-17766-7-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | clk: qcom: Add graphics clock controller driver for SC7180Taniya Das2020-01-043-0/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the graphics clock controller found on SC7180 based devices. This would allow graphics drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1577428714-17766-4-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | clk: qcom: apcs-msm8916: use clk_parent_data to specify the parentNiklas Cassel2020-01-041-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow accessing the parent clock names required for the driver operation by using the device tree 'clock-names' property, while falling back to the previous method of using names in the global name space. This permits extending the driver to other platforms without having to modify its source code. Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Link: https://lkml.kernel.org/r/20200103111429.1347-1-nks@flawful.org Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | Merge branch 'clk-register-dt-node-better' into clk-qcomStephen Boyd2020-01-041-2/+25
| | | | | | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-register-dt-node-better: clk: Use parent node pointer during registration if necessary
| | | | | | * | | | clk: qcom: Add display clock controller driver for SC7180Taniya Das2019-12-233-0/+786
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the display clock controller found on SC7180 based devices. This would allow display drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1573812245-23827-4-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | | clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibrationTaniya Das2019-12-232-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the cases where the PLL is not calibrated the PLL could fail to lock. Add support for prepare ops which would take care of the same. Fabia PLL user/test control registers might required to be configured, so add support for configuring them. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1573812304-24074-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | | clk: qcom: alpha-pll: Remove useless read from set rateTaniya Das2019-12-231-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PLL_MODE read in fabia set rate is not required, thus remove the same. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1573812304-24074-2-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | | clk: qcom: Add missing msm8998 gcc_bimc_gfx_clkJeffrey Hugo2019-12-231-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc_bimc_gfx_clk is a required clock for booting the GPU and GPU SMMU. Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support) Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191217164913.4783-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | | clk: qcom: apcs-msm8916: silently error out on EPROBE_DEFERJorge Ramirez-Ortiz2019-12-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If devm_clk_get() fails due to probe deferral, we shouldn't print an error message. Just be silent in this case. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Link: https://lkml.kernel.org/r/20191125135910.679310-7-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | | clk: qcom: hfpll: use clk_parent_data to specify the parentJorge Ramirez-Ortiz2019-12-181-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This permits extending the driver to other platforms without having to modify its source code. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Link: https://lkml.kernel.org/r/20191125135910.679310-6-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | | clk: qcom: hfpll: CLK_IGNORE_UNUSEDJorge Ramirez-Ortiz2019-12-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When COMMON_CLK_DISABLED_UNUSED is set, in an effort to save power and to keep the software model of the clock in line with reality, the framework transverses the clock tree and disables those clocks that were enabled by the firmware but have not been enabled by any device driver. If CPUFREQ is enabled, early during the system boot, it might attempt to change the CPU frequency ("set_rate"). If the HFPLL is selected as a provider, it will then change the rate for this clock. As boot continues, clk_disable_unused_subtree will run. Since it wont find a valid counter (enable_count) for a clock that is actually enabled it will attempt to disable it which will cause the CPU to stop. Notice that in this driver, calls to check whether the clock is enabled are routed via the is_enabled callback which queries the hardware. The following commit, rather than marking the clock critical and forcing the clock to be always enabled, addresses the above scenario making sure the clock is not disabled but it continues to rely on the firmware to enable the clock. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/20191125135910.679310-5-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | | clk: qcom: hfpll: register as clock providerJorge Ramirez-Ortiz2019-12-181-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the output of the high frequency pll a clock provider. On the QCS404 this PLL controls cpu frequency scaling. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20191125135910.679310-4-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | | clk: qcom: gcc: limit GPLL0_AO_OUT operating frequencyJorge Ramirez-Ortiz2019-12-183-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware specifications. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20191125135910.679310-3-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | | clk: qcom: smd: Add missing bimc clockJeffrey Hugo2019-12-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out booting the modem is dependent on a bimc vote from Linux on msm8998. To make the modem happy, add the bimc clock to rely on the default vote from rpmcc. Once we have interconnect support, bimc should be controlled properly. Fixes: 6131dc81211c ("clk: qcom: smd: Add support for MSM8998 rpm clocks") Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191217165409.4919-1-jeffrey.l.hugo@gmail.com Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | | clk: qcom: Add MSM8998 Multimedia Clock Controller (MMCC) driverJeffrey Hugo2019-12-183-0/+2923
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the multimedia clock controller found on MSM8998 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/1576596033-10189-1-git-send-email-jhugo@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | | clk: qcom: mmcc8974: move gfx3d_clk_src from the mmcc to rpmBrian Masney2019-12-182-13/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gfx3d_clk_src for msm8974 was introduced into the MMCC by commit d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)") to ensure that all of the clocks for this platform are documented upstream. This clock actually belongs on the RPM. Since then, commit 685dc94b7d8f ("clk: qcom: smd-rpmcc: Add msm8974 clocks") was introduced, which contains the proper definition for gfx3d_clk_src. Let's drop the definition from the mmcc and register the clock with the rpm instead. This change was tested on a Nexus 5 (hammerhead) phone. Signed-off-by: Brian Masney <masneyb@onstation.org> Link: https://lkml.kernel.org/r/20191115123931.18919-1-masneyb@onstation.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | | clk: qcom: dispcc: Add support for display port clocksTaniya Das2019-12-181-1/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SDM845 dispcc supports RCG and CBCRs for display port, so add support for the same. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20190731182713.8123-3-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | | * | | | clk: qcom: rcg2: Add support for display port clock opsTaniya Das2019-12-183-0/+79
| | | | | | | |/ / | | | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New display port clock ops supported for display port clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20190731182713.8123-2-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | * | | | clk: tegra20/30: Explicitly set parent clock for Video DecoderDmitry Osipenko2020-01-102-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VDE parent won't be changed automatically to PLLC if bootloader didn't do that for us, hence let's explicitly set the parent for consistency. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | | | | * | | | clk: tegra20/30: Don't pre-initialize displays parent clockDmitry Osipenko2020-01-102-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both Tegra20 and Tegra30 are initializing display's parent clock incorrectly because PLLP is running at 216/408MHz while display rate is set to 600MHz, but pre-setting the parent isn't needed at all because display driver selects proper parent anyways. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | | | | * | | | clk: tegra: divider: Check UART's divider enable-bit state on rate's ↵Dmitry Osipenko2020-01-101-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | recalculation UART clock is divided using divisor values from DLM/DLL registers when enable-bit is unset in clk register and clk's divider configuration isn't taken onto account in this case. This doesn't cause any problems, but let's add a check for the divider's enable-bit state, for consistency. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | | | | * | | | clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()Sowjanya Komatineni2020-01-101-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pm_runtime_irq_safe() is not needed as interrupts are allowed during suspend and resume. This was added mistakenly during DFLL suspend and resume support patch. While at it, also update the description of the dev argument that is passed to the tegra_dfll_suspend() function. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | | | | * | | | clk: tegra: Mark fuse clock as criticalStephen Warren2020-01-081-1/+5
| | | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For a little over a year, U-Boot on Tegra124 has configured the flow controller to perform automatic RAM re-repair on off->on power transitions of the CPU rail[1]. This is mandatory for correct operation of Tegra124. However, RAM re-repair relies on certain clocks, which the kernel must enable and leave running. The fuse clock is one of those clocks. Mark this clock as critical so that LP1 power mode (system suspend) operates correctly. [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair Reported-by: Jonathan Hunter <jonathanh@nvidia.com> Cc: stable@vger.kernel.org Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | | | * | | | clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flagTejas Patel2020-01-231-5/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Existing clock divider functions is not checking for base of divider. So, if any clock divider is power of 2 then clock rate calculation will be wrong. Add support to calculate divider value for the clocks with CLK_DIVIDER_POWER_OF_TWO flag. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lkml.kernel.org/r/1575527759-26452-7-git-send-email-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3-71-gd317 (git 2.46.0) at 2026-01-22 21:10:33 +0000