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path: root/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21
Commit message (Expand)AuthorAgeFilesLines
* drm/amd/display: Fic incorrect pipe being used for clk updateBhawanpreet Lakha2022-05-261-1/+1
* drm/amd/display: Insert pulling smu busy status before sending another requestOliver Logush2022-04-121-0/+3
* drm/amd/display: Power down hardware if timer not triggerPaul Hsieh2022-04-121-3/+14
* drm/amd/display: Revert W/A for hard hangs on DCN20/DCN21Mario Limonciello2022-01-141-10/+1
* drm/amd/display: fix function scopesIsabella Basso2021-12-132-19/+8
* drm/amd: add some extra checks that is_dig_enabled is definedMario Limonciello2021-12-131-1/+2
* drm/amd: append missing includesIsabella Basso2021-12-131-0/+2
* drm/amd/display: Replace referral of dal with dcQingqing Zhuo2021-09-281-1/+1
* drm/amd/display: Apply w/a for hard hang on HPDQingqing Zhuo2021-09-141-1/+11
* drm/amd/display: Revert "dc: w/a for hard hang on HPD on native DP"Qingqing Zhuo2021-09-141-3/+1
* drm/amd/display: workaround for hard hang on HPD on native DPQingqing Zhuo2021-08-051-1/+3
* drm/amd/display: Round KHz up when calculating clock requestsAric Cyr2021-07-081-8/+8
* drm/amd/display: Revert "Fix clock table filling logic"Ilya Bakoulin2021-06-081-51/+27
* drm/amd/display: treat memory as a single-channel for asymmetric memory V3Hugo Hu2021-05-191-2/+46
* drm/amd/display: Handle potential dpp_inst mismatch with pipe_idxAnthony Wang2021-05-101-3/+3
* drm/amd/display: Fix clock table filling logicIlya Bakoulin2021-05-101-27/+53
* drm/amdgpu/dc: Revert commit "treat memory as a single-channel"Aric Cyr2021-05-101-46/+2
* drm/amd/display: Revert wait vblank on update dpp clockLewis Huang2021-04-281-9/+1
* drm/amd/display: treat memory as a single-channel for asymmetric memory v2Hugo Hu2021-04-201-2/+46
* drm/amd/display: wait vblank when stream enabled and update dpp clockLewis Huang2021-04-151-1/+9
* drm/amd/display: Populate socclk entries for dcn2.1Roman Li2021-04-091-0/+13
* drm/amd/display: always program DPPDTO unless not safe to lowerJake Wang2020-12-231-6/+5
* drm/amd/display: updated wm table for RenoirJake Wang2020-12-231-8/+8
* drm/amd/display: Update RN/VGH active display count workaroundMichael Strauss2020-12-231-8/+1
* drm/amd/display: change SMU repsonse timeout to 2s.Yongqiang Sun2020-12-231-1/+1
* drm/amd/display: updated wm table for RenoirJake Wang2020-12-151-6/+6
* drm/amd/display: Add wm table for RenoirSung Lee2020-12-081-4/+89
* drm/amd/display: Init clock value by current vbios CLKsBrandon Syu2020-12-011-2/+11
* drm/amd/display: Increase sr enter/exit in rn ddr4 watermark tableWyatt Wood2020-11-161-2/+2
* drm/amd/display: set dpp dto as per requested clk for lower case.Yongqiang Sun2020-11-161-5/+23
* drm/amd/display: Handle Unknown Result for SMU Periodic Retraining on DCN2.1Sung Lee2020-11-161-1/+2
* drm/amd/display: Program dpp dto based on actual dpp clkYongqiang Sun2020-11-161-3/+26
* drm/amd/display: check actual clock value.Yongqiang Sun2020-11-102-3/+14
* drm/amd/display: update dpp dto phase and modulo.Yongqiang Sun2020-11-101-4/+2
* drm/amd/display: DCN2.1 Disable 48MHz Powerdown Debug OptionSung Lee2020-10-261-1/+1
* drm/amd/display: remove duplicate call to rn_vbios_smu_get_smu_version()Dirk Gouders2020-09-291-1/+0
* drm/amd/display: Check clock table returnRodrigo Siqueira2020-09-151-2/+5
* drm/amd/display: Send DISPLAY_OFF after power down on bootSung Lee2020-08-261-0/+10
* drm/amd/display: reduce sr_xxx_time by 3 us when ppt disableChiawen Huang2020-07-143-3/+54
* drm/amd/display: Request PHYCLK adjustment on PHY enable/disableJoshua Aberback2020-07-081-6/+21
* drm/amd/display: Handle SMU msg responseYongqiang Sun2020-07-021-2/+38
* drm/amd/display: Red screen observed on startupPeikang Zhang2020-07-011-1/+2
* drm/amd/display: Check for null fclk voltage when parsing clock tableMichael Strauss2020-04-071-1/+1
* drm/amd/display: Remove DISPCLK Limit Floor for Certain SMU VersionsSung Lee2020-03-051-0/+8
* drm/amd/display: make some rn_clk_mgr structs and funcs staticAnthony Koo2020-02-251-4/+4
* drm/amd/display: Limit minimum DPPCLK to 100MHz.Yongqiang Sun2020-02-061-0/+6
* drm/amd/display: Add wm ranges to clk_mgrSung Lee2020-02-061-3/+2
* drm/amd/display: Use dcfclk to populate watermark rangesSung Lee2020-02-061-7/+7
* drm/amd/display: Update HDMI hang w/a to apply to all TMDS signalsMichael Strauss2020-01-161-4/+6
* drm/amd/display: Remove unneeded semicolonzhengbin2019-12-181-1/+1
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