| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | interconnect: qcom: Add OSM L3 support on SC7180 | Sibi Sankar | 2020-03-03 | 1 | -0/+2 |
| | | | | | | | | | | | Add Operating State Manager (OSM) L3 interconnect provider support on SC7180 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Link: https://lore.kernel.org/r/20200227105632.15041-6-sibis@codeaurora.org Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> | ||||
| * | interconnect: qcom: Add SC7180 interconnect provider driver | Odelu Kukatla | 2020-03-03 | 1 | -0/+149 |
| Add driver for the Qualcomm interconnect buses found in SC7180 based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> Link: https://lore.kernel.org/r/1583241493-21212-3-git-send-email-okukatla@codeaurora.org Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> | |||||
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index : sinitax/cachepc-linux | |
| Fork of AMDESE/linux with modifications for CachePC side-channel attack | Louis Burda |
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