From 55b0f44cc2895460c7a244384b08e9d744894de8 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 12 Dec 2016 22:02:44 -0600 Subject: ARM: dts: socfpga: enable GPIO and LEDs for Cyclone5 and Arria5 devkits Enable all the GPIO ports and define the GPIO-based leds on the Cyclone5 and Arria5 devkits. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria5_socdk.dts | 35 ++++++++++++++++++++++++++++ arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 31 ++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index f739ead074a2..fa70c394dcfe 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -39,6 +39,29 @@ ethernet0 = &gmac1; }; + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&porta 0 1>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 11 1>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&porta 17 1>; + }; + + hps3 { + label = "hps_led3"; + gpios = <&porta 18 1>; + }; + }; + regulator_3_3v: 3-3-v-regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; @@ -61,6 +84,18 @@ rxc-skew-ps = <2000>; }; +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 6306d008f01b..6d3188bfefd8 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -39,6 +39,29 @@ ethernet0 = &gmac1; }; + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 15 1>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 14 1>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 13 1>; + }; + + hps3 { + label = "hps_led3"; + gpios = <&portb 12 1>; + }; + }; + regulator_3_3v: 3-3-v-regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; @@ -61,10 +84,18 @@ rxc-skew-ps = <2000>; }; +&gpio0 { + status = "okay"; +}; + &gpio1 { status = "okay"; }; +&gpio2 { + status = "okay"; +}; + &i2c0 { status = "okay"; -- cgit v1.2.3-71-gd317 From 4d3e72b1198bff5de939379d23c20d90e632b287 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 13 Dec 2016 16:52:11 -0600 Subject: ARM: dts: socfpga: set desired i2c clock on Cyclone5 and Arria5 devkits The I2C LCD display on the Cyclone5 and Arria5 devkits is only capable of the standard 100 kHz clock. Set the "clock-frequency" of the I2C node to be 100000. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria5_socdk.dts | 8 ++++++++ arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index fa70c394dcfe..8672edf9ba4e 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -98,6 +98,14 @@ &i2c0 { status = "okay"; + clock-frequency = <100000>; + + /* + * adjust the falling times to decrease the i2c frequency to 50Khz + * because the LCD module does not work at the standard 100Khz + */ + i2c-sda-falling-time-ns = <5000>; + i2c-scl-falling-time-ns = <5000>; eeprom@51 { compatible = "atmel,24c32"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 6d3188bfefd8..24650bafcef4 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -98,6 +98,14 @@ &i2c0 { status = "okay"; + clock-frequency = <100000>; + + /* + * adjust the falling times to decrease the i2c frequency to 50Khz + * because the LCD module does not work at the standard 100Khz + */ + i2c-sda-falling-time-ns = <5000>; + i2c-scl-falling-time-ns = <5000>; eeprom@51 { compatible = "atmel,24c32"; -- cgit v1.2.3-71-gd317 From c4fb689307fbb12284efa9f8c95de60bec728964 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 15 Dec 2016 23:30:03 -0600 Subject: ARM: dts: socfpga: Add Rohm DH2228FV DAC Enable the SPI node and add the Rohm DH2228FV DAC. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 24650bafcef4..c2884c9d0d09 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -159,6 +159,16 @@ }; }; +&spi0 { + status = "okay"; + + spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + &usb1 { status = "okay"; }; -- cgit v1.2.3-71-gd317 From a7f9dac38c0c500aaaf5335d904c5a48584f0eeb Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 16 Dec 2016 16:55:44 -0600 Subject: ARM: dts: socfpga: enable CAN on Cyclone5 devkit Enable the CAN node on the Cyclone5 devkit. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index c2884c9d0d09..7ea32c81e720 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -70,6 +70,10 @@ }; }; +&can0 { + status = "okay"; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; -- cgit v1.2.3-71-gd317 From a0c7807c3e8a303a6d9d492d55754ad1a1612dd7 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 16 Dec 2016 17:15:00 -0600 Subject: ARM: dts: socfpga: enable watchdog timer on Arria5 and Arria10 Enable the watchdog for Arria5 and Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 4 ++++ arch/arm/boot/dts/socfpga_arria5.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index eb00ae37f316..17ec17abf3c8 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -154,3 +154,7 @@ &usb0 { status = "okay"; }; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index 1907cc600452..8c037297296c 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -42,3 +42,7 @@ }; }; }; + +&watchdog0 { + status = "okay"; +}; -- cgit v1.2.3-71-gd317 From 3e2c972ca3204c73a777c7cfe91cc00c4dd1a7d3 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Sat, 17 Dec 2016 21:42:32 -0600 Subject: ARM: dts: socfpga: add the LTC2977 power monitor on Arria10 devkit Add the I2C LTC 2977 power monitor that is on the Arria10 devkit. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 17ec17abf3c8..4c99c99d1752 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -145,6 +145,11 @@ compatible = "dallas,ds1339"; reg = <0x68>; }; + + ltc@5c { + compatible = "ltc2977"; + reg = <0x5c>; + }; }; &uart1 { -- cgit v1.2.3-71-gd317 From f8a892815fee8766518c64bcbc95557d16410ba2 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Sat, 17 Dec 2016 22:45:03 -0600 Subject: ARM: dts: socfpga: add fpga-manager node for Arria10 Add the FPGA manger DTS entry for Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 551c636a4f01..3ceb4e496517 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -512,6 +512,15 @@ }; }; + fpga_mgr: fpga-mgr@ffd03000 { + compatible = "altr,socfpga-a10-fpga-mgr"; + reg = <0xffd03000 0x100 + 0xffcfe400 0x20>; + clocks = <&l4_mp_clk>; + resets = <&rst FPGAMGR_RESET>; + reset-names = "fpgamgr"; + }; + i2c0: i2c@ffc02200 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3-71-gd317 From f549af06e9b64a47b5ad6a45701d1b39330ddb48 Mon Sep 17 00:00:00 2001 From: Graham Moore Date: Tue, 7 Jul 2015 09:58:36 -0500 Subject: ARM: dts: socfpga: Add NAND device tree for Arria10 Add socfpga_arria10_socdk_nand.dts board file for supporting NAND. Signed-off-by: Graham Moore Signed-off-by: Dinh Nguyen --- v2: move nand dts node to socfpga_arria10.dtsi --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/socfpga_arria10.dtsi | 13 ++++++++++ arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts | 31 ++++++++++++++++++++++++ 3 files changed, 45 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index cccdbcb557b6..380d9bb66847 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -717,6 +717,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ + socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_mcvevk.dtb \ diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 3ceb4e496517..1139d3b212a2 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -614,6 +614,19 @@ status = "disabled"; }; + nand: nand@ffb90000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand"; + reg = <0xffb90000 0x72000>, + <0xffb80000 0x10000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0 99 4>; + dma-mask = <0xffffffff>; + clocks = <&nand_clk>; + status = "disabled"; + }; + ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x40000>; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts new file mode 100644 index 000000000000..d14f9ccb6e10 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2015 Altera Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" + +&nand { + status = "okay"; + + partition@nand-boot { + label = "Boot and fpga data"; + reg = <0x0 0x1C00000>; + }; + partition@nand-rootfs { + label = "Root Filesystem - JFFS2"; + reg = <0x1C00000 0x6400000>; + }; +}; -- cgit v1.2.3-71-gd317 From 6ed6bf47623fbcceb9a1187159a80c20f2874fcc Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 19 Dec 2016 22:34:00 -0600 Subject: ARM: dts: socfpga: fpga manager data is 32 bits Adjust regs property for the FPGA manager data register to properly reflect that it is a single 32 bit register. Signed-off-by: Dalon Westergreen Signed-off-by: Alan Tull Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index da689659131f..de291724e0be 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -516,7 +516,7 @@ fpgamgr0: fpgamgr@ff706000 { compatible = "altr,socfpga-fpga-mgr"; reg = <0xff706000 0x1000 - 0xffb90000 0x1000>; + 0xffb90000 0x4>; interrupts = <0 175 4>; }; -- cgit v1.2.3-71-gd317 From 7c8e5afd68733d0747c4ac2b5de58c54fb19763e Mon Sep 17 00:00:00 2001 From: Alan Tull Date: Fri, 26 Feb 2016 14:21:04 -0600 Subject: ARM: dts: socfpga: add base fpga region and fpga bridges Add h2f and lwh2f bridges. Add base FPGA Region to support DT overlays for FPGA programming. Add l3regs. Signed-off-by: Alan Tull Signed-off-by: Dinh Nguyen --- v2: removed fpga-bridges, ranges, and reset-names --- arch/arm/boot/dts/socfpga.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index de291724e0be..c984f5302cee 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -93,6 +93,14 @@ }; }; + base_fpga_region { + compatible = "fpga-region"; + fpga-mgr = <&fpgamgr0>; + + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + can0: can@ffc00000 { compatible = "bosch,d_can"; reg = <0xffc00000 0x1000>; @@ -513,6 +521,20 @@ }; }; + fpga_bridge0: fpga_bridge@ff400000 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + reg = <0xff400000 0x100000>; + resets = <&rst LWHPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + }; + + fpga_bridge1: fpga_bridge@ff500000 { + compatible = "altr,socfpga-hps2fpga-bridge"; + reg = <0xff500000 0x10000>; + resets = <&rst HPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + }; + fpgamgr0: fpgamgr@ff706000 { compatible = "altr,socfpga-fpga-mgr"; reg = <0xff706000 0x1000 @@ -694,6 +716,11 @@ arm,prefetch-offset = <7>; }; + l3regs@0xff800000 { + compatible = "altr,l3regs", "syscon"; + reg = <0xff800000 0x1000>; + }; + mmc: dwmmc0@ff704000 { compatible = "altr,socfpga-dw-mshc"; reg = <0xff704000 0x1000>; -- cgit v1.2.3-71-gd317 From 984442b72c23981510762518696a82d564d71a97 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 19 Dec 2016 23:21:27 -0600 Subject: ARM: dts: socfpga: add fpga region support on Arria10 Add the base FPGA region for DT overlay support in FPGA programming. Signed-off-by: Alan Tull Signed-off-by: Matthew Gerlach Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 1139d3b212a2..f21be425a9e5 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -83,6 +83,14 @@ }; }; + base_fpga_region { + #address-cells = <0x1>; + #size-cells = <0x1>; + + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr>; + }; + clkmgr@ffd04000 { compatible = "altr,clk-mgr"; reg = <0xffd04000 0x1000>; -- cgit v1.2.3-71-gd317 From 7f0f5460d46867a8f980683136a054cff1357780 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 20 Dec 2016 00:01:48 -0600 Subject: ARM: dts: socfpga: add missing compatible string for SDRAM controller Add "altr,sdr-ctl" to the SDRAM controller node. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 2 +- arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index c984f5302cee..2c43c4d85dee 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -778,7 +778,7 @@ }; sdr: sdr@ffc25000 { - compatible = "syscon"; + compatible = "altr,sdr-ctl", "syscon"; reg = <0xffc25000 0x1000>; }; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index f21be425a9e5..65904db153be 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -595,7 +595,7 @@ }; sdr: sdr@ffc25000 { - compatible = "syscon"; + compatible = "altr,sdr-ctl", "syscon"; reg = <0xffcfb100 0x80>; }; -- cgit v1.2.3-71-gd317