From 647cea2e68420fa73efb97c908cdf0c852c22cec Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Thu, 1 Dec 2016 18:27:26 -0800 Subject: arm64: dts: rockchip: add rk3399 thermal_zones phandle We're going to need to amend this table in board files. Signed-off-by: Brian Norris Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index c928015d39a2..cd18914692fe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -607,7 +607,7 @@ status = "disabled"; }; - thermal-zones { + thermal_zones: thermal-zones { cpu_thermal: cpu { polling-delay-passive = <100>; polling-delay = <1000>; -- cgit v1.2.3-71-gd317 From 8742466a43c9dea57684012175e146f0db3eec3b Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Thu, 1 Dec 2016 18:27:27 -0800 Subject: arm64: dts: rockchip: add rk3399 eDP HPD pinctrl We haven't enabled eDP support yet, but we might as well describe the pin now. Signed-off-by: Brian Norris Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index cd18914692fe..fc0642d7eab2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1436,6 +1436,13 @@ }; }; + edp { + edp_hpd: edp-hpd { + rockchip,pins = + <4 23 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + gmac { rgmii_pins: rgmii-pins { rockchip,pins = -- cgit v1.2.3-71-gd317 From b5d1c57299734f5b54035ef2e61706b83041f20c Mon Sep 17 00:00:00 2001 From: William wu Date: Wed, 21 Dec 2016 18:41:05 +0800 Subject: arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399 We found that the suspend process was blocked when it run into ehci/ohci module due to clk-480m of usb2-phy was disabled. The root cause is that usb2-phy suspended earlier than ehci/ohci (usb2-phy will be auto suspended if no devices plug-in). and the clk-480m provided by it was disabled if no module used. However, some suspend process related ehci/ohci are base on this clock, so we should refer it into ehci/ohci driver to prevent this case. The u2phy clock flow like this: === u2phy ________________ | | |-----> UTMI_CLK ---------> | EHCI | OSC_24M ---|---> PHY_PLL----|----| |________^_______| |-----> 480M_CLK ---|G|---> | USBPHY_480M_SRC| ----> USBPHY_480M for SoC | | GRF === Signed-off-by: William wu Signed-off-by: Xing Zheng Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index fc0642d7eab2..3761d061c173 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -321,8 +321,10 @@ compatible = "generic-ehci"; reg = <0x0 0xfe380000 0x0 0x20000>; interrupts = ; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; - clock-names = "hclk_host0", "hclk_host0_arb"; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, + <&u2phy0>; + clock-names = "usbhost", "arbiter", + "utmi"; phys = <&u2phy0_host>; phy-names = "usb"; status = "disabled"; @@ -332,8 +334,12 @@ compatible = "generic-ohci"; reg = <0x0 0xfe3a0000 0x0 0x20000>; interrupts = ; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; - clock-names = "hclk_host0", "hclk_host0_arb"; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, + <&u2phy0>; + clock-names = "usbhost", "arbiter", + "utmi"; + phys = <&u2phy0_host>; + phy-names = "usb"; status = "disabled"; }; @@ -341,8 +347,10 @@ compatible = "generic-ehci"; reg = <0x0 0xfe3c0000 0x0 0x20000>; interrupts = ; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; - clock-names = "hclk_host1", "hclk_host1_arb"; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, + <&u2phy1>; + clock-names = "usbhost", "arbiter", + "utmi"; phys = <&u2phy1_host>; phy-names = "usb"; status = "disabled"; @@ -352,8 +360,12 @@ compatible = "generic-ohci"; reg = <0x0 0xfe3e0000 0x0 0x20000>; interrupts = ; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; - clock-names = "hclk_host1", "hclk_host1_arb"; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, + <&u2phy1>; + clock-names = "usbhost", "arbiter", + "utmi"; + phys = <&u2phy1_host>; + phy-names = "usb"; status = "disabled"; }; -- cgit v1.2.3-71-gd317 From 4eb45558909e922757555ed65362c4701885d8a5 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sat, 22 Oct 2016 20:59:04 +0800 Subject: arm64: dts: rockchip: use pin constants to describe gpios Use macros to describe gpios will make the dts easier to read and write. Signed-off-by: Andy Yan [converted interrupt-gpios and new rk3399-evb backlight] Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi | 10 +++++----- arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts | 10 +++++----- arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts | 14 +++++++------- arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts | 10 +++++----- arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 16 ++++++++-------- arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 8 ++++---- 6 files changed, 34 insertions(+), 34 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi index fff8b1931f26..4772917c5f7e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi @@ -90,7 +90,7 @@ 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>; default-brightness-level = <128>; - enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&bl_en>; pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>; @@ -101,7 +101,7 @@ compatible = "mmc-pwrseq-emmc"; pinctrl-0 = <&emmc_reset>; pinctrl-names = "default"; - reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; }; keys: gpio-keys { @@ -111,7 +111,7 @@ power { wakeup-source; - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; linux,code = ; }; @@ -121,7 +121,7 @@ vcc_host: vcc-host-regulator { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&host_vbus_drv>; regulator-name = "vcc_host"; @@ -166,7 +166,7 @@ phy-supply = <&vcc_lan>; phy-mode = "rmii"; clock_in_out = "output"; - snps,reset-gpio = <&gpio3 12 0>; + snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; snps,reset-active-low; snps,reset-delays-us = <0 10000 1000000>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts index e5eeca2c2456..e631d424f08e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts @@ -66,7 +66,7 @@ ir: ir-receiver { compatible = "gpio-ir-receiver"; - gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ir_int>; }; @@ -77,7 +77,7 @@ pinctrl-0 = <&pwr_key>; power { - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; linux,code = ; wakeup-source; @@ -88,13 +88,13 @@ compatible = "gpio-leds"; blue { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; label = "geekbox:blue:led"; default-state = "on"; }; red { - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; label = "geekbox:red:led"; default-state = "off"; }; @@ -146,7 +146,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pmic_int>, <&pmic_sleep>; interrupt-parent = <&gpio0>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; rockchip,system-power-controller; vcc1-supply = <&vcc_sys>; vcc2-supply = <&vcc_sys>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts index ff5a40399d02..fac116acc12f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts @@ -61,7 +61,7 @@ compatible = "mmc-pwrseq-emmc"; pinctrl-0 = <&emmc_reset>; pinctrl-names = "default"; - reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; }; ext_gmac: external-gmac-clock { @@ -78,7 +78,7 @@ power { wakeup-source; - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; label = "GPIO Power"; linux,code = ; }; @@ -88,7 +88,7 @@ compatible = "gpio-leds"; red { - gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; label = "orion:red:led"; pinctrl-names = "default"; pinctrl-0 = <&led_ctl>; @@ -96,7 +96,7 @@ }; blue { - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; label = "orion:blue:led"; pinctrl-names = "default"; pinctrl-0 = <&stby_pwren>; @@ -117,7 +117,7 @@ /* supplies both host and otg */ vcc_host: vcc-host-regulator { compatible = "regulator-fixed"; - gpio = <&gpio0 4 GPIO_ACTIVE_LOW>; + gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&host_vbus_drv>; regulator-name = "vcc_host"; @@ -149,7 +149,7 @@ vcc_sd: vcc-sd-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_sd"; - gpio = <&gpio3 11 GPIO_ACTIVE_LOW>; + gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; vin-supply = <&vcc_io>; @@ -217,7 +217,7 @@ phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 12 0>; + snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; snps,reset-active-low; snps,reset-delays-us = <0 10000 1000000>; tx_delay = <0x30>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts index 85f7a243d744..8cdb3bff9c55 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts @@ -63,7 +63,7 @@ pinctrl-0 = <&pwr_key>; power { - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; linux,code = ; wakeup-source; @@ -105,7 +105,7 @@ compatible = "rockchip,rk808"; reg = <0x1b>; interrupt-parent = <&gpio0>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&pmic_int>, <&pmic_sleep>; rockchip,system-power-controller; @@ -236,7 +236,7 @@ compatible = "bosch,bma250"; reg = <0x18>; interrupt-parent = <&gpio2>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; }; @@ -247,8 +247,8 @@ compatible = "silead,gsl1680"; reg = <0x40>; interrupt-parent = <&gpio3>; - interrupts = <28 IRQ_TYPE_EDGE_FALLING>; - power-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + interrupts = ; + power-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; touchscreen-size-x = <800>; touchscreen-size-y = <1280>; silead,max-fingers = <5>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts index eed1ef6669ff..7134181f1dc2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts @@ -61,7 +61,7 @@ compatible = "mmc-pwrseq-emmc"; pinctrl-0 = <&emmc_reset>; pinctrl-names = "default"; - reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; }; keys: gpio-keys { @@ -71,7 +71,7 @@ power { wakeup-source; - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; linux,code = ; }; @@ -81,7 +81,7 @@ compatible = "gpio-leds"; work { - gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; label = "r88:green:led"; pinctrl-names = "default"; pinctrl-0 = <&led_ctl>; @@ -90,7 +90,7 @@ ir: ir-receiver { compatible = "gpio-ir-receiver"; - gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ir_int>; }; @@ -104,10 +104,10 @@ reset-gpios = /* BT_RST_N */ - <&gpio3 5 GPIO_ACTIVE_LOW>, + <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ - <&gpio3 4 GPIO_ACTIVE_LOW>; + <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; }; vcc_18: vcc18-regulator { @@ -124,7 +124,7 @@ vcc_host: vcc-host-regulator { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&host_vbus_drv>; regulator-name = "vcc_host"; @@ -199,7 +199,7 @@ phy-supply = <&vcc_lan>; phy-mode = "rmii"; clock_in_out = "output"; - snps,reset-gpio = <&gpio3 12 0>; + snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; snps,reset-active-low; snps,reset-delays-us = <0 10000 1000000>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts index 3040a989d699..42033bcc614c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts @@ -85,7 +85,7 @@ 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>; default-brightness-level = <200>; - enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; pwms = <&pwm0 0 25000 0>; }; @@ -128,7 +128,7 @@ vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_host_en>; regulator-name = "vcc5v0_host"; @@ -163,7 +163,7 @@ phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; snps,reset-active-low; snps,reset-delays-us = <0 10000 50000>; tx_delay = <0x28>; @@ -196,7 +196,7 @@ }; &pcie0 { - ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; num-lanes = <4>; pinctrl-names = "default"; pinctrl-0 = <&pcie_clkreqn>; -- cgit v1.2.3-71-gd317 From 712fa1777207c2f2703a6eb618a9699099cbe37b Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 16 Dec 2016 17:42:36 +0800 Subject: arm64: dts: rockchip: add max-link-speed for rk3399 Per the errata of TRM, rk3399 won't support gen2 from now on, so let's set max-link-speed to 1 in order not to doing training for gen2. Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 3761d061c173..92b731f592c6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -297,6 +297,7 @@ <0 0 0 2 &pcie0_intc 1>, <0 0 0 3 &pcie0_intc 2>, <0 0 0 4 &pcie0_intc 3>; + max-link-speed = <1>; msi-map = <0x0 &its 0x0 0x1000>; phys = <&pcie_phy>; phy-names = "pcie-phy"; -- cgit v1.2.3-71-gd317 From 59cf70be5b7c6e3370f669976e3778104f4327ca Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 16 Dec 2016 17:42:37 +0800 Subject: arm64: dts: rockchip: add aspm-no-l0s for rk3399 Per the discussion of bug fix[1], we now actually leaves the default clock choice for pcie phy is derived from 24MHz OSC to guarantee the least BER. So let's add aspm-no-l0s here and folks could delete this property from their dts. [1] https://patchwork.kernel.org/patch/9470519/ Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 92b731f592c6..a28b51ce4232 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -283,6 +283,7 @@ #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; + aspm-no-l0s; bus-range = <0x0 0x1>; clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; -- cgit v1.2.3-71-gd317 From 8cbb59af7ecf183b1761a178835e1c771167fa28 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Tue, 10 Jan 2017 14:15:29 +0800 Subject: arm64: dts: rockchip: add rockchip,grf property for RK3399 PMUCRU/CRU The structure rockchip_clk_provider needs to refer the GRF regmap in somewhere, if the CRU node has not "rockchip,grf" property, calling syscon_regmap_lookup_by_phandle will return an invalid GRF regmap, and the MUXGRF type clock will be not supported. Therefore, we need to add them. Signed-off-by: Xing Zheng Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index a28b51ce4232..8e6d1bdeb9c3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1091,6 +1091,7 @@ pmucru: pmu-clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; + rockchip,grf = <&pmugrf>; #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&pmucru PLL_PPLL>; @@ -1100,6 +1101,7 @@ cru: clock-controller@ff760000 { compatible = "rockchip,rk3399-cru"; reg = <0x0 0xff760000 0x0 0x1000>; + rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = -- cgit v1.2.3-71-gd317