From 3b0b278312ba7d6c1eb8b2fb48d459fb7f341a20 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 29 Jul 2019 16:35:03 +0300 Subject: NFC: nxp-nci: Get rid of platform data Legacy platform data must go away. We are on the safe side here since there are no users of it in the kernel. If anyone by any odd reason needs it the GPIO lookup tables and built-in device properties at your service. Signed-off-by: Andy Shevchenko Tested-by: Sedat Dilek Signed-off-by: David S. Miller --- include/linux/platform_data/nxp-nci.h | 19 ------------------- 1 file changed, 19 deletions(-) delete mode 100644 include/linux/platform_data/nxp-nci.h (limited to 'include/linux/platform_data') diff --git a/include/linux/platform_data/nxp-nci.h b/include/linux/platform_data/nxp-nci.h deleted file mode 100644 index 97827ad468e2..000000000000 --- a/include/linux/platform_data/nxp-nci.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Generic platform data for the NXP NCI NFC chips. - * - * Copyright (C) 2014 NXP Semiconductors All rights reserved. - * - * Authors: Clément Perrochaud - */ - -#ifndef _NXP_NCI_H_ -#define _NXP_NCI_H_ - -struct nxp_nci_nfc_platform_data { - unsigned int gpio_en; - unsigned int gpio_fw; - unsigned int irq; -}; - -#endif /* _NXP_NCI_H_ */ -- cgit v1.2.3-71-gd317 From 156189a6d7a797d6fa0b13dd6b4f32b11d234a99 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Jul 2019 01:40:15 +0900 Subject: leds: netxbig: remove legacy board-file support Since commit ebc278f15759 ("ARM: mvebu: remove static LED setup for netxbig boards"), no one in upstream passes in the platform data to this driver. Squash leds-kirkwood-netxbig.h into the driver, and remove the legacy board-file support. Link: https://lkml.org/lkml/2019/7/20/83 Suggested-by: Arnd Bergmann Signed-off-by: Masahiro Yamada Signed-off-by: Jacek Anaszewski --- drivers/leds/Kconfig | 1 + drivers/leds/leds-netxbig.c | 70 +++++++++++++++------- .../linux/platform_data/leds-kirkwood-netxbig.h | 54 ----------------- 3 files changed, 51 insertions(+), 74 deletions(-) delete mode 100644 include/linux/platform_data/leds-kirkwood-netxbig.h (limited to 'include/linux/platform_data') diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index f7a3dd7ecf3d..1988de1d64c0 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -590,6 +590,7 @@ config LEDS_NETXBIG tristate "LED support for Big Network series LEDs" depends on LEDS_CLASS depends on MACH_KIRKWOOD + depends on OF_GPIO default y help This option enables support for LEDs found on the LaCie 2Big diff --git a/drivers/leds/leds-netxbig.c b/drivers/leds/leds-netxbig.c index 10497a466775..0944cb111c34 100644 --- a/drivers/leds/leds-netxbig.c +++ b/drivers/leds/leds-netxbig.c @@ -15,7 +15,48 @@ #include #include #include -#include + +struct netxbig_gpio_ext { + unsigned int *addr; + int num_addr; + unsigned int *data; + int num_data; + unsigned int enable; +}; + +enum netxbig_led_mode { + NETXBIG_LED_OFF, + NETXBIG_LED_ON, + NETXBIG_LED_SATA, + NETXBIG_LED_TIMER1, + NETXBIG_LED_TIMER2, + NETXBIG_LED_MODE_NUM, +}; + +#define NETXBIG_LED_INVALID_MODE NETXBIG_LED_MODE_NUM + +struct netxbig_led_timer { + unsigned long delay_on; + unsigned long delay_off; + enum netxbig_led_mode mode; +}; + +struct netxbig_led { + const char *name; + const char *default_trigger; + int mode_addr; + int *mode_val; + int bright_addr; + int bright_max; +}; + +struct netxbig_led_platform_data { + struct netxbig_gpio_ext *gpio_ext; + struct netxbig_led_timer *timer; + int num_timer; + struct netxbig_led *leds; + int num_leds; +}; /* * GPIO extension bus. @@ -306,7 +347,6 @@ static int create_netxbig_led(struct platform_device *pdev, return devm_led_classdev_register(&pdev->dev, &led_dat->cdev); } -#ifdef CONFIG_OF_GPIO static int gpio_ext_get_of_pdata(struct device *dev, struct device_node *np, struct netxbig_gpio_ext *gpio_ext) { @@ -522,30 +562,20 @@ static const struct of_device_id of_netxbig_leds_match[] = { {}, }; MODULE_DEVICE_TABLE(of, of_netxbig_leds_match); -#else -static inline int -netxbig_leds_get_of_pdata(struct device *dev, - struct netxbig_led_platform_data *pdata) -{ - return -ENODEV; -} -#endif /* CONFIG_OF_GPIO */ static int netxbig_led_probe(struct platform_device *pdev) { - struct netxbig_led_platform_data *pdata = dev_get_platdata(&pdev->dev); + struct netxbig_led_platform_data *pdata; struct netxbig_led_data *leds_data; int i; int ret; - if (!pdata) { - pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); - if (!pdata) - return -ENOMEM; - ret = netxbig_leds_get_of_pdata(&pdev->dev, pdata); - if (ret) - return ret; - } + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + ret = netxbig_leds_get_of_pdata(&pdev->dev, pdata); + if (ret) + return ret; leds_data = devm_kcalloc(&pdev->dev, pdata->num_leds, sizeof(*leds_data), @@ -571,7 +601,7 @@ static struct platform_driver netxbig_led_driver = { .probe = netxbig_led_probe, .driver = { .name = "leds-netxbig", - .of_match_table = of_match_ptr(of_netxbig_leds_match), + .of_match_table = of_netxbig_leds_match, }, }; diff --git a/include/linux/platform_data/leds-kirkwood-netxbig.h b/include/linux/platform_data/leds-kirkwood-netxbig.h deleted file mode 100644 index 3c85a735c380..000000000000 --- a/include/linux/platform_data/leds-kirkwood-netxbig.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Platform data structure for netxbig LED driver - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __LEDS_KIRKWOOD_NETXBIG_H -#define __LEDS_KIRKWOOD_NETXBIG_H - -struct netxbig_gpio_ext { - unsigned *addr; - int num_addr; - unsigned *data; - int num_data; - unsigned enable; -}; - -enum netxbig_led_mode { - NETXBIG_LED_OFF, - NETXBIG_LED_ON, - NETXBIG_LED_SATA, - NETXBIG_LED_TIMER1, - NETXBIG_LED_TIMER2, - NETXBIG_LED_MODE_NUM, -}; - -#define NETXBIG_LED_INVALID_MODE NETXBIG_LED_MODE_NUM - -struct netxbig_led_timer { - unsigned long delay_on; - unsigned long delay_off; - enum netxbig_led_mode mode; -}; - -struct netxbig_led { - const char *name; - const char *default_trigger; - int mode_addr; - int *mode_val; - int bright_addr; - int bright_max; -}; - -struct netxbig_led_platform_data { - struct netxbig_gpio_ext *gpio_ext; - struct netxbig_led_timer *timer; - int num_timer; - struct netxbig_led *leds; - int num_leds; -}; - -#endif /* __LEDS_KIRKWOOD_NETXBIG_H */ -- cgit v1.2.3-71-gd317 From 2889ffcfc2522d6d25e5bda704275064062bbb21 Mon Sep 17 00:00:00 2001 From: Daniel Drake Date: Mon, 29 Jul 2019 16:27:37 +0800 Subject: platform/x86: asus-wmi: cleanup AGFN fan handling The asus-wmi driver currently uses the "AGFN" interface and the FAN_CTRL device for fan control. According to the spec, this interface is very dated and marked as pending removal from products currently in development. Clean up the way that the AGFN fan is detected and handled, also preparing the driver for the introduction of an alternate fan control method needed to support recent Asus products. Not anticipating further development of this interface, simplify the code by dropping any notion of being able to control multiple AGFN fans (this was already limited to just a single fan through only exposing a single fan in sysfs). Check for the presence of AGFN fans at probe time, simplifying the code flow in asus_hwmon_sysfs_is_visible(). Signed-off-by: Daniel Drake Signed-off-by: Andy Shevchenko --- drivers/platform/x86/asus-wmi.c | 238 +++++++++++++---------------- include/linux/platform_data/x86/asus-wmi.h | 4 +- 2 files changed, 109 insertions(+), 133 deletions(-) (limited to 'include/linux/platform_data') diff --git a/drivers/platform/x86/asus-wmi.c b/drivers/platform/x86/asus-wmi.c index 0c6a810fcb72..fc2939ac1cfe 100644 --- a/drivers/platform/x86/asus-wmi.c +++ b/drivers/platform/x86/asus-wmi.c @@ -65,6 +65,8 @@ MODULE_LICENSE("GPL"); #define ASUS_FAN_MFUN 0x13 #define ASUS_FAN_SFUN_READ 0x06 #define ASUS_FAN_SFUN_WRITE 0x07 + +/* Based on standard hwmon pwmX_enable values */ #define ASUS_FAN_CTRL_MANUAL 1 #define ASUS_FAN_CTRL_AUTO 2 @@ -120,7 +122,7 @@ struct agfn_args { } __packed; /* struct used for calling fan read and write methods */ -struct fan_args { +struct agfn_fan_args { struct agfn_args agfn; /* common fields */ u8 fan; /* fan number: 0: set auto mode 1: 1st fan */ u32 speed; /* read: RPM/100 - write: 0-255 */ @@ -148,6 +150,11 @@ struct asus_rfkill { u32 dev_id; }; +enum fan_type { + FAN_TYPE_NONE = 0, + FAN_TYPE_AGFN, /* deprecated on newer platforms */ +}; + struct asus_wmi { int dsts_id; int spec; @@ -178,9 +185,9 @@ struct asus_wmi { struct asus_rfkill gps; struct asus_rfkill uwb; - bool asus_hwmon_fan_manual_mode; - int asus_hwmon_num_fans; - int asus_hwmon_pwm; + enum fan_type fan_type; + int fan_pwm_mode; + int agfn_pwm; bool fan_boost_mode_available; u8 fan_boost_mode_mask; @@ -1125,10 +1132,10 @@ static void asus_wmi_set_als(void) /* Hwmon device ***************************************************************/ -static int asus_hwmon_agfn_fan_speed_read(struct asus_wmi *asus, int fan, +static int asus_agfn_fan_speed_read(struct asus_wmi *asus, int fan, int *speed) { - struct fan_args args = { + struct agfn_fan_args args = { .agfn.len = sizeof(args), .agfn.mfun = ASUS_FAN_MFUN, .agfn.sfun = ASUS_FAN_SFUN_READ, @@ -1152,10 +1159,10 @@ static int asus_hwmon_agfn_fan_speed_read(struct asus_wmi *asus, int fan, return 0; } -static int asus_hwmon_agfn_fan_speed_write(struct asus_wmi *asus, int fan, +static int asus_agfn_fan_speed_write(struct asus_wmi *asus, int fan, int *speed) { - struct fan_args args = { + struct agfn_fan_args args = { .agfn.len = sizeof(args), .agfn.mfun = ASUS_FAN_MFUN, .agfn.sfun = ASUS_FAN_SFUN_WRITE, @@ -1175,7 +1182,7 @@ static int asus_hwmon_agfn_fan_speed_write(struct asus_wmi *asus, int fan, return -ENXIO; if (speed && fan == 1) - asus->asus_hwmon_pwm = *speed; + asus->agfn_pwm = *speed; return 0; } @@ -1184,87 +1191,75 @@ static int asus_hwmon_agfn_fan_speed_write(struct asus_wmi *asus, int fan, * Check if we can read the speed of one fan. If true we assume we can also * control it. */ -static int asus_hwmon_get_fan_number(struct asus_wmi *asus, int *num_fans) +static bool asus_wmi_has_agfn_fan(struct asus_wmi *asus) { int status; - int speed = 0; + int speed; + u32 value; - *num_fans = 0; + status = asus_agfn_fan_speed_read(asus, 1, &speed); + if (status != 0) + return false; - status = asus_hwmon_agfn_fan_speed_read(asus, 1, &speed); - if (!status) - *num_fans = 1; + status = asus_wmi_get_devstate(asus, ASUS_WMI_DEVID_FAN_CTRL, &value); + if (status != 0) + return false; - return 0; + /* + * We need to find a better way, probably using sfun, + * bits or spec ... + * Currently we disable it if: + * - ASUS_WMI_UNSUPPORTED_METHOD is returned + * - reverved bits are non-zero + * - sfun and presence bit are not set + */ + return !(value == ASUS_WMI_UNSUPPORTED_METHOD || value & 0xFFF80000 + || (!asus->sfun && !(value & ASUS_WMI_DSTS_PRESENCE_BIT))); } -static int asus_hwmon_fan_set_auto(struct asus_wmi *asus) +static int asus_fan_set_auto(struct asus_wmi *asus) { int status; - status = asus_hwmon_agfn_fan_speed_write(asus, 0, NULL); + status = asus_agfn_fan_speed_write(asus, 0, NULL); if (status) return -ENXIO; - asus->asus_hwmon_fan_manual_mode = false; - return 0; } -static int asus_hwmon_fan_rpm_show(struct device *dev, int fan) +static ssize_t pwm1_show(struct device *dev, + struct device_attribute *attr, + char *buf) { struct asus_wmi *asus = dev_get_drvdata(dev); - int value; - int ret; - - /* no speed readable on manual mode */ - if (asus->asus_hwmon_fan_manual_mode) - return -ENXIO; - - ret = asus_hwmon_agfn_fan_speed_read(asus, fan+1, &value); - if (ret) { - pr_warn("reading fan speed failed: %d\n", ret); - return -ENXIO; - } - - return value; -} - -static void asus_hwmon_pwm_show(struct asus_wmi *asus, int fan, int *value) -{ int err; + int value; - if (asus->asus_hwmon_pwm >= 0) { - *value = asus->asus_hwmon_pwm; - return; - } + /* If we already set a value then just return it */ + if (asus->agfn_pwm >= 0) + return sprintf(buf, "%d\n", asus->agfn_pwm); - err = asus_wmi_get_devstate(asus, ASUS_WMI_DEVID_FAN_CTRL, value); + /* + * If we haven't set already set a value through the AGFN interface, + * we read a current value through the (now-deprecated) FAN_CTRL device. + */ + err = asus_wmi_get_devstate(asus, ASUS_WMI_DEVID_FAN_CTRL, &value); if (err < 0) - return; + return err; - *value &= 0xFF; - - if (*value == 1) /* Low Speed */ - *value = 85; - else if (*value == 2) - *value = 170; - else if (*value == 3) - *value = 255; - else if (*value) { - pr_err("Unknown fan speed %#x\n", *value); - *value = -1; + value &= 0xFF; + + if (value == 1) /* Low Speed */ + value = 85; + else if (value == 2) + value = 170; + else if (value == 3) + value = 255; + else if (value) { + pr_err("Unknown fan speed %#x\n", value); + value = -1; } -} - -static ssize_t pwm1_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct asus_wmi *asus = dev_get_drvdata(dev); - int value; - - asus_hwmon_pwm_show(asus, 0, &value); return sprintf(buf, "%d\n", value); } @@ -1284,11 +1279,11 @@ static ssize_t pwm1_store(struct device *dev, value = clamp(value, 0, 255); - state = asus_hwmon_agfn_fan_speed_write(asus, 1, &value); + state = asus_agfn_fan_speed_write(asus, 1, &value); if (state) pr_warn("Setting fan speed failed: %d\n", state); else - asus->asus_hwmon_fan_manual_mode = true; + asus->fan_pwm_mode = ASUS_FAN_CTRL_MANUAL; return count; } @@ -1297,10 +1292,21 @@ static ssize_t fan1_input_show(struct device *dev, struct device_attribute *attr, char *buf) { - int value = asus_hwmon_fan_rpm_show(dev, 0); + struct asus_wmi *asus = dev_get_drvdata(dev); + int value; + int ret; - return sprintf(buf, "%d\n", value < 0 ? -1 : value*100); + /* no speed readable on manual mode */ + if (asus->fan_pwm_mode == ASUS_FAN_CTRL_MANUAL) + return -ENXIO; + + ret = asus_agfn_fan_speed_read(asus, 1, &value); + if (ret) { + pr_warn("reading fan speed failed: %d\n", ret); + return -ENXIO; + } + return sprintf(buf, "%d\n", value < 0 ? -1 : value*100); } static ssize_t pwm1_enable_show(struct device *dev, @@ -1309,10 +1315,7 @@ static ssize_t pwm1_enable_show(struct device *dev, { struct asus_wmi *asus = dev_get_drvdata(dev); - if (asus->asus_hwmon_fan_manual_mode) - return sprintf(buf, "%d\n", ASUS_FAN_CTRL_MANUAL); - - return sprintf(buf, "%d\n", ASUS_FAN_CTRL_AUTO); + return sprintf(buf, "%d\n", asus->fan_pwm_mode); } static ssize_t pwm1_enable_store(struct device *dev, @@ -1329,14 +1332,21 @@ static ssize_t pwm1_enable_store(struct device *dev, if (ret) return ret; - if (state == ASUS_FAN_CTRL_MANUAL) - asus->asus_hwmon_fan_manual_mode = true; - else - status = asus_hwmon_fan_set_auto(asus); + switch (state) { + case ASUS_FAN_CTRL_MANUAL: + break; - if (status) - return status; + case ASUS_FAN_CTRL_AUTO: + status = asus_fan_set_auto(asus); + if (status) + return status; + break; + default: + return -EINVAL; + } + + asus->fan_pwm_mode = state; return count; } @@ -1389,59 +1399,31 @@ static umode_t asus_hwmon_sysfs_is_visible(struct kobject *kobj, { struct device *dev = container_of(kobj, struct device, kobj); struct asus_wmi *asus = dev_get_drvdata(dev->parent); - int dev_id = -1; - int fan_attr = -1; u32 value = ASUS_WMI_UNSUPPORTED_METHOD; - bool ok = true; - - if (attr == &dev_attr_pwm1.attr) - dev_id = ASUS_WMI_DEVID_FAN_CTRL; - else if (attr == &dev_attr_temp1_input.attr) - dev_id = ASUS_WMI_DEVID_THERMAL_CTRL; - if (attr == &dev_attr_fan1_input.attr || attr == &dev_attr_fan1_label.attr || attr == &dev_attr_pwm1.attr || attr == &dev_attr_pwm1_enable.attr) { - fan_attr = 1; - } - - if (dev_id != -1) { - int err = asus_wmi_get_devstate(asus, dev_id, &value); + if (asus->fan_type == FAN_TYPE_NONE) + return 0; + } else if (attr == &dev_attr_temp1_input.attr) { + int err = asus_wmi_get_devstate(asus, + ASUS_WMI_DEVID_THERMAL_CTRL, + &value); - if (err < 0 && fan_attr == -1) + if (err < 0) return 0; /* can't return negative here */ - } - if (dev_id == ASUS_WMI_DEVID_FAN_CTRL) { - /* - * We need to find a better way, probably using sfun, - * bits or spec ... - * Currently we disable it if: - * - ASUS_WMI_UNSUPPORTED_METHOD is returned - * - reverved bits are non-zero - * - sfun and presence bit are not set - */ - if (value == ASUS_WMI_UNSUPPORTED_METHOD || value & 0xFFF80000 - || (!asus->sfun && !(value & ASUS_WMI_DSTS_PRESENCE_BIT))) - ok = false; - else - ok = fan_attr <= asus->asus_hwmon_num_fans; - } else if (dev_id == ASUS_WMI_DEVID_THERMAL_CTRL) { /* * If the temperature value in deci-Kelvin is near the absolute * zero temperature, something is clearly wrong */ if (value == 0 || value == 1) - ok = false; - } else if (fan_attr <= asus->asus_hwmon_num_fans && fan_attr != -1) { - ok = true; - } else { - ok = false; + return 0; } - return ok ? attr->mode : 0; + return attr->mode; } static const struct attribute_group hwmon_attribute_group = { @@ -1467,21 +1449,16 @@ static int asus_wmi_hwmon_init(struct asus_wmi *asus) static int asus_wmi_fan_init(struct asus_wmi *asus) { - int status; - - asus->asus_hwmon_pwm = -1; - asus->asus_hwmon_num_fans = -1; - asus->asus_hwmon_fan_manual_mode = false; + asus->fan_type = FAN_TYPE_NONE; + asus->agfn_pwm = -1; - status = asus_hwmon_get_fan_number(asus, &asus->asus_hwmon_num_fans); - if (status) { - asus->asus_hwmon_num_fans = 0; - pr_warn("Could not determine number of fans: %d\n", status); - return -ENXIO; + if (asus_wmi_has_agfn_fan(asus)) { + asus->fan_type = FAN_TYPE_AGFN; + asus_fan_set_auto(asus); + asus->fan_pwm_mode = ASUS_FAN_CTRL_AUTO; } - pr_info("Number of fans: %d\n", asus->asus_hwmon_num_fans); - return 0; + return asus->fan_type != FAN_TYPE_NONE; } /* Fan mode *******************************************************************/ @@ -2333,7 +2310,6 @@ static int asus_wmi_add(struct platform_device *pdev) goto fail_input; err = asus_wmi_fan_init(asus); /* probably no problems on error */ - asus_hwmon_fan_set_auto(asus); err = asus_wmi_hwmon_init(asus); if (err) @@ -2425,7 +2401,7 @@ static int asus_wmi_remove(struct platform_device *device) asus_wmi_rfkill_exit(asus); asus_wmi_debugfs_exit(asus); asus_wmi_sysfs_exit(asus->platform_device); - asus_hwmon_fan_set_auto(asus); + asus_fan_set_auto(asus); kfree(asus); return 0; diff --git a/include/linux/platform_data/x86/asus-wmi.h b/include/linux/platform_data/x86/asus-wmi.h index 4802cd2c7309..5ae9c062a1f6 100644 --- a/include/linux/platform_data/x86/asus-wmi.h +++ b/include/linux/platform_data/x86/asus-wmi.h @@ -12,7 +12,7 @@ #define ASUS_WMI_METHODID_GPID 0x44495047 /* Get Panel ID?? (Resol) */ #define ASUS_WMI_METHODID_QMOD 0x444F4D51 /* Quiet MODe */ #define ASUS_WMI_METHODID_SPLV 0x4C425053 /* Set Panel Light Value */ -#define ASUS_WMI_METHODID_AGFN 0x4E464741 /* FaN? */ +#define ASUS_WMI_METHODID_AGFN 0x4E464741 /* Atk Generic FuNction */ #define ASUS_WMI_METHODID_SFUN 0x4E554653 /* FUNCtionalities */ #define ASUS_WMI_METHODID_SDSP 0x50534453 /* Set DiSPlay output */ #define ASUS_WMI_METHODID_GDSP 0x50534447 /* Get DiSPlay output */ @@ -72,7 +72,7 @@ /* Fan, Thermal */ #define ASUS_WMI_DEVID_THERMAL_CTRL 0x00110011 -#define ASUS_WMI_DEVID_FAN_CTRL 0x00110012 +#define ASUS_WMI_DEVID_FAN_CTRL 0x00110012 /* deprecated */ /* Power */ #define ASUS_WMI_DEVID_PROCESSOR_STATE 0x00120012 -- cgit v1.2.3-71-gd317 From e3168b874321d04c160c9eb937919eb926ae232f Mon Sep 17 00:00:00 2001 From: Daniel Drake Date: Mon, 29 Jul 2019 16:27:39 +0800 Subject: platform/x86: asus-wmi: fix CPU fan control on recent products Previously, asus-wmi was using the AGFN interface and FAN_CTRL device for CPU fan control. However, this code has been found to be not fully working on some recent products, and having checked the spec, these interfaces are marked as being removed from future products currently in development. The replacement appears to be the CPU_FAN device, added in spec version 8.3 (March 2014) and present on many modern Asus laptops. Add support for this device, and use it whenever it is detected. The older approach based on AGFN and FAN_CTRL is used as a fallback on products that do not have such device. Other than switching between automatic and full speed, there is no fan speed control through this new interface. Signed-off-by: Daniel Drake Signed-off-by: Andy Shevchenko --- drivers/platform/x86/asus-wmi.c | 125 +++++++++++++++++++++++------ include/linux/platform_data/x86/asus-wmi.h | 1 + 2 files changed, 101 insertions(+), 25 deletions(-) (limited to 'include/linux/platform_data') diff --git a/drivers/platform/x86/asus-wmi.c b/drivers/platform/x86/asus-wmi.c index 25f1e256c442..34dfbed65332 100644 --- a/drivers/platform/x86/asus-wmi.c +++ b/drivers/platform/x86/asus-wmi.c @@ -67,6 +67,7 @@ MODULE_LICENSE("GPL"); #define ASUS_FAN_SFUN_WRITE 0x07 /* Based on standard hwmon pwmX_enable values */ +#define ASUS_FAN_CTRL_FULLSPEED 0 #define ASUS_FAN_CTRL_MANUAL 1 #define ASUS_FAN_CTRL_AUTO 2 @@ -153,6 +154,7 @@ struct asus_rfkill { enum fan_type { FAN_TYPE_NONE = 0, FAN_TYPE_AGFN, /* deprecated on newer platforms */ + FAN_TYPE_SPEC83, /* starting in Spec 8.3, use CPU_FAN_CTRL */ }; struct asus_wmi { @@ -1211,10 +1213,29 @@ static bool asus_wmi_has_agfn_fan(struct asus_wmi *asus) static int asus_fan_set_auto(struct asus_wmi *asus) { int status; + u32 retval; - status = asus_agfn_fan_speed_write(asus, 0, NULL); - if (status) + switch (asus->fan_type) { + case FAN_TYPE_SPEC83: + status = asus_wmi_set_devstate(ASUS_WMI_DEVID_CPU_FAN_CTRL, + 0, &retval); + if (status) + return status; + + if (retval != 1) + return -EIO; + break; + + case FAN_TYPE_AGFN: + status = asus_agfn_fan_speed_write(asus, 0, NULL); + if (status) + return -ENXIO; + break; + + default: return -ENXIO; + } + return 0; } @@ -1287,13 +1308,29 @@ static ssize_t fan1_input_show(struct device *dev, int value; int ret; - /* no speed readable on manual mode */ - if (asus->fan_pwm_mode == ASUS_FAN_CTRL_MANUAL) - return -ENXIO; + switch (asus->fan_type) { + case FAN_TYPE_SPEC83: + ret = asus_wmi_get_devstate(asus, ASUS_WMI_DEVID_CPU_FAN_CTRL, + &value); + if (ret < 0) + return ret; - ret = asus_agfn_fan_speed_read(asus, 1, &value); - if (ret) { - pr_warn("reading fan speed failed: %d\n", ret); + value &= 0xffff; + break; + + case FAN_TYPE_AGFN: + /* no speed readable on manual mode */ + if (asus->fan_pwm_mode == ASUS_FAN_CTRL_MANUAL) + return -ENXIO; + + ret = asus_agfn_fan_speed_read(asus, 1, &value); + if (ret) { + pr_warn("reading fan speed failed: %d\n", ret); + return -ENXIO; + } + break; + + default: return -ENXIO; } @@ -1306,6 +1343,15 @@ static ssize_t pwm1_enable_show(struct device *dev, { struct asus_wmi *asus = dev_get_drvdata(dev); + /* + * Just read back the cached pwm mode. + * + * For the CPU_FAN device, the spec indicates that we should be + * able to read the device status and consult bit 19 to see if we + * are in Full On or Automatic mode. However, this does not work + * in practice on X532FL at least (the bit is always 0) and there's + * also nothing in the DSDT to indicate that this behaviour exists. + */ return sprintf(buf, "%d\n", asus->fan_pwm_mode); } @@ -1316,25 +1362,48 @@ static ssize_t pwm1_enable_store(struct device *dev, struct asus_wmi *asus = dev_get_drvdata(dev); int status = 0; int state; + int value; int ret; + u32 retval; ret = kstrtouint(buf, 10, &state); if (ret) return ret; - switch (state) { - case ASUS_FAN_CTRL_MANUAL: - break; + if (asus->fan_type == FAN_TYPE_SPEC83) { + switch (state) { /* standard documented hwmon values */ + case ASUS_FAN_CTRL_FULLSPEED: + value = 1; + break; + case ASUS_FAN_CTRL_AUTO: + value = 0; + break; + default: + return -EINVAL; + } - case ASUS_FAN_CTRL_AUTO: - status = asus_fan_set_auto(asus); - if (status) - return status; - break; + ret = asus_wmi_set_devstate(ASUS_WMI_DEVID_CPU_FAN_CTRL, + value, &retval); + if (ret) + return ret; - default: - return -EINVAL; + if (retval != 1) + return -EIO; + } else if (asus->fan_type == FAN_TYPE_AGFN) { + switch (state) { + case ASUS_FAN_CTRL_MANUAL: + break; + + case ASUS_FAN_CTRL_AUTO: + status = asus_fan_set_auto(asus); + if (status) + return status; + break; + + default: + return -EINVAL; + } } asus->fan_pwm_mode = state; @@ -1392,9 +1461,11 @@ static umode_t asus_hwmon_sysfs_is_visible(struct kobject *kobj, struct asus_wmi *asus = dev_get_drvdata(dev->parent); u32 value = ASUS_WMI_UNSUPPORTED_METHOD; - if (attr == &dev_attr_fan1_input.attr + if (attr == &dev_attr_pwm1.attr) { + if (asus->fan_type != FAN_TYPE_AGFN) + return 0; + } else if (attr == &dev_attr_fan1_input.attr || attr == &dev_attr_fan1_label.attr - || attr == &dev_attr_pwm1.attr || attr == &dev_attr_pwm1_enable.attr) { if (asus->fan_type == FAN_TYPE_NONE) return 0; @@ -1443,13 +1514,17 @@ static int asus_wmi_fan_init(struct asus_wmi *asus) asus->fan_type = FAN_TYPE_NONE; asus->agfn_pwm = -1; - if (asus_wmi_has_agfn_fan(asus)) { + if (asus_wmi_dev_is_present(asus, ASUS_WMI_DEVID_CPU_FAN_CTRL)) + asus->fan_type = FAN_TYPE_SPEC83; + else if (asus_wmi_has_agfn_fan(asus)) asus->fan_type = FAN_TYPE_AGFN; - asus_fan_set_auto(asus); - asus->fan_pwm_mode = ASUS_FAN_CTRL_AUTO; - } - return asus->fan_type != FAN_TYPE_NONE; + if (asus->fan_type == FAN_TYPE_NONE) + return -ENODEV; + + asus_fan_set_auto(asus); + asus->fan_pwm_mode = ASUS_FAN_CTRL_AUTO; + return 0; } /* Fan mode *******************************************************************/ diff --git a/include/linux/platform_data/x86/asus-wmi.h b/include/linux/platform_data/x86/asus-wmi.h index 5ae9c062a1f6..409e16064f4b 100644 --- a/include/linux/platform_data/x86/asus-wmi.h +++ b/include/linux/platform_data/x86/asus-wmi.h @@ -73,6 +73,7 @@ /* Fan, Thermal */ #define ASUS_WMI_DEVID_THERMAL_CTRL 0x00110011 #define ASUS_WMI_DEVID_FAN_CTRL 0x00110012 /* deprecated */ +#define ASUS_WMI_DEVID_CPU_FAN_CTRL 0x00110013 /* Power */ #define ASUS_WMI_DEVID_PROCESSOR_STATE 0x00120012 -- cgit v1.2.3-71-gd317 From 9cdd273e29f3b901712ec3c298b1d506861f48e3 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 31 Jul 2019 17:08:50 -0300 Subject: spi: docs: convert to ReST and add it to the kABI bookset While there's one file there with briefily describes the uAPI, the documentation was written just like most subsystems: focused on kernel developers. So, add it together with driver-api books. Signed-off-by: Mauro Carvalho Chehab Acked-by: Jonathan Cameron # for iio Signed-off-by: Jonathan Corbet --- Documentation/index.rst | 1 + Documentation/spi/butterfly | 68 ---- Documentation/spi/butterfly.rst | 74 ++++ Documentation/spi/index.rst | 22 ++ Documentation/spi/pxa2xx | 235 ------------ Documentation/spi/pxa2xx.rst | 240 ++++++++++++ Documentation/spi/spi-lm70llp | 79 ---- Documentation/spi/spi-lm70llp.rst | 84 +++++ Documentation/spi/spi-sc18is602 | 36 -- Documentation/spi/spi-sc18is602.rst | 39 ++ Documentation/spi/spi-summary | 631 ------------------------------- Documentation/spi/spi-summary.rst | 644 ++++++++++++++++++++++++++++++++ Documentation/spi/spidev | 149 -------- Documentation/spi/spidev.rst | 163 ++++++++ drivers/iio/dummy/iio_simple_dummy.c | 2 +- drivers/spi/Kconfig | 2 +- drivers/spi/spi-butterfly.c | 2 +- drivers/spi/spi-lm70llp.c | 2 +- include/linux/platform_data/sc18is602.h | 2 +- 19 files changed, 1272 insertions(+), 1203 deletions(-) delete mode 100644 Documentation/spi/butterfly create mode 100644 Documentation/spi/butterfly.rst create mode 100644 Documentation/spi/index.rst delete mode 100644 Documentation/spi/pxa2xx create mode 100644 Documentation/spi/pxa2xx.rst delete mode 100644 Documentation/spi/spi-lm70llp create mode 100644 Documentation/spi/spi-lm70llp.rst delete mode 100644 Documentation/spi/spi-sc18is602 create mode 100644 Documentation/spi/spi-sc18is602.rst delete mode 100644 Documentation/spi/spi-summary create mode 100644 Documentation/spi/spi-summary.rst delete mode 100644 Documentation/spi/spidev create mode 100644 Documentation/spi/spidev.rst (limited to 'include/linux/platform_data') diff --git a/Documentation/index.rst b/Documentation/index.rst index 6217acab92db..472b8abe52e9 100644 --- a/Documentation/index.rst +++ b/Documentation/index.rst @@ -116,6 +116,7 @@ needed). power/index target/index timers/index + spi/index watchdog/index virtual/index input/index diff --git a/Documentation/spi/butterfly b/Documentation/spi/butterfly deleted file mode 100644 index 9927af7a629c..000000000000 --- a/Documentation/spi/butterfly +++ /dev/null @@ -1,68 +0,0 @@ -spi_butterfly - parport-to-butterfly adapter driver -=================================================== - -This is a hardware and software project that includes building and using -a parallel port adapter cable, together with an "AVR Butterfly" to run -firmware for user interfacing and/or sensors. A Butterfly is a $US20 -battery powered card with an AVR microcontroller and lots of goodies: -sensors, LCD, flash, toggle stick, and more. You can use AVR-GCC to -develop firmware for this, and flash it using this adapter cable. - -You can make this adapter from an old printer cable and solder things -directly to the Butterfly. Or (if you have the parts and skills) you -can come up with something fancier, providing ciruit protection to the -Butterfly and the printer port, or with a better power supply than two -signal pins from the printer port. Or for that matter, you can use -similar cables to talk to many AVR boards, even a breadboard. - -This is more powerful than "ISP programming" cables since it lets kernel -SPI protocol drivers interact with the AVR, and could even let the AVR -issue interrupts to them. Later, your protocol driver should work -easily with a "real SPI controller", instead of this bitbanger. - - -The first cable connections will hook Linux up to one SPI bus, with the -AVR and a DataFlash chip; and to the AVR reset line. This is all you -need to reflash the firmware, and the pins are the standard Atmel "ISP" -connector pins (used also on non-Butterfly AVR boards). On the parport -side this is like "sp12" programming cables. - - Signal Butterfly Parport (DB-25) - ------ --------- --------------- - SCK = J403.PB1/SCK = pin 2/D0 - RESET = J403.nRST = pin 3/D1 - VCC = J403.VCC_EXT = pin 8/D6 - MOSI = J403.PB2/MOSI = pin 9/D7 - MISO = J403.PB3/MISO = pin 11/S7,nBUSY - GND = J403.GND = pin 23/GND - -Then to let Linux master that bus to talk to the DataFlash chip, you must -(a) flash new firmware that disables SPI (set PRR.2, and disable pullups -by clearing PORTB.[0-3]); (b) configure the mtd_dataflash driver; and -(c) cable in the chipselect. - - Signal Butterfly Parport (DB-25) - ------ --------- --------------- - VCC = J400.VCC_EXT = pin 7/D5 - SELECT = J400.PB0/nSS = pin 17/C3,nSELECT - GND = J400.GND = pin 24/GND - -Or you could flash firmware making the AVR into an SPI slave (keeping the -DataFlash in reset) and tweak the spi_butterfly driver to make it bind to -the driver for your custom SPI-based protocol. - -The "USI" controller, using J405, can also be used for a second SPI bus. -That would let you talk to the AVR using custom SPI-with-USI firmware, -while letting either Linux or the AVR use the DataFlash. There are plenty -of spare parport pins to wire this one up, such as: - - Signal Butterfly Parport (DB-25) - ------ --------- --------------- - SCK = J403.PE4/USCK = pin 5/D3 - MOSI = J403.PE5/DI = pin 6/D4 - MISO = J403.PE6/DO = pin 12/S5,nPAPEROUT - GND = J403.GND = pin 22/GND - - IRQ = J402.PF4 = pin 10/S6,ACK - GND = J402.GND(P2) = pin 25/GND - diff --git a/Documentation/spi/butterfly.rst b/Documentation/spi/butterfly.rst new file mode 100644 index 000000000000..e614a589547c --- /dev/null +++ b/Documentation/spi/butterfly.rst @@ -0,0 +1,74 @@ +=================================================== +spi_butterfly - parport-to-butterfly adapter driver +=================================================== + +This is a hardware and software project that includes building and using +a parallel port adapter cable, together with an "AVR Butterfly" to run +firmware for user interfacing and/or sensors. A Butterfly is a $US20 +battery powered card with an AVR microcontroller and lots of goodies: +sensors, LCD, flash, toggle stick, and more. You can use AVR-GCC to +develop firmware for this, and flash it using this adapter cable. + +You can make this adapter from an old printer cable and solder things +directly to the Butterfly. Or (if you have the parts and skills) you +can come up with something fancier, providing ciruit protection to the +Butterfly and the printer port, or with a better power supply than two +signal pins from the printer port. Or for that matter, you can use +similar cables to talk to many AVR boards, even a breadboard. + +This is more powerful than "ISP programming" cables since it lets kernel +SPI protocol drivers interact with the AVR, and could even let the AVR +issue interrupts to them. Later, your protocol driver should work +easily with a "real SPI controller", instead of this bitbanger. + + +The first cable connections will hook Linux up to one SPI bus, with the +AVR and a DataFlash chip; and to the AVR reset line. This is all you +need to reflash the firmware, and the pins are the standard Atmel "ISP" +connector pins (used also on non-Butterfly AVR boards). On the parport +side this is like "sp12" programming cables. + + ====== ============= =================== + Signal Butterfly Parport (DB-25) + ====== ============= =================== + SCK J403.PB1/SCK pin 2/D0 + RESET J403.nRST pin 3/D1 + VCC J403.VCC_EXT pin 8/D6 + MOSI J403.PB2/MOSI pin 9/D7 + MISO J403.PB3/MISO pin 11/S7,nBUSY + GND J403.GND pin 23/GND + ====== ============= =================== + +Then to let Linux master that bus to talk to the DataFlash chip, you must +(a) flash new firmware that disables SPI (set PRR.2, and disable pullups +by clearing PORTB.[0-3]); (b) configure the mtd_dataflash driver; and +(c) cable in the chipselect. + + ====== ============ =================== + Signal Butterfly Parport (DB-25) + ====== ============ =================== + VCC J400.VCC_EXT pin 7/D5 + SELECT J400.PB0/nSS pin 17/C3,nSELECT + GND J400.GND pin 24/GND + ====== ============ =================== + +Or you could flash firmware making the AVR into an SPI slave (keeping the +DataFlash in reset) and tweak the spi_butterfly driver to make it bind to +the driver for your custom SPI-based protocol. + +The "USI" controller, using J405, can also be used for a second SPI bus. +That would let you talk to the AVR using custom SPI-with-USI firmware, +while letting either Linux or the AVR use the DataFlash. There are plenty +of spare parport pins to wire this one up, such as: + + ====== ============= =================== + Signal Butterfly Parport (DB-25) + ====== ============= =================== + SCK J403.PE4/USCK pin 5/D3 + MOSI J403.PE5/DI pin 6/D4 + MISO J403.PE6/DO pin 12/S5,nPAPEROUT + GND J403.GND pin 22/GND + + IRQ J402.PF4 pin 10/S6,ACK + GND J402.GND(P2) pin 25/GND + ====== ============= =================== diff --git a/Documentation/spi/index.rst b/Documentation/spi/index.rst new file mode 100644 index 000000000000..06c34ea11bcf --- /dev/null +++ b/Documentation/spi/index.rst @@ -0,0 +1,22 @@ +.. SPDX-License-Identifier: GPL-2.0 + +================================= +Serial Peripheral Interface (SPI) +================================= + +.. toctree:: + :maxdepth: 1 + + spi-summary + spidev + butterfly + pxa2xx + spi-lm70llp + spi-sc18is602 + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/spi/pxa2xx b/Documentation/spi/pxa2xx deleted file mode 100644 index 551325b66b23..000000000000 --- a/Documentation/spi/pxa2xx +++ /dev/null @@ -1,235 +0,0 @@ -PXA2xx SPI on SSP driver HOWTO -=================================================== -This a mini howto on the pxa2xx_spi driver. The driver turns a PXA2xx -synchronous serial port into a SPI master controller -(see Documentation/spi/spi-summary). The driver has the following features - -- Support for any PXA2xx SSP -- SSP PIO and SSP DMA data transfers. -- External and Internal (SSPFRM) chip selects. -- Per slave device (chip) configuration. -- Full suspend, freeze, resume support. - -The driver is built around a "spi_message" fifo serviced by workqueue and a -tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet -(pump_transfer) is responsible for queuing SPI transactions and setting up and -launching the dma/interrupt driven transfers. - -Declaring PXA2xx Master Controllers ------------------------------------ -Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a -"platform device". The master configuration is passed to the driver via a table -found in include/linux/spi/pxa2xx_spi.h: - -struct pxa2xx_spi_controller { - u16 num_chipselect; - u8 enable_dma; -}; - -The "pxa2xx_spi_controller.num_chipselect" field is used to determine the number of -slave device (chips) attached to this SPI master. - -The "pxa2xx_spi_controller.enable_dma" field informs the driver that SSP DMA should -be used. This caused the driver to acquire two DMA channels: rx_channel and -tx_channel. The rx_channel has a higher DMA service priority the tx_channel. -See the "PXA2xx Developer Manual" section "DMA Controller". - -NSSP MASTER SAMPLE ------------------- -Below is a sample configuration using the PXA255 NSSP. - -static struct resource pxa_spi_nssp_resources[] = { - [0] = { - .start = __PREG(SSCR0_P(2)), /* Start address of NSSP */ - .end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */ - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_NSSP, /* NSSP IRQ */ - .end = IRQ_NSSP, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct pxa2xx_spi_controller pxa_nssp_master_info = { - .num_chipselect = 1, /* Matches the number of chips attached to NSSP */ - .enable_dma = 1, /* Enables NSSP DMA */ -}; - -static struct platform_device pxa_spi_nssp = { - .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */ - .id = 2, /* Bus number, MUST MATCH SSP number 1..n */ - .resource = pxa_spi_nssp_resources, - .num_resources = ARRAY_SIZE(pxa_spi_nssp_resources), - .dev = { - .platform_data = &pxa_nssp_master_info, /* Passed to driver */ - }, -}; - -static struct platform_device *devices[] __initdata = { - &pxa_spi_nssp, -}; - -static void __init board_init(void) -{ - (void)platform_add_device(devices, ARRAY_SIZE(devices)); -} - -Declaring Slave Devices ------------------------ -Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c -using the "spi_board_info" structure found in "linux/spi/spi.h". See -"Documentation/spi/spi-summary" for additional information. - -Each slave device attached to the PXA must provide slave specific configuration -information via the structure "pxa2xx_spi_chip" found in -"include/linux/spi/pxa2xx_spi.h". The pxa2xx_spi master controller driver -will uses the configuration whenever the driver communicates with the slave -device. All fields are optional. - -struct pxa2xx_spi_chip { - u8 tx_threshold; - u8 rx_threshold; - u8 dma_burst_size; - u32 timeout; - u8 enable_loopback; - void (*cs_control)(u32 command); -}; - -The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are -used to configure the SSP hardware fifo. These fields are critical to the -performance of pxa2xx_spi driver and misconfiguration will result in rx -fifo overruns (especially in PIO mode transfers). Good default values are - - .tx_threshold = 8, - .rx_threshold = 8, - -The range is 1 to 16 where zero indicates "use default". - -The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA -engine and is related the "spi_device.bits_per_word" field. Read and understand -the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers -to determine the correct value. An SSP configured for byte-wide transfers would -use a value of 8. The driver will determine a reasonable default if -dma_burst_size == 0. - -The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle -trailing bytes in the SSP receiver fifo. The correct value for this field is -dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific -slave device. Please note that the PXA2xx SSP 1 does not support trailing byte -timeouts and must busy-wait any trailing bytes. - -The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting -into internal loopback mode. In this mode the SSP controller internally -connects the SSPTX pin to the SSPRX pin. This is useful for initial setup -testing. - -The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific -function for asserting/deasserting a slave device chip select. If the field is -NULL, the pxa2xx_spi master controller driver assumes that the SSP port is -configured to use SSPFRM instead. - -NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the -chipselect is dropped after each spi_transfer. Most devices need chip select -asserted around the complete message. Use SSPFRM as a GPIO (through cs_control) -to accommodate these chips. - - -NSSP SLAVE SAMPLE ------------------ -The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the -"spi_board_info.controller_data" field. Below is a sample configuration using -the PXA255 NSSP. - -/* Chip Select control for the CS8415A SPI slave device */ -static void cs8415a_cs_control(u32 command) -{ - if (command & PXA2XX_CS_ASSERT) - GPCR(2) = GPIO_bit(2); - else - GPSR(2) = GPIO_bit(2); -} - -/* Chip Select control for the CS8405A SPI slave device */ -static void cs8405a_cs_control(u32 command) -{ - if (command & PXA2XX_CS_ASSERT) - GPCR(3) = GPIO_bit(3); - else - GPSR(3) = GPIO_bit(3); -} - -static struct pxa2xx_spi_chip cs8415a_chip_info = { - .tx_threshold = 8, /* SSP hardward FIFO threshold */ - .rx_threshold = 8, /* SSP hardward FIFO threshold */ - .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ - .timeout = 235, /* See Intel documentation */ - .cs_control = cs8415a_cs_control, /* Use external chip select */ -}; - -static struct pxa2xx_spi_chip cs8405a_chip_info = { - .tx_threshold = 8, /* SSP hardward FIFO threshold */ - .rx_threshold = 8, /* SSP hardward FIFO threshold */ - .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ - .timeout = 235, /* See Intel documentation */ - .cs_control = cs8405a_cs_control, /* Use external chip select */ -}; - -static struct spi_board_info streetracer_spi_board_info[] __initdata = { - { - .modalias = "cs8415a", /* Name of spi_driver for this device */ - .max_speed_hz = 3686400, /* Run SSP as fast a possbile */ - .bus_num = 2, /* Framework bus number */ - .chip_select = 0, /* Framework chip select */ - .platform_data = NULL; /* No spi_driver specific config */ - .controller_data = &cs8415a_chip_info, /* Master chip config */ - .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */ - }, - { - .modalias = "cs8405a", /* Name of spi_driver for this device */ - .max_speed_hz = 3686400, /* Run SSP as fast a possbile */ - .bus_num = 2, /* Framework bus number */ - .chip_select = 1, /* Framework chip select */ - .controller_data = &cs8405a_chip_info, /* Master chip config */ - .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */ - }, -}; - -static void __init streetracer_init(void) -{ - spi_register_board_info(streetracer_spi_board_info, - ARRAY_SIZE(streetracer_spi_board_info)); -} - - -DMA and PIO I/O Support ------------------------ -The pxa2xx_spi driver supports both DMA and interrupt driven PIO message -transfers. The driver defaults to PIO mode and DMA transfers must be enabled -by setting the "enable_dma" flag in the "pxa2xx_spi_controller" structure. The DMA -mode supports both coherent and stream based DMA mappings. - -The following logic is used to determine the type of I/O to be used on -a per "spi_transfer" basis: - -if !enable_dma then - always use PIO transfers - -if spi_message.len > 8191 then - print "rate limited" warning - use PIO transfers - -if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then - use coherent DMA mode - -if rx_buf and tx_buf are aligned on 8 byte boundary then - use streaming DMA mode - -otherwise - use PIO transfer - -THANKS TO ---------- - -David Brownell and others for mentoring the development of this driver. - diff --git a/Documentation/spi/pxa2xx.rst b/Documentation/spi/pxa2xx.rst new file mode 100644 index 000000000000..882d3cc72cc2 --- /dev/null +++ b/Documentation/spi/pxa2xx.rst @@ -0,0 +1,240 @@ +============================== +PXA2xx SPI on SSP driver HOWTO +============================== + +This a mini howto on the pxa2xx_spi driver. The driver turns a PXA2xx +synchronous serial port into a SPI master controller +(see Documentation/spi/spi-summary.rst). The driver has the following features + +- Support for any PXA2xx SSP +- SSP PIO and SSP DMA data transfers. +- External and Internal (SSPFRM) chip selects. +- Per slave device (chip) configuration. +- Full suspend, freeze, resume support. + +The driver is built around a "spi_message" fifo serviced by workqueue and a +tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet +(pump_transfer) is responsible for queuing SPI transactions and setting up and +launching the dma/interrupt driven transfers. + +Declaring PXA2xx Master Controllers +----------------------------------- +Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a +"platform device". The master configuration is passed to the driver via a table +found in include/linux/spi/pxa2xx_spi.h:: + + struct pxa2xx_spi_controller { + u16 num_chipselect; + u8 enable_dma; + }; + +The "pxa2xx_spi_controller.num_chipselect" field is used to determine the number of +slave device (chips) attached to this SPI master. + +The "pxa2xx_spi_controller.enable_dma" field informs the driver that SSP DMA should +be used. This caused the driver to acquire two DMA channels: rx_channel and +tx_channel. The rx_channel has a higher DMA service priority the tx_channel. +See the "PXA2xx Developer Manual" section "DMA Controller". + +NSSP MASTER SAMPLE +------------------ +Below is a sample configuration using the PXA255 NSSP:: + + static struct resource pxa_spi_nssp_resources[] = { + [0] = { + .start = __PREG(SSCR0_P(2)), /* Start address of NSSP */ + .end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */ + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_NSSP, /* NSSP IRQ */ + .end = IRQ_NSSP, + .flags = IORESOURCE_IRQ, + }, + }; + + static struct pxa2xx_spi_controller pxa_nssp_master_info = { + .num_chipselect = 1, /* Matches the number of chips attached to NSSP */ + .enable_dma = 1, /* Enables NSSP DMA */ + }; + + static struct platform_device pxa_spi_nssp = { + .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */ + .id = 2, /* Bus number, MUST MATCH SSP number 1..n */ + .resource = pxa_spi_nssp_resources, + .num_resources = ARRAY_SIZE(pxa_spi_nssp_resources), + .dev = { + .platform_data = &pxa_nssp_master_info, /* Passed to driver */ + }, + }; + + static struct platform_device *devices[] __initdata = { + &pxa_spi_nssp, + }; + + static void __init board_init(void) + { + (void)platform_add_device(devices, ARRAY_SIZE(devices)); + } + +Declaring Slave Devices +----------------------- +Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c +using the "spi_board_info" structure found in "linux/spi/spi.h". See +"Documentation/spi/spi-summary.rst" for additional information. + +Each slave device attached to the PXA must provide slave specific configuration +information via the structure "pxa2xx_spi_chip" found in +"include/linux/spi/pxa2xx_spi.h". The pxa2xx_spi master controller driver +will uses the configuration whenever the driver communicates with the slave +device. All fields are optional. + +:: + + struct pxa2xx_spi_chip { + u8 tx_threshold; + u8 rx_threshold; + u8 dma_burst_size; + u32 timeout; + u8 enable_loopback; + void (*cs_control)(u32 command); + }; + +The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are +used to configure the SSP hardware fifo. These fields are critical to the +performance of pxa2xx_spi driver and misconfiguration will result in rx +fifo overruns (especially in PIO mode transfers). Good default values are:: + + .tx_threshold = 8, + .rx_threshold = 8, + +The range is 1 to 16 where zero indicates "use default". + +The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA +engine and is related the "spi_device.bits_per_word" field. Read and understand +the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers +to determine the correct value. An SSP configured for byte-wide transfers would +use a value of 8. The driver will determine a reasonable default if +dma_burst_size == 0. + +The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle +trailing bytes in the SSP receiver fifo. The correct value for this field is +dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific +slave device. Please note that the PXA2xx SSP 1 does not support trailing byte +timeouts and must busy-wait any trailing bytes. + +The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting +into internal loopback mode. In this mode the SSP controller internally +connects the SSPTX pin to the SSPRX pin. This is useful for initial setup +testing. + +The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific +function for asserting/deasserting a slave device chip select. If the field is +NULL, the pxa2xx_spi master controller driver assumes that the SSP port is +configured to use SSPFRM instead. + +NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the +chipselect is dropped after each spi_transfer. Most devices need chip select +asserted around the complete message. Use SSPFRM as a GPIO (through cs_control) +to accommodate these chips. + + +NSSP SLAVE SAMPLE +----------------- +The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the +"spi_board_info.controller_data" field. Below is a sample configuration using +the PXA255 NSSP. + +:: + + /* Chip Select control for the CS8415A SPI slave device */ + static void cs8415a_cs_control(u32 command) + { + if (command & PXA2XX_CS_ASSERT) + GPCR(2) = GPIO_bit(2); + else + GPSR(2) = GPIO_bit(2); + } + + /* Chip Select control for the CS8405A SPI slave device */ + static void cs8405a_cs_control(u32 command) + { + if (command & PXA2XX_CS_ASSERT) + GPCR(3) = GPIO_bit(3); + else + GPSR(3) = GPIO_bit(3); + } + + static struct pxa2xx_spi_chip cs8415a_chip_info = { + .tx_threshold = 8, /* SSP hardward FIFO threshold */ + .rx_threshold = 8, /* SSP hardward FIFO threshold */ + .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ + .timeout = 235, /* See Intel documentation */ + .cs_control = cs8415a_cs_control, /* Use external chip select */ + }; + + static struct pxa2xx_spi_chip cs8405a_chip_info = { + .tx_threshold = 8, /* SSP hardward FIFO threshold */ + .rx_threshold = 8, /* SSP hardward FIFO threshold */ + .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ + .timeout = 235, /* See Intel documentation */ + .cs_control = cs8405a_cs_control, /* Use external chip select */ + }; + + static struct spi_board_info streetracer_spi_board_info[] __initdata = { + { + .modalias = "cs8415a", /* Name of spi_driver for this device */ + .max_speed_hz = 3686400, /* Run SSP as fast a possbile */ + .bus_num = 2, /* Framework bus number */ + .chip_select = 0, /* Framework chip select */ + .platform_data = NULL; /* No spi_driver specific config */ + .controller_data = &cs8415a_chip_info, /* Master chip config */ + .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */ + }, + { + .modalias = "cs8405a", /* Name of spi_driver for this device */ + .max_speed_hz = 3686400, /* Run SSP as fast a possbile */ + .bus_num = 2, /* Framework bus number */ + .chip_select = 1, /* Framework chip select */ + .controller_data = &cs8405a_chip_info, /* Master chip config */ + .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */ + }, + }; + + static void __init streetracer_init(void) + { + spi_register_board_info(streetracer_spi_board_info, + ARRAY_SIZE(streetracer_spi_board_info)); + } + + +DMA and PIO I/O Support +----------------------- +The pxa2xx_spi driver supports both DMA and interrupt driven PIO message +transfers. The driver defaults to PIO mode and DMA transfers must be enabled +by setting the "enable_dma" flag in the "pxa2xx_spi_controller" structure. The DMA +mode supports both coherent and stream based DMA mappings. + +The following logic is used to determine the type of I/O to be used on +a per "spi_transfer" basis:: + + if !enable_dma then + always use PIO transfers + + if spi_message.len > 8191 then + print "rate limited" warning + use PIO transfers + + if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then + use coherent DMA mode + + if rx_buf and tx_buf are aligned on 8 byte boundary then + use streaming DMA mode + + otherwise + use PIO transfer + +THANKS TO +--------- + +David Brownell and others for mentoring the development of this driver. diff --git a/Documentation/spi/spi-lm70llp b/Documentation/spi/spi-lm70llp deleted file mode 100644 index 463f6d01fa15..000000000000 --- a/Documentation/spi/spi-lm70llp +++ /dev/null @@ -1,79 +0,0 @@ -spi_lm70llp : LM70-LLP parport-to-SPI adapter -============================================== - -Supported board/chip: - * National Semiconductor LM70 LLP evaluation board - Datasheet: http://www.national.com/pf/LM/LM70.html - -Author: - Kaiwan N Billimoria - -Description ------------ -This driver provides glue code connecting a National Semiconductor LM70 LLP -temperature sensor evaluation board to the kernel's SPI core subsystem. - -This is a SPI master controller driver. It can be used in conjunction with -(layered under) the LM70 logical driver (a "SPI protocol driver"). -In effect, this driver turns the parallel port interface on the eval board -into a SPI bus with a single device, which will be driven by the generic -LM70 driver (drivers/hwmon/lm70.c). - - -Hardware Interfacing --------------------- -The schematic for this particular board (the LM70EVAL-LLP) is -available (on page 4) here: - - http://www.national.com/appinfo/tempsensors/files/LM70LLPEVALmanual.pdf - -The hardware interfacing on the LM70 LLP eval board is as follows: - - Parallel LM70 LLP - Port Direction JP2 Header - ----------- --------- ---------------- - D0 2 - - - D1 3 --> V+ 5 - D2 4 --> V+ 5 - D3 5 --> V+ 5 - D4 6 --> V+ 5 - D5 7 --> nCS 8 - D6 8 --> SCLK 3 - D7 9 --> SI/O 5 - GND 25 - GND 7 - Select 13 <-- SI/O 1 - ----------- --------- ---------------- - -Note that since the LM70 uses a "3-wire" variant of SPI, the SI/SO pin -is connected to both pin D7 (as Master Out) and Select (as Master In) -using an arrangement that lets either the parport or the LM70 pull the -pin low. This can't be shared with true SPI devices, but other 3-wire -devices might share the same SI/SO pin. - -The bitbanger routine in this driver (lm70_txrx) is called back from -the bound "hwmon/lm70" protocol driver through its sysfs hook, using a -spi_write_then_read() call. It performs Mode 0 (SPI/Microwire) bitbanging. -The lm70 driver then inteprets the resulting digital temperature value -and exports it through sysfs. - -A "gotcha": National Semiconductor's LM70 LLP eval board circuit schematic -shows that the SI/O line from the LM70 chip is connected to the base of a -transistor Q1 (and also a pullup, and a zener diode to D7); while the -collector is tied to VCC. - -Interpreting this circuit, when the LM70 SI/O line is High (or tristate -and not grounded by the host via D7), the transistor conducts and switches -the collector to zero, which is reflected on pin 13 of the DB25 parport -connector. When SI/O is Low (driven by the LM70 or the host) on the other -hand, the transistor is cut off and the voltage tied to it's collector is -reflected on pin 13 as a High level. - -So: the getmiso inline routine in this driver takes this fact into account, -inverting the value read at pin 13. - - -Thanks to ---------- -o David Brownell for mentoring the SPI-side driver development. -o Dr.Craig Hollabaugh for the (early) "manual" bitbanging driver version. -o Nadir Billimoria for help interpreting the circuit schematic. diff --git a/Documentation/spi/spi-lm70llp.rst b/Documentation/spi/spi-lm70llp.rst new file mode 100644 index 000000000000..07631aef4343 --- /dev/null +++ b/Documentation/spi/spi-lm70llp.rst @@ -0,0 +1,84 @@ +============================================== +spi_lm70llp : LM70-LLP parport-to-SPI adapter +============================================== + +Supported board/chip: + + * National Semiconductor LM70 LLP evaluation board + + Datasheet: http://www.national.com/pf/LM/LM70.html + +Author: + Kaiwan N Billimoria + +Description +----------- +This driver provides glue code connecting a National Semiconductor LM70 LLP +temperature sensor evaluation board to the kernel's SPI core subsystem. + +This is a SPI master controller driver. It can be used in conjunction with +(layered under) the LM70 logical driver (a "SPI protocol driver"). +In effect, this driver turns the parallel port interface on the eval board +into a SPI bus with a single device, which will be driven by the generic +LM70 driver (drivers/hwmon/lm70.c). + + +Hardware Interfacing +-------------------- +The schematic for this particular board (the LM70EVAL-LLP) is +available (on page 4) here: + + http://www.national.com/appinfo/tempsensors/files/LM70LLPEVALmanual.pdf + +The hardware interfacing on the LM70 LLP eval board is as follows: + + ======== == ========= ========== + Parallel LM70 LLP + Port . Direction JP2 Header + ======== == ========= ========== + D0 2 - - + D1 3 --> V+ 5 + D2 4 --> V+ 5 + D3 5 --> V+ 5 + D4 6 --> V+ 5 + D5 7 --> nCS 8 + D6 8 --> SCLK 3 + D7 9 --> SI/O 5 + GND 25 - GND 7 + Select 13 <-- SI/O 1 + ======== == ========= ========== + +Note that since the LM70 uses a "3-wire" variant of SPI, the SI/SO pin +is connected to both pin D7 (as Master Out) and Select (as Master In) +using an arrangement that lets either the parport or the LM70 pull the +pin low. This can't be shared with true SPI devices, but other 3-wire +devices might share the same SI/SO pin. + +The bitbanger routine in this driver (lm70_txrx) is called back from +the bound "hwmon/lm70" protocol driver through its sysfs hook, using a +spi_write_then_read() call. It performs Mode 0 (SPI/Microwire) bitbanging. +The lm70 driver then inteprets the resulting digital temperature value +and exports it through sysfs. + +A "gotcha": National Semiconductor's LM70 LLP eval board circuit schematic +shows that the SI/O line from the LM70 chip is connected to the base of a +transistor Q1 (and also a pullup, and a zener diode to D7); while the +collector is tied to VCC. + +Interpreting this circuit, when the LM70 SI/O line is High (or tristate +and not grounded by the host via D7), the transistor conducts and switches +the collector to zero, which is reflected on pin 13 of the DB25 parport +connector. When SI/O is Low (driven by the LM70 or the host) on the other +hand, the transistor is cut off and the voltage tied to it's collector is +reflected on pin 13 as a High level. + +So: the getmiso inline routine in this driver takes this fact into account, +inverting the value read at pin 13. + + +Thanks to +--------- + +- David Brownell for mentoring the SPI-side driver development. +- Dr.Craig Hollabaugh for the (early) "manual" bitbanging driver version. +- Nadir Billimoria for help interpreting the circuit schematic. diff --git a/Documentation/spi/spi-sc18is602 b/Documentation/spi/spi-sc18is602 deleted file mode 100644 index 0feffd5af411..000000000000 --- a/Documentation/spi/spi-sc18is602 +++ /dev/null @@ -1,36 +0,0 @@ -Kernel driver spi-sc18is602 -=========================== - -Supported chips: - * NXP SI18IS602/602B/603 - Datasheet: http://www.nxp.com/documents/data_sheet/SC18IS602_602B_603.pdf - -Author: - Guenter Roeck - - -Description ------------ - -This driver provides connects a NXP SC18IS602/603 I2C-bus to SPI bridge to the -kernel's SPI core subsystem. - -The driver does not probe for supported chips, since the SI18IS602/603 does not -support Chip ID registers. You will have to instantiate the devices explicitly. -Please see Documentation/i2c/instantiating-devices.rst for details. - - -Usage Notes ------------ - -This driver requires the I2C adapter driver to support raw I2C messages. I2C -adapter drivers which can only handle the SMBus protocol are not supported. - -The maximum SPI message size supported by SC18IS602/603 is 200 bytes. Attempts -to initiate longer transfers will fail with -EINVAL. EEPROM read operations and -similar large accesses have to be split into multiple chunks of no more than -200 bytes per SPI message (128 bytes of data per message is recommended). This -means that programs such as "cp" or "od", which automatically use large block -sizes to access a device, can not be used directly to read data from EEPROM. -Programs such as dd, where the block size can be specified, should be used -instead. diff --git a/Documentation/spi/spi-sc18is602.rst b/Documentation/spi/spi-sc18is602.rst new file mode 100644 index 000000000000..2a31dc722321 --- /dev/null +++ b/Documentation/spi/spi-sc18is602.rst @@ -0,0 +1,39 @@ +=========================== +Kernel driver spi-sc18is602 +=========================== + +Supported chips: + + * NXP SI18IS602/602B/603 + + Datasheet: http://www.nxp.com/documents/data_sheet/SC18IS602_602B_603.pdf + +Author: + Guenter Roeck + + +Description +----------- + +This driver provides connects a NXP SC18IS602/603 I2C-bus to SPI bridge to the +kernel's SPI core subsystem. + +The driver does not probe for supported chips, since the SI18IS602/603 does not +support Chip ID registers. You will have to instantiate the devices explicitly. +Please see Documentation/i2c/instantiating-devices.rst for details. + + +Usage Notes +----------- + +This driver requires the I2C adapter driver to support raw I2C messages. I2C +adapter drivers which can only handle the SMBus protocol are not supported. + +The maximum SPI message size supported by SC18IS602/603 is 200 bytes. Attempts +to initiate longer transfers will fail with -EINVAL. EEPROM read operations and +similar large accesses have to be split into multiple chunks of no more than +200 bytes per SPI message (128 bytes of data per message is recommended). This +means that programs such as "cp" or "od", which automatically use large block +sizes to access a device, can not be used directly to read data from EEPROM. +Programs such as dd, where the block size can be specified, should be used +instead. diff --git a/Documentation/spi/spi-summary b/Documentation/spi/spi-summary deleted file mode 100644 index 1a63194b74d7..000000000000 --- a/Documentation/spi/spi-summary +++ /dev/null @@ -1,631 +0,0 @@ -Overview of Linux kernel SPI support -==================================== - -02-Feb-2012 - -What is SPI? ------------- -The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial -link used to connect microcontrollers to sensors, memory, and peripherals. -It's a simple "de facto" standard, not complicated enough to acquire a -standardization body. SPI uses a master/slave configuration. - -The three signal wires hold a clock (SCK, often on the order of 10 MHz), -and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In, -Slave Out" (MISO) signals. (Other names are also used.) There are four -clocking modes through which data is exchanged; mode-0 and mode-3 are most -commonly used. Each clock cycle shifts data out and data in; the clock -doesn't cycle except when there is a data bit to shift. Not all data bits -are used though; not every protocol uses those full duplex capabilities. - -SPI masters use a fourth "chip select" line to activate a given SPI slave -device, so those three signal wires may be connected to several chips -in parallel. All SPI slaves support chipselects; they are usually active -low signals, labeled nCSx for slave 'x' (e.g. nCS0). Some devices have -other signals, often including an interrupt to the master. - -Unlike serial busses like USB or SMBus, even low level protocols for -SPI slave functions are usually not interoperable between vendors -(except for commodities like SPI memory chips). - - - SPI may be used for request/response style device protocols, as with - touchscreen sensors and memory chips. - - - It may also be used to stream data in either direction (half duplex), - or both of them at the same time (full duplex). - - - Some devices may use eight bit words. Others may use different word - lengths, such as streams of 12-bit or 20-bit digital samples. - - - Words are usually sent with their most significant bit (MSB) first, - but sometimes the least significant bit (LSB) goes first instead. - - - Sometimes SPI is used to daisy-chain devices, like shift registers. - -In the same way, SPI slaves will only rarely support any kind of automatic -discovery/enumeration protocol. The tree of slave devices accessible from -a given SPI master will normally be set up manually, with configuration -tables. - -SPI is only one of the names used by such four-wire protocols, and -most controllers have no problem handling "MicroWire" (think of it as -half-duplex SPI, for request/response protocols), SSP ("Synchronous -Serial Protocol"), PSP ("Programmable Serial Protocol"), and other -related protocols. - -Some chips eliminate a signal line by combining MOSI and MISO, and -limiting themselves to half-duplex at the hardware level. In fact -some SPI chips have this signal mode as a strapping option. These -can be accessed using the same programming interface as SPI, but of -course they won't handle full duplex transfers. You may find such -chips described as using "three wire" signaling: SCK, data, nCSx. -(That data line is sometimes called MOMI or SISO.) - -Microcontrollers often support both master and slave sides of the SPI -protocol. This document (and Linux) supports both the master and slave -sides of SPI interactions. - - -Who uses it? On what kinds of systems? ---------------------------------------- -Linux developers using SPI are probably writing device drivers for embedded -systems boards. SPI is used to control external chips, and it is also a -protocol supported by every MMC or SD memory card. (The older "DataFlash" -cards, predating MMC cards but using the same connectors and card shape, -support only SPI.) Some PC hardware uses SPI flash for BIOS code. - -SPI slave chips range from digital/analog converters used for analog -sensors and codecs, to memory, to peripherals like USB controllers -or Ethernet adapters; and more. - -Most systems using SPI will integrate a few devices on a mainboard. -Some provide SPI links on expansion connectors; in cases where no -dedicated SPI controller exists, GPIO pins can be used to create a -low speed "bitbanging" adapter. Very few systems will "hotplug" an SPI -controller; the reasons to use SPI focus on low cost and simple operation, -and if dynamic reconfiguration is important, USB will often be a more -appropriate low-pincount peripheral bus. - -Many microcontrollers that can run Linux integrate one or more I/O -interfaces with SPI modes. Given SPI support, they could use MMC or SD -cards without needing a special purpose MMC/SD/SDIO controller. - - -I'm confused. What are these four SPI "clock modes"? ------------------------------------------------------ -It's easy to be confused here, and the vendor documentation you'll -find isn't necessarily helpful. The four modes combine two mode bits: - - - CPOL indicates the initial clock polarity. CPOL=0 means the - clock starts low, so the first (leading) edge is rising, and - the second (trailing) edge is falling. CPOL=1 means the clock - starts high, so the first (leading) edge is falling. - - - CPHA indicates the clock phase used to sample data; CPHA=0 says - sample on the leading edge, CPHA=1 means the trailing edge. - - Since the signal needs to stablize before it's sampled, CPHA=0 - implies that its data is written half a clock before the first - clock edge. The chipselect may have made it become available. - -Chip specs won't always say "uses SPI mode X" in as many words, -but their timing diagrams will make the CPOL and CPHA modes clear. - -In the SPI mode number, CPOL is the high order bit and CPHA is the -low order bit. So when a chip's timing diagram shows the clock -starting low (CPOL=0) and data stabilized for sampling during the -trailing clock edge (CPHA=1), that's SPI mode 1. - -Note that the clock mode is relevant as soon as the chipselect goes -active. So the master must set the clock to inactive before selecting -a slave, and the slave can tell the chosen polarity by sampling the -clock level when its select line goes active. That's why many devices -support for example both modes 0 and 3: they don't care about polarity, -and always clock data in/out on rising clock edges. - - -How do these driver programming interfaces work? ------------------------------------------------- -The header file includes kerneldoc, as does the -main source code, and you should certainly read that chapter of the -kernel API document. This is just an overview, so you get the big -picture before those details. - -SPI requests always go into I/O queues. Requests for a given SPI device -are always executed in FIFO order, and complete asynchronously through -completion callbacks. There are also some simple synchronous wrappers -for those calls, including ones for common transaction types like writing -a command and then reading its response. - -There are two types of SPI driver, here called: - - Controller drivers ... controllers may be built into System-On-Chip - processors, and often support both Master and Slave roles. - These drivers touch hardware registers and may use DMA. - Or they can be PIO bitbangers, needing just GPIO pins. - - Protocol drivers ... these pass messages through the controller - driver to communicate with a Slave or Master device on the - other side of an SPI link. - -So for example one protocol driver might talk to the MTD layer to export -data to filesystems stored on SPI flash like DataFlash; and others might -control audio interfaces, present touchscreen sensors as input interfaces, -or monitor temperature and voltage levels during industrial processing. -And those might all be sharing the same controller driver. - -A "struct spi_device" encapsulates the controller-side interface between -those two types of drivers. - -There is a minimal core of SPI programming interfaces, focussing on -using the driver model to connect controller and protocol drivers using -device tables provided by board specific initialization code. SPI -shows up in sysfs in several locations: - - /sys/devices/.../CTLR ... physical node for a given SPI controller - - /sys/devices/.../CTLR/spiB.C ... spi_device on bus "B", - chipselect C, accessed through CTLR. - - /sys/bus/spi/devices/spiB.C ... symlink to that physical - .../CTLR/spiB.C device - - /sys/devices/.../CTLR/spiB.C/modalias ... identifies the driver - that should be used with this device (for hotplug/coldplug) - - /sys/bus/spi/drivers/D ... driver for one or more spi*.* devices - - /sys/class/spi_master/spiB ... symlink (or actual device node) to - a logical node which could hold class related state for the SPI - master controller managing bus "B". All spiB.* devices share one - physical SPI bus segment, with SCLK, MOSI, and MISO. - - /sys/devices/.../CTLR/slave ... virtual file for (un)registering the - slave device for an SPI slave controller. - Writing the driver name of an SPI slave handler to this file - registers the slave device; writing "(null)" unregisters the slave - device. - Reading from this file shows the name of the slave device ("(null)" - if not registered). - - /sys/class/spi_slave/spiB ... symlink (or actual device node) to - a logical node which could hold class related state for the SPI - slave controller on bus "B". When registered, a single spiB.* - device is present here, possible sharing the physical SPI bus - segment with other SPI slave devices. - -Note that the actual location of the controller's class state depends -on whether you enabled CONFIG_SYSFS_DEPRECATED or not. At this time, -the only class-specific state is the bus number ("B" in "spiB"), so -those /sys/class entries are only useful to quickly identify busses. - - -How does board-specific init code declare SPI devices? ------------------------------------------------------- -Linux needs several kinds of information to properly configure SPI devices. -That information is normally provided by board-specific code, even for -chips that do support some of automated discovery/enumeration. - -DECLARE CONTROLLERS - -The first kind of information is a list of what SPI controllers exist. -For System-on-Chip (SOC) based boards, these will usually be platform -devices, and the controller may need some platform_data in order to -operate properly. The "struct platform_device" will include resources -like the physical address of the controller's first register and its IRQ. - -Platforms will often abstract the "register SPI controller" operation, -maybe coupling it with code to initialize pin configurations, so that -the arch/.../mach-*/board-*.c files for several boards can all share the -same basic controller setup code. This is because most SOCs have several -SPI-capable controllers, and only the ones actually usable on a given -board should normally be set up and registered. - -So for example arch/.../mach-*/board-*.c files might have code like: - - #include /* for mysoc_spi_data */ - - /* if your mach-* infrastructure doesn't support kernels that can - * run on multiple boards, pdata wouldn't benefit from "__init". - */ - static struct mysoc_spi_data pdata __initdata = { ... }; - - static __init board_init(void) - { - ... - /* this board only uses SPI controller #2 */ - mysoc_register_spi(2, &pdata); - ... - } - -And SOC-specific utility code might look something like: - - #include - - static struct platform_device spi2 = { ... }; - - void mysoc_register_spi(unsigned n, struct mysoc_spi_data *pdata) - { - struct mysoc_spi_data *pdata2; - - pdata2 = kmalloc(sizeof *pdata2, GFP_KERNEL); - *pdata2 = pdata; - ... - if (n == 2) { - spi2->dev.platform_data = pdata2; - register_platform_device(&spi2); - - /* also: set up pin modes so the spi2 signals are - * visible on the relevant pins ... bootloaders on - * production boards may already have done this, but - * developer boards will often need Linux to do it. - */ - } - ... - } - -Notice how the platform_data for boards may be different, even if the -same SOC controller is used. For example, on one board SPI might use -an external clock, where another derives the SPI clock from current -settings of some master clock. - - -DECLARE SLAVE DEVICES - -The second kind of information is a list of what SPI slave devices exist -on the target board, often with some board-specific data needed for the -driver to work correctly. - -Normally your arch/.../mach-*/board-*.c files would provide a small table -listing the SPI devices on each board. (This would typically be only a -small handful.) That might look like: - - static struct ads7846_platform_data ads_info = { - .vref_delay_usecs = 100, - .x_plate_ohms = 580, - .y_plate_ohms = 410, - }; - - static struct spi_board_info spi_board_info[] __initdata = { - { - .modalias = "ads7846", - .platform_data = &ads_info, - .mode = SPI_MODE_0, - .irq = GPIO_IRQ(31), - .max_speed_hz = 120000 /* max sample rate at 3V */ * 16, - .bus_num = 1, - .chip_select = 0, - }, - }; - -Again, notice how board-specific information is provided; each chip may need -several types. This example shows generic constraints like the fastest SPI -clock to allow (a function of board voltage in this case) or how an IRQ pin -is wired, plus chip-specific constraints like an important delay that's -changed by the capacitance at one pin. - -(There's also "controller_data", information that may be useful to the -controller driver. An example would be peripheral-specific DMA tuning -data or chipselect callbacks. This is stored in spi_device later.) - -The board_info should provide enough information to let the system work -without the chip's driver being loaded. The most troublesome aspect of -that is likely the SPI_CS_HIGH bit in the spi_device.mode field, since -sharing a bus with a device that interprets chipselect "backwards" is -not possible until the infrastructure knows how to deselect it. - -Then your board initialization code would register that table with the SPI -infrastructure, so that it's available later when the SPI master controller -driver is registered: - - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); - -Like with other static board-specific setup, you won't unregister those. - -The widely used "card" style computers bundle memory, cpu, and little else -onto a card that's maybe just thirty square centimeters. On such systems, -your arch/.../mach-.../board-*.c file would primarily provide information -about the devices on the mainboard into which such a card is plugged. That -certainly includes SPI devices hooked up through the card connectors! - - -NON-STATIC CONFIGURATIONS - -Developer boards often play by different rules than product boards, and one -example is the potential need to hotplug SPI devices and/or controllers. - -For those cases you might need to use spi_busnum_to_master() to look -up the spi bus master, and will likely need spi_new_device() to provide the -board info based on the board that was hotplugged. Of course, you'd later -call at least spi_unregister_device() when that board is removed. - -When Linux includes support for MMC/SD/SDIO/DataFlash cards through SPI, those -configurations will also be dynamic. Fortunately, such devices all support -basic device identification probes, so they should hotplug normally. - - -How do I write an "SPI Protocol Driver"? ----------------------------------------- -Most SPI drivers are currently kernel drivers, but there's also support -for userspace drivers. Here we talk only about kernel drivers. - -SPI protocol drivers somewhat resemble platform device drivers: - - static struct spi_driver CHIP_driver = { - .driver = { - .name = "CHIP", - .owner = THIS_MODULE, - .pm = &CHIP_pm_ops, - }, - - .probe = CHIP_probe, - .remove = CHIP_remove, - }; - -The driver core will automatically attempt to bind this driver to any SPI -device whose board_info gave a modalias of "CHIP". Your probe() code -might look like this unless you're creating a device which is managing -a bus (appearing under /sys/class/spi_master). - - static int CHIP_probe(struct spi_device *spi) - { - struct CHIP *chip; - struct CHIP_platform_data *pdata; - - /* assuming the driver requires board-specific data: */ - pdata = &spi->dev.platform_data; - if (!pdata) - return -ENODEV; - - /* get memory for driver's per-chip state */ - chip = kzalloc(sizeof *chip, GFP_KERNEL); - if (!chip) - return -ENOMEM; - spi_set_drvdata(spi, chip); - - ... etc - return 0; - } - -As soon as it enters probe(), the driver may issue I/O requests to -the SPI device using "struct spi_message". When remove() returns, -or after probe() fails, the driver guarantees that it won't submit -any more such messages. - - - An spi_message is a sequence of protocol operations, executed - as one atomic sequence. SPI driver controls include: - - + when bidirectional reads and writes start ... by how its - sequence of spi_transfer requests is arranged; - - + which I/O buffers are used ... each spi_transfer wraps a - buffer for each transfer direction, supporting full duplex - (two pointers, maybe the same one in both cases) and half - duplex (one pointer is NULL) transfers; - - + optionally defining short delays after transfers ... using - the spi_transfer.delay_usecs setting (this delay can be the - only protocol effect, if the buffer length is zero); - - + whether the chipselect becomes inactive after a transfer and - any delay ... by using the spi_transfer.cs_change flag; - - + hinting whether the next message is likely to go to this same - device ... using the spi_transfer.cs_change flag on the last - transfer in that atomic group, and potentially saving costs - for chip deselect and select operations. - - - Follow standard kernel rules, and provide DMA-safe buffers in - your messages. That way controller drivers using DMA aren't forced - to make extra copies unless the hardware requires it (e.g. working - around hardware errata that force the use of bounce buffering). - - If standard dma_map_single() handling of these buffers is inappropriate, - you can use spi_message.is_dma_mapped to tell the controller driver - that you've already provided the relevant DMA addresses. - - - The basic I/O primitive is spi_async(). Async requests may be - issued in any context (irq handler, task, etc) and completion - is reported using a callback provided with the message. - After any detected error, the chip is deselected and processing - of that spi_message is aborted. - - - There are also synchronous wrappers like spi_sync(), and wrappers - like spi_read(), spi_write(), and spi_write_then_read(). These - may be issued only in contexts that may sleep, and they're all - clean (and small, and "optional") layers over spi_async(). - - - The spi_write_then_read() call, and convenience wrappers around - it, should only be used with small amounts of data where the - cost of an extra copy may be ignored. It's designed to support - common RPC-style requests, such as writing an eight bit command - and reading a sixteen bit response -- spi_w8r16() being one its - wrappers, doing exactly that. - -Some drivers may need to modify spi_device characteristics like the -transfer mode, wordsize, or clock rate. This is done with spi_setup(), -which would normally be called from probe() before the first I/O is -done to the device. However, that can also be called at any time -that no message is pending for that device. - -While "spi_device" would be the bottom boundary of the driver, the -upper boundaries might include sysfs (especially for sensor readings), -the input layer, ALSA, networking, MTD, the character device framework, -or other Linux subsystems. - -Note that there are two types of memory your driver must manage as part -of interacting with SPI devices. - - - I/O buffers use the usual Linux rules, and must be DMA-safe. - You'd normally allocate them from the heap or free page pool. - Don't use the stack, or anything that's declared "static". - - - The spi_message and spi_transfer metadata used to glue those - I/O buffers into a group of protocol transactions. These can - be allocated anywhere it's convenient, including as part of - other allocate-once driver data structures. Zero-init these. - -If you like, spi_message_alloc() and spi_message_free() convenience -routines are available to allocate and zero-initialize an spi_message -with several transfers. - - -How do I write an "SPI Master Controller Driver"? -------------------------------------------------- -An SPI controller will probably be registered on the platform_bus; write -a driver to bind to the device, whichever bus is involved. - -The main task of this type of driver is to provide an "spi_master". -Use spi_alloc_master() to allocate the master, and spi_master_get_devdata() -to get the driver-private data allocated for that device. - - struct spi_master *master; - struct CONTROLLER *c; - - master = spi_alloc_master(dev, sizeof *c); - if (!master) - return -ENODEV; - - c = spi_master_get_devdata(master); - -The driver will initialize the fields of that spi_master, including the -bus number (maybe the same as the platform device ID) and three methods -used to interact with the SPI core and SPI protocol drivers. It will -also initialize its own internal state. (See below about bus numbering -and those methods.) - -After you initialize the spi_master, then use spi_register_master() to -publish it to the rest of the system. At that time, device nodes for the -controller and any predeclared spi devices will be made available, and -the driver model core will take care of binding them to drivers. - -If you need to remove your SPI controller driver, spi_unregister_master() -will reverse the effect of spi_register_master(). - - -BUS NUMBERING - -Bus numbering is important, since that's how Linux identifies a given -SPI bus (shared SCK, MOSI, MISO). Valid bus numbers start at zero. On -SOC systems, the bus numbers should match the numbers defined by the chip -manufacturer. For example, hardware controller SPI2 would be bus number 2, -and spi_board_info for devices connected to it would use that number. - -If you don't have such hardware-assigned bus number, and for some reason -you can't just assign them, then provide a negative bus number. That will -then be replaced by a dynamically assigned number. You'd then need to treat -this as a non-static configuration (see above). - - -SPI MASTER METHODS - - master->setup(struct spi_device *spi) - This sets up the device clock rate, SPI mode, and word sizes. - Drivers may change the defaults provided by board_info, and then - call spi_setup(spi) to invoke this routine. It may sleep. - - Unless each SPI slave has its own configuration registers, don't - change them right away ... otherwise drivers could corrupt I/O - that's in progress for other SPI devices. - - ** BUG ALERT: for some reason the first version of - ** many spi_master drivers seems to get this wrong. - ** When you code setup(), ASSUME that the controller - ** is actively processing transfers for another device. - - master->cleanup(struct spi_device *spi) - Your controller driver may use spi_device.controller_state to hold - state it dynamically associates with that device. If you do that, - be sure to provide the cleanup() method to free that state. - - master->prepare_transfer_hardware(struct spi_master *master) - This will be called by the queue mechanism to signal to the driver - that a message is coming in soon, so the subsystem requests the - driver to prepare the transfer hardware by issuing this call. - This may sleep. - - master->unprepare_transfer_hardware(struct spi_master *master) - This will be called by the queue mechanism to signal to the driver - that there are no more messages pending in the queue and it may - relax the hardware (e.g. by power management calls). This may sleep. - - master->transfer_one_message(struct spi_master *master, - struct spi_message *mesg) - The subsystem calls the driver to transfer a single message while - queuing transfers that arrive in the meantime. When the driver is - finished with this message, it must call - spi_finalize_current_message() so the subsystem can issue the next - message. This may sleep. - - master->transfer_one(struct spi_master *master, struct spi_device *spi, - struct spi_transfer *transfer) - The subsystem calls the driver to transfer a single transfer while - queuing transfers that arrive in the meantime. When the driver is - finished with this transfer, it must call - spi_finalize_current_transfer() so the subsystem can issue the next - transfer. This may sleep. Note: transfer_one and transfer_one_message - are mutually exclusive; when both are set, the generic subsystem does - not call your transfer_one callback. - - Return values: - negative errno: error - 0: transfer is finished - 1: transfer is still in progress - - master->set_cs_timing(struct spi_device *spi, u8 setup_clk_cycles, - u8 hold_clk_cycles, u8 inactive_clk_cycles) - This method allows SPI client drivers to request SPI master controller - for configuring device specific CS setup, hold and inactive timing - requirements. - - DEPRECATED METHODS - - master->transfer(struct spi_device *spi, struct spi_message *message) - This must not sleep. Its responsibility is to arrange that the - transfer happens and its complete() callback is issued. The two - will normally happen later, after other transfers complete, and - if the controller is idle it will need to be kickstarted. This - method is not used on queued controllers and must be NULL if - transfer_one_message() and (un)prepare_transfer_hardware() are - implemented. - - -SPI MESSAGE QUEUE - -If you are happy with the standard queueing mechanism provided by the -SPI subsystem, just implement the queued methods specified above. Using -the message queue has the upside of centralizing a lot of code and -providing pure process-context execution of methods. The message queue -can also be elevated to realtime priority on high-priority SPI traffic. - -Unless the queueing mechanism in the SPI subsystem is selected, the bulk -of the driver will be managing the I/O queue fed by the now deprecated -function transfer(). - -That queue could be purely conceptual. For example, a driver used only -for low-frequency sensor access might be fine using synchronous PIO. - -But the queue will probably be very real, using message->queue, PIO, -often DMA (especially if the root filesystem is in SPI flash), and -execution contexts like IRQ handlers, tasklets, or workqueues (such -as keventd). Your driver can be as fancy, or as simple, as you need. -Such a transfer() method would normally just add the message to a -queue, and then start some asynchronous transfer engine (unless it's -already running). - - -THANKS TO ---------- -Contributors to Linux-SPI discussions include (in alphabetical order, -by last name): - -Mark Brown -David Brownell -Russell King -Grant Likely -Dmitry Pervushin -Stephen Street -Mark Underwood -Andrew Victor -Linus Walleij -Vitaly Wool diff --git a/Documentation/spi/spi-summary.rst b/Documentation/spi/spi-summary.rst new file mode 100644 index 000000000000..f1daffe10d78 --- /dev/null +++ b/Documentation/spi/spi-summary.rst @@ -0,0 +1,644 @@ +==================================== +Overview of Linux kernel SPI support +==================================== + +02-Feb-2012 + +What is SPI? +------------ +The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial +link used to connect microcontrollers to sensors, memory, and peripherals. +It's a simple "de facto" standard, not complicated enough to acquire a +standardization body. SPI uses a master/slave configuration. + +The three signal wires hold a clock (SCK, often on the order of 10 MHz), +and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In, +Slave Out" (MISO) signals. (Other names are also used.) There are four +clocking modes through which data is exchanged; mode-0 and mode-3 are most +commonly used. Each clock cycle shifts data out and data in; the clock +doesn't cycle except when there is a data bit to shift. Not all data bits +are used though; not every protocol uses those full duplex capabilities. + +SPI masters use a fourth "chip select" line to activate a given SPI slave +device, so those three signal wires may be connected to several chips +in parallel. All SPI slaves support chipselects; they are usually active +low signals, labeled nCSx for slave 'x' (e.g. nCS0). Some devices have +other signals, often including an interrupt to the master. + +Unlike serial busses like USB or SMBus, even low level protocols for +SPI slave functions are usually not interoperable between vendors +(except for commodities like SPI memory chips). + + - SPI may be used for request/response style device protocols, as with + touchscreen sensors and memory chips. + + - It may also be used to stream data in either direction (half duplex), + or both of them at the same time (full duplex). + + - Some devices may use eight bit words. Others may use different word + lengths, such as streams of 12-bit or 20-bit digital samples. + + - Words are usually sent with their most significant bit (MSB) first, + but sometimes the least significant bit (LSB) goes first instead. + + - Sometimes SPI is used to daisy-chain devices, like shift registers. + +In the same way, SPI slaves will only rarely support any kind of automatic +discovery/enumeration protocol. The tree of slave devices accessible from +a given SPI master will normally be set up manually, with configuration +tables. + +SPI is only one of the names used by such four-wire protocols, and +most controllers have no problem handling "MicroWire" (think of it as +half-duplex SPI, for request/response protocols), SSP ("Synchronous +Serial Protocol"), PSP ("Programmable Serial Protocol"), and other +related protocols. + +Some chips eliminate a signal line by combining MOSI and MISO, and +limiting themselves to half-duplex at the hardware level. In fact +some SPI chips have this signal mode as a strapping option. These +can be accessed using the same programming interface as SPI, but of +course they won't handle full duplex transfers. You may find such +chips described as using "three wire" signaling: SCK, data, nCSx. +(That data line is sometimes called MOMI or SISO.) + +Microcontrollers often support both master and slave sides of the SPI +protocol. This document (and Linux) supports both the master and slave +sides of SPI interactions. + + +Who uses it? On what kinds of systems? +--------------------------------------- +Linux developers using SPI are probably writing device drivers for embedded +systems boards. SPI is used to control external chips, and it is also a +protocol supported by every MMC or SD memory card. (The older "DataFlash" +cards, predating MMC cards but using the same connectors and card shape, +support only SPI.) Some PC hardware uses SPI flash for BIOS code. + +SPI slave chips range from digital/analog converters used for analog +sensors and codecs, to memory, to peripherals like USB controllers +or Ethernet adapters; and more. + +Most systems using SPI will integrate a few devices on a mainboard. +Some provide SPI links on expansion connectors; in cases where no +dedicated SPI controller exists, GPIO pins can be used to create a +low speed "bitbanging" adapter. Very few systems will "hotplug" an SPI +controller; the reasons to use SPI focus on low cost and simple operation, +and if dynamic reconfiguration is important, USB will often be a more +appropriate low-pincount peripheral bus. + +Many microcontrollers that can run Linux integrate one or more I/O +interfaces with SPI modes. Given SPI support, they could use MMC or SD +cards without needing a special purpose MMC/SD/SDIO controller. + + +I'm confused. What are these four SPI "clock modes"? +----------------------------------------------------- +It's easy to be confused here, and the vendor documentation you'll +find isn't necessarily helpful. The four modes combine two mode bits: + + - CPOL indicates the initial clock polarity. CPOL=0 means the + clock starts low, so the first (leading) edge is rising, and + the second (trailing) edge is falling. CPOL=1 means the clock + starts high, so the first (leading) edge is falling. + + - CPHA indicates the clock phase used to sample data; CPHA=0 says + sample on the leading edge, CPHA=1 means the trailing edge. + + Since the signal needs to stablize before it's sampled, CPHA=0 + implies that its data is written half a clock before the first + clock edge. The chipselect may have made it become available. + +Chip specs won't always say "uses SPI mode X" in as many words, +but their timing diagrams will make the CPOL and CPHA modes clear. + +In the SPI mode number, CPOL is the high order bit and CPHA is the +low order bit. So when a chip's timing diagram shows the clock +starting low (CPOL=0) and data stabilized for sampling during the +trailing clock edge (CPHA=1), that's SPI mode 1. + +Note that the clock mode is relevant as soon as the chipselect goes +active. So the master must set the clock to inactive before selecting +a slave, and the slave can tell the chosen polarity by sampling the +clock level when its select line goes active. That's why many devices +support for example both modes 0 and 3: they don't care about polarity, +and always clock data in/out on rising clock edges. + + +How do these driver programming interfaces work? +------------------------------------------------ +The header file includes kerneldoc, as does the +main source code, and you should certainly read that chapter of the +kernel API document. This is just an overview, so you get the big +picture before those details. + +SPI requests always go into I/O queues. Requests for a given SPI device +are always executed in FIFO order, and complete asynchronously through +completion callbacks. There are also some simple synchronous wrappers +for those calls, including ones for common transaction types like writing +a command and then reading its response. + +There are two types of SPI driver, here called: + + Controller drivers ... + controllers may be built into System-On-Chip + processors, and often support both Master and Slave roles. + These drivers touch hardware registers and may use DMA. + Or they can be PIO bitbangers, needing just GPIO pins. + + Protocol drivers ... + these pass messages through the controller + driver to communicate with a Slave or Master device on the + other side of an SPI link. + +So for example one protocol driver might talk to the MTD layer to export +data to filesystems stored on SPI flash like DataFlash; and others might +control audio interfaces, present touchscreen sensors as input interfaces, +or monitor temperature and voltage levels during industrial processing. +And those might all be sharing the same controller driver. + +A "struct spi_device" encapsulates the controller-side interface between +those two types of drivers. + +There is a minimal core of SPI programming interfaces, focussing on +using the driver model to connect controller and protocol drivers using +device tables provided by board specific initialization code. SPI +shows up in sysfs in several locations:: + + /sys/devices/.../CTLR ... physical node for a given SPI controller + + /sys/devices/.../CTLR/spiB.C ... spi_device on bus "B", + chipselect C, accessed through CTLR. + + /sys/bus/spi/devices/spiB.C ... symlink to that physical + .../CTLR/spiB.C device + + /sys/devices/.../CTLR/spiB.C/modalias ... identifies the driver + that should be used with this device (for hotplug/coldplug) + + /sys/bus/spi/drivers/D ... driver for one or more spi*.* devices + + /sys/class/spi_master/spiB ... symlink (or actual device node) to + a logical node which could hold class related state for the SPI + master controller managing bus "B". All spiB.* devices share one + physical SPI bus segment, with SCLK, MOSI, and MISO. + + /sys/devices/.../CTLR/slave ... virtual file for (un)registering the + slave device for an SPI slave controller. + Writing the driver name of an SPI slave handler to this file + registers the slave device; writing "(null)" unregisters the slave + device. + Reading from this file shows the name of the slave device ("(null)" + if not registered). + + /sys/class/spi_slave/spiB ... symlink (or actual device node) to + a logical node which could hold class related state for the SPI + slave controller on bus "B". When registered, a single spiB.* + device is present here, possible sharing the physical SPI bus + segment with other SPI slave devices. + +Note that the actual location of the controller's class state depends +on whether you enabled CONFIG_SYSFS_DEPRECATED or not. At this time, +the only class-specific state is the bus number ("B" in "spiB"), so +those /sys/class entries are only useful to quickly identify busses. + + +How does board-specific init code declare SPI devices? +------------------------------------------------------ +Linux needs several kinds of information to properly configure SPI devices. +That information is normally provided by board-specific code, even for +chips that do support some of automated discovery/enumeration. + +Declare Controllers +^^^^^^^^^^^^^^^^^^^ + +The first kind of information is a list of what SPI controllers exist. +For System-on-Chip (SOC) based boards, these will usually be platform +devices, and the controller may need some platform_data in order to +operate properly. The "struct platform_device" will include resources +like the physical address of the controller's first register and its IRQ. + +Platforms will often abstract the "register SPI controller" operation, +maybe coupling it with code to initialize pin configurations, so that +the arch/.../mach-*/board-*.c files for several boards can all share the +same basic controller setup code. This is because most SOCs have several +SPI-capable controllers, and only the ones actually usable on a given +board should normally be set up and registered. + +So for example arch/.../mach-*/board-*.c files might have code like:: + + #include /* for mysoc_spi_data */ + + /* if your mach-* infrastructure doesn't support kernels that can + * run on multiple boards, pdata wouldn't benefit from "__init". + */ + static struct mysoc_spi_data pdata __initdata = { ... }; + + static __init board_init(void) + { + ... + /* this board only uses SPI controller #2 */ + mysoc_register_spi(2, &pdata); + ... + } + +And SOC-specific utility code might look something like:: + + #include + + static struct platform_device spi2 = { ... }; + + void mysoc_register_spi(unsigned n, struct mysoc_spi_data *pdata) + { + struct mysoc_spi_data *pdata2; + + pdata2 = kmalloc(sizeof *pdata2, GFP_KERNEL); + *pdata2 = pdata; + ... + if (n == 2) { + spi2->dev.platform_data = pdata2; + register_platform_device(&spi2); + + /* also: set up pin modes so the spi2 signals are + * visible on the relevant pins ... bootloaders on + * production boards may already have done this, but + * developer boards will often need Linux to do it. + */ + } + ... + } + +Notice how the platform_data for boards may be different, even if the +same SOC controller is used. For example, on one board SPI might use +an external clock, where another derives the SPI clock from current +settings of some master clock. + +Declare Slave Devices +^^^^^^^^^^^^^^^^^^^^^ + +The second kind of information is a list of what SPI slave devices exist +on the target board, often with some board-specific data needed for the +driver to work correctly. + +Normally your arch/.../mach-*/board-*.c files would provide a small table +listing the SPI devices on each board. (This would typically be only a +small handful.) That might look like:: + + static struct ads7846_platform_data ads_info = { + .vref_delay_usecs = 100, + .x_plate_ohms = 580, + .y_plate_ohms = 410, + }; + + static struct spi_board_info spi_board_info[] __initdata = { + { + .modalias = "ads7846", + .platform_data = &ads_info, + .mode = SPI_MODE_0, + .irq = GPIO_IRQ(31), + .max_speed_hz = 120000 /* max sample rate at 3V */ * 16, + .bus_num = 1, + .chip_select = 0, + }, + }; + +Again, notice how board-specific information is provided; each chip may need +several types. This example shows generic constraints like the fastest SPI +clock to allow (a function of board voltage in this case) or how an IRQ pin +is wired, plus chip-specific constraints like an important delay that's +changed by the capacitance at one pin. + +(There's also "controller_data", information that may be useful to the +controller driver. An example would be peripheral-specific DMA tuning +data or chipselect callbacks. This is stored in spi_device later.) + +The board_info should provide enough information to let the system work +without the chip's driver being loaded. The most troublesome aspect of +that is likely the SPI_CS_HIGH bit in the spi_device.mode field, since +sharing a bus with a device that interprets chipselect "backwards" is +not possible until the infrastructure knows how to deselect it. + +Then your board initialization code would register that table with the SPI +infrastructure, so that it's available later when the SPI master controller +driver is registered:: + + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); + +Like with other static board-specific setup, you won't unregister those. + +The widely used "card" style computers bundle memory, cpu, and little else +onto a card that's maybe just thirty square centimeters. On such systems, +your ``arch/.../mach-.../board-*.c`` file would primarily provide information +about the devices on the mainboard into which such a card is plugged. That +certainly includes SPI devices hooked up through the card connectors! + + +Non-static Configurations +^^^^^^^^^^^^^^^^^^^^^^^^^ + +Developer boards often play by different rules than product boards, and one +example is the potential need to hotplug SPI devices and/or controllers. + +For those cases you might need to use spi_busnum_to_master() to look +up the spi bus master, and will likely need spi_new_device() to provide the +board info based on the board that was hotplugged. Of course, you'd later +call at least spi_unregister_device() when that board is removed. + +When Linux includes support for MMC/SD/SDIO/DataFlash cards through SPI, those +configurations will also be dynamic. Fortunately, such devices all support +basic device identification probes, so they should hotplug normally. + + +How do I write an "SPI Protocol Driver"? +---------------------------------------- +Most SPI drivers are currently kernel drivers, but there's also support +for userspace drivers. Here we talk only about kernel drivers. + +SPI protocol drivers somewhat resemble platform device drivers:: + + static struct spi_driver CHIP_driver = { + .driver = { + .name = "CHIP", + .owner = THIS_MODULE, + .pm = &CHIP_pm_ops, + }, + + .probe = CHIP_probe, + .remove = CHIP_remove, + }; + +The driver core will automatically attempt to bind this driver to any SPI +device whose board_info gave a modalias of "CHIP". Your probe() code +might look like this unless you're creating a device which is managing +a bus (appearing under /sys/class/spi_master). + +:: + + static int CHIP_probe(struct spi_device *spi) + { + struct CHIP *chip; + struct CHIP_platform_data *pdata; + + /* assuming the driver requires board-specific data: */ + pdata = &spi->dev.platform_data; + if (!pdata) + return -ENODEV; + + /* get memory for driver's per-chip state */ + chip = kzalloc(sizeof *chip, GFP_KERNEL); + if (!chip) + return -ENOMEM; + spi_set_drvdata(spi, chip); + + ... etc + return 0; + } + +As soon as it enters probe(), the driver may issue I/O requests to +the SPI device using "struct spi_message". When remove() returns, +or after probe() fails, the driver guarantees that it won't submit +any more such messages. + + - An spi_message is a sequence of protocol operations, executed + as one atomic sequence. SPI driver controls include: + + + when bidirectional reads and writes start ... by how its + sequence of spi_transfer requests is arranged; + + + which I/O buffers are used ... each spi_transfer wraps a + buffer for each transfer direction, supporting full duplex + (two pointers, maybe the same one in both cases) and half + duplex (one pointer is NULL) transfers; + + + optionally defining short delays after transfers ... using + the spi_transfer.delay_usecs setting (this delay can be the + only protocol effect, if the buffer length is zero); + + + whether the chipselect becomes inactive after a transfer and + any delay ... by using the spi_transfer.cs_change flag; + + + hinting whether the next message is likely to go to this same + device ... using the spi_transfer.cs_change flag on the last + transfer in that atomic group, and potentially saving costs + for chip deselect and select operations. + + - Follow standard kernel rules, and provide DMA-safe buffers in + your messages. That way controller drivers using DMA aren't forced + to make extra copies unless the hardware requires it (e.g. working + around hardware errata that force the use of bounce buffering). + + If standard dma_map_single() handling of these buffers is inappropriate, + you can use spi_message.is_dma_mapped to tell the controller driver + that you've already provided the relevant DMA addresses. + + - The basic I/O primitive is spi_async(). Async requests may be + issued in any context (irq handler, task, etc) and completion + is reported using a callback provided with the message. + After any detected error, the chip is deselected and processing + of that spi_message is aborted. + + - There are also synchronous wrappers like spi_sync(), and wrappers + like spi_read(), spi_write(), and spi_write_then_read(). These + may be issued only in contexts that may sleep, and they're all + clean (and small, and "optional") layers over spi_async(). + + - The spi_write_then_read() call, and convenience wrappers around + it, should only be used with small amounts of data where the + cost of an extra copy may be ignored. It's designed to support + common RPC-style requests, such as writing an eight bit command + and reading a sixteen bit response -- spi_w8r16() being one its + wrappers, doing exactly that. + +Some drivers may need to modify spi_device characteristics like the +transfer mode, wordsize, or clock rate. This is done with spi_setup(), +which would normally be called from probe() before the first I/O is +done to the device. However, that can also be called at any time +that no message is pending for that device. + +While "spi_device" would be the bottom boundary of the driver, the +upper boundaries might include sysfs (especially for sensor readings), +the input layer, ALSA, networking, MTD, the character device framework, +or other Linux subsystems. + +Note that there are two types of memory your driver must manage as part +of interacting with SPI devices. + + - I/O buffers use the usual Linux rules, and must be DMA-safe. + You'd normally allocate them from the heap or free page pool. + Don't use the stack, or anything that's declared "static". + + - The spi_message and spi_transfer metadata used to glue those + I/O buffers into a group of protocol transactions. These can + be allocated anywhere it's convenient, including as part of + other allocate-once driver data structures. Zero-init these. + +If you like, spi_message_alloc() and spi_message_free() convenience +routines are available to allocate and zero-initialize an spi_message +with several transfers. + + +How do I write an "SPI Master Controller Driver"? +------------------------------------------------- +An SPI controller will probably be registered on the platform_bus; write +a driver to bind to the device, whichever bus is involved. + +The main task of this type of driver is to provide an "spi_master". +Use spi_alloc_master() to allocate the master, and spi_master_get_devdata() +to get the driver-private data allocated for that device. + +:: + + struct spi_master *master; + struct CONTROLLER *c; + + master = spi_alloc_master(dev, sizeof *c); + if (!master) + return -ENODEV; + + c = spi_master_get_devdata(master); + +The driver will initialize the fields of that spi_master, including the +bus number (maybe the same as the platform device ID) and three methods +used to interact with the SPI core and SPI protocol drivers. It will +also initialize its own internal state. (See below about bus numbering +and those methods.) + +After you initialize the spi_master, then use spi_register_master() to +publish it to the rest of the system. At that time, device nodes for the +controller and any predeclared spi devices will be made available, and +the driver model core will take care of binding them to drivers. + +If you need to remove your SPI controller driver, spi_unregister_master() +will reverse the effect of spi_register_master(). + + +Bus Numbering +^^^^^^^^^^^^^ + +Bus numbering is important, since that's how Linux identifies a given +SPI bus (shared SCK, MOSI, MISO). Valid bus numbers start at zero. On +SOC systems, the bus numbers should match the numbers defined by the chip +manufacturer. For example, hardware controller SPI2 would be bus number 2, +and spi_board_info for devices connected to it would use that number. + +If you don't have such hardware-assigned bus number, and for some reason +you can't just assign them, then provide a negative bus number. That will +then be replaced by a dynamically assigned number. You'd then need to treat +this as a non-static configuration (see above). + + +SPI Master Methods +^^^^^^^^^^^^^^^^^^ + +``master->setup(struct spi_device *spi)`` + This sets up the device clock rate, SPI mode, and word sizes. + Drivers may change the defaults provided by board_info, and then + call spi_setup(spi) to invoke this routine. It may sleep. + + Unless each SPI slave has its own configuration registers, don't + change them right away ... otherwise drivers could corrupt I/O + that's in progress for other SPI devices. + + .. note:: + + BUG ALERT: for some reason the first version of + many spi_master drivers seems to get this wrong. + When you code setup(), ASSUME that the controller + is actively processing transfers for another device. + +``master->cleanup(struct spi_device *spi)`` + Your controller driver may use spi_device.controller_state to hold + state it dynamically associates with that device. If you do that, + be sure to provide the cleanup() method to free that state. + +``master->prepare_transfer_hardware(struct spi_master *master)`` + This will be called by the queue mechanism to signal to the driver + that a message is coming in soon, so the subsystem requests the + driver to prepare the transfer hardware by issuing this call. + This may sleep. + +``master->unprepare_transfer_hardware(struct spi_master *master)`` + This will be called by the queue mechanism to signal to the driver + that there are no more messages pending in the queue and it may + relax the hardware (e.g. by power management calls). This may sleep. + +``master->transfer_one_message(struct spi_master *master, struct spi_message *mesg)`` + The subsystem calls the driver to transfer a single message while + queuing transfers that arrive in the meantime. When the driver is + finished with this message, it must call + spi_finalize_current_message() so the subsystem can issue the next + message. This may sleep. + +``master->transfer_one(struct spi_master *master, struct spi_device *spi, struct spi_transfer *transfer)`` + The subsystem calls the driver to transfer a single transfer while + queuing transfers that arrive in the meantime. When the driver is + finished with this transfer, it must call + spi_finalize_current_transfer() so the subsystem can issue the next + transfer. This may sleep. Note: transfer_one and transfer_one_message + are mutually exclusive; when both are set, the generic subsystem does + not call your transfer_one callback. + + Return values: + + * negative errno: error + * 0: transfer is finished + * 1: transfer is still in progress + +``master->set_cs_timing(struct spi_device *spi, u8 setup_clk_cycles, u8 hold_clk_cycles, u8 inactive_clk_cycles)`` + This method allows SPI client drivers to request SPI master controller + for configuring device specific CS setup, hold and inactive timing + requirements. + +Deprecated Methods +^^^^^^^^^^^^^^^^^^ + +``master->transfer(struct spi_device *spi, struct spi_message *message)`` + This must not sleep. Its responsibility is to arrange that the + transfer happens and its complete() callback is issued. The two + will normally happen later, after other transfers complete, and + if the controller is idle it will need to be kickstarted. This + method is not used on queued controllers and must be NULL if + transfer_one_message() and (un)prepare_transfer_hardware() are + implemented. + + +SPI Message Queue +^^^^^^^^^^^^^^^^^ + +If you are happy with the standard queueing mechanism provided by the +SPI subsystem, just implement the queued methods specified above. Using +the message queue has the upside of centralizing a lot of code and +providing pure process-context execution of methods. The message queue +can also be elevated to realtime priority on high-priority SPI traffic. + +Unless the queueing mechanism in the SPI subsystem is selected, the bulk +of the driver will be managing the I/O queue fed by the now deprecated +function transfer(). + +That queue could be purely conceptual. For example, a driver used only +for low-frequency sensor access might be fine using synchronous PIO. + +But the queue will probably be very real, using message->queue, PIO, +often DMA (especially if the root filesystem is in SPI flash), and +execution contexts like IRQ handlers, tasklets, or workqueues (such +as keventd). Your driver can be as fancy, or as simple, as you need. +Such a transfer() method would normally just add the message to a +queue, and then start some asynchronous transfer engine (unless it's +already running). + + +THANKS TO +--------- +Contributors to Linux-SPI discussions include (in alphabetical order, +by last name): + +- Mark Brown +- David Brownell +- Russell King +- Grant Likely +- Dmitry Pervushin +- Stephen Street +- Mark Underwood +- Andrew Victor +- Linus Walleij +- Vitaly Wool diff --git a/Documentation/spi/spidev b/Documentation/spi/spidev deleted file mode 100644 index 3d14035b1766..000000000000 --- a/Documentation/spi/spidev +++ /dev/null @@ -1,149 +0,0 @@ -SPI devices have a limited userspace API, supporting basic half-duplex -read() and write() access to SPI slave devices. Using ioctl() requests, -full duplex transfers and device I/O configuration are also available. - - #include - #include - #include - #include - #include - -Some reasons you might want to use this programming interface include: - - * Prototyping in an environment that's not crash-prone; stray pointers - in userspace won't normally bring down any Linux system. - - * Developing simple protocols used to talk to microcontrollers acting - as SPI slaves, which you may need to change quite often. - -Of course there are drivers that can never be written in userspace, because -they need to access kernel interfaces (such as IRQ handlers or other layers -of the driver stack) that are not accessible to userspace. - - -DEVICE CREATION, DRIVER BINDING -=============================== -The simplest way to arrange to use this driver is to just list it in the -spi_board_info for a device as the driver it should use: the "modalias" -entry is "spidev", matching the name of the driver exposing this API. -Set up the other device characteristics (bits per word, SPI clocking, -chipselect polarity, etc) as usual, so you won't always need to override -them later. - -(Sysfs also supports userspace driven binding/unbinding of drivers to -devices. That mechanism might be supported here in the future.) - -When you do that, the sysfs node for the SPI device will include a child -device node with a "dev" attribute that will be understood by udev or mdev. -(Larger systems will have "udev". Smaller ones may configure "mdev" into -busybox; it's less featureful, but often enough.) For a SPI device with -chipselect C on bus B, you should see: - - /dev/spidevB.C ... character special device, major number 153 with - a dynamically chosen minor device number. This is the node - that userspace programs will open, created by "udev" or "mdev". - - /sys/devices/.../spiB.C ... as usual, the SPI device node will - be a child of its SPI master controller. - - /sys/class/spidev/spidevB.C ... created when the "spidev" driver - binds to that device. (Directory or symlink, based on whether - or not you enabled the "deprecated sysfs files" Kconfig option.) - -Do not try to manage the /dev character device special file nodes by hand. -That's error prone, and you'd need to pay careful attention to system -security issues; udev/mdev should already be configured securely. - -If you unbind the "spidev" driver from that device, those two "spidev" nodes -(in sysfs and in /dev) should automatically be removed (respectively by the -kernel and by udev/mdev). You can unbind by removing the "spidev" driver -module, which will affect all devices using this driver. You can also unbind -by having kernel code remove the SPI device, probably by removing the driver -for its SPI controller (so its spi_master vanishes). - -Since this is a standard Linux device driver -- even though it just happens -to expose a low level API to userspace -- it can be associated with any number -of devices at a time. Just provide one spi_board_info record for each such -SPI device, and you'll get a /dev device node for each device. - - -BASIC CHARACTER DEVICE API -========================== -Normal open() and close() operations on /dev/spidevB.D files work as you -would expect. - -Standard read() and write() operations are obviously only half-duplex, and -the chipselect is deactivated between those operations. Full-duplex access, -and composite operation without chipselect de-activation, is available using -the SPI_IOC_MESSAGE(N) request. - -Several ioctl() requests let your driver read or override the device's current -settings for data transfer parameters: - - SPI_IOC_RD_MODE, SPI_IOC_WR_MODE ... pass a pointer to a byte which will - return (RD) or assign (WR) the SPI transfer mode. Use the constants - SPI_MODE_0..SPI_MODE_3; or if you prefer you can combine SPI_CPOL - (clock polarity, idle high iff this is set) or SPI_CPHA (clock phase, - sample on trailing edge iff this is set) flags. - Note that this request is limited to SPI mode flags that fit in a - single byte. - - SPI_IOC_RD_MODE32, SPI_IOC_WR_MODE32 ... pass a pointer to a uin32_t - which will return (RD) or assign (WR) the full SPI transfer mode, - not limited to the bits that fit in one byte. - - SPI_IOC_RD_LSB_FIRST, SPI_IOC_WR_LSB_FIRST ... pass a pointer to a byte - which will return (RD) or assign (WR) the bit justification used to - transfer SPI words. Zero indicates MSB-first; other values indicate - the less common LSB-first encoding. In both cases the specified value - is right-justified in each word, so that unused (TX) or undefined (RX) - bits are in the MSBs. - - SPI_IOC_RD_BITS_PER_WORD, SPI_IOC_WR_BITS_PER_WORD ... pass a pointer to - a byte which will return (RD) or assign (WR) the number of bits in - each SPI transfer word. The value zero signifies eight bits. - - SPI_IOC_RD_MAX_SPEED_HZ, SPI_IOC_WR_MAX_SPEED_HZ ... pass a pointer to a - u32 which will return (RD) or assign (WR) the maximum SPI transfer - speed, in Hz. The controller can't necessarily assign that specific - clock speed. - -NOTES: - - - At this time there is no async I/O support; everything is purely - synchronous. - - - There's currently no way to report the actual bit rate used to - shift data to/from a given device. - - - From userspace, you can't currently change the chip select polarity; - that could corrupt transfers to other devices sharing the SPI bus. - Each SPI device is deselected when it's not in active use, allowing - other drivers to talk to other devices. - - - There's a limit on the number of bytes each I/O request can transfer - to the SPI device. It defaults to one page, but that can be changed - using a module parameter. - - - Because SPI has no low-level transfer acknowledgement, you usually - won't see any I/O errors when talking to a non-existent device. - - -FULL DUPLEX CHARACTER DEVICE API -================================ - -See the spidev_fdx.c sample program for one example showing the use of the -full duplex programming interface. (Although it doesn't perform a full duplex -transfer.) The model is the same as that used in the kernel spi_sync() -request; the individual transfers offer the same capabilities as are -available to kernel drivers (except that it's not asynchronous). - -The example shows one half-duplex RPC-style request and response message. -These requests commonly require that the chip not be deselected between -the request and response. Several such requests could be chained into -a single kernel request, even allowing the chip to be deselected after -each response. (Other protocol options include changing the word size -and bitrate for each transfer segment.) - -To make a full duplex request, provide both rx_buf and tx_buf for the -same transfer. It's even OK if those are the same buffer. diff --git a/Documentation/spi/spidev.rst b/Documentation/spi/spidev.rst new file mode 100644 index 000000000000..f05dbc5ccdbc --- /dev/null +++ b/Documentation/spi/spidev.rst @@ -0,0 +1,163 @@ +================= +SPI userspace API +================= + +SPI devices have a limited userspace API, supporting basic half-duplex +read() and write() access to SPI slave devices. Using ioctl() requests, +full duplex transfers and device I/O configuration are also available. + +:: + + #include + #include + #include + #include + #include + +Some reasons you might want to use this programming interface include: + + * Prototyping in an environment that's not crash-prone; stray pointers + in userspace won't normally bring down any Linux system. + + * Developing simple protocols used to talk to microcontrollers acting + as SPI slaves, which you may need to change quite often. + +Of course there are drivers that can never be written in userspace, because +they need to access kernel interfaces (such as IRQ handlers or other layers +of the driver stack) that are not accessible to userspace. + + +DEVICE CREATION, DRIVER BINDING +=============================== +The simplest way to arrange to use this driver is to just list it in the +spi_board_info for a device as the driver it should use: the "modalias" +entry is "spidev", matching the name of the driver exposing this API. +Set up the other device characteristics (bits per word, SPI clocking, +chipselect polarity, etc) as usual, so you won't always need to override +them later. + +(Sysfs also supports userspace driven binding/unbinding of drivers to +devices. That mechanism might be supported here in the future.) + +When you do that, the sysfs node for the SPI device will include a child +device node with a "dev" attribute that will be understood by udev or mdev. +(Larger systems will have "udev". Smaller ones may configure "mdev" into +busybox; it's less featureful, but often enough.) For a SPI device with +chipselect C on bus B, you should see: + + /dev/spidevB.C ... + character special device, major number 153 with + a dynamically chosen minor device number. This is the node + that userspace programs will open, created by "udev" or "mdev". + + /sys/devices/.../spiB.C ... + as usual, the SPI device node will + be a child of its SPI master controller. + + /sys/class/spidev/spidevB.C ... + created when the "spidev" driver + binds to that device. (Directory or symlink, based on whether + or not you enabled the "deprecated sysfs files" Kconfig option.) + +Do not try to manage the /dev character device special file nodes by hand. +That's error prone, and you'd need to pay careful attention to system +security issues; udev/mdev should already be configured securely. + +If you unbind the "spidev" driver from that device, those two "spidev" nodes +(in sysfs and in /dev) should automatically be removed (respectively by the +kernel and by udev/mdev). You can unbind by removing the "spidev" driver +module, which will affect all devices using this driver. You can also unbind +by having kernel code remove the SPI device, probably by removing the driver +for its SPI controller (so its spi_master vanishes). + +Since this is a standard Linux device driver -- even though it just happens +to expose a low level API to userspace -- it can be associated with any number +of devices at a time. Just provide one spi_board_info record for each such +SPI device, and you'll get a /dev device node for each device. + + +BASIC CHARACTER DEVICE API +========================== +Normal open() and close() operations on /dev/spidevB.D files work as you +would expect. + +Standard read() and write() operations are obviously only half-duplex, and +the chipselect is deactivated between those operations. Full-duplex access, +and composite operation without chipselect de-activation, is available using +the SPI_IOC_MESSAGE(N) request. + +Several ioctl() requests let your driver read or override the device's current +settings for data transfer parameters: + + SPI_IOC_RD_MODE, SPI_IOC_WR_MODE ... + pass a pointer to a byte which will + return (RD) or assign (WR) the SPI transfer mode. Use the constants + SPI_MODE_0..SPI_MODE_3; or if you prefer you can combine SPI_CPOL + (clock polarity, idle high iff this is set) or SPI_CPHA (clock phase, + sample on trailing edge iff this is set) flags. + Note that this request is limited to SPI mode flags that fit in a + single byte. + + SPI_IOC_RD_MODE32, SPI_IOC_WR_MODE32 ... + pass a pointer to a uin32_t + which will return (RD) or assign (WR) the full SPI transfer mode, + not limited to the bits that fit in one byte. + + SPI_IOC_RD_LSB_FIRST, SPI_IOC_WR_LSB_FIRST ... + pass a pointer to a byte + which will return (RD) or assign (WR) the bit justification used to + transfer SPI words. Zero indicates MSB-first; other values indicate + the less common LSB-first encoding. In both cases the specified value + is right-justified in each word, so that unused (TX) or undefined (RX) + bits are in the MSBs. + + SPI_IOC_RD_BITS_PER_WORD, SPI_IOC_WR_BITS_PER_WORD ... + pass a pointer to + a byte which will return (RD) or assign (WR) the number of bits in + each SPI transfer word. The value zero signifies eight bits. + + SPI_IOC_RD_MAX_SPEED_HZ, SPI_IOC_WR_MAX_SPEED_HZ ... + pass a pointer to a + u32 which will return (RD) or assign (WR) the maximum SPI transfer + speed, in Hz. The controller can't necessarily assign that specific + clock speed. + +NOTES: + + - At this time there is no async I/O support; everything is purely + synchronous. + + - There's currently no way to report the actual bit rate used to + shift data to/from a given device. + + - From userspace, you can't currently change the chip select polarity; + that could corrupt transfers to other devices sharing the SPI bus. + Each SPI device is deselected when it's not in active use, allowing + other drivers to talk to other devices. + + - There's a limit on the number of bytes each I/O request can transfer + to the SPI device. It defaults to one page, but that can be changed + using a module parameter. + + - Because SPI has no low-level transfer acknowledgement, you usually + won't see any I/O errors when talking to a non-existent device. + + +FULL DUPLEX CHARACTER DEVICE API +================================ + +See the spidev_fdx.c sample program for one example showing the use of the +full duplex programming interface. (Although it doesn't perform a full duplex +transfer.) The model is the same as that used in the kernel spi_sync() +request; the individual transfers offer the same capabilities as are +available to kernel drivers (except that it's not asynchronous). + +The example shows one half-duplex RPC-style request and response message. +These requests commonly require that the chip not be deselected between +the request and response. Several such requests could be chained into +a single kernel request, even allowing the chip to be deselected after +each response. (Other protocol options include changing the word size +and bitrate for each transfer segment.) + +To make a full duplex request, provide both rx_buf and tx_buf for the +same transfer. It's even OK if those are the same buffer. diff --git a/drivers/iio/dummy/iio_simple_dummy.c b/drivers/iio/dummy/iio_simple_dummy.c index d28974ad9e0e..6cb02299a215 100644 --- a/drivers/iio/dummy/iio_simple_dummy.c +++ b/drivers/iio/dummy/iio_simple_dummy.c @@ -695,7 +695,7 @@ static int iio_dummy_remove(struct iio_sw_device *swd) * i2c: * Documentation/i2c/writing-clients.rst * spi: - * Documentation/spi/spi-summary + * Documentation/spi/spi-summary.rst */ static const struct iio_sw_device_ops iio_dummy_device_ops = { .probe = iio_dummy_probe, diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3a1d8f1170de..d5a24fe983e7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -543,7 +543,7 @@ config SPI_PXA2XX help This enables using a PXA2xx or Sodaville SSP port as a SPI master controller. The driver can be configured to use any SSP port and - additional documentation can be found a Documentation/spi/pxa2xx. + additional documentation can be found a Documentation/spi/pxa2xx.rst. config SPI_PXA2XX_PCI def_tristate SPI_PXA2XX && PCI && COMMON_CLK diff --git a/drivers/spi/spi-butterfly.c b/drivers/spi/spi-butterfly.c index 8c77d1114ad3..7e71a351f3b7 100644 --- a/drivers/spi/spi-butterfly.c +++ b/drivers/spi/spi-butterfly.c @@ -23,7 +23,7 @@ * with a battery powered AVR microcontroller and lots of goodies. You * can use GCC to develop firmware for this. * - * See Documentation/spi/butterfly for information about how to build + * See Documentation/spi/butterfly.rst for information about how to build * and use this custom parallel port cable. */ diff --git a/drivers/spi/spi-lm70llp.c b/drivers/spi/spi-lm70llp.c index f18f912c9dea..174dba29b1dd 100644 --- a/drivers/spi/spi-lm70llp.c +++ b/drivers/spi/spi-lm70llp.c @@ -34,7 +34,7 @@ * available (on page 4) here: * http://www.national.com/appinfo/tempsensors/files/LM70LLPEVALmanual.pdf * - * Also see Documentation/spi/spi-lm70llp. The SPI<->parport code here is + * Also see Documentation/spi/spi-lm70llp.rst. The SPI<->parport code here is * (heavily) based on spi-butterfly by David Brownell. * * The LM70 LLP connects to the PC parallel port in the following manner: diff --git a/include/linux/platform_data/sc18is602.h b/include/linux/platform_data/sc18is602.h index e066d3b0d6d8..0e91489edfe6 100644 --- a/include/linux/platform_data/sc18is602.h +++ b/include/linux/platform_data/sc18is602.h @@ -4,7 +4,7 @@ * * Copyright (C) 2012 Guenter Roeck * - * For further information, see the Documentation/spi/spi-sc18is602 file. + * For further information, see the Documentation/spi/spi-sc18is602.rst file. */ /** -- cgit v1.2.3-71-gd317 From 3d6ade0abfe1ac833b525349ade156a269979cf0 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 20 Jul 2019 20:58:58 +0900 Subject: pinctrl: pinctrl-single: add header include guard Add a header include guard just in case. Signed-off-by: Masahiro Yamada Link: https://lore.kernel.org/r/20190720115858.7015-1-yamada.masahiro@socionext.com Signed-off-by: Linus Walleij --- include/linux/platform_data/pinctrl-single.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/linux/platform_data') diff --git a/include/linux/platform_data/pinctrl-single.h b/include/linux/platform_data/pinctrl-single.h index 1cf36fdf9510..7473d3c4cabf 100644 --- a/include/linux/platform_data/pinctrl-single.h +++ b/include/linux/platform_data/pinctrl-single.h @@ -1,4 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _PINCTRL_SINGLE_H +#define _PINCTRL_SINGLE_H + /** * irq: optional wake-up interrupt * rearm: optional soc specific rearm function @@ -11,3 +15,5 @@ struct pcs_pdata { int irq; void (*rearm)(void); }; + +#endif /* _PINCTRL_SINGLE_H */ -- cgit v1.2.3-71-gd317 From b2a3974253d32374af556541141d7fdad8fe2ce0 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sun, 21 Jul 2019 16:36:49 +0900 Subject: usb: dwc3: omap: squash include/linux/platform_data/dwc3-omap.h This enum is only used in drivers/usb/dwc3/dwc3-omap3.c Signed-off-by: Masahiro Yamada Signed-off-by: Felipe Balbi --- drivers/usb/dwc3/dwc3-omap.c | 7 +++++- include/linux/platform_data/dwc3-omap.h | 43 --------------------------------- 2 files changed, 6 insertions(+), 44 deletions(-) delete mode 100644 include/linux/platform_data/dwc3-omap.h (limited to 'include/linux/platform_data') diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c index 84c459c15222..c2940dbfb683 100644 --- a/drivers/usb/dwc3/dwc3-omap.c +++ b/drivers/usb/dwc3/dwc3-omap.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -106,6 +105,12 @@ #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID BIT(2) #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID BIT(1) +enum dwc3_omap_utmi_mode { + DWC3_OMAP_UTMI_MODE_UNKNOWN = 0, + DWC3_OMAP_UTMI_MODE_HW, + DWC3_OMAP_UTMI_MODE_SW, +}; + struct dwc3_omap { struct device *dev; diff --git a/include/linux/platform_data/dwc3-omap.h b/include/linux/platform_data/dwc3-omap.h deleted file mode 100644 index 1d36ca874cc8..000000000000 --- a/include/linux/platform_data/dwc3-omap.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * dwc3-omap.h - OMAP Specific Glue layer, header. - * - * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com - * All rights reserved. - * - * Author: Felipe Balbi - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The names of the above-listed copyright holders may not be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * ALTERNATIVELY, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2, as published by the Free - * Software Foundation. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -enum dwc3_omap_utmi_mode { - DWC3_OMAP_UTMI_MODE_UNKNOWN = 0, - DWC3_OMAP_UTMI_MODE_HW, - DWC3_OMAP_UTMI_MODE_SW, -}; -- cgit v1.2.3-71-gd317 From 3846a3b9511c5166082a93536d919a9c42abcd91 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 7 Aug 2019 11:26:45 +0300 Subject: iommu/omap: fix boot issue on remoteprocs with AMMU/Unicache Support has been added to the OMAP IOMMU driver to fix a boot hang issue on OMAP remoteprocs with AMMU/Unicache, caused by an improper AMMU/Unicache state upon initial deassertion of the processor reset. The issue is described in detail in the next three paragraphs. All the Cortex M3/M4 IPU processor subsystems in OMAP SoCs have a AMMU/Unicache IP that dictates the memory attributes for addresses seen by the processor cores. The AMMU/Unicache is configured/enabled by the SCACHE_CONFIG.BYPASS bit - a value of 1 enables the cache and mandates all addresses accessed by M3/M4 be defined in the AMMU. This bit is not programmable from the host processor. The M3/M4 boot sequence starts out with the AMMU/Unicache in disabled state, and SYS/BIOS programs the AMMU regions and enables the Unicache during one of its initial boot steps. This SCACHE_CONFIG.BYPASS bit is however enabled by default whenever a RET reset is applied to the IP, irrespective of whether it was previously enabled or not. The AMMU registers lose their context whenever this reset is applied. The reset is effective as long as the MMU portion of the subsystem is enabled and clocked. This behavior is common to all the IPU and DSP subsystems that have an AMMU/Unicache. The IPU boot sequence involves enabling and programming the MMU, and loading the processor and releasing the reset(s) for the processor. The PM setup code currently sets the target state for most of the power domains to RET. The L2 MMU can be enabled, programmed and accessed properly just fine with the domain in hardware supervised mode, while the power domain goes through a RET->ON->RET transition during the programming sequence. However, the ON->RET transition asserts a RET reset, and the SCACHE_CONFIG.BYPASS bit gets auto-set. An AMMU fault is thrown immediately when the M3/M4 core's reset is released since the first instruction address itself will not be defined in any valid AMMU regions. The ON->RET transition happens automatically on the power domain after enabling the iommu due to the hardware supervised mode. This patch adds and invokes the .set_pwrdm_constraint pdata ops, if present, during the OMAP IOMMU enable and disable functions to resolve the above boot hang issue. The ops will allow to invoke a mach-omap2 layer API pwrdm_set_next_pwrst() in a multi-arch kernel environment. The ops also returns the current power domain state while enforcing the constraint so that the driver can store it and use it to set back the power domain state while releasing the constraint. The pdata ops implementation restricts the target power domain to ON during enable, and back to the original power domain state during disable, and thereby eliminating the conditions for the boot issue. The implementation is effective only when the original power domain state is either RET or OFF, and is a no-op when it is ON or INACTIVE. The .set_pwrdm_constraint ops need to be plugged in pdata-quirks for the affected remote processors to be able to boot properly. Note that the current issue is seen only on kernels with the affected power domains programmed to enter RET. For eg., IPU1 on DRA7xx is in a separate domain and is susceptible to this bug, while the IPU2 subsystem is within CORE power domain, and CORE RET is not supported on this SoC. IPUs on OMAP4 and OMAP5 are also susceptible since they are in CORE power domain, and CORE RET is a valid power target on these SoCs. Signed-off-by: Suman Anna Signed-off-by: Joerg Roedel --- arch/arm/mach-omap2/Makefile | 2 ++ arch/arm/mach-omap2/omap-iommu.c | 43 ++++++++++++++++++++++++++++++++ drivers/iommu/omap-iommu.c | 17 +++++++++++++ drivers/iommu/omap-iommu.h | 2 ++ include/linux/platform_data/iommu-omap.h | 2 ++ 5 files changed, 66 insertions(+) create mode 100644 arch/arm/mach-omap2/omap-iommu.c (limited to 'include/linux/platform_data') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 600650551621..d4f11c5070ae 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -229,3 +229,5 @@ include/generated/ti-pm-asm-offsets.h: arch/arm/mach-omap2/pm-asm-offsets.s FORC $(obj)/sleep33xx.o $(obj)/sleep43xx.o: include/generated/ti-pm-asm-offsets.h targets += pm-asm-offsets.s + +obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c new file mode 100644 index 000000000000..f1a6ece8108e --- /dev/null +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * OMAP IOMMU quirks for various TI SoCs + * + * Copyright (C) 2015-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Suman Anna + */ + +#include +#include + +#include "omap_hwmod.h" +#include "omap_device.h" +#include "powerdomain.h" + +int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request, + u8 *pwrst) +{ + struct powerdomain *pwrdm; + struct omap_device *od; + u8 next_pwrst; + + od = to_omap_device(pdev); + if (!od) + return -ENODEV; + + if (od->hwmods_cnt != 1) + return -EINVAL; + + pwrdm = omap_hwmod_get_pwrdm(od->hwmods[0]); + if (!pwrdm) + return -EINVAL; + + if (request) + *pwrst = pwrdm_read_next_pwrst(pwrdm); + + if (*pwrst > PWRDM_POWER_RET) + return 0; + + next_pwrst = request ? PWRDM_POWER_ON : *pwrst; + + return pwrdm_set_next_pwrst(pwrdm, next_pwrst); +} diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index dfb961d8c21b..84b99d5841ae 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -190,6 +190,14 @@ static int iommu_enable(struct omap_iommu *obj) struct platform_device *pdev = to_platform_device(obj->dev); struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev); + if (pdata && pdata->set_pwrdm_constraint) { + err = pdata->set_pwrdm_constraint(pdev, true, &obj->pwrst); + if (err) { + dev_warn(obj->dev, "pwrdm_constraint failed to be set, status = %d\n", + err); + } + } + if (pdata && pdata->deassert_reset) { err = pdata->deassert_reset(pdev, pdata->reset_name); if (err) { @@ -209,6 +217,7 @@ static void iommu_disable(struct omap_iommu *obj) { struct platform_device *pdev = to_platform_device(obj->dev); struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev); + int ret; omap2_iommu_disable(obj); @@ -216,6 +225,14 @@ static void iommu_disable(struct omap_iommu *obj) if (pdata && pdata->assert_reset) pdata->assert_reset(pdev, pdata->reset_name); + + if (pdata && pdata->set_pwrdm_constraint) { + ret = pdata->set_pwrdm_constraint(pdev, false, &obj->pwrst); + if (ret) { + dev_warn(obj->dev, "pwrdm_constraint failed to be reset, status = %d\n", + ret); + } + } } /* diff --git a/drivers/iommu/omap-iommu.h b/drivers/iommu/omap-iommu.h index 09968a02d291..aac1ca65ef9d 100644 --- a/drivers/iommu/omap-iommu.h +++ b/drivers/iommu/omap-iommu.h @@ -78,6 +78,8 @@ struct omap_iommu { struct iommu_device iommu; struct iommu_group *group; + + u8 pwrst; }; /** diff --git a/include/linux/platform_data/iommu-omap.h b/include/linux/platform_data/iommu-omap.h index 44d913a7580c..1ed60265a20e 100644 --- a/include/linux/platform_data/iommu-omap.h +++ b/include/linux/platform_data/iommu-omap.h @@ -13,4 +13,6 @@ struct iommu_platform_data { const char *reset_name; int (*assert_reset)(struct platform_device *pdev, const char *name); int (*deassert_reset)(struct platform_device *pdev, const char *name); + int (*set_pwrdm_constraint)(struct platform_device *pdev, bool request, + u8 *pwrst); }; -- cgit v1.2.3-71-gd317 From 74c116df66d25a9fb48d44ce545a505edc5fbbba Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 7 Aug 2019 11:26:46 +0300 Subject: iommu/omap: add pdata ops for omap_device_enable/idle Add two new platform data ops to allow the OMAP iommu driver to be able to invoke the omap_device_enable and omap_device_idle from within the driver. These are being added to streamline the sequence between managing the hard reset lines and the clocks during the suspend path, as the default device pm_domain callback sequences in omap_device layer are not conducive for the OMAP IOMMU driver. This could have been done by expanding the existing pdata ops for reset management (like in the OMAP remoteproc driver), but this was chosen to avoid adding additional code in the separate file in the mach-omap2 layer. Signed-off-by: Suman Anna Signed-off-by: Joerg Roedel --- include/linux/platform_data/iommu-omap.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/linux/platform_data') diff --git a/include/linux/platform_data/iommu-omap.h b/include/linux/platform_data/iommu-omap.h index 1ed60265a20e..8474a0208b34 100644 --- a/include/linux/platform_data/iommu-omap.h +++ b/include/linux/platform_data/iommu-omap.h @@ -13,6 +13,8 @@ struct iommu_platform_data { const char *reset_name; int (*assert_reset)(struct platform_device *pdev, const char *name); int (*deassert_reset)(struct platform_device *pdev, const char *name); + int (*device_enable)(struct platform_device *pdev); + int (*device_idle)(struct platform_device *pdev); int (*set_pwrdm_constraint)(struct platform_device *pdev, bool request, u8 *pwrst); }; -- cgit v1.2.3-71-gd317 From 54d662227caebaabd25823c6d955ba92dfa361a8 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 13 Aug 2019 04:13:32 -0700 Subject: bus: ti-sysc: Switch to SPDX license identifier Use the appropriate SPDX license identifier in the TI sysc interconnect target driver source files and drop the previous boilerplate license text. Also, add the the SPDX license identifier in the associated ti-sysc header files. Signed-off-by: Suman Anna Acked-by: Roger Quadros Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 10 +--------- include/linux/platform_data/ti-sysc.h | 2 ++ 2 files changed, 3 insertions(+), 9 deletions(-) (limited to 'include/linux/platform_data') diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 2db474ab4c6b..45e08528fdff 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1,14 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * ti-sysc.c - Texas Instruments sysc interconnect target driver - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h index 0c587d4fc718..7d009dc08a54 100644 --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + #ifndef __TI_SYSC_DATA_H__ #define __TI_SYSC_DATA_H__ -- cgit v1.2.3-71-gd317 From b58056da2ec28e2c1b66096cd5109997f04d3fd1 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 13 Aug 2019 04:13:32 -0700 Subject: bus: ti-sysc: Add missing kerneldoc comments A few fields in various structures is missing the corresponding kerneldoc comments. Add them. Also, fixed the comment for sidlemodes. Signed-off-by: Suman Anna Acked-by: Roger Quadros Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 7 +++++++ include/linux/platform_data/ti-sysc.h | 5 +++-- 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'include/linux/platform_data') diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 45e08528fdff..35997a2b2dc4 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -54,15 +54,22 @@ static const char * const clock_names[SYSC_MAX_CLOCKS] = { * @module_size: size of the interconnect target module * @module_va: virtual address of the interconnect target module * @offsets: register offsets from module base + * @mdata: ti-sysc to hwmod translation data for a module * @clocks: clocks used by the interconnect target module * @clock_roles: clock role names for the found clocks * @nr_clocks: number of clocks used by the interconnect target module + * @rsts: resets used by the interconnect target module * @legacy_mode: configured for legacy mode if set * @cap: interconnect target module capabilities * @cfg: interconnect target module configuration + * @cookie: data used by legacy platform callbacks * @name: name if available * @revision: interconnect target module revision + * @enabled: sysc runtime enabled status * @needs_resume: runtime resume needed on resume from suspend + * @child_needs_resume: runtime resume needed for child on resume from suspend + * @disable_on_idle: status flag used for disabling modules with resets + * @idle_work: work structure used to perform delayed idle on a module * @clk_enable_quirk: module specific clock enable quirk * @clk_disable_quirk: module specific clock disable quirk * @reset_done_quirk: module specific reset done quirk diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h index 7d009dc08a54..1a0905435b32 100644 --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h @@ -72,7 +72,7 @@ struct sysc_regbits { /** * struct sysc_capabilities - capabilities for an interconnect target module - * + * @type: sysc type identifier for the module * @sysc_mask: bitmask of supported SYSCONFIG register bits * @regbits: bitmask of SYSCONFIG register bits * @mod_quirks: bitmask of module specific quirks @@ -87,8 +87,9 @@ struct sysc_capabilities { /** * struct sysc_config - configuration for an interconnect target module * @sysc_val: configured value for sysc register + * @syss_mask: configured mask value for SYSSTATUS register * @midlemodes: bitmask of supported master idle modes - * @sidlemodes: bitmask of supported master idle modes + * @sidlemodes: bitmask of supported slave idle modes * @srst_udelay: optional delay needed after OCP soft reset * @quirks: bitmask of enabled quirks */ -- cgit v1.2.3-71-gd317 From aad7ad2a01e774f5cd0dde8f0bc6e253ae3f0d35 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 18:33:18 +0200 Subject: dma: iop-adma: allow building without platform headers Now that iop3xx and iop13xx are gone, the iop-adma driver no longer needs to deal with incompatible register layout defined in machine specific header files. Move the iop32x specific definitions into drivers/dma/iop-adma.h and the platform_data into include/linux/platform_data/dma-iop32x.h, and change the machine code to no longer reference those. The DMA0_ID/DMA1_ID/AAU_ID macros are required as part of the platform data interface and still need to be visible, so move those from one header to the other. Link: https://lore.kernel.org/r/20190809163334.489360-4-arnd@arndb.de Signed-off-by: Arnd Bergmann --- arch/arm/include/asm/hardware/iop3xx-adma.h | 919 ---------------------------- arch/arm/include/asm/hardware/iop_adma.h | 106 ---- arch/arm/mach-iop32x/include/mach/adma.h | 6 - arch/arm/plat-iop/adma.c | 3 +- drivers/dma/Kconfig | 4 +- drivers/dma/iop-adma.c | 3 +- drivers/dma/iop-adma.h | 914 +++++++++++++++++++++++++++ include/linux/platform_data/dma-iop32x.h | 110 ++++ 8 files changed, 1028 insertions(+), 1037 deletions(-) delete mode 100644 arch/arm/include/asm/hardware/iop3xx-adma.h delete mode 100644 arch/arm/include/asm/hardware/iop_adma.h delete mode 100644 arch/arm/mach-iop32x/include/mach/adma.h create mode 100644 drivers/dma/iop-adma.h create mode 100644 include/linux/platform_data/dma-iop32x.h (limited to 'include/linux/platform_data') diff --git a/arch/arm/include/asm/hardware/iop3xx-adma.h b/arch/arm/include/asm/hardware/iop3xx-adma.h deleted file mode 100644 index 6d998df17efd..000000000000 --- a/arch/arm/include/asm/hardware/iop3xx-adma.h +++ /dev/null @@ -1,919 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright © 2006, Intel Corporation. - */ -#ifndef _ADMA_H -#define _ADMA_H -#include -#include -#include -#include - -/* Memory copy units */ -#define DMA_CCR(chan) (chan->mmr_base + 0x0) -#define DMA_CSR(chan) (chan->mmr_base + 0x4) -#define DMA_DAR(chan) (chan->mmr_base + 0xc) -#define DMA_NDAR(chan) (chan->mmr_base + 0x10) -#define DMA_PADR(chan) (chan->mmr_base + 0x14) -#define DMA_PUADR(chan) (chan->mmr_base + 0x18) -#define DMA_LADR(chan) (chan->mmr_base + 0x1c) -#define DMA_BCR(chan) (chan->mmr_base + 0x20) -#define DMA_DCR(chan) (chan->mmr_base + 0x24) - -/* Application accelerator unit */ -#define AAU_ACR(chan) (chan->mmr_base + 0x0) -#define AAU_ASR(chan) (chan->mmr_base + 0x4) -#define AAU_ADAR(chan) (chan->mmr_base + 0x8) -#define AAU_ANDAR(chan) (chan->mmr_base + 0xc) -#define AAU_SAR(src, chan) (chan->mmr_base + (0x10 + ((src) << 2))) -#define AAU_DAR(chan) (chan->mmr_base + 0x20) -#define AAU_ABCR(chan) (chan->mmr_base + 0x24) -#define AAU_ADCR(chan) (chan->mmr_base + 0x28) -#define AAU_SAR_EDCR(src_edc) (chan->mmr_base + (0x02c + ((src_edc-4) << 2))) -#define AAU_EDCR0_IDX 8 -#define AAU_EDCR1_IDX 17 -#define AAU_EDCR2_IDX 26 - -#define DMA0_ID 0 -#define DMA1_ID 1 -#define AAU_ID 2 - -struct iop3xx_aau_desc_ctrl { - unsigned int int_en:1; - unsigned int blk1_cmd_ctrl:3; - unsigned int blk2_cmd_ctrl:3; - unsigned int blk3_cmd_ctrl:3; - unsigned int blk4_cmd_ctrl:3; - unsigned int blk5_cmd_ctrl:3; - unsigned int blk6_cmd_ctrl:3; - unsigned int blk7_cmd_ctrl:3; - unsigned int blk8_cmd_ctrl:3; - unsigned int blk_ctrl:2; - unsigned int dual_xor_en:1; - unsigned int tx_complete:1; - unsigned int zero_result_err:1; - unsigned int zero_result_en:1; - unsigned int dest_write_en:1; -}; - -struct iop3xx_aau_e_desc_ctrl { - unsigned int reserved:1; - unsigned int blk1_cmd_ctrl:3; - unsigned int blk2_cmd_ctrl:3; - unsigned int blk3_cmd_ctrl:3; - unsigned int blk4_cmd_ctrl:3; - unsigned int blk5_cmd_ctrl:3; - unsigned int blk6_cmd_ctrl:3; - unsigned int blk7_cmd_ctrl:3; - unsigned int blk8_cmd_ctrl:3; - unsigned int reserved2:7; -}; - -struct iop3xx_dma_desc_ctrl { - unsigned int pci_transaction:4; - unsigned int int_en:1; - unsigned int dac_cycle_en:1; - unsigned int mem_to_mem_en:1; - unsigned int crc_data_tx_en:1; - unsigned int crc_gen_en:1; - unsigned int crc_seed_dis:1; - unsigned int reserved:21; - unsigned int crc_tx_complete:1; -}; - -struct iop3xx_desc_dma { - u32 next_desc; - union { - u32 pci_src_addr; - u32 pci_dest_addr; - u32 src_addr; - }; - union { - u32 upper_pci_src_addr; - u32 upper_pci_dest_addr; - }; - union { - u32 local_pci_src_addr; - u32 local_pci_dest_addr; - u32 dest_addr; - }; - u32 byte_count; - union { - u32 desc_ctrl; - struct iop3xx_dma_desc_ctrl desc_ctrl_field; - }; - u32 crc_addr; -}; - -struct iop3xx_desc_aau { - u32 next_desc; - u32 src[4]; - u32 dest_addr; - u32 byte_count; - union { - u32 desc_ctrl; - struct iop3xx_aau_desc_ctrl desc_ctrl_field; - }; - union { - u32 src_addr; - u32 e_desc_ctrl; - struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field; - } src_edc[31]; -}; - -struct iop3xx_aau_gfmr { - unsigned int gfmr1:8; - unsigned int gfmr2:8; - unsigned int gfmr3:8; - unsigned int gfmr4:8; -}; - -struct iop3xx_desc_pq_xor { - u32 next_desc; - u32 src[3]; - union { - u32 data_mult1; - struct iop3xx_aau_gfmr data_mult1_field; - }; - u32 dest_addr; - u32 byte_count; - union { - u32 desc_ctrl; - struct iop3xx_aau_desc_ctrl desc_ctrl_field; - }; - union { - u32 src_addr; - u32 e_desc_ctrl; - struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field; - u32 data_multiplier; - struct iop3xx_aau_gfmr data_mult_field; - u32 reserved; - } src_edc_gfmr[19]; -}; - -struct iop3xx_desc_dual_xor { - u32 next_desc; - u32 src0_addr; - u32 src1_addr; - u32 h_src_addr; - u32 d_src_addr; - u32 h_dest_addr; - u32 byte_count; - union { - u32 desc_ctrl; - struct iop3xx_aau_desc_ctrl desc_ctrl_field; - }; - u32 d_dest_addr; -}; - -union iop3xx_desc { - struct iop3xx_desc_aau *aau; - struct iop3xx_desc_dma *dma; - struct iop3xx_desc_pq_xor *pq_xor; - struct iop3xx_desc_dual_xor *dual_xor; - void *ptr; -}; - -/* No support for p+q operations */ -static inline int -iop_chan_pq_slot_count(size_t len, int src_cnt, int *slots_per_op) -{ - BUG(); - return 0; -} - -static inline void -iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - BUG(); -} - -static inline void -iop_desc_set_pq_addr(struct iop_adma_desc_slot *desc, dma_addr_t *addr) -{ - BUG(); -} - -static inline void -iop_desc_set_pq_src_addr(struct iop_adma_desc_slot *desc, int src_idx, - dma_addr_t addr, unsigned char coef) -{ - BUG(); -} - -static inline int -iop_chan_pq_zero_sum_slot_count(size_t len, int src_cnt, int *slots_per_op) -{ - BUG(); - return 0; -} - -static inline void -iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - BUG(); -} - -static inline void -iop_desc_set_pq_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) -{ - BUG(); -} - -#define iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr - -static inline void -iop_desc_set_pq_zero_sum_addr(struct iop_adma_desc_slot *desc, int pq_idx, - dma_addr_t *src) -{ - BUG(); -} - -static inline int iop_adma_get_max_xor(void) -{ - return 32; -} - -static inline int iop_adma_get_max_pq(void) -{ - BUG(); - return 0; -} - -static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) -{ - int id = chan->device->id; - - switch (id) { - case DMA0_ID: - case DMA1_ID: - return __raw_readl(DMA_DAR(chan)); - case AAU_ID: - return __raw_readl(AAU_ADAR(chan)); - default: - BUG(); - } - return 0; -} - -static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan, - u32 next_desc_addr) -{ - int id = chan->device->id; - - switch (id) { - case DMA0_ID: - case DMA1_ID: - __raw_writel(next_desc_addr, DMA_NDAR(chan)); - break; - case AAU_ID: - __raw_writel(next_desc_addr, AAU_ANDAR(chan)); - break; - } - -} - -#define IOP_ADMA_STATUS_BUSY (1 << 10) -#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT (1024) -#define IOP_ADMA_XOR_MAX_BYTE_COUNT (16 * 1024 * 1024) -#define IOP_ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) - -static inline int iop_chan_is_busy(struct iop_adma_chan *chan) -{ - u32 status = __raw_readl(DMA_CSR(chan)); - return (status & IOP_ADMA_STATUS_BUSY) ? 1 : 0; -} - -static inline int iop_desc_is_aligned(struct iop_adma_desc_slot *desc, - int num_slots) -{ - /* num_slots will only ever be 1, 2, 4, or 8 */ - return (desc->idx & (num_slots - 1)) ? 0 : 1; -} - -/* to do: support large (i.e. > hw max) buffer sizes */ -static inline int iop_chan_memcpy_slot_count(size_t len, int *slots_per_op) -{ - *slots_per_op = 1; - return 1; -} - -/* to do: support large (i.e. > hw max) buffer sizes */ -static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op) -{ - *slots_per_op = 1; - return 1; -} - -static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt, - int *slots_per_op) -{ - static const char slot_count_table[] = { - 1, 1, 1, 1, /* 01 - 04 */ - 2, 2, 2, 2, /* 05 - 08 */ - 4, 4, 4, 4, /* 09 - 12 */ - 4, 4, 4, 4, /* 13 - 16 */ - 8, 8, 8, 8, /* 17 - 20 */ - 8, 8, 8, 8, /* 21 - 24 */ - 8, 8, 8, 8, /* 25 - 28 */ - 8, 8, 8, 8, /* 29 - 32 */ - }; - *slots_per_op = slot_count_table[src_cnt - 1]; - return *slots_per_op; -} - -static inline int -iop_chan_interrupt_slot_count(int *slots_per_op, struct iop_adma_chan *chan) -{ - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - return iop_chan_memcpy_slot_count(0, slots_per_op); - case AAU_ID: - return iop3xx_aau_xor_slot_count(0, 2, slots_per_op); - default: - BUG(); - } - return 0; -} - -static inline int iop_chan_xor_slot_count(size_t len, int src_cnt, - int *slots_per_op) -{ - int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op); - - if (len <= IOP_ADMA_XOR_MAX_BYTE_COUNT) - return slot_cnt; - - len -= IOP_ADMA_XOR_MAX_BYTE_COUNT; - while (len > IOP_ADMA_XOR_MAX_BYTE_COUNT) { - len -= IOP_ADMA_XOR_MAX_BYTE_COUNT; - slot_cnt += *slots_per_op; - } - - slot_cnt += *slots_per_op; - - return slot_cnt; -} - -/* zero sum on iop3xx is limited to 1k at a time so it requires multiple - * descriptors - */ -static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt, - int *slots_per_op) -{ - int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op); - - if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) - return slot_cnt; - - len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; - while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { - len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; - slot_cnt += *slots_per_op; - } - - slot_cnt += *slots_per_op; - - return slot_cnt; -} - -static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan) -{ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - return hw_desc.dma->byte_count; - case AAU_ID: - return hw_desc.aau->byte_count; - default: - BUG(); - } - return 0; -} - -/* translate the src_idx to a descriptor word index */ -static inline int __desc_idx(int src_idx) -{ - static const int desc_idx_table[] = { 0, 0, 0, 0, - 0, 1, 2, 3, - 5, 6, 7, 8, - 9, 10, 11, 12, - 14, 15, 16, 17, - 18, 19, 20, 21, - 23, 24, 25, 26, - 27, 28, 29, 30, - }; - - return desc_idx_table[src_idx]; -} - -static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan, - int src_idx) -{ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - return hw_desc.dma->src_addr; - case AAU_ID: - break; - default: - BUG(); - } - - if (src_idx < 4) - return hw_desc.aau->src[src_idx]; - else - return hw_desc.aau->src_edc[__desc_idx(src_idx)].src_addr; -} - -static inline void iop3xx_aau_desc_set_src_addr(struct iop3xx_desc_aau *hw_desc, - int src_idx, dma_addr_t addr) -{ - if (src_idx < 4) - hw_desc->src[src_idx] = addr; - else - hw_desc->src_edc[__desc_idx(src_idx)].src_addr = addr; -} - -static inline void -iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags) -{ - struct iop3xx_desc_dma *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop3xx_dma_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - u_desc_ctrl.field.mem_to_mem_en = 1; - u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */ - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; - hw_desc->upper_pci_src_addr = 0; - hw_desc->crc_addr = 0; -} - -static inline void -iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags) -{ - struct iop3xx_desc_aau *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop3xx_aau_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */ - u_desc_ctrl.field.dest_write_en = 1; - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; -} - -static inline u32 -iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, - unsigned long flags) -{ - int i, shift; - u32 edcr; - union { - u32 value; - struct iop3xx_aau_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - switch (src_cnt) { - case 25 ... 32: - u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ - edcr = 0; - shift = 1; - for (i = 24; i < src_cnt; i++) { - edcr |= (1 << shift); - shift += 3; - } - hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr; - src_cnt = 24; - /* fall through */ - case 17 ... 24: - if (!u_desc_ctrl.field.blk_ctrl) { - hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; - u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ - } - edcr = 0; - shift = 1; - for (i = 16; i < src_cnt; i++) { - edcr |= (1 << shift); - shift += 3; - } - hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr; - src_cnt = 16; - /* fall through */ - case 9 ... 16: - if (!u_desc_ctrl.field.blk_ctrl) - u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */ - edcr = 0; - shift = 1; - for (i = 8; i < src_cnt; i++) { - edcr |= (1 << shift); - shift += 3; - } - hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr; - src_cnt = 8; - /* fall through */ - case 2 ... 8: - shift = 1; - for (i = 0; i < src_cnt; i++) { - u_desc_ctrl.value |= (1 << shift); - shift += 3; - } - - if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4) - u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */ - } - - u_desc_ctrl.field.dest_write_en = 1; - u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */ - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; - - return u_desc_ctrl.value; -} - -static inline void -iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - iop3xx_desc_init_xor(desc->hw_desc, src_cnt, flags); -} - -/* return the number of operations */ -static inline int -iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; - struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter; - union { - u32 value; - struct iop3xx_aau_desc_ctrl field; - } u_desc_ctrl; - int i, j; - - hw_desc = desc->hw_desc; - - for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0; - i += slots_per_op, j++) { - iter = iop_hw_desc_slot_idx(hw_desc, i); - u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, flags); - u_desc_ctrl.field.dest_write_en = 0; - u_desc_ctrl.field.zero_result_en = 1; - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - iter->desc_ctrl = u_desc_ctrl.value; - - /* for the subsequent descriptors preserve the store queue - * and chain them together - */ - if (i) { - prev_hw_desc = - iop_hw_desc_slot_idx(hw_desc, i - slots_per_op); - prev_hw_desc->next_desc = - (u32) (desc->async_tx.phys + (i << 5)); - } - } - - return j; -} - -static inline void -iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - struct iop3xx_desc_aau *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop3xx_aau_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - switch (src_cnt) { - case 25 ... 32: - u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ - hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; - /* fall through */ - case 17 ... 24: - if (!u_desc_ctrl.field.blk_ctrl) { - hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; - u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ - } - hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0; - /* fall through */ - case 9 ... 16: - if (!u_desc_ctrl.field.blk_ctrl) - u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */ - hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0; - /* fall through */ - case 1 ... 8: - if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4) - u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */ - } - - u_desc_ctrl.field.dest_write_en = 0; - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; -} - -static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan, - u32 byte_count) -{ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - hw_desc.dma->byte_count = byte_count; - break; - case AAU_ID: - hw_desc.aau->byte_count = byte_count; - break; - default: - BUG(); - } -} - -static inline void -iop_desc_init_interrupt(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan) -{ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - iop_desc_init_memcpy(desc, 1); - hw_desc.dma->byte_count = 0; - hw_desc.dma->dest_addr = 0; - hw_desc.dma->src_addr = 0; - break; - case AAU_ID: - iop_desc_init_null_xor(desc, 2, 1); - hw_desc.aau->byte_count = 0; - hw_desc.aau->dest_addr = 0; - hw_desc.aau->src[0] = 0; - hw_desc.aau->src[1] = 0; - break; - default: - BUG(); - } -} - -static inline void -iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) -{ - int slots_per_op = desc->slots_per_op; - struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; - int i = 0; - - if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { - hw_desc->byte_count = len; - } else { - do { - iter = iop_hw_desc_slot_idx(hw_desc, i); - iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; - len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; - i += slots_per_op; - } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT); - - iter = iop_hw_desc_slot_idx(hw_desc, i); - iter->byte_count = len; - } -} - -static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan, - dma_addr_t addr) -{ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - hw_desc.dma->dest_addr = addr; - break; - case AAU_ID: - hw_desc.aau->dest_addr = addr; - break; - default: - BUG(); - } -} - -static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc, - dma_addr_t addr) -{ - struct iop3xx_desc_dma *hw_desc = desc->hw_desc; - hw_desc->src_addr = addr; -} - -static inline void -iop_desc_set_zero_sum_src_addr(struct iop_adma_desc_slot *desc, int src_idx, - dma_addr_t addr) -{ - - struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; - int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; - int i; - - for (i = 0; (slot_cnt -= slots_per_op) >= 0; - i += slots_per_op, addr += IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { - iter = iop_hw_desc_slot_idx(hw_desc, i); - iop3xx_aau_desc_set_src_addr(iter, src_idx, addr); - } -} - -static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc, - int src_idx, dma_addr_t addr) -{ - - struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; - int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; - int i; - - for (i = 0; (slot_cnt -= slots_per_op) >= 0; - i += slots_per_op, addr += IOP_ADMA_XOR_MAX_BYTE_COUNT) { - iter = iop_hw_desc_slot_idx(hw_desc, i); - iop3xx_aau_desc_set_src_addr(iter, src_idx, addr); - } -} - -static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, - u32 next_desc_addr) -{ - /* hw_desc->next_desc is the same location for all channels */ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - - iop_paranoia(hw_desc.dma->next_desc); - hw_desc.dma->next_desc = next_desc_addr; -} - -static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc) -{ - /* hw_desc->next_desc is the same location for all channels */ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - return hw_desc.dma->next_desc; -} - -static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc) -{ - /* hw_desc->next_desc is the same location for all channels */ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - hw_desc.dma->next_desc = 0; -} - -static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, - u32 val) -{ - struct iop3xx_desc_aau *hw_desc = desc->hw_desc; - hw_desc->src[0] = val; -} - -static inline enum sum_check_flags -iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) -{ - struct iop3xx_desc_aau *hw_desc = desc->hw_desc; - struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; - - iop_paranoia(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en)); - return desc_ctrl.zero_result_err << SUM_CHECK_P; -} - -static inline void iop_chan_append(struct iop_adma_chan *chan) -{ - u32 dma_chan_ctrl; - - dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); - dma_chan_ctrl |= 0x2; - __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); -} - -static inline u32 iop_chan_get_status(struct iop_adma_chan *chan) -{ - return __raw_readl(DMA_CSR(chan)); -} - -static inline void iop_chan_disable(struct iop_adma_chan *chan) -{ - u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); - dma_chan_ctrl &= ~1; - __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); -} - -static inline void iop_chan_enable(struct iop_adma_chan *chan) -{ - u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); - - dma_chan_ctrl |= 1; - __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); -} - -static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan) -{ - u32 status = __raw_readl(DMA_CSR(chan)); - status &= (1 << 9); - __raw_writel(status, DMA_CSR(chan)); -} - -static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan) -{ - u32 status = __raw_readl(DMA_CSR(chan)); - status &= (1 << 8); - __raw_writel(status, DMA_CSR(chan)); -} - -static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan) -{ - u32 status = __raw_readl(DMA_CSR(chan)); - - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - status &= (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1); - break; - case AAU_ID: - status &= (1 << 5); - break; - default: - BUG(); - } - - __raw_writel(status, DMA_CSR(chan)); -} - -static inline int -iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan) -{ - return 0; -} - -static inline int -iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan) -{ - return 0; -} - -static inline int -iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan) -{ - return 0; -} - -static inline int -iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan) -{ - return test_bit(5, &status); -} - -static inline int -iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan) -{ - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - return test_bit(2, &status); - default: - return 0; - } -} - -static inline int -iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan) -{ - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - return test_bit(3, &status); - default: - return 0; - } -} - -static inline int -iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan) -{ - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - return test_bit(1, &status); - default: - return 0; - } -} -#endif /* _ADMA_H */ diff --git a/arch/arm/include/asm/hardware/iop_adma.h b/arch/arm/include/asm/hardware/iop_adma.h deleted file mode 100644 index bcedbab90ac0..000000000000 --- a/arch/arm/include/asm/hardware/iop_adma.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright © 2006, Intel Corporation. - */ -#ifndef IOP_ADMA_H -#define IOP_ADMA_H -#include -#include -#include - -#define IOP_ADMA_SLOT_SIZE 32 -#define IOP_ADMA_THRESHOLD 4 -#ifdef DEBUG -#define IOP_PARANOIA 1 -#else -#define IOP_PARANOIA 0 -#endif -#define iop_paranoia(x) BUG_ON(IOP_PARANOIA && (x)) - -/** - * struct iop_adma_device - internal representation of an ADMA device - * @pdev: Platform device - * @id: HW ADMA Device selector - * @dma_desc_pool: base of DMA descriptor region (DMA address) - * @dma_desc_pool_virt: base of DMA descriptor region (CPU address) - * @common: embedded struct dma_device - */ -struct iop_adma_device { - struct platform_device *pdev; - int id; - dma_addr_t dma_desc_pool; - void *dma_desc_pool_virt; - struct dma_device common; -}; - -/** - * struct iop_adma_chan - internal representation of an ADMA device - * @pending: allows batching of hardware operations - * @lock: serializes enqueue/dequeue operations to the slot pool - * @mmr_base: memory mapped register base - * @chain: device chain view of the descriptors - * @device: parent device - * @common: common dmaengine channel object members - * @last_used: place holder for allocation to continue from where it left off - * @all_slots: complete domain of slots usable by the channel - * @slots_allocated: records the actual size of the descriptor slot pool - * @irq_tasklet: bottom half where iop_adma_slot_cleanup runs - */ -struct iop_adma_chan { - int pending; - spinlock_t lock; /* protects the descriptor slot pool */ - void __iomem *mmr_base; - struct list_head chain; - struct iop_adma_device *device; - struct dma_chan common; - struct iop_adma_desc_slot *last_used; - struct list_head all_slots; - int slots_allocated; - struct tasklet_struct irq_tasklet; -}; - -/** - * struct iop_adma_desc_slot - IOP-ADMA software descriptor - * @slot_node: node on the iop_adma_chan.all_slots list - * @chain_node: node on the op_adma_chan.chain list - * @hw_desc: virtual address of the hardware descriptor chain - * @phys: hardware address of the hardware descriptor chain - * @group_head: first operation in a transaction - * @slot_cnt: total slots used in an transaction (group of operations) - * @slots_per_op: number of slots per operation - * @idx: pool index - * @tx_list: list of descriptors that are associated with one operation - * @async_tx: support for the async_tx api - * @group_list: list of slots that make up a multi-descriptor transaction - * for example transfer lengths larger than the supported hw max - * @xor_check_result: result of zero sum - * @crc32_result: result crc calculation - */ -struct iop_adma_desc_slot { - struct list_head slot_node; - struct list_head chain_node; - void *hw_desc; - struct iop_adma_desc_slot *group_head; - u16 slot_cnt; - u16 slots_per_op; - u16 idx; - struct list_head tx_list; - struct dma_async_tx_descriptor async_tx; - union { - u32 *xor_check_result; - u32 *crc32_result; - u32 *pq_check_result; - }; -}; - -struct iop_adma_platform_data { - int hw_id; - dma_cap_mask_t cap_mask; - size_t pool_size; -}; - -#define to_iop_sw_desc(addr_hw_desc) \ - container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc) -#define iop_hw_desc_slot_idx(hw_desc, idx) \ - ( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) ) -#endif diff --git a/arch/arm/mach-iop32x/include/mach/adma.h b/arch/arm/mach-iop32x/include/mach/adma.h deleted file mode 100644 index 2b20063123ad..000000000000 --- a/arch/arm/mach-iop32x/include/mach/adma.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef IOP32X_ADMA_H -#define IOP32X_ADMA_H -#include -#endif - diff --git a/arch/arm/plat-iop/adma.c b/arch/arm/plat-iop/adma.c index 368496471e60..601cc9c11b07 100644 --- a/arch/arm/plat-iop/adma.c +++ b/arch/arm/plat-iop/adma.c @@ -6,8 +6,7 @@ #include #include #include -#include -#include +#include #define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT #define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index cc84863bc52b..7c511e3db4c8 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -294,8 +294,8 @@ config INTEL_IOATDMA If unsure, say N. config INTEL_IOP_ADMA - tristate "Intel IOP ADMA support" - depends on ARCH_IOP32X + tristate "Intel IOP32x ADMA support" + depends on ARCH_IOP32X || COMPILE_TEST select DMA_ENGINE select ASYNC_TX_ENABLE_CHANNEL_SWITCH help diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c index aebdd671651a..03f4a588cf7f 100644 --- a/drivers/dma/iop-adma.c +++ b/drivers/dma/iop-adma.c @@ -22,8 +22,7 @@ #include #include -#include - +#include "iop-adma.h" #include "dmaengine.h" #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common) diff --git a/drivers/dma/iop-adma.h b/drivers/dma/iop-adma.h new file mode 100644 index 000000000000..c499c9578f00 --- /dev/null +++ b/drivers/dma/iop-adma.h @@ -0,0 +1,914 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright © 2006, Intel Corporation. + */ +#ifndef _ADMA_H +#define _ADMA_H +#include +#include +#include + +/* Memory copy units */ +#define DMA_CCR(chan) (chan->mmr_base + 0x0) +#define DMA_CSR(chan) (chan->mmr_base + 0x4) +#define DMA_DAR(chan) (chan->mmr_base + 0xc) +#define DMA_NDAR(chan) (chan->mmr_base + 0x10) +#define DMA_PADR(chan) (chan->mmr_base + 0x14) +#define DMA_PUADR(chan) (chan->mmr_base + 0x18) +#define DMA_LADR(chan) (chan->mmr_base + 0x1c) +#define DMA_BCR(chan) (chan->mmr_base + 0x20) +#define DMA_DCR(chan) (chan->mmr_base + 0x24) + +/* Application accelerator unit */ +#define AAU_ACR(chan) (chan->mmr_base + 0x0) +#define AAU_ASR(chan) (chan->mmr_base + 0x4) +#define AAU_ADAR(chan) (chan->mmr_base + 0x8) +#define AAU_ANDAR(chan) (chan->mmr_base + 0xc) +#define AAU_SAR(src, chan) (chan->mmr_base + (0x10 + ((src) << 2))) +#define AAU_DAR(chan) (chan->mmr_base + 0x20) +#define AAU_ABCR(chan) (chan->mmr_base + 0x24) +#define AAU_ADCR(chan) (chan->mmr_base + 0x28) +#define AAU_SAR_EDCR(src_edc) (chan->mmr_base + (0x02c + ((src_edc-4) << 2))) +#define AAU_EDCR0_IDX 8 +#define AAU_EDCR1_IDX 17 +#define AAU_EDCR2_IDX 26 + +struct iop3xx_aau_desc_ctrl { + unsigned int int_en:1; + unsigned int blk1_cmd_ctrl:3; + unsigned int blk2_cmd_ctrl:3; + unsigned int blk3_cmd_ctrl:3; + unsigned int blk4_cmd_ctrl:3; + unsigned int blk5_cmd_ctrl:3; + unsigned int blk6_cmd_ctrl:3; + unsigned int blk7_cmd_ctrl:3; + unsigned int blk8_cmd_ctrl:3; + unsigned int blk_ctrl:2; + unsigned int dual_xor_en:1; + unsigned int tx_complete:1; + unsigned int zero_result_err:1; + unsigned int zero_result_en:1; + unsigned int dest_write_en:1; +}; + +struct iop3xx_aau_e_desc_ctrl { + unsigned int reserved:1; + unsigned int blk1_cmd_ctrl:3; + unsigned int blk2_cmd_ctrl:3; + unsigned int blk3_cmd_ctrl:3; + unsigned int blk4_cmd_ctrl:3; + unsigned int blk5_cmd_ctrl:3; + unsigned int blk6_cmd_ctrl:3; + unsigned int blk7_cmd_ctrl:3; + unsigned int blk8_cmd_ctrl:3; + unsigned int reserved2:7; +}; + +struct iop3xx_dma_desc_ctrl { + unsigned int pci_transaction:4; + unsigned int int_en:1; + unsigned int dac_cycle_en:1; + unsigned int mem_to_mem_en:1; + unsigned int crc_data_tx_en:1; + unsigned int crc_gen_en:1; + unsigned int crc_seed_dis:1; + unsigned int reserved:21; + unsigned int crc_tx_complete:1; +}; + +struct iop3xx_desc_dma { + u32 next_desc; + union { + u32 pci_src_addr; + u32 pci_dest_addr; + u32 src_addr; + }; + union { + u32 upper_pci_src_addr; + u32 upper_pci_dest_addr; + }; + union { + u32 local_pci_src_addr; + u32 local_pci_dest_addr; + u32 dest_addr; + }; + u32 byte_count; + union { + u32 desc_ctrl; + struct iop3xx_dma_desc_ctrl desc_ctrl_field; + }; + u32 crc_addr; +}; + +struct iop3xx_desc_aau { + u32 next_desc; + u32 src[4]; + u32 dest_addr; + u32 byte_count; + union { + u32 desc_ctrl; + struct iop3xx_aau_desc_ctrl desc_ctrl_field; + }; + union { + u32 src_addr; + u32 e_desc_ctrl; + struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field; + } src_edc[31]; +}; + +struct iop3xx_aau_gfmr { + unsigned int gfmr1:8; + unsigned int gfmr2:8; + unsigned int gfmr3:8; + unsigned int gfmr4:8; +}; + +struct iop3xx_desc_pq_xor { + u32 next_desc; + u32 src[3]; + union { + u32 data_mult1; + struct iop3xx_aau_gfmr data_mult1_field; + }; + u32 dest_addr; + u32 byte_count; + union { + u32 desc_ctrl; + struct iop3xx_aau_desc_ctrl desc_ctrl_field; + }; + union { + u32 src_addr; + u32 e_desc_ctrl; + struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field; + u32 data_multiplier; + struct iop3xx_aau_gfmr data_mult_field; + u32 reserved; + } src_edc_gfmr[19]; +}; + +struct iop3xx_desc_dual_xor { + u32 next_desc; + u32 src0_addr; + u32 src1_addr; + u32 h_src_addr; + u32 d_src_addr; + u32 h_dest_addr; + u32 byte_count; + union { + u32 desc_ctrl; + struct iop3xx_aau_desc_ctrl desc_ctrl_field; + }; + u32 d_dest_addr; +}; + +union iop3xx_desc { + struct iop3xx_desc_aau *aau; + struct iop3xx_desc_dma *dma; + struct iop3xx_desc_pq_xor *pq_xor; + struct iop3xx_desc_dual_xor *dual_xor; + void *ptr; +}; + +/* No support for p+q operations */ +static inline int +iop_chan_pq_slot_count(size_t len, int src_cnt, int *slots_per_op) +{ + BUG(); + return 0; +} + +static inline void +iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) +{ + BUG(); +} + +static inline void +iop_desc_set_pq_addr(struct iop_adma_desc_slot *desc, dma_addr_t *addr) +{ + BUG(); +} + +static inline void +iop_desc_set_pq_src_addr(struct iop_adma_desc_slot *desc, int src_idx, + dma_addr_t addr, unsigned char coef) +{ + BUG(); +} + +static inline int +iop_chan_pq_zero_sum_slot_count(size_t len, int src_cnt, int *slots_per_op) +{ + BUG(); + return 0; +} + +static inline void +iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) +{ + BUG(); +} + +static inline void +iop_desc_set_pq_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) +{ + BUG(); +} + +#define iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr + +static inline void +iop_desc_set_pq_zero_sum_addr(struct iop_adma_desc_slot *desc, int pq_idx, + dma_addr_t *src) +{ + BUG(); +} + +static inline int iop_adma_get_max_xor(void) +{ + return 32; +} + +static inline int iop_adma_get_max_pq(void) +{ + BUG(); + return 0; +} + +static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) +{ + int id = chan->device->id; + + switch (id) { + case DMA0_ID: + case DMA1_ID: + return __raw_readl(DMA_DAR(chan)); + case AAU_ID: + return __raw_readl(AAU_ADAR(chan)); + default: + BUG(); + } + return 0; +} + +static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan, + u32 next_desc_addr) +{ + int id = chan->device->id; + + switch (id) { + case DMA0_ID: + case DMA1_ID: + __raw_writel(next_desc_addr, DMA_NDAR(chan)); + break; + case AAU_ID: + __raw_writel(next_desc_addr, AAU_ANDAR(chan)); + break; + } + +} + +#define IOP_ADMA_STATUS_BUSY (1 << 10) +#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT (1024) +#define IOP_ADMA_XOR_MAX_BYTE_COUNT (16 * 1024 * 1024) +#define IOP_ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) + +static inline int iop_chan_is_busy(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(DMA_CSR(chan)); + return (status & IOP_ADMA_STATUS_BUSY) ? 1 : 0; +} + +static inline int iop_desc_is_aligned(struct iop_adma_desc_slot *desc, + int num_slots) +{ + /* num_slots will only ever be 1, 2, 4, or 8 */ + return (desc->idx & (num_slots - 1)) ? 0 : 1; +} + +/* to do: support large (i.e. > hw max) buffer sizes */ +static inline int iop_chan_memcpy_slot_count(size_t len, int *slots_per_op) +{ + *slots_per_op = 1; + return 1; +} + +/* to do: support large (i.e. > hw max) buffer sizes */ +static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op) +{ + *slots_per_op = 1; + return 1; +} + +static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt, + int *slots_per_op) +{ + static const char slot_count_table[] = { + 1, 1, 1, 1, /* 01 - 04 */ + 2, 2, 2, 2, /* 05 - 08 */ + 4, 4, 4, 4, /* 09 - 12 */ + 4, 4, 4, 4, /* 13 - 16 */ + 8, 8, 8, 8, /* 17 - 20 */ + 8, 8, 8, 8, /* 21 - 24 */ + 8, 8, 8, 8, /* 25 - 28 */ + 8, 8, 8, 8, /* 29 - 32 */ + }; + *slots_per_op = slot_count_table[src_cnt - 1]; + return *slots_per_op; +} + +static inline int +iop_chan_interrupt_slot_count(int *slots_per_op, struct iop_adma_chan *chan) +{ + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return iop_chan_memcpy_slot_count(0, slots_per_op); + case AAU_ID: + return iop3xx_aau_xor_slot_count(0, 2, slots_per_op); + default: + BUG(); + } + return 0; +} + +static inline int iop_chan_xor_slot_count(size_t len, int src_cnt, + int *slots_per_op) +{ + int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op); + + if (len <= IOP_ADMA_XOR_MAX_BYTE_COUNT) + return slot_cnt; + + len -= IOP_ADMA_XOR_MAX_BYTE_COUNT; + while (len > IOP_ADMA_XOR_MAX_BYTE_COUNT) { + len -= IOP_ADMA_XOR_MAX_BYTE_COUNT; + slot_cnt += *slots_per_op; + } + + slot_cnt += *slots_per_op; + + return slot_cnt; +} + +/* zero sum on iop3xx is limited to 1k at a time so it requires multiple + * descriptors + */ +static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt, + int *slots_per_op) +{ + int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op); + + if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) + return slot_cnt; + + len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { + len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + slot_cnt += *slots_per_op; + } + + slot_cnt += *slots_per_op; + + return slot_cnt; +} + +static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return hw_desc.dma->byte_count; + case AAU_ID: + return hw_desc.aau->byte_count; + default: + BUG(); + } + return 0; +} + +/* translate the src_idx to a descriptor word index */ +static inline int __desc_idx(int src_idx) +{ + static const int desc_idx_table[] = { 0, 0, 0, 0, + 0, 1, 2, 3, + 5, 6, 7, 8, + 9, 10, 11, 12, + 14, 15, 16, 17, + 18, 19, 20, 21, + 23, 24, 25, 26, + 27, 28, 29, 30, + }; + + return desc_idx_table[src_idx]; +} + +static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + int src_idx) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return hw_desc.dma->src_addr; + case AAU_ID: + break; + default: + BUG(); + } + + if (src_idx < 4) + return hw_desc.aau->src[src_idx]; + else + return hw_desc.aau->src_edc[__desc_idx(src_idx)].src_addr; +} + +static inline void iop3xx_aau_desc_set_src_addr(struct iop3xx_desc_aau *hw_desc, + int src_idx, dma_addr_t addr) +{ + if (src_idx < 4) + hw_desc->src[src_idx] = addr; + else + hw_desc->src_edc[__desc_idx(src_idx)].src_addr = addr; +} + +static inline void +iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags) +{ + struct iop3xx_desc_dma *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop3xx_dma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.mem_to_mem_en = 1; + u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */ + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->upper_pci_src_addr = 0; + hw_desc->crc_addr = 0; +} + +static inline void +iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags) +{ + struct iop3xx_desc_aau *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop3xx_aau_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */ + u_desc_ctrl.field.dest_write_en = 1; + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; + hw_desc->desc_ctrl = u_desc_ctrl.value; +} + +static inline u32 +iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, + unsigned long flags) +{ + int i, shift; + u32 edcr; + union { + u32 value; + struct iop3xx_aau_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + switch (src_cnt) { + case 25 ... 32: + u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ + edcr = 0; + shift = 1; + for (i = 24; i < src_cnt; i++) { + edcr |= (1 << shift); + shift += 3; + } + hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr; + src_cnt = 24; + /* fall through */ + case 17 ... 24: + if (!u_desc_ctrl.field.blk_ctrl) { + hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; + u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ + } + edcr = 0; + shift = 1; + for (i = 16; i < src_cnt; i++) { + edcr |= (1 << shift); + shift += 3; + } + hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr; + src_cnt = 16; + /* fall through */ + case 9 ... 16: + if (!u_desc_ctrl.field.blk_ctrl) + u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */ + edcr = 0; + shift = 1; + for (i = 8; i < src_cnt; i++) { + edcr |= (1 << shift); + shift += 3; + } + hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr; + src_cnt = 8; + /* fall through */ + case 2 ... 8: + shift = 1; + for (i = 0; i < src_cnt; i++) { + u_desc_ctrl.value |= (1 << shift); + shift += 3; + } + + if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4) + u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */ + } + + u_desc_ctrl.field.dest_write_en = 1; + u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */ + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; + hw_desc->desc_ctrl = u_desc_ctrl.value; + + return u_desc_ctrl.value; +} + +static inline void +iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) +{ + iop3xx_desc_init_xor(desc->hw_desc, src_cnt, flags); +} + +/* return the number of operations */ +static inline int +iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) +{ + int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; + struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter; + union { + u32 value; + struct iop3xx_aau_desc_ctrl field; + } u_desc_ctrl; + int i, j; + + hw_desc = desc->hw_desc; + + for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0; + i += slots_per_op, j++) { + iter = iop_hw_desc_slot_idx(hw_desc, i); + u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, flags); + u_desc_ctrl.field.dest_write_en = 0; + u_desc_ctrl.field.zero_result_en = 1; + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; + iter->desc_ctrl = u_desc_ctrl.value; + + /* for the subsequent descriptors preserve the store queue + * and chain them together + */ + if (i) { + prev_hw_desc = + iop_hw_desc_slot_idx(hw_desc, i - slots_per_op); + prev_hw_desc->next_desc = + (u32) (desc->async_tx.phys + (i << 5)); + } + } + + return j; +} + +static inline void +iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) +{ + struct iop3xx_desc_aau *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop3xx_aau_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + switch (src_cnt) { + case 25 ... 32: + u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ + hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; + /* fall through */ + case 17 ... 24: + if (!u_desc_ctrl.field.blk_ctrl) { + hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; + u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ + } + hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0; + /* fall through */ + case 9 ... 16: + if (!u_desc_ctrl.field.blk_ctrl) + u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */ + hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0; + /* fall through */ + case 1 ... 8: + if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4) + u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */ + } + + u_desc_ctrl.field.dest_write_en = 0; + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; + hw_desc->desc_ctrl = u_desc_ctrl.value; +} + +static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + u32 byte_count) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + hw_desc.dma->byte_count = byte_count; + break; + case AAU_ID: + hw_desc.aau->byte_count = byte_count; + break; + default: + BUG(); + } +} + +static inline void +iop_desc_init_interrupt(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + iop_desc_init_memcpy(desc, 1); + hw_desc.dma->byte_count = 0; + hw_desc.dma->dest_addr = 0; + hw_desc.dma->src_addr = 0; + break; + case AAU_ID: + iop_desc_init_null_xor(desc, 2, 1); + hw_desc.aau->byte_count = 0; + hw_desc.aau->dest_addr = 0; + hw_desc.aau->src[0] = 0; + hw_desc.aau->src[1] = 0; + break; + default: + BUG(); + } +} + +static inline void +iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) +{ + int slots_per_op = desc->slots_per_op; + struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; + int i = 0; + + if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { + hw_desc->byte_count = len; + } else { + do { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + i += slots_per_op; + } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT); + + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->byte_count = len; + } +} + +static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + dma_addr_t addr) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + hw_desc.dma->dest_addr = addr; + break; + case AAU_ID: + hw_desc.aau->dest_addr = addr; + break; + default: + BUG(); + } +} + +static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc, + dma_addr_t addr) +{ + struct iop3xx_desc_dma *hw_desc = desc->hw_desc; + hw_desc->src_addr = addr; +} + +static inline void +iop_desc_set_zero_sum_src_addr(struct iop_adma_desc_slot *desc, int src_idx, + dma_addr_t addr) +{ + + struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; + int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; + int i; + + for (i = 0; (slot_cnt -= slots_per_op) >= 0; + i += slots_per_op, addr += IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iop3xx_aau_desc_set_src_addr(iter, src_idx, addr); + } +} + +static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc, + int src_idx, dma_addr_t addr) +{ + + struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; + int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; + int i; + + for (i = 0; (slot_cnt -= slots_per_op) >= 0; + i += slots_per_op, addr += IOP_ADMA_XOR_MAX_BYTE_COUNT) { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iop3xx_aau_desc_set_src_addr(iter, src_idx, addr); + } +} + +static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, + u32 next_desc_addr) +{ + /* hw_desc->next_desc is the same location for all channels */ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + iop_paranoia(hw_desc.dma->next_desc); + hw_desc.dma->next_desc = next_desc_addr; +} + +static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc) +{ + /* hw_desc->next_desc is the same location for all channels */ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + return hw_desc.dma->next_desc; +} + +static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc) +{ + /* hw_desc->next_desc is the same location for all channels */ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + hw_desc.dma->next_desc = 0; +} + +static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, + u32 val) +{ + struct iop3xx_desc_aau *hw_desc = desc->hw_desc; + hw_desc->src[0] = val; +} + +static inline enum sum_check_flags +iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) +{ + struct iop3xx_desc_aau *hw_desc = desc->hw_desc; + struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; + + iop_paranoia(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en)); + return desc_ctrl.zero_result_err << SUM_CHECK_P; +} + +static inline void iop_chan_append(struct iop_adma_chan *chan) +{ + u32 dma_chan_ctrl; + + dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); + dma_chan_ctrl |= 0x2; + __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); +} + +static inline u32 iop_chan_get_status(struct iop_adma_chan *chan) +{ + return __raw_readl(DMA_CSR(chan)); +} + +static inline void iop_chan_disable(struct iop_adma_chan *chan) +{ + u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); + dma_chan_ctrl &= ~1; + __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); +} + +static inline void iop_chan_enable(struct iop_adma_chan *chan) +{ + u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); + + dma_chan_ctrl |= 1; + __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); +} + +static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(DMA_CSR(chan)); + status &= (1 << 9); + __raw_writel(status, DMA_CSR(chan)); +} + +static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(DMA_CSR(chan)); + status &= (1 << 8); + __raw_writel(status, DMA_CSR(chan)); +} + +static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(DMA_CSR(chan)); + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + status &= (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1); + break; + case AAU_ID: + status &= (1 << 5); + break; + default: + BUG(); + } + + __raw_writel(status, DMA_CSR(chan)); +} + +static inline int +iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(5, &status); +} + +static inline int +iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan) +{ + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return test_bit(2, &status); + default: + return 0; + } +} + +static inline int +iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan) +{ + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return test_bit(3, &status); + default: + return 0; + } +} + +static inline int +iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan) +{ + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return test_bit(1, &status); + default: + return 0; + } +} +#endif /* _ADMA_H */ diff --git a/include/linux/platform_data/dma-iop32x.h b/include/linux/platform_data/dma-iop32x.h new file mode 100644 index 000000000000..ac83cff89549 --- /dev/null +++ b/include/linux/platform_data/dma-iop32x.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright © 2006, Intel Corporation. + */ +#ifndef IOP_ADMA_H +#define IOP_ADMA_H +#include +#include +#include + +#define IOP_ADMA_SLOT_SIZE 32 +#define IOP_ADMA_THRESHOLD 4 +#ifdef DEBUG +#define IOP_PARANOIA 1 +#else +#define IOP_PARANOIA 0 +#endif +#define iop_paranoia(x) BUG_ON(IOP_PARANOIA && (x)) + +#define DMA0_ID 0 +#define DMA1_ID 1 +#define AAU_ID 2 + +/** + * struct iop_adma_device - internal representation of an ADMA device + * @pdev: Platform device + * @id: HW ADMA Device selector + * @dma_desc_pool: base of DMA descriptor region (DMA address) + * @dma_desc_pool_virt: base of DMA descriptor region (CPU address) + * @common: embedded struct dma_device + */ +struct iop_adma_device { + struct platform_device *pdev; + int id; + dma_addr_t dma_desc_pool; + void *dma_desc_pool_virt; + struct dma_device common; +}; + +/** + * struct iop_adma_chan - internal representation of an ADMA device + * @pending: allows batching of hardware operations + * @lock: serializes enqueue/dequeue operations to the slot pool + * @mmr_base: memory mapped register base + * @chain: device chain view of the descriptors + * @device: parent device + * @common: common dmaengine channel object members + * @last_used: place holder for allocation to continue from where it left off + * @all_slots: complete domain of slots usable by the channel + * @slots_allocated: records the actual size of the descriptor slot pool + * @irq_tasklet: bottom half where iop_adma_slot_cleanup runs + */ +struct iop_adma_chan { + int pending; + spinlock_t lock; /* protects the descriptor slot pool */ + void __iomem *mmr_base; + struct list_head chain; + struct iop_adma_device *device; + struct dma_chan common; + struct iop_adma_desc_slot *last_used; + struct list_head all_slots; + int slots_allocated; + struct tasklet_struct irq_tasklet; +}; + +/** + * struct iop_adma_desc_slot - IOP-ADMA software descriptor + * @slot_node: node on the iop_adma_chan.all_slots list + * @chain_node: node on the op_adma_chan.chain list + * @hw_desc: virtual address of the hardware descriptor chain + * @phys: hardware address of the hardware descriptor chain + * @group_head: first operation in a transaction + * @slot_cnt: total slots used in an transaction (group of operations) + * @slots_per_op: number of slots per operation + * @idx: pool index + * @tx_list: list of descriptors that are associated with one operation + * @async_tx: support for the async_tx api + * @group_list: list of slots that make up a multi-descriptor transaction + * for example transfer lengths larger than the supported hw max + * @xor_check_result: result of zero sum + * @crc32_result: result crc calculation + */ +struct iop_adma_desc_slot { + struct list_head slot_node; + struct list_head chain_node; + void *hw_desc; + struct iop_adma_desc_slot *group_head; + u16 slot_cnt; + u16 slots_per_op; + u16 idx; + struct list_head tx_list; + struct dma_async_tx_descriptor async_tx; + union { + u32 *xor_check_result; + u32 *crc32_result; + u32 *pq_check_result; + }; +}; + +struct iop_adma_platform_data { + int hw_id; + dma_cap_mask_t cap_mask; + size_t pool_size; +}; + +#define to_iop_sw_desc(addr_hw_desc) \ + container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc) +#define iop_hw_desc_slot_idx(hw_desc, idx) \ + ( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) ) +#endif -- cgit v1.2.3-71-gd317 From d507a54f5865d8dcbdd16c66a1a2da15640878ca Mon Sep 17 00:00:00 2001 From: Kristian Klausen Date: Mon, 5 Aug 2019 21:23:05 +0200 Subject: platform/x86: asus-wmi: Add support for charge threshold Most newer ASUS laptops supports limiting the battery charge level, which help prolonging the battery life. Tested on a Zenbook UX430UNR. Signed-off-by: Kristian Klausen Signed-off-by: Andy Shevchenko --- drivers/platform/x86/asus-wmi.c | 48 ++++++++++++++++++++++++++++++ include/linux/platform_data/x86/asus-wmi.h | 1 + 2 files changed, 49 insertions(+) (limited to 'include/linux/platform_data') diff --git a/drivers/platform/x86/asus-wmi.c b/drivers/platform/x86/asus-wmi.c index 34dfbed65332..22ae350e0a96 100644 --- a/drivers/platform/x86/asus-wmi.c +++ b/drivers/platform/x86/asus-wmi.c @@ -195,6 +195,8 @@ struct asus_wmi { u8 fan_boost_mode_mask; u8 fan_boost_mode; + int charge_threshold; + struct hotplug_slot hotplug_slot; struct mutex hotplug_lock; struct mutex wmi_lock; @@ -2075,6 +2077,43 @@ static ssize_t cpufv_store(struct device *dev, struct device_attribute *attr, static DEVICE_ATTR_WO(cpufv); + +static ssize_t charge_threshold_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct asus_wmi *asus = dev_get_drvdata(dev); + int value, ret, rv; + + ret = kstrtouint(buf, 10, &value); + + if (!count || ret != 0) + return -EINVAL; + if (value < 0 || value > 100) + return -EINVAL; + + asus_wmi_set_devstate(ASUS_WMI_CHARGE_THRESHOLD, value, &rv); + + if (rv != 1) + return -EIO; + + /* There isn't any method in the DSDT to read the threshold, so we + * save the threshold. + */ + asus->charge_threshold = value; + return count; +} + +static ssize_t charge_threshold_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct asus_wmi *asus = dev_get_drvdata(dev); + + return sprintf(buf, "%d\n", asus->charge_threshold); +} + +static DEVICE_ATTR_RW(charge_threshold); + static struct attribute *platform_attributes[] = { &dev_attr_cpufv.attr, &dev_attr_camera.attr, @@ -2083,6 +2122,7 @@ static struct attribute *platform_attributes[] = { &dev_attr_lid_resume.attr, &dev_attr_als_enable.attr, &dev_attr_fan_boost_mode.attr, + &dev_attr_charge_threshold.attr, NULL }; @@ -2106,6 +2146,8 @@ static umode_t asus_sysfs_is_visible(struct kobject *kobj, devid = ASUS_WMI_DEVID_ALS_ENABLE; else if (attr == &dev_attr_fan_boost_mode.attr) ok = asus->fan_boost_mode_available; + else if (attr == &dev_attr_charge_threshold.attr) + devid = ASUS_WMI_CHARGE_THRESHOLD; if (devid != -1) ok = !(asus_wmi_get_devstate_simple(asus, devid) < 0); @@ -2434,6 +2476,12 @@ static int asus_wmi_add(struct platform_device *pdev) } asus_wmi_debugfs_init(asus); + /* The charge threshold is only reset when the system is power cycled, + * and we can't get the current threshold so let set it to 100% on + * module load. + */ + asus_wmi_set_devstate(ASUS_WMI_CHARGE_THRESHOLD, 100, NULL); + asus->charge_threshold = 100; return 0; diff --git a/include/linux/platform_data/x86/asus-wmi.h b/include/linux/platform_data/x86/asus-wmi.h index 409e16064f4b..53934ef38d98 100644 --- a/include/linux/platform_data/x86/asus-wmi.h +++ b/include/linux/platform_data/x86/asus-wmi.h @@ -61,6 +61,7 @@ /* Misc */ #define ASUS_WMI_DEVID_CAMERA 0x00060013 +#define ASUS_WMI_CHARGE_THRESHOLD 0x00120057 /* Storage */ #define ASUS_WMI_DEVID_CARDREADER 0x00080013 -- cgit v1.2.3-71-gd317 From d7f563db7794a6a271b6e9dd6e65a437d6a1d933 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 14 Aug 2019 05:18:16 -0700 Subject: bus: ti-sysc: Add module enable quirk for SGX on omap36xx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add module enable quirk for SGX needed on omap36xx. Cc: Adam Ford Cc: Filip Matijević Cc: "H. Nikolaus Schaller" Cc: Ivaylo Dimitrov Cc: moaz korena Cc: Merlijn Wajer Cc: Paweł Chmiel Cc: Philipp Rossak Cc: Tomi Valkeinen Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 21 +++++++++++++++++++++ include/linux/platform_data/ti-sysc.h | 1 + 2 files changed, 22 insertions(+) (limited to 'include/linux/platform_data') diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 2587a616cee7..d4fc04320ea5 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -73,6 +73,7 @@ static const char * const clock_names[SYSC_MAX_CLOCKS] = { * @clk_enable_quirk: module specific clock enable quirk * @clk_disable_quirk: module specific clock disable quirk * @reset_done_quirk: module specific reset done quirk + * @module_enable_quirk: module specific enable quirk */ struct sysc { struct device *dev; @@ -98,6 +99,7 @@ struct sysc { void (*clk_enable_quirk)(struct sysc *sysc); void (*clk_disable_quirk)(struct sysc *sysc); void (*reset_done_quirk)(struct sysc *sysc); + void (*module_enable_quirk)(struct sysc *sysc); }; static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, @@ -928,6 +930,9 @@ set_autoidle: sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); } + if (ddata->module_enable_quirk) + ddata->module_enable_quirk(ddata); + return 0; } @@ -1241,6 +1246,9 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { SYSC_MODULE_QUIRK_I2C), SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, SYSC_MODULE_QUIRK_I2C), + SYSC_QUIRK("gpu", 0x50000000, 0x14, -1, -1, 0x00010201, 0xffffffff, 0), + SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, + SYSC_MODULE_QUIRK_SGX), SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, SYSC_MODULE_QUIRK_WDT), @@ -1258,6 +1266,7 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0), SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0), SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0), + SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 0), SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0), SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0), @@ -1409,6 +1418,15 @@ static void sysc_clk_disable_quirk_i2c(struct sysc *ddata) sysc_clk_quirk_i2c(ddata, false); } +/* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */ +static void sysc_module_enable_quirk_sgx(struct sysc *ddata) +{ + int offset = 0xff08; /* OCP_DEBUG_CONFIG */ + u32 val = BIT(31); /* THALIA_INT_BYPASS */ + + sysc_write(ddata, offset, val); +} + /* Watchdog timer needs a disable sequence after reset */ static void sysc_reset_done_quirk_wdt(struct sysc *ddata) { @@ -1451,6 +1469,9 @@ static void sysc_init_module_quirks(struct sysc *ddata) return; } + if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) + ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; + if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; } diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h index 1a0905435b32..b5b7a3423ca8 100644 --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h @@ -49,6 +49,7 @@ struct sysc_regbits { s8 emufree_shift; }; +#define SYSC_MODULE_QUIRK_SGX BIT(18) #define SYSC_MODULE_QUIRK_HDQ1W BIT(17) #define SYSC_MODULE_QUIRK_I2C BIT(16) #define SYSC_MODULE_QUIRK_WDT BIT(15) -- cgit v1.2.3-71-gd317 From eda2e30c6684d67288edb841c6125d48c608a242 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Mon, 2 Sep 2019 11:53:02 +0200 Subject: mfd / platform: cros_ec: Miscellaneous character device to talk with the EC That's a driver to talk with the ChromeOS Embedded Controller via a miscellaneous character device, it creates an entry in /dev for every instance and implements basic file operations for communicating with the Embedded Controller with an userspace application. The API is moved to the uapi folder, which is supposed to contain the user space API of the kernel. Note that this will replace current character device interface implemented in the cros-ec-dev driver in the MFD subsystem. The idea is to move all the functionality that extends the bounds of what MFD was designed to platform/chrome subsystem. Signed-off-by: Enric Balletbo i Serra Acked-by: Andy Shevchenko Reviewed-by: Gwendal Grignou Tested-by: Gwendal Grignou Signed-off-by: Lee Jones --- drivers/mfd/cros_ec_dev.c | 4 +- drivers/mfd/cros_ec_dev.h | 35 ---- drivers/platform/chrome/Kconfig | 11 ++ drivers/platform/chrome/Makefile | 1 + drivers/platform/chrome/cros_ec_chardev.c | 251 ++++++++++++++++++++++++++ include/linux/platform_data/cros_ec_chardev.h | 37 ++++ 6 files changed, 303 insertions(+), 36 deletions(-) delete mode 100644 drivers/mfd/cros_ec_dev.h create mode 100644 drivers/platform/chrome/cros_ec_chardev.c create mode 100644 include/linux/platform_data/cros_ec_chardev.h (limited to 'include/linux/platform_data') diff --git a/drivers/mfd/cros_ec_dev.c b/drivers/mfd/cros_ec_dev.c index 41dccced5026..4c96445b1bf5 100644 --- a/drivers/mfd/cros_ec_dev.c +++ b/drivers/mfd/cros_ec_dev.c @@ -7,15 +7,17 @@ #include #include +#include +#include #include #include +#include #include #include #include #include #include -#include "cros_ec_dev.h" #define DRV_NAME "cros-ec-dev" diff --git a/drivers/mfd/cros_ec_dev.h b/drivers/mfd/cros_ec_dev.h deleted file mode 100644 index 7a42c3ef50e4..000000000000 --- a/drivers/mfd/cros_ec_dev.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * cros_ec_dev - expose the Chrome OS Embedded Controller to userspace - * - * Copyright (C) 2014 Google, Inc. - */ - -#ifndef _CROS_EC_DEV_H_ -#define _CROS_EC_DEV_H_ - -#include -#include -#include - -#define CROS_EC_DEV_VERSION "1.0.0" - -/** - * struct cros_ec_readmem - Struct used to read mapped memory. - * @offset: Within EC_LPC_ADDR_MEMMAP region. - * @bytes: Number of bytes to read. Zero means "read a string" (including '\0') - * At most only EC_MEMMAP_SIZE bytes can be read. - * @buffer: Where to store the result. The ioctl returns the number of bytes - * read or negative on error. - */ -struct cros_ec_readmem { - uint32_t offset; - uint32_t bytes; - uint8_t buffer[EC_MEMMAP_SIZE]; -}; - -#define CROS_EC_DEV_IOC 0xEC -#define CROS_EC_DEV_IOCXCMD _IOWR(CROS_EC_DEV_IOC, 0, struct cros_ec_command) -#define CROS_EC_DEV_IOCRDMEM _IOWR(CROS_EC_DEV_IOC, 1, struct cros_ec_readmem) - -#endif /* _CROS_EC_DEV_H_ */ diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig index eaeb04e07335..bd3524bd6b37 100644 --- a/drivers/platform/chrome/Kconfig +++ b/drivers/platform/chrome/Kconfig @@ -136,6 +136,17 @@ config CROS_KBD_LED_BACKLIGHT To compile this driver as a module, choose M here: the module will be called cros_kbd_led_backlight. +config CROS_EC_CHARDEV + tristate "ChromeOS EC miscdevice" + depends on MFD_CROS_EC_CHARDEV + default MFD_CROS_EC_CHARDEV + help + This driver adds file operations support to talk with the + ChromeOS EC from userspace via a character device. + + To compile this driver as a module, choose M here: the + module will be called cros_ec_chardev. + config CROS_EC_LIGHTBAR tristate "Chromebook Pixel's lightbar support" depends on MFD_CROS_EC_CHARDEV diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile index 12ff8de5ac7a..477ec3d1d1c9 100644 --- a/drivers/platform/chrome/Makefile +++ b/drivers/platform/chrome/Makefile @@ -15,6 +15,7 @@ cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o obj-$(CONFIG_CROS_EC_PROTO) += cros_ec_proto.o cros_ec_trace.o obj-$(CONFIG_CROS_KBD_LED_BACKLIGHT) += cros_kbd_led_backlight.o +obj-$(CONFIG_CROS_EC_CHARDEV) += cros_ec_chardev.o obj-$(CONFIG_CROS_EC_LIGHTBAR) += cros_ec_lightbar.o obj-$(CONFIG_CROS_EC_VBC) += cros_ec_vbc.o obj-$(CONFIG_CROS_EC_DEBUGFS) += cros_ec_debugfs.o diff --git a/drivers/platform/chrome/cros_ec_chardev.c b/drivers/platform/chrome/cros_ec_chardev.c new file mode 100644 index 000000000000..174f940822c9 --- /dev/null +++ b/drivers/platform/chrome/cros_ec_chardev.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Miscellaneous character driver for ChromeOS Embedded Controller + * + * Copyright 2014 Google, Inc. + * Copyright 2019 Google LLC + * + * This file is a rework and part of the code is ported from + * drivers/mfd/cros_ec_dev.c that was originally written by + * Bill Richardson. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "cros-ec-chardev" + +struct chardev_data { + struct cros_ec_dev *ec_dev; + struct miscdevice misc; +}; + +static int ec_get_version(struct cros_ec_dev *ec, char *str, int maxlen) +{ + static const char * const current_image_name[] = { + "unknown", "read-only", "read-write", "invalid", + }; + struct ec_response_get_version *resp; + struct cros_ec_command *msg; + int ret; + + msg = kzalloc(sizeof(*msg) + sizeof(*resp), GFP_KERNEL); + if (!msg) + return -ENOMEM; + + msg->command = EC_CMD_GET_VERSION + ec->cmd_offset; + msg->insize = sizeof(*resp); + + ret = cros_ec_cmd_xfer_status(ec->ec_dev, msg); + if (ret < 0) { + snprintf(str, maxlen, + "Unknown EC version, returned error: %d\n", + msg->result); + goto exit; + } + + resp = (struct ec_response_get_version *)msg->data; + if (resp->current_image >= ARRAY_SIZE(current_image_name)) + resp->current_image = 3; /* invalid */ + + snprintf(str, maxlen, "%s\n%s\n%s\n%s\n", CROS_EC_DEV_VERSION, + resp->version_string_ro, resp->version_string_rw, + current_image_name[resp->current_image]); + + ret = 0; +exit: + kfree(msg); + return ret; +} + +/* + * Device file ops + */ +static int cros_ec_chardev_open(struct inode *inode, struct file *filp) +{ + struct miscdevice *mdev = filp->private_data; + struct cros_ec_dev *ec_dev = dev_get_drvdata(mdev->parent); + + filp->private_data = ec_dev; + nonseekable_open(inode, filp); + + return 0; +} + +static ssize_t cros_ec_chardev_read(struct file *filp, char __user *buffer, + size_t length, loff_t *offset) +{ + char msg[sizeof(struct ec_response_get_version) + + sizeof(CROS_EC_DEV_VERSION)]; + struct cros_ec_dev *ec = filp->private_data; + size_t count; + int ret; + + if (*offset != 0) + return 0; + + ret = ec_get_version(ec, msg, sizeof(msg)); + if (ret) + return ret; + + count = min(length, strlen(msg)); + + if (copy_to_user(buffer, msg, count)) + return -EFAULT; + + *offset = count; + return count; +} + +/* + * Ioctls + */ +static long cros_ec_chardev_ioctl_xcmd(struct cros_ec_dev *ec, void __user *arg) +{ + struct cros_ec_command *s_cmd; + struct cros_ec_command u_cmd; + long ret; + + if (copy_from_user(&u_cmd, arg, sizeof(u_cmd))) + return -EFAULT; + + if (u_cmd.outsize > EC_MAX_MSG_BYTES || + u_cmd.insize > EC_MAX_MSG_BYTES) + return -EINVAL; + + s_cmd = kmalloc(sizeof(*s_cmd) + max(u_cmd.outsize, u_cmd.insize), + GFP_KERNEL); + if (!s_cmd) + return -ENOMEM; + + if (copy_from_user(s_cmd, arg, sizeof(*s_cmd) + u_cmd.outsize)) { + ret = -EFAULT; + goto exit; + } + + if (u_cmd.outsize != s_cmd->outsize || + u_cmd.insize != s_cmd->insize) { + ret = -EINVAL; + goto exit; + } + + s_cmd->command += ec->cmd_offset; + ret = cros_ec_cmd_xfer(ec->ec_dev, s_cmd); + /* Only copy data to userland if data was received. */ + if (ret < 0) + goto exit; + + if (copy_to_user(arg, s_cmd, sizeof(*s_cmd) + s_cmd->insize)) + ret = -EFAULT; +exit: + kfree(s_cmd); + return ret; +} + +static long cros_ec_chardev_ioctl_readmem(struct cros_ec_dev *ec, + void __user *arg) +{ + struct cros_ec_device *ec_dev = ec->ec_dev; + struct cros_ec_readmem s_mem = { }; + long num; + + /* Not every platform supports direct reads */ + if (!ec_dev->cmd_readmem) + return -ENOTTY; + + if (copy_from_user(&s_mem, arg, sizeof(s_mem))) + return -EFAULT; + + num = ec_dev->cmd_readmem(ec_dev, s_mem.offset, s_mem.bytes, + s_mem.buffer); + if (num <= 0) + return num; + + if (copy_to_user((void __user *)arg, &s_mem, sizeof(s_mem))) + return -EFAULT; + + return num; +} + +static long cros_ec_chardev_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + struct cros_ec_dev *ec = filp->private_data; + + if (_IOC_TYPE(cmd) != CROS_EC_DEV_IOC) + return -ENOTTY; + + switch (cmd) { + case CROS_EC_DEV_IOCXCMD: + return cros_ec_chardev_ioctl_xcmd(ec, (void __user *)arg); + case CROS_EC_DEV_IOCRDMEM: + return cros_ec_chardev_ioctl_readmem(ec, (void __user *)arg); + } + + return -ENOTTY; +} + +static const struct file_operations chardev_fops = { + .open = cros_ec_chardev_open, + .read = cros_ec_chardev_read, + .unlocked_ioctl = cros_ec_chardev_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = cros_ec_chardev_ioctl, +#endif +}; + +static int cros_ec_chardev_probe(struct platform_device *pdev) +{ + struct cros_ec_dev *ec_dev = dev_get_drvdata(pdev->dev.parent); + struct cros_ec_platform *ec_platform = dev_get_platdata(ec_dev->dev); + struct chardev_data *data; + + /* Create a char device: we want to create it anew */ + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->ec_dev = ec_dev; + data->misc.minor = MISC_DYNAMIC_MINOR; + data->misc.fops = &chardev_fops; + data->misc.name = ec_platform->ec_name; + data->misc.parent = pdev->dev.parent; + + dev_set_drvdata(&pdev->dev, data); + + return misc_register(&data->misc); +} + +static int cros_ec_chardev_remove(struct platform_device *pdev) +{ + struct chardev_data *data = dev_get_drvdata(&pdev->dev); + + misc_deregister(&data->misc); + + return 0; +} + +static struct platform_driver cros_ec_chardev_driver = { + .driver = { + .name = DRV_NAME, + }, + .probe = cros_ec_chardev_probe, + .remove = cros_ec_chardev_remove, +}; + +module_platform_driver(cros_ec_chardev_driver); + +MODULE_ALIAS("platform:" DRV_NAME); +MODULE_AUTHOR("Enric Balletbo i Serra "); +MODULE_DESCRIPTION("ChromeOS EC Miscellaneous Character Driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/platform_data/cros_ec_chardev.h b/include/linux/platform_data/cros_ec_chardev.h new file mode 100644 index 000000000000..6600b54f531c --- /dev/null +++ b/include/linux/platform_data/cros_ec_chardev.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * ChromeOS EC device interface. + * + * Copyright (C) 2014 Google, Inc. + */ + +#ifndef _UAPI_LINUX_CROS_EC_DEV_H_ +#define _UAPI_LINUX_CROS_EC_DEV_H_ + +#include +#include +#include + +#include + +#define CROS_EC_DEV_VERSION "1.0.0" + +/** + * struct cros_ec_readmem - Struct used to read mapped memory. + * @offset: Within EC_LPC_ADDR_MEMMAP region. + * @bytes: Number of bytes to read. Zero means "read a string" (including '\0') + * At most only EC_MEMMAP_SIZE bytes can be read. + * @buffer: Where to store the result. The ioctl returns the number of bytes + * read or negative on error. + */ +struct cros_ec_readmem { + uint32_t offset; + uint32_t bytes; + uint8_t buffer[EC_MEMMAP_SIZE]; +}; + +#define CROS_EC_DEV_IOC 0xEC +#define CROS_EC_DEV_IOCXCMD _IOWR(CROS_EC_DEV_IOC, 0, struct cros_ec_command) +#define CROS_EC_DEV_IOCRDMEM _IOWR(CROS_EC_DEV_IOC, 1, struct cros_ec_readmem) + +#endif /* _CROS_EC_DEV_H_ */ -- cgit v1.2.3-71-gd317 From 840d9f131f65b021e0a73f3371f3194897dba6ad Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Mon, 2 Sep 2019 11:53:05 +0200 Subject: mfd / platform: cros_ec: Reorganize platform and mfd includes There is a bit of mess between cros-ec mfd includes and platform includes. For example, we have a linux/mfd/cros_ec.h include that exports the interface implemented in platform/chrome/cros_ec_proto.c. Or we have a linux/mfd/cros_ec_commands.h file that is non related to the multifunction device (in the sense that is not exporting any function of the mfd device). This causes crossed includes between mfd and platform/chrome subsystems and makes the code difficult to read, apart from creating 'curious' situations where a platform/chrome driver includes a linux/mfd/cros_ec.h file just to get the exported functions that are implemented in another platform/chrome driver. In order to have a better separation on what the cros-ec multifunction driver does and what the cros-ec core provides move and rework the affected includes doing: - Move cros_ec_commands.h to include/linux/platform_data/cros_ec_commands.h - Get rid of the parts that are implemented in the platform/chrome/cros_ec_proto.c driver from include/linux/mfd/cros_ec.h to a new file include/linux/platform_data/cros_ec_proto.h - Update all the drivers with the new includes, so - Drivers that only need to know about the protocol include - linux/platform_data/cros_ec_proto.h - linux/platform_data/cros_ec_commands.h - Drivers that need to know about the cros-ec mfd device also include - linux/mfd/cros_ec.h Signed-off-by: Enric Balletbo i Serra Acked-by: Andy Shevchenko Acked-by: Mark Brown Acked-by: Wolfram Sang Acked-by: Neil Armstrong Acked-by: Alexandre Belloni Acked-by: Jonathan Cameron Acked-by: Benjamin Tissoires Acked-by: Dmitry Torokhov Acked-by: Sebastian Reichel Acked-by: Chanwoo Choi Reviewed-by: Gwendal Grignou Tested-by: Gwendal Grignou Series changes: 3 - Fix dereferencing pointer to incomplete type 'struct cros_ec_dev' (lkp) Signed-off-by: Lee Jones --- drivers/extcon/extcon-usbc-cros-ec.c | 3 +- drivers/hid/hid-google-hammer.c | 4 +- drivers/i2c/busses/i2c-cros-ec-tunnel.c | 4 +- drivers/iio/accel/cros_ec_accel_legacy.c | 3 +- .../iio/common/cros_ec_sensors/cros_ec_lid_angle.c | 3 +- .../iio/common/cros_ec_sensors/cros_ec_sensors.c | 3 +- .../common/cros_ec_sensors/cros_ec_sensors_core.c | 3 +- drivers/iio/light/cros_ec_light_prox.c | 3 +- drivers/iio/pressure/cros_ec_baro.c | 3 +- drivers/input/keyboard/cros_ec_keyb.c | 4 +- drivers/media/platform/cros-ec-cec/cros-ec-cec.c | 5 +- drivers/mfd/cros_ec_dev.c | 3 +- drivers/platform/chrome/cros_ec.c | 3 +- drivers/platform/chrome/cros_ec_chardev.c | 3 +- drivers/platform/chrome/cros_ec_debugfs.c | 3 +- drivers/platform/chrome/cros_ec_i2c.c | 4 +- drivers/platform/chrome/cros_ec_ishtp.c | 5 +- drivers/platform/chrome/cros_ec_lightbar.c | 3 +- drivers/platform/chrome/cros_ec_lpc.c | 4 +- drivers/platform/chrome/cros_ec_proto.c | 3 +- drivers/platform/chrome/cros_ec_rpmsg.c | 4 +- drivers/platform/chrome/cros_ec_spi.c | 4 +- drivers/platform/chrome/cros_ec_sysfs.c | 3 +- drivers/platform/chrome/cros_ec_trace.c | 2 +- drivers/platform/chrome/cros_ec_trace.h | 4 +- drivers/platform/chrome/cros_ec_vbc.c | 3 +- drivers/platform/chrome/cros_usbpd_logger.c | 5 +- drivers/power/supply/cros_usbpd-charger.c | 5 +- drivers/pwm/pwm-cros-ec.c | 4 +- drivers/rtc/rtc-cros-ec.c | 3 +- include/Kbuild | 2 +- include/linux/iio/common/cros_ec_sensors_core.h | 3 +- include/linux/mfd/cros_ec.h | 308 -- include/linux/mfd/cros_ec_commands.h | 5713 -------------------- include/linux/platform_data/cros_ec_chardev.h | 2 +- include/linux/platform_data/cros_ec_commands.h | 5713 ++++++++++++++++++++ include/linux/platform_data/cros_ec_proto.h | 319 ++ sound/soc/codecs/cros_ec_codec.c | 4 +- 38 files changed, 6100 insertions(+), 6070 deletions(-) delete mode 100644 include/linux/mfd/cros_ec_commands.h create mode 100644 include/linux/platform_data/cros_ec_commands.h create mode 100644 include/linux/platform_data/cros_ec_proto.h (limited to 'include/linux/platform_data') diff --git a/drivers/extcon/extcon-usbc-cros-ec.c b/drivers/extcon/extcon-usbc-cros-ec.c index 43c0a936ab82..5290cc2d19d9 100644 --- a/drivers/extcon/extcon-usbc-cros-ec.c +++ b/drivers/extcon/extcon-usbc-cros-ec.c @@ -6,10 +6,11 @@ #include #include -#include #include #include #include +#include +#include #include #include #include diff --git a/drivers/hid/hid-google-hammer.c b/drivers/hid/hid-google-hammer.c index ee5e0bdcf078..84f8c127ebdc 100644 --- a/drivers/hid/hid-google-hammer.c +++ b/drivers/hid/hid-google-hammer.c @@ -16,9 +16,9 @@ #include #include #include -#include -#include #include +#include +#include #include #include #include diff --git a/drivers/i2c/busses/i2c-cros-ec-tunnel.c b/drivers/i2c/busses/i2c-cros-ec-tunnel.c index 82bcd9a78759..c551aa96a2e3 100644 --- a/drivers/i2c/busses/i2c-cros-ec-tunnel.c +++ b/drivers/i2c/busses/i2c-cros-ec-tunnel.c @@ -5,8 +5,8 @@ #include #include -#include -#include +#include +#include #include #include diff --git a/drivers/iio/accel/cros_ec_accel_legacy.c b/drivers/iio/accel/cros_ec_accel_legacy.c index 46bb2e421bb9..fd9a634f741e 100644 --- a/drivers/iio/accel/cros_ec_accel_legacy.c +++ b/drivers/iio/accel/cros_ec_accel_legacy.c @@ -18,9 +18,10 @@ #include #include #include -#include #include #include +#include +#include #include #define DRV_NAME "cros-ec-accel-legacy" diff --git a/drivers/iio/common/cros_ec_sensors/cros_ec_lid_angle.c b/drivers/iio/common/cros_ec_sensors/cros_ec_lid_angle.c index 876dfd176b0e..1dcc2a16ab2d 100644 --- a/drivers/iio/common/cros_ec_sensors/cros_ec_lid_angle.c +++ b/drivers/iio/common/cros_ec_sensors/cros_ec_lid_angle.c @@ -20,9 +20,8 @@ #include #include #include -#include -#include #include +#include #include #include diff --git a/drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c b/drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c index 17af4e0fd5f8..40dc24ff0ee5 100644 --- a/drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c +++ b/drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c @@ -17,8 +17,9 @@ #include #include #include -#include #include +#include +#include #include #include diff --git a/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c b/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c index 130362ca421b..37b3f1df0ceb 100644 --- a/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c +++ b/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c @@ -14,9 +14,10 @@ #include #include #include -#include #include #include +#include +#include #include static char *cros_ec_loc[] = { diff --git a/drivers/iio/light/cros_ec_light_prox.c b/drivers/iio/light/cros_ec_light_prox.c index 308ee6ff2e22..437e0eae9178 100644 --- a/drivers/iio/light/cros_ec_light_prox.c +++ b/drivers/iio/light/cros_ec_light_prox.c @@ -15,8 +15,9 @@ #include #include #include -#include #include +#include +#include #include #include diff --git a/drivers/iio/pressure/cros_ec_baro.c b/drivers/iio/pressure/cros_ec_baro.c index 034ce98d6e97..956dc01f1295 100644 --- a/drivers/iio/pressure/cros_ec_baro.c +++ b/drivers/iio/pressure/cros_ec_baro.c @@ -15,9 +15,10 @@ #include #include #include -#include #include #include +#include +#include #include /* diff --git a/drivers/input/keyboard/cros_ec_keyb.c b/drivers/input/keyboard/cros_ec_keyb.c index 38cb6d82d8fe..a29e81fdf186 100644 --- a/drivers/input/keyboard/cros_ec_keyb.c +++ b/drivers/input/keyboard/cros_ec_keyb.c @@ -22,8 +22,8 @@ #include #include #include -#include -#include +#include +#include #include diff --git a/drivers/media/platform/cros-ec-cec/cros-ec-cec.c b/drivers/media/platform/cros-ec-cec/cros-ec-cec.c index 068df9888dbf..f9fd4bda2a94 100644 --- a/drivers/media/platform/cros-ec-cec/cros-ec-cec.c +++ b/drivers/media/platform/cros-ec-cec/cros-ec-cec.c @@ -14,10 +14,11 @@ #include #include #include +#include +#include +#include #include #include -#include -#include #define DRV_NAME "cros-ec-cec" diff --git a/drivers/mfd/cros_ec_dev.c b/drivers/mfd/cros_ec_dev.c index 0c1c0ce3453e..091d428f5531 100644 --- a/drivers/mfd/cros_ec_dev.c +++ b/drivers/mfd/cros_ec_dev.c @@ -7,12 +7,13 @@ #include #include -#include #include #include #include #include #include +#include +#include #include #define DRV_NAME "cros-ec-dev" diff --git a/drivers/platform/chrome/cros_ec.c b/drivers/platform/chrome/cros_ec.c index a54ad47c7b02..fd77e6fa74c2 100644 --- a/drivers/platform/chrome/cros_ec.c +++ b/drivers/platform/chrome/cros_ec.c @@ -13,7 +13,8 @@ #include #include #include -#include +#include +#include #include #include diff --git a/drivers/platform/chrome/cros_ec_chardev.c b/drivers/platform/chrome/cros_ec_chardev.c index 174f940822c9..08abd7e5c7bf 100644 --- a/drivers/platform/chrome/cros_ec_chardev.c +++ b/drivers/platform/chrome/cros_ec_chardev.c @@ -14,10 +14,11 @@ #include #include #include -#include #include #include #include +#include +#include #include #include #include diff --git a/drivers/platform/chrome/cros_ec_debugfs.c b/drivers/platform/chrome/cros_ec_debugfs.c index 8ec1cc2889f2..6ae484989d1f 100644 --- a/drivers/platform/chrome/cros_ec_debugfs.c +++ b/drivers/platform/chrome/cros_ec_debugfs.c @@ -8,9 +8,10 @@ #include #include #include -#include #include #include +#include +#include #include #include #include diff --git a/drivers/platform/chrome/cros_ec_i2c.c b/drivers/platform/chrome/cros_ec_i2c.c index 6bb82dfa7dae..9bd97bc8454b 100644 --- a/drivers/platform/chrome/cros_ec_i2c.c +++ b/drivers/platform/chrome/cros_ec_i2c.c @@ -9,8 +9,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/drivers/platform/chrome/cros_ec_ishtp.c b/drivers/platform/chrome/cros_ec_ishtp.c index e504d255d5ce..7d050db5b1ca 100644 --- a/drivers/platform/chrome/cros_ec_ishtp.c +++ b/drivers/platform/chrome/cros_ec_ishtp.c @@ -8,11 +8,10 @@ // (ISH-TP). #include -#include -#include -#include #include #include +#include +#include #include /* diff --git a/drivers/platform/chrome/cros_ec_lightbar.c b/drivers/platform/chrome/cros_ec_lightbar.c index 609598bbb6c3..c0f2eec35a48 100644 --- a/drivers/platform/chrome/cros_ec_lightbar.c +++ b/drivers/platform/chrome/cros_ec_lightbar.c @@ -9,8 +9,9 @@ #include #include #include -#include #include +#include +#include #include #include #include diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index 5939c4a5869c..7d10d909435f 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -16,9 +16,9 @@ #include #include #include -#include -#include #include +#include +#include #include #include #include diff --git a/drivers/platform/chrome/cros_ec_proto.c b/drivers/platform/chrome/cros_ec_proto.c index 3d2325197a68..f659f96bda12 100644 --- a/drivers/platform/chrome/cros_ec_proto.c +++ b/drivers/platform/chrome/cros_ec_proto.c @@ -3,10 +3,11 @@ // // Copyright (C) 2015 Google, Inc -#include #include #include #include +#include +#include #include #include diff --git a/drivers/platform/chrome/cros_ec_rpmsg.c b/drivers/platform/chrome/cros_ec_rpmsg.c index 520e507bfa54..9633e5417686 100644 --- a/drivers/platform/chrome/cros_ec_rpmsg.c +++ b/drivers/platform/chrome/cros_ec_rpmsg.c @@ -6,9 +6,9 @@ #include #include #include -#include -#include #include +#include +#include #include #include #include diff --git a/drivers/platform/chrome/cros_ec_spi.c b/drivers/platform/chrome/cros_ec_spi.c index 2e21f2776063..9006e1872942 100644 --- a/drivers/platform/chrome/cros_ec_spi.c +++ b/drivers/platform/chrome/cros_ec_spi.c @@ -6,9 +6,9 @@ #include #include #include -#include -#include #include +#include +#include #include #include #include diff --git a/drivers/platform/chrome/cros_ec_sysfs.c b/drivers/platform/chrome/cros_ec_sysfs.c index 3edb237bf8ed..74d36b8d4f46 100644 --- a/drivers/platform/chrome/cros_ec_sysfs.c +++ b/drivers/platform/chrome/cros_ec_sysfs.c @@ -9,8 +9,9 @@ #include #include #include -#include #include +#include +#include #include #include #include diff --git a/drivers/platform/chrome/cros_ec_trace.c b/drivers/platform/chrome/cros_ec_trace.c index 0a76412095a9..6f80ff4532ae 100644 --- a/drivers/platform/chrome/cros_ec_trace.c +++ b/drivers/platform/chrome/cros_ec_trace.c @@ -6,7 +6,7 @@ #define TRACE_SYMBOL(a) {a, #a} // Generate the list using the following script: -// sed -n 's/^#define \(EC_CMD_[[:alnum:]_]*\)\s.*/\tTRACE_SYMBOL(\1), \\/p' include/linux/mfd/cros_ec_commands.h +// sed -n 's/^#define \(EC_CMD_[[:alnum:]_]*\)\s.*/\tTRACE_SYMBOL(\1), \\/p' include/linux/platform_data/cros_ec_commands.h #define EC_CMDS \ TRACE_SYMBOL(EC_CMD_PROTO_VERSION), \ TRACE_SYMBOL(EC_CMD_HELLO), \ diff --git a/drivers/platform/chrome/cros_ec_trace.h b/drivers/platform/chrome/cros_ec_trace.h index 7ae3b89c78b9..0dd4df30fa89 100644 --- a/drivers/platform/chrome/cros_ec_trace.h +++ b/drivers/platform/chrome/cros_ec_trace.h @@ -11,8 +11,10 @@ #if !defined(_CROS_EC_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ) #define _CROS_EC_TRACE_H_ +#include #include -#include +#include +#include #include diff --git a/drivers/platform/chrome/cros_ec_vbc.c b/drivers/platform/chrome/cros_ec_vbc.c index 2aaefed87eb4..f11a1283e5c8 100644 --- a/drivers/platform/chrome/cros_ec_vbc.c +++ b/drivers/platform/chrome/cros_ec_vbc.c @@ -7,8 +7,9 @@ #include #include #include -#include #include +#include +#include #include #define DRV_NAME "cros-ec-vbc" diff --git a/drivers/platform/chrome/cros_usbpd_logger.c b/drivers/platform/chrome/cros_usbpd_logger.c index 7c7b267626a0..c549a9b49b56 100644 --- a/drivers/platform/chrome/cros_usbpd_logger.c +++ b/drivers/platform/chrome/cros_usbpd_logger.c @@ -6,10 +6,11 @@ */ #include -#include #include -#include +#include #include +#include +#include #include #include diff --git a/drivers/power/supply/cros_usbpd-charger.c b/drivers/power/supply/cros_usbpd-charger.c index 3a9ea94c3de3..6cc7c3910e09 100644 --- a/drivers/power/supply/cros_usbpd-charger.c +++ b/drivers/power/supply/cros_usbpd-charger.c @@ -5,9 +5,10 @@ * Copyright (c) 2014 - 2018 Google, Inc */ -#include #include -#include +#include +#include +#include #include #include #include diff --git a/drivers/pwm/pwm-cros-ec.c b/drivers/pwm/pwm-cros-ec.c index 98f6ac6cf6ab..85bea2d40b7d 100644 --- a/drivers/pwm/pwm-cros-ec.c +++ b/drivers/pwm/pwm-cros-ec.c @@ -6,8 +6,8 @@ */ #include -#include -#include +#include +#include #include #include #include diff --git a/drivers/rtc/rtc-cros-ec.c b/drivers/rtc/rtc-cros-ec.c index 4d6bf9304ceb..6909e01936d9 100644 --- a/drivers/rtc/rtc-cros-ec.c +++ b/drivers/rtc/rtc-cros-ec.c @@ -6,8 +6,9 @@ #include #include -#include #include +#include +#include #include #include #include diff --git a/include/Kbuild b/include/Kbuild index c38f0d46b267..b30824615814 100644 --- a/include/Kbuild +++ b/include/Kbuild @@ -310,7 +310,6 @@ header-test- += linux/mfd/adp5520.h header-test- += linux/mfd/arizona/pdata.h header-test- += linux/mfd/as3711.h header-test- += linux/mfd/as3722.h -header-test- += linux/mfd/cros_ec_commands.h header-test- += linux/mfd/da903x.h header-test- += linux/mfd/da9055/pdata.h header-test- += linux/mfd/da9063/pdata.h @@ -480,6 +479,7 @@ header-test- += linux/platform_data/ata-pxa.h header-test- += linux/platform_data/atmel.h header-test- += linux/platform_data/bh1770glc.h header-test- += linux/platform_data/brcmfmac.h +header-test- += linux/platform_data/cros_ec_commands.h header-test- += linux/platform_data/clk-u300.h header-test- += linux/platform_data/cyttsp4.h header-test- += linux/platform_data/dma-coh901318.h diff --git a/include/linux/iio/common/cros_ec_sensors_core.h b/include/linux/iio/common/cros_ec_sensors_core.h index 0c636b9fe8d7..77a7d65746b6 100644 --- a/include/linux/iio/common/cros_ec_sensors_core.h +++ b/include/linux/iio/common/cros_ec_sensors_core.h @@ -10,7 +10,8 @@ #include #include -#include +#include +#include enum { CROS_EC_SENSOR_X, diff --git a/include/linux/mfd/cros_ec.h b/include/linux/mfd/cros_ec.h index 569428ad1cb1..61c2875c2a40 100644 --- a/include/linux/mfd/cros_ec.h +++ b/include/linux/mfd/cros_ec.h @@ -8,186 +8,7 @@ #ifndef __LINUX_MFD_CROS_EC_H #define __LINUX_MFD_CROS_EC_H -#include #include -#include -#include -#include - -#define CROS_EC_DEV_NAME "cros_ec" -#define CROS_EC_DEV_FP_NAME "cros_fp" -#define CROS_EC_DEV_PD_NAME "cros_pd" -#define CROS_EC_DEV_TP_NAME "cros_tp" -#define CROS_EC_DEV_ISH_NAME "cros_ish" -#define CROS_EC_DEV_SCP_NAME "cros_scp" - -/* - * The EC is unresponsive for a time after a reboot command. Add a - * simple delay to make sure that the bus stays locked. - */ -#define EC_REBOOT_DELAY_MS 50 - -/* - * Max bus-specific overhead incurred by request/responses. - * I2C requires 1 additional byte for requests. - * I2C requires 2 additional bytes for responses. - * SPI requires up to 32 additional bytes for responses. - */ -#define EC_PROTO_VERSION_UNKNOWN 0 -#define EC_MAX_REQUEST_OVERHEAD 1 -#define EC_MAX_RESPONSE_OVERHEAD 32 - -/* - * Command interface between EC and AP, for LPC, I2C and SPI interfaces. - */ -enum { - EC_MSG_TX_HEADER_BYTES = 3, - EC_MSG_TX_TRAILER_BYTES = 1, - EC_MSG_TX_PROTO_BYTES = EC_MSG_TX_HEADER_BYTES + - EC_MSG_TX_TRAILER_BYTES, - EC_MSG_RX_PROTO_BYTES = 3, - - /* Max length of messages for proto 2*/ - EC_PROTO2_MSG_BYTES = EC_PROTO2_MAX_PARAM_SIZE + - EC_MSG_TX_PROTO_BYTES, - - EC_MAX_MSG_BYTES = 64 * 1024, -}; - -/** - * struct cros_ec_command - Information about a ChromeOS EC command. - * @version: Command version number (often 0). - * @command: Command to send (EC_CMD_...). - * @outsize: Outgoing length in bytes. - * @insize: Max number of bytes to accept from the EC. - * @result: EC's response to the command (separate from communication failure). - * @data: Where to put the incoming data from EC and outgoing data to EC. - */ -struct cros_ec_command { - uint32_t version; - uint32_t command; - uint32_t outsize; - uint32_t insize; - uint32_t result; - uint8_t data[0]; -}; - -/** - * struct cros_ec_device - Information about a ChromeOS EC device. - * @phys_name: Name of physical comms layer (e.g. 'i2c-4'). - * @dev: Device pointer for physical comms device - * @was_wake_device: True if this device was set to wake the system from - * sleep at the last suspend. - * @cros_class: The class structure for this device. - * @cmd_readmem: Direct read of the EC memory-mapped region, if supported. - * @offset: Is within EC_LPC_ADDR_MEMMAP region. - * @bytes: Number of bytes to read. zero means "read a string" (including - * the trailing '\0'). At most only EC_MEMMAP_SIZE bytes can be - * read. Caller must ensure that the buffer is large enough for the - * result when reading a string. - * @max_request: Max size of message requested. - * @max_response: Max size of message response. - * @max_passthru: Max sice of passthru message. - * @proto_version: The protocol version used for this device. - * @priv: Private data. - * @irq: Interrupt to use. - * @id: Device id. - * @din: Input buffer (for data from EC). This buffer will always be - * dword-aligned and include enough space for up to 7 word-alignment - * bytes also, so we can ensure that the body of the message is always - * dword-aligned (64-bit). We use this alignment to keep ARM and x86 - * happy. Probably word alignment would be OK, there might be a small - * performance advantage to using dword. - * @dout: Output buffer (for data to EC). This buffer will always be - * dword-aligned and include enough space for up to 7 word-alignment - * bytes also, so we can ensure that the body of the message is always - * dword-aligned (64-bit). We use this alignment to keep ARM and x86 - * happy. Probably word alignment would be OK, there might be a small - * performance advantage to using dword. - * @din_size: Size of din buffer to allocate (zero to use static din). - * @dout_size: Size of dout buffer to allocate (zero to use static dout). - * @wake_enabled: True if this device can wake the system from sleep. - * @suspended: True if this device had been suspended. - * @cmd_xfer: Send command to EC and get response. - * Returns the number of bytes received if the communication - * succeeded, but that doesn't mean the EC was happy with the - * command. The caller should check msg.result for the EC's result - * code. - * @pkt_xfer: Send packet to EC and get response. - * @lock: One transaction at a time. - * @mkbp_event_supported: True if this EC supports the MKBP event protocol. - * @host_sleep_v1: True if this EC supports the sleep v1 command. - * @event_notifier: Interrupt event notifier for transport devices. - * @event_data: Raw payload transferred with the MKBP event. - * @event_size: Size in bytes of the event data. - * @host_event_wake_mask: Mask of host events that cause wake from suspend. - * @ec: The platform_device used by the mfd driver to interface with the - * main EC. - * @pd: The platform_device used by the mfd driver to interface with the - * PD behind an EC. - */ -struct cros_ec_device { - /* These are used by other drivers that want to talk to the EC */ - const char *phys_name; - struct device *dev; - bool was_wake_device; - struct class *cros_class; - int (*cmd_readmem)(struct cros_ec_device *ec, unsigned int offset, - unsigned int bytes, void *dest); - - /* These are used to implement the platform-specific interface */ - u16 max_request; - u16 max_response; - u16 max_passthru; - u16 proto_version; - void *priv; - int irq; - u8 *din; - u8 *dout; - int din_size; - int dout_size; - bool wake_enabled; - bool suspended; - int (*cmd_xfer)(struct cros_ec_device *ec, - struct cros_ec_command *msg); - int (*pkt_xfer)(struct cros_ec_device *ec, - struct cros_ec_command *msg); - struct mutex lock; - bool mkbp_event_supported; - bool host_sleep_v1; - struct blocking_notifier_head event_notifier; - - struct ec_response_get_next_event_v1 event_data; - int event_size; - u32 host_event_wake_mask; - u32 last_resume_result; - - /* The platform devices used by the mfd driver */ - struct platform_device *ec; - struct platform_device *pd; -}; - -/** - * struct cros_ec_sensor_platform - ChromeOS EC sensor platform information. - * @sensor_num: Id of the sensor, as reported by the EC. - */ -struct cros_ec_sensor_platform { - u8 sensor_num; -}; - -/** - * struct cros_ec_platform - ChromeOS EC platform information. - * @ec_name: Name of EC device (e.g. 'cros-ec', 'cros-pd', ...) - * used in /dev/ and sysfs. - * @cmd_offset: Offset to apply for each command. Set when - * registering a device behind another one. - */ -struct cros_ec_platform { - const char *ec_name; - u16 cmd_offset; -}; - -struct cros_ec_debugfs; /** * struct cros_ec_dev - ChromeOS EC device entry point. @@ -211,133 +32,4 @@ struct cros_ec_dev { #define to_cros_ec_dev(dev) container_of(dev, struct cros_ec_dev, class_dev) -/** - * cros_ec_suspend() - Handle a suspend operation for the ChromeOS EC device. - * @ec_dev: Device to suspend. - * - * This can be called by drivers to handle a suspend event. - * - * Return: 0 on success or negative error code. - */ -int cros_ec_suspend(struct cros_ec_device *ec_dev); - -/** - * cros_ec_resume() - Handle a resume operation for the ChromeOS EC device. - * @ec_dev: Device to resume. - * - * This can be called by drivers to handle a resume event. - * - * Return: 0 on success or negative error code. - */ -int cros_ec_resume(struct cros_ec_device *ec_dev); - -/** - * cros_ec_prepare_tx() - Prepare an outgoing message in the output buffer. - * @ec_dev: Device to register. - * @msg: Message to write. - * - * This is intended to be used by all ChromeOS EC drivers, but at present - * only SPI uses it. Once LPC uses the same protocol it can start using it. - * I2C could use it now, with a refactor of the existing code. - * - * Return: 0 on success or negative error code. - */ -int cros_ec_prepare_tx(struct cros_ec_device *ec_dev, - struct cros_ec_command *msg); - -/** - * cros_ec_check_result() - Check ec_msg->result. - * @ec_dev: EC device. - * @msg: Message to check. - * - * This is used by ChromeOS EC drivers to check the ec_msg->result for - * errors and to warn about them. - * - * Return: 0 on success or negative error code. - */ -int cros_ec_check_result(struct cros_ec_device *ec_dev, - struct cros_ec_command *msg); - -/** - * cros_ec_cmd_xfer() - Send a command to the ChromeOS EC. - * @ec_dev: EC device. - * @msg: Message to write. - * - * Call this to send a command to the ChromeOS EC. This should be used - * instead of calling the EC's cmd_xfer() callback directly. - * - * Return: 0 on success or negative error code. - */ -int cros_ec_cmd_xfer(struct cros_ec_device *ec_dev, - struct cros_ec_command *msg); - -/** - * cros_ec_cmd_xfer_status() - Send a command to the ChromeOS EC. - * @ec_dev: EC device. - * @msg: Message to write. - * - * This function is identical to cros_ec_cmd_xfer, except it returns success - * status only if both the command was transmitted successfully and the EC - * replied with success status. It's not necessary to check msg->result when - * using this function. - * - * Return: The number of bytes transferred on success or negative error code. - */ -int cros_ec_cmd_xfer_status(struct cros_ec_device *ec_dev, - struct cros_ec_command *msg); - -/** - * cros_ec_register() - Register a new ChromeOS EC, using the provided info. - * @ec_dev: Device to register. - * - * Before calling this, allocate a pointer to a new device and then fill - * in all the fields up to the --private-- marker. - * - * Return: 0 on success or negative error code. - */ -int cros_ec_register(struct cros_ec_device *ec_dev); - -/** - * cros_ec_unregister() - Remove a ChromeOS EC. - * @ec_dev: Device to unregister. - * - * Call this to deregister a ChromeOS EC, then clean up any private data. - * - * Return: 0 on success or negative error code. - */ -int cros_ec_unregister(struct cros_ec_device *ec_dev); - -/** - * cros_ec_query_all() - Query the protocol version supported by the - * ChromeOS EC. - * @ec_dev: Device to register. - * - * Return: 0 on success or negative error code. - */ -int cros_ec_query_all(struct cros_ec_device *ec_dev); - -/** - * cros_ec_get_next_event() - Fetch next event from the ChromeOS EC. - * @ec_dev: Device to fetch event from. - * @wake_event: Pointer to a bool set to true upon return if the event might be - * treated as a wake event. Ignored if null. - * - * Return: negative error code on errors; 0 for no data; or else number of - * bytes received (i.e., an event was retrieved successfully). Event types are - * written out to @ec_dev->event_data.event_type on success. - */ -int cros_ec_get_next_event(struct cros_ec_device *ec_dev, bool *wake_event); - -/** - * cros_ec_get_host_event() - Return a mask of event set by the ChromeOS EC. - * @ec_dev: Device to fetch event from. - * - * When MKBP is supported, when the EC raises an interrupt, we collect the - * events raised and call the functions in the ec notifier. This function - * is a helper to know which events are raised. - * - * Return: 0 on error or non-zero bitmask of one or more EC_HOST_EVENT_*. - */ -u32 cros_ec_get_host_event(struct cros_ec_device *ec_dev); - #endif /* __LINUX_MFD_CROS_EC_H */ diff --git a/include/linux/mfd/cros_ec_commands.h b/include/linux/mfd/cros_ec_commands.h deleted file mode 100644 index 7ccb8757b79d..000000000000 --- a/include/linux/mfd/cros_ec_commands.h +++ /dev/null @@ -1,5713 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Host communication command constants for ChromeOS EC - * - * Copyright (C) 2012 Google, Inc - * - * NOTE: This file is auto-generated from ChromeOS EC Open Source code from - * https://chromium.googlesource.com/chromiumos/platform/ec/+/master/include/ec_commands.h - */ - -/* Host communication command constants for Chrome EC */ - -#ifndef __CROS_EC_COMMANDS_H -#define __CROS_EC_COMMANDS_H - - - - -#define BUILD_ASSERT(_cond) - -/* - * Current version of this protocol - * - * TODO(crosbug.com/p/11223): This is effectively useless; protocol is - * determined in other ways. Remove this once the kernel code no longer - * depends on it. - */ -#define EC_PROTO_VERSION 0x00000002 - -/* Command version mask */ -#define EC_VER_MASK(version) BIT(version) - -/* I/O addresses for ACPI commands */ -#define EC_LPC_ADDR_ACPI_DATA 0x62 -#define EC_LPC_ADDR_ACPI_CMD 0x66 - -/* I/O addresses for host command */ -#define EC_LPC_ADDR_HOST_DATA 0x200 -#define EC_LPC_ADDR_HOST_CMD 0x204 - -/* I/O addresses for host command args and params */ -/* Protocol version 2 */ -#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ -#define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is - * EC_PROTO2_MAX_PARAM_SIZE - */ -/* Protocol version 3 */ -#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ -#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ - -/* - * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff - * and they tell the kernel that so we have to think of it as two parts. - */ -#define EC_HOST_CMD_REGION0 0x800 -#define EC_HOST_CMD_REGION1 0x880 -#define EC_HOST_CMD_REGION_SIZE 0x80 - -/* EC command register bit functions */ -#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */ -#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */ -#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */ -#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */ -#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */ -#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */ -#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */ - -#define EC_LPC_ADDR_MEMMAP 0x900 -#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ -#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */ - -/* The offset address of each type of data in mapped memory. */ -#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */ -#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */ -#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */ -#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */ -#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ -#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ -#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ -#define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */ -#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ -#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */ -/* Unused 0x28 - 0x2f */ -#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */ -/* Unused 0x31 - 0x33 */ -#define EC_MEMMAP_HOST_EVENTS 0x34 /* 64 bits */ -/* Battery values are all 32 bits, unless otherwise noted. */ -#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ -#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ -#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ -#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, see below (8-bit) */ -#define EC_MEMMAP_BATT_COUNT 0x4d /* Battery Count (8-bit) */ -#define EC_MEMMAP_BATT_INDEX 0x4e /* Current Battery Data Index (8-bit) */ -/* Unused 0x4f */ -#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */ -#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ -#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ -#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ -/* Strings are all 8 bytes (EC_MEMMAP_TEXT_MAX) */ -#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ -#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ -#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ -#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ -#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */ -/* Unused 0x84 - 0x8f */ -#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/ -/* Unused 0x91 */ -#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */ -/* 0x92: Lid Angle if available, LID_ANGLE_UNRELIABLE otherwise */ -/* 0x94 - 0x99: 1st Accelerometer */ -/* 0x9a - 0x9f: 2nd Accelerometer */ -#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ -/* Unused 0xa6 - 0xdf */ - -/* - * ACPI is unable to access memory mapped data at or above this offset due to - * limitations of the ACPI protocol. Do not place data in the range 0xe0 - 0xfe - * which might be needed by ACPI. - */ -#define EC_MEMMAP_NO_ACPI 0xe0 - -/* Define the format of the accelerometer mapped memory status byte. */ -#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f -#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4) -#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7) - -/* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */ -#define EC_TEMP_SENSOR_ENTRIES 16 -/* - * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B. - * - * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2. - */ -#define EC_TEMP_SENSOR_B_ENTRIES 8 - -/* Special values for mapped temperature sensors */ -#define EC_TEMP_SENSOR_NOT_PRESENT 0xff -#define EC_TEMP_SENSOR_ERROR 0xfe -#define EC_TEMP_SENSOR_NOT_POWERED 0xfd -#define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc -/* - * The offset of temperature value stored in mapped memory. This allows - * reporting a temperature range of 200K to 454K = -73C to 181C. - */ -#define EC_TEMP_SENSOR_OFFSET 200 - -/* - * Number of ALS readings at EC_MEMMAP_ALS - */ -#define EC_ALS_ENTRIES 2 - -/* - * The default value a temperature sensor will return when it is present but - * has not been read this boot. This is a reasonable number to avoid - * triggering alarms on the host. - */ -#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET) - -#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ -#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ -#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */ - -/* Battery bit flags at EC_MEMMAP_BATT_FLAG. */ -#define EC_BATT_FLAG_AC_PRESENT 0x01 -#define EC_BATT_FLAG_BATT_PRESENT 0x02 -#define EC_BATT_FLAG_DISCHARGING 0x04 -#define EC_BATT_FLAG_CHARGING 0x08 -#define EC_BATT_FLAG_LEVEL_CRITICAL 0x10 -/* Set if some of the static/dynamic data is invalid (or outdated). */ -#define EC_BATT_FLAG_INVALID_DATA 0x20 - -/* Switch flags at EC_MEMMAP_SWITCHES */ -#define EC_SWITCH_LID_OPEN 0x01 -#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 -#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04 -/* Was recovery requested via keyboard; now unused. */ -#define EC_SWITCH_IGNORE1 0x08 -/* Recovery requested via dedicated signal (from servo board) */ -#define EC_SWITCH_DEDICATED_RECOVERY 0x10 -/* Was fake developer mode switch; now unused. Remove in next refactor. */ -#define EC_SWITCH_IGNORE0 0x20 - -/* Host command interface flags */ -/* Host command interface supports LPC args (LPC interface only) */ -#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 -/* Host command interface supports version 3 protocol */ -#define EC_HOST_CMD_FLAG_VERSION_3 0x02 - -/* Wireless switch flags */ -#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */ -#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */ -#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */ -#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */ -#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */ - -/*****************************************************************************/ -/* - * ACPI commands - * - * These are valid ONLY on the ACPI command/data port. - */ - -/* - * ACPI Read Embedded Controller - * - * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*). - * - * Use the following sequence: - * - * - Write EC_CMD_ACPI_READ to EC_LPC_ADDR_ACPI_CMD - * - Wait for EC_LPC_CMDR_PENDING bit to clear - * - Write address to EC_LPC_ADDR_ACPI_DATA - * - Wait for EC_LPC_CMDR_DATA bit to set - * - Read value from EC_LPC_ADDR_ACPI_DATA - */ -#define EC_CMD_ACPI_READ 0x0080 - -/* - * ACPI Write Embedded Controller - * - * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*). - * - * Use the following sequence: - * - * - Write EC_CMD_ACPI_WRITE to EC_LPC_ADDR_ACPI_CMD - * - Wait for EC_LPC_CMDR_PENDING bit to clear - * - Write address to EC_LPC_ADDR_ACPI_DATA - * - Wait for EC_LPC_CMDR_PENDING bit to clear - * - Write value to EC_LPC_ADDR_ACPI_DATA - */ -#define EC_CMD_ACPI_WRITE 0x0081 - -/* - * ACPI Burst Enable Embedded Controller - * - * This enables burst mode on the EC to allow the host to issue several - * commands back-to-back. While in this mode, writes to mapped multi-byte - * data are locked out to ensure data consistency. - */ -#define EC_CMD_ACPI_BURST_ENABLE 0x0082 - -/* - * ACPI Burst Disable Embedded Controller - * - * This disables burst mode on the EC and stops preventing EC writes to mapped - * multi-byte data. - */ -#define EC_CMD_ACPI_BURST_DISABLE 0x0083 - -/* - * ACPI Query Embedded Controller - * - * This clears the lowest-order bit in the currently pending host events, and - * sets the result code to the 1-based index of the bit (event 0x00000001 = 1, - * event 0x80000000 = 32), or 0 if no event was pending. - */ -#define EC_CMD_ACPI_QUERY_EVENT 0x0084 - -/* Valid addresses in ACPI memory space, for read/write commands */ - -/* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */ -#define EC_ACPI_MEM_VERSION 0x00 -/* - * Test location; writing value here updates test compliment byte to (0xff - - * value). - */ -#define EC_ACPI_MEM_TEST 0x01 -/* Test compliment; writes here are ignored. */ -#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 - -/* Keyboard backlight brightness percent (0 - 100) */ -#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03 -/* DPTF Target Fan Duty (0-100, 0xff for auto/none) */ -#define EC_ACPI_MEM_FAN_DUTY 0x04 - -/* - * DPTF temp thresholds. Any of the EC's temp sensors can have up to two - * independent thresholds attached to them. The current value of the ID - * register determines which sensor is affected by the THRESHOLD and COMMIT - * registers. The THRESHOLD register uses the same EC_TEMP_SENSOR_OFFSET scheme - * as the memory-mapped sensors. The COMMIT register applies those settings. - * - * The spec does not mandate any way to read back the threshold settings - * themselves, but when a threshold is crossed the AP needs a way to determine - * which sensor(s) are responsible. Each reading of the ID register clears and - * returns one sensor ID that has crossed one of its threshold (in either - * direction) since the last read. A value of 0xFF means "no new thresholds - * have tripped". Setting or enabling the thresholds for a sensor will clear - * the unread event count for that sensor. - */ -#define EC_ACPI_MEM_TEMP_ID 0x05 -#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06 -#define EC_ACPI_MEM_TEMP_COMMIT 0x07 -/* - * Here are the bits for the COMMIT register: - * bit 0 selects the threshold index for the chosen sensor (0/1) - * bit 1 enables/disables the selected threshold (0 = off, 1 = on) - * Each write to the commit register affects one threshold. - */ -#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK BIT(0) -#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK BIT(1) -/* - * Example: - * - * Set the thresholds for sensor 2 to 50 C and 60 C: - * write 2 to [0x05] -- select temp sensor 2 - * write 0x7b to [0x06] -- C_TO_K(50) - EC_TEMP_SENSOR_OFFSET - * write 0x2 to [0x07] -- enable threshold 0 with this value - * write 0x85 to [0x06] -- C_TO_K(60) - EC_TEMP_SENSOR_OFFSET - * write 0x3 to [0x07] -- enable threshold 1 with this value - * - * Disable the 60 C threshold, leaving the 50 C threshold unchanged: - * write 2 to [0x05] -- select temp sensor 2 - * write 0x1 to [0x07] -- disable threshold 1 - */ - -/* DPTF battery charging current limit */ -#define EC_ACPI_MEM_CHARGING_LIMIT 0x08 - -/* Charging limit is specified in 64 mA steps */ -#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64 -/* Value to disable DPTF battery charging limit */ -#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff - -/* - * Report device orientation - * Bits Definition - * 3:1 Device DPTF Profile Number (DDPN) - * 0 = Reserved for backward compatibility (indicates no valid - * profile number. Host should fall back to using TBMD). - * 1..7 = DPTF Profile number to indicate to host which table needs - * to be loaded. - * 0 Tablet Mode Device Indicator (TBMD) - */ -#define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09 -#define EC_ACPI_MEM_TBMD_SHIFT 0 -#define EC_ACPI_MEM_TBMD_MASK 0x1 -#define EC_ACPI_MEM_DDPN_SHIFT 1 -#define EC_ACPI_MEM_DDPN_MASK 0x7 - -/* - * Report device features. Uses the same format as the host command, except: - * - * bit 0 (EC_FEATURE_LIMITED) changes meaning from "EC code has a limited set - * of features", which is of limited interest when the system is already - * interpreting ACPI bytecode, to "EC_FEATURES[0-7] is not supported". Since - * these are supported, it defaults to 0. - * This allows detecting the presence of this field since older versions of - * the EC codebase would simply return 0xff to that unknown address. Check - * FEATURES0 != 0xff (or FEATURES0[0] == 0) to make sure that the other bits - * are valid. - */ -#define EC_ACPI_MEM_DEVICE_FEATURES0 0x0a -#define EC_ACPI_MEM_DEVICE_FEATURES1 0x0b -#define EC_ACPI_MEM_DEVICE_FEATURES2 0x0c -#define EC_ACPI_MEM_DEVICE_FEATURES3 0x0d -#define EC_ACPI_MEM_DEVICE_FEATURES4 0x0e -#define EC_ACPI_MEM_DEVICE_FEATURES5 0x0f -#define EC_ACPI_MEM_DEVICE_FEATURES6 0x10 -#define EC_ACPI_MEM_DEVICE_FEATURES7 0x11 - -#define EC_ACPI_MEM_BATTERY_INDEX 0x12 - -/* - * USB Port Power. Each bit indicates whether the corresponding USB ports' power - * is enabled (1) or disabled (0). - * bit 0 USB port ID 0 - * ... - * bit 7 USB port ID 7 - */ -#define EC_ACPI_MEM_USB_PORT_POWER 0x13 - -/* - * ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf. This data - * is read-only from the AP. Added in EC_ACPI_MEM_VERSION 2. - */ -#define EC_ACPI_MEM_MAPPED_BEGIN 0x20 -#define EC_ACPI_MEM_MAPPED_SIZE 0xe0 - -/* Current version of ACPI memory address space */ -#define EC_ACPI_MEM_VERSION_CURRENT 2 - - -/* - * This header file is used in coreboot both in C and ACPI code. The ACPI code - * is pre-processed to handle constants but the ASL compiler is unable to - * handle actual C code so keep it separate. - */ - - -/* - * Attributes for EC request and response packets. Just defining __packed - * results in inefficient assembly code on ARM, if the structure is actually - * 32-bit aligned, as it should be for all buffers. - * - * Be very careful when adding these to existing structures. They will round - * up the structure size to the specified boundary. - * - * Also be very careful to make that if a structure is included in some other - * parent structure that the alignment will still be true given the packing of - * the parent structure. This is particularly important if the sub-structure - * will be passed as a pointer to another function, since that function will - * not know about the misaligment caused by the parent structure's packing. - * - * Also be very careful using __packed - particularly when nesting non-packed - * structures inside packed ones. In fact, DO NOT use __packed directly; - * always use one of these attributes. - * - * Once everything is annotated properly, the following search strings should - * not return ANY matches in this file other than right here: - * - * "__packed" - generates inefficient code; all sub-structs must also be packed - * - * "struct [^_]" - all structs should be annotated, except for structs that are - * members of other structs/unions (and their original declarations should be - * annotated). - */ - -/* - * Packed structures make no assumption about alignment, so they do inefficient - * byte-wise reads. - */ -#define __ec_align1 __packed -#define __ec_align2 __packed -#define __ec_align4 __packed -#define __ec_align_size1 __packed -#define __ec_align_offset1 __packed -#define __ec_align_offset2 __packed -#define __ec_todo_packed __packed -#define __ec_todo_unpacked - - -/* LPC command status byte masks */ -/* EC has written a byte in the data register and host hasn't read it yet */ -#define EC_LPC_STATUS_TO_HOST 0x01 -/* Host has written a command/data byte and the EC hasn't read it yet */ -#define EC_LPC_STATUS_FROM_HOST 0x02 -/* EC is processing a command */ -#define EC_LPC_STATUS_PROCESSING 0x04 -/* Last write to EC was a command, not data */ -#define EC_LPC_STATUS_LAST_CMD 0x08 -/* EC is in burst mode */ -#define EC_LPC_STATUS_BURST_MODE 0x10 -/* SCI event is pending (requesting SCI query) */ -#define EC_LPC_STATUS_SCI_PENDING 0x20 -/* SMI event is pending (requesting SMI query) */ -#define EC_LPC_STATUS_SMI_PENDING 0x40 -/* (reserved) */ -#define EC_LPC_STATUS_RESERVED 0x80 - -/* - * EC is busy. This covers both the EC processing a command, and the host has - * written a new command but the EC hasn't picked it up yet. - */ -#define EC_LPC_STATUS_BUSY_MASK \ - (EC_LPC_STATUS_FROM_HOST | EC_LPC_STATUS_PROCESSING) - -/* - * Host command response codes (16-bit). Note that response codes should be - * stored in a uint16_t rather than directly in a value of this type. - */ -enum ec_status { - EC_RES_SUCCESS = 0, - EC_RES_INVALID_COMMAND = 1, - EC_RES_ERROR = 2, - EC_RES_INVALID_PARAM = 3, - EC_RES_ACCESS_DENIED = 4, - EC_RES_INVALID_RESPONSE = 5, - EC_RES_INVALID_VERSION = 6, - EC_RES_INVALID_CHECKSUM = 7, - EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */ - EC_RES_UNAVAILABLE = 9, /* No response available */ - EC_RES_TIMEOUT = 10, /* We got a timeout */ - EC_RES_OVERFLOW = 11, /* Table / data overflow */ - EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ - EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ - EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */ - EC_RES_BUS_ERROR = 15, /* Communications bus error */ - EC_RES_BUSY = 16, /* Up but too busy. Should retry */ - EC_RES_INVALID_HEADER_VERSION = 17, /* Header version invalid */ - EC_RES_INVALID_HEADER_CRC = 18, /* Header CRC invalid */ - EC_RES_INVALID_DATA_CRC = 19, /* Data CRC invalid */ - EC_RES_DUP_UNAVAILABLE = 20, /* Can't resend response */ -}; - -/* - * Host event codes. Note these are 1-based, not 0-based, because ACPI query - * EC command uses code 0 to mean "no event pending". We explicitly specify - * each value in the enum listing so they won't change if we delete/insert an - * item or rearrange the list (it needs to be stable across platforms, not - * just within a single compiled instance). - */ -enum host_event_code { - EC_HOST_EVENT_LID_CLOSED = 1, - EC_HOST_EVENT_LID_OPEN = 2, - EC_HOST_EVENT_POWER_BUTTON = 3, - EC_HOST_EVENT_AC_CONNECTED = 4, - EC_HOST_EVENT_AC_DISCONNECTED = 5, - EC_HOST_EVENT_BATTERY_LOW = 6, - EC_HOST_EVENT_BATTERY_CRITICAL = 7, - EC_HOST_EVENT_BATTERY = 8, - EC_HOST_EVENT_THERMAL_THRESHOLD = 9, - /* Event generated by a device attached to the EC */ - EC_HOST_EVENT_DEVICE = 10, - EC_HOST_EVENT_THERMAL = 11, - EC_HOST_EVENT_USB_CHARGER = 12, - EC_HOST_EVENT_KEY_PRESSED = 13, - /* - * EC has finished initializing the host interface. The host can check - * for this event following sending a EC_CMD_REBOOT_EC command to - * determine when the EC is ready to accept subsequent commands. - */ - EC_HOST_EVENT_INTERFACE_READY = 14, - /* Keyboard recovery combo has been pressed */ - EC_HOST_EVENT_KEYBOARD_RECOVERY = 15, - - /* Shutdown due to thermal overload */ - EC_HOST_EVENT_THERMAL_SHUTDOWN = 16, - /* Shutdown due to battery level too low */ - EC_HOST_EVENT_BATTERY_SHUTDOWN = 17, - - /* Suggest that the AP throttle itself */ - EC_HOST_EVENT_THROTTLE_START = 18, - /* Suggest that the AP resume normal speed */ - EC_HOST_EVENT_THROTTLE_STOP = 19, - - /* Hang detect logic detected a hang and host event timeout expired */ - EC_HOST_EVENT_HANG_DETECT = 20, - /* Hang detect logic detected a hang and warm rebooted the AP */ - EC_HOST_EVENT_HANG_REBOOT = 21, - - /* PD MCU triggering host event */ - EC_HOST_EVENT_PD_MCU = 22, - - /* Battery Status flags have changed */ - EC_HOST_EVENT_BATTERY_STATUS = 23, - - /* EC encountered a panic, triggering a reset */ - EC_HOST_EVENT_PANIC = 24, - - /* Keyboard fastboot combo has been pressed */ - EC_HOST_EVENT_KEYBOARD_FASTBOOT = 25, - - /* EC RTC event occurred */ - EC_HOST_EVENT_RTC = 26, - - /* Emulate MKBP event */ - EC_HOST_EVENT_MKBP = 27, - - /* EC desires to change state of host-controlled USB mux */ - EC_HOST_EVENT_USB_MUX = 28, - - /* TABLET/LAPTOP mode or detachable base attach/detach event */ - EC_HOST_EVENT_MODE_CHANGE = 29, - - /* Keyboard recovery combo with hardware reinitialization */ - EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT = 30, - - /* - * The high bit of the event mask is not used as a host event code. If - * it reads back as set, then the entire event mask should be - * considered invalid by the host. This can happen when reading the - * raw event status via EC_MEMMAP_HOST_EVENTS but the LPC interface is - * not initialized on the EC, or improperly configured on the host. - */ - EC_HOST_EVENT_INVALID = 32 -}; -/* Host event mask */ -#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1) - -/** - * struct ec_lpc_host_args - Arguments at EC_LPC_ADDR_HOST_ARGS - * @flags: The host argument flags. - * @command_version: Command version. - * @data_size: The length of data. - * @checksum: Checksum; sum of command + flags + command_version + data_size + - * all params/response data bytes. - */ -struct ec_lpc_host_args { - uint8_t flags; - uint8_t command_version; - uint8_t data_size; - uint8_t checksum; -} __ec_align4; - -/* Flags for ec_lpc_host_args.flags */ -/* - * Args are from host. Data area at EC_LPC_ADDR_HOST_PARAM contains command - * params. - * - * If EC gets a command and this flag is not set, this is an old-style command. - * Command version is 0 and params from host are at EC_LPC_ADDR_OLD_PARAM with - * unknown length. EC must respond with an old-style response (that is, - * without setting EC_HOST_ARGS_FLAG_TO_HOST). - */ -#define EC_HOST_ARGS_FLAG_FROM_HOST 0x01 -/* - * Args are from EC. Data area at EC_LPC_ADDR_HOST_PARAM contains response. - * - * If EC responds to a command and this flag is not set, this is an old-style - * response. Command version is 0 and response data from EC is at - * EC_LPC_ADDR_OLD_PARAM with unknown length. - */ -#define EC_HOST_ARGS_FLAG_TO_HOST 0x02 - -/*****************************************************************************/ -/* - * Byte codes returned by EC over SPI interface. - * - * These can be used by the AP to debug the EC interface, and to determine - * when the EC is not in a state where it will ever get around to responding - * to the AP. - * - * Example of sequence of bytes read from EC for a current good transfer: - * 1. - - AP asserts chip select (CS#) - * 2. EC_SPI_OLD_READY - AP sends first byte(s) of request - * 3. - - EC starts handling CS# interrupt - * 4. EC_SPI_RECEIVING - AP sends remaining byte(s) of request - * 5. EC_SPI_PROCESSING - EC starts processing request; AP is clocking in - * bytes looking for EC_SPI_FRAME_START - * 6. - - EC finishes processing and sets up response - * 7. EC_SPI_FRAME_START - AP reads frame byte - * 8. (response packet) - AP reads response packet - * 9. EC_SPI_PAST_END - Any additional bytes read by AP - * 10 - - AP deasserts chip select - * 11 - - EC processes CS# interrupt and sets up DMA for - * next request - * - * If the AP is waiting for EC_SPI_FRAME_START and sees any value other than - * the following byte values: - * EC_SPI_OLD_READY - * EC_SPI_RX_READY - * EC_SPI_RECEIVING - * EC_SPI_PROCESSING - * - * Then the EC found an error in the request, or was not ready for the request - * and lost data. The AP should give up waiting for EC_SPI_FRAME_START, - * because the EC is unable to tell when the AP is done sending its request. - */ - -/* - * Framing byte which precedes a response packet from the EC. After sending a - * request, the AP will clock in bytes until it sees the framing byte, then - * clock in the response packet. - */ -#define EC_SPI_FRAME_START 0xec - -/* - * Padding bytes which are clocked out after the end of a response packet. - */ -#define EC_SPI_PAST_END 0xed - -/* - * EC is ready to receive, and has ignored the byte sent by the AP. EC expects - * that the AP will send a valid packet header (starting with - * EC_COMMAND_PROTOCOL_3) in the next 32 bytes. - */ -#define EC_SPI_RX_READY 0xf8 - -/* - * EC has started receiving the request from the AP, but hasn't started - * processing it yet. - */ -#define EC_SPI_RECEIVING 0xf9 - -/* EC has received the entire request from the AP and is processing it. */ -#define EC_SPI_PROCESSING 0xfa - -/* - * EC received bad data from the AP, such as a packet header with an invalid - * length. EC will ignore all data until chip select deasserts. - */ -#define EC_SPI_RX_BAD_DATA 0xfb - -/* - * EC received data from the AP before it was ready. That is, the AP asserted - * chip select and started clocking data before the EC was ready to receive it. - * EC will ignore all data until chip select deasserts. - */ -#define EC_SPI_NOT_READY 0xfc - -/* - * EC was ready to receive a request from the AP. EC has treated the byte sent - * by the AP as part of a request packet, or (for old-style ECs) is processing - * a fully received packet but is not ready to respond yet. - */ -#define EC_SPI_OLD_READY 0xfd - -/*****************************************************************************/ - -/* - * Protocol version 2 for I2C and SPI send a request this way: - * - * 0 EC_CMD_VERSION0 + (command version) - * 1 Command number - * 2 Length of params = N - * 3..N+2 Params, if any - * N+3 8-bit checksum of bytes 0..N+2 - * - * The corresponding response is: - * - * 0 Result code (EC_RES_*) - * 1 Length of params = M - * 2..M+1 Params, if any - * M+2 8-bit checksum of bytes 0..M+1 - */ -#define EC_PROTO2_REQUEST_HEADER_BYTES 3 -#define EC_PROTO2_REQUEST_TRAILER_BYTES 1 -#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \ - EC_PROTO2_REQUEST_TRAILER_BYTES) - -#define EC_PROTO2_RESPONSE_HEADER_BYTES 2 -#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1 -#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \ - EC_PROTO2_RESPONSE_TRAILER_BYTES) - -/* Parameter length was limited by the LPC interface */ -#define EC_PROTO2_MAX_PARAM_SIZE 0xfc - -/* Maximum request and response packet sizes for protocol version 2 */ -#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \ - EC_PROTO2_MAX_PARAM_SIZE) -#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \ - EC_PROTO2_MAX_PARAM_SIZE) - -/*****************************************************************************/ - -/* - * Value written to legacy command port / prefix byte to indicate protocol - * 3+ structs are being used. Usage is bus-dependent. - */ -#define EC_COMMAND_PROTOCOL_3 0xda - -#define EC_HOST_REQUEST_VERSION 3 - -/** - * struct ec_host_request - Version 3 request from host. - * @struct_version: Should be 3. The EC will return EC_RES_INVALID_HEADER if it - * receives a header with a version it doesn't know how to - * parse. - * @checksum: Checksum of request and data; sum of all bytes including checksum - * should total to 0. - * @command: Command to send (EC_CMD_...) - * @command_version: Command version. - * @reserved: Unused byte in current protocol version; set to 0. - * @data_len: Length of data which follows this header. - */ -struct ec_host_request { - uint8_t struct_version; - uint8_t checksum; - uint16_t command; - uint8_t command_version; - uint8_t reserved; - uint16_t data_len; -} __ec_align4; - -#define EC_HOST_RESPONSE_VERSION 3 - -/** - * struct ec_host_response - Version 3 response from EC. - * @struct_version: Struct version (=3). - * @checksum: Checksum of response and data; sum of all bytes including - * checksum should total to 0. - * @result: EC's response to the command (separate from communication failure) - * @data_len: Length of data which follows this header. - * @reserved: Unused bytes in current protocol version; set to 0. - */ -struct ec_host_response { - uint8_t struct_version; - uint8_t checksum; - uint16_t result; - uint16_t data_len; - uint16_t reserved; -} __ec_align4; - -/*****************************************************************************/ - -/* - * Host command protocol V4. - * - * Packets always start with a request or response header. They are followed - * by data_len bytes of data. If the data_crc_present flag is set, the data - * bytes are followed by a CRC-8 of that data, using using x^8 + x^2 + x + 1 - * polynomial. - * - * Host algorithm when sending a request q: - * - * 101) tries_left=(some value, e.g. 3); - * 102) q.seq_num++ - * 103) q.seq_dup=0 - * 104) Calculate q.header_crc. - * 105) Send request q to EC. - * 106) Wait for response r. Go to 201 if received or 301 if timeout. - * - * 201) If r.struct_version != 4, go to 301. - * 202) If r.header_crc mismatches calculated CRC for r header, go to 301. - * 203) If r.data_crc_present and r.data_crc mismatches, go to 301. - * 204) If r.seq_num != q.seq_num, go to 301. - * 205) If r.seq_dup == q.seq_dup, return success. - * 207) If r.seq_dup == 1, go to 301. - * 208) Return error. - * - * 301) If --tries_left <= 0, return error. - * 302) If q.seq_dup == 1, go to 105. - * 303) q.seq_dup = 1 - * 304) Go to 104. - * - * EC algorithm when receiving a request q. - * EC has response buffer r, error buffer e. - * - * 101) If q.struct_version != 4, set e.result = EC_RES_INVALID_HEADER_VERSION - * and go to 301 - * 102) If q.header_crc mismatches calculated CRC, set e.result = - * EC_RES_INVALID_HEADER_CRC and go to 301 - * 103) If q.data_crc_present, calculate data CRC. If that mismatches the CRC - * byte at the end of the packet, set e.result = EC_RES_INVALID_DATA_CRC - * and go to 301. - * 104) If q.seq_dup == 0, go to 201. - * 105) If q.seq_num != r.seq_num, go to 201. - * 106) If q.seq_dup == r.seq_dup, go to 205, else go to 203. - * - * 201) Process request q into response r. - * 202) r.seq_num = q.seq_num - * 203) r.seq_dup = q.seq_dup - * 204) Calculate r.header_crc - * 205) If r.data_len > 0 and data is no longer available, set e.result = - * EC_RES_DUP_UNAVAILABLE and go to 301. - * 206) Send response r. - * - * 301) e.seq_num = q.seq_num - * 302) e.seq_dup = q.seq_dup - * 303) Calculate e.header_crc. - * 304) Send error response e. - */ - -/* Version 4 request from host */ -struct ec_host_request4 { - /* - * bits 0-3: struct_version: Structure version (=4) - * bit 4: is_response: Is response (=0) - * bits 5-6: seq_num: Sequence number - * bit 7: seq_dup: Sequence duplicate flag - */ - uint8_t fields0; - - /* - * bits 0-4: command_version: Command version - * bits 5-6: Reserved (set 0, ignore on read) - * bit 7: data_crc_present: Is data CRC present after data - */ - uint8_t fields1; - - /* Command code (EC_CMD_*) */ - uint16_t command; - - /* Length of data which follows this header (not including data CRC) */ - uint16_t data_len; - - /* Reserved (set 0, ignore on read) */ - uint8_t reserved; - - /* CRC-8 of above fields, using x^8 + x^2 + x + 1 polynomial */ - uint8_t header_crc; -} __ec_align4; - -/* Version 4 response from EC */ -struct ec_host_response4 { - /* - * bits 0-3: struct_version: Structure version (=4) - * bit 4: is_response: Is response (=1) - * bits 5-6: seq_num: Sequence number - * bit 7: seq_dup: Sequence duplicate flag - */ - uint8_t fields0; - - /* - * bits 0-6: Reserved (set 0, ignore on read) - * bit 7: data_crc_present: Is data CRC present after data - */ - uint8_t fields1; - - /* Result code (EC_RES_*) */ - uint16_t result; - - /* Length of data which follows this header (not including data CRC) */ - uint16_t data_len; - - /* Reserved (set 0, ignore on read) */ - uint8_t reserved; - - /* CRC-8 of above fields, using x^8 + x^2 + x + 1 polynomial */ - uint8_t header_crc; -} __ec_align4; - -/* Fields in fields0 byte */ -#define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f -#define EC_PACKET4_0_IS_RESPONSE_MASK 0x10 -#define EC_PACKET4_0_SEQ_NUM_SHIFT 5 -#define EC_PACKET4_0_SEQ_NUM_MASK 0x60 -#define EC_PACKET4_0_SEQ_DUP_MASK 0x80 - -/* Fields in fields1 byte */ -#define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f /* (request only) */ -#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80 - -/*****************************************************************************/ -/* - * Notes on commands: - * - * Each command is an 16-bit command value. Commands which take params or - * return response data specify structures for that data. If no structure is - * specified, the command does not input or output data, respectively. - * Parameter/response length is implicit in the structs. Some underlying - * communication protocols (I2C, SPI) may add length or checksum headers, but - * those are implementation-dependent and not defined here. - * - * All commands MUST be #defined to be 4-digit UPPER CASE hex values - * (e.g., 0x00AB, not 0xab) for CONFIG_HOSTCMD_SECTION_SORTED to work. - */ - -/*****************************************************************************/ -/* General / test commands */ - -/* - * Get protocol version, used to deal with non-backward compatible protocol - * changes. - */ -#define EC_CMD_PROTO_VERSION 0x0000 - -/** - * struct ec_response_proto_version - Response to the proto version command. - * @version: The protocol version. - */ -struct ec_response_proto_version { - uint32_t version; -} __ec_align4; - -/* - * Hello. This is a simple command to test the EC is responsive to - * commands. - */ -#define EC_CMD_HELLO 0x0001 - -/** - * struct ec_params_hello - Parameters to the hello command. - * @in_data: Pass anything here. - */ -struct ec_params_hello { - uint32_t in_data; -} __ec_align4; - -/** - * struct ec_response_hello - Response to the hello command. - * @out_data: Output will be in_data + 0x01020304. - */ -struct ec_response_hello { - uint32_t out_data; -} __ec_align4; - -/* Get version number */ -#define EC_CMD_GET_VERSION 0x0002 - -enum ec_current_image { - EC_IMAGE_UNKNOWN = 0, - EC_IMAGE_RO, - EC_IMAGE_RW -}; - -/** - * struct ec_response_get_version - Response to the get version command. - * @version_string_ro: Null-terminated RO firmware version string. - * @version_string_rw: Null-terminated RW firmware version string. - * @reserved: Unused bytes; was previously RW-B firmware version string. - * @current_image: One of ec_current_image. - */ -struct ec_response_get_version { - char version_string_ro[32]; - char version_string_rw[32]; - char reserved[32]; - uint32_t current_image; -} __ec_align4; - -/* Read test */ -#define EC_CMD_READ_TEST 0x0003 - -/** - * struct ec_params_read_test - Parameters for the read test command. - * @offset: Starting value for read buffer. - * @size: Size to read in bytes. - */ -struct ec_params_read_test { - uint32_t offset; - uint32_t size; -} __ec_align4; - -/** - * struct ec_response_read_test - Response to the read test command. - * @data: Data returned by the read test command. - */ -struct ec_response_read_test { - uint32_t data[32]; -} __ec_align4; - -/* - * Get build information - * - * Response is null-terminated string. - */ -#define EC_CMD_GET_BUILD_INFO 0x0004 - -/* Get chip info */ -#define EC_CMD_GET_CHIP_INFO 0x0005 - -/** - * struct ec_response_get_chip_info - Response to the get chip info command. - * @vendor: Null-terminated string for chip vendor. - * @name: Null-terminated string for chip name. - * @revision: Null-terminated string for chip mask version. - */ -struct ec_response_get_chip_info { - char vendor[32]; - char name[32]; - char revision[32]; -} __ec_align4; - -/* Get board HW version */ -#define EC_CMD_GET_BOARD_VERSION 0x0006 - -/** - * struct ec_response_board_version - Response to the board version command. - * @board_version: A monotonously incrementing number. - */ -struct ec_response_board_version { - uint16_t board_version; -} __ec_align2; - -/* - * Read memory-mapped data. - * - * This is an alternate interface to memory-mapped data for bus protocols - * which don't support direct-mapped memory - I2C, SPI, etc. - * - * Response is params.size bytes of data. - */ -#define EC_CMD_READ_MEMMAP 0x0007 - -/** - * struct ec_params_read_memmap - Parameters for the read memory map command. - * @offset: Offset in memmap (EC_MEMMAP_*). - * @size: Size to read in bytes. - */ -struct ec_params_read_memmap { - uint8_t offset; - uint8_t size; -} __ec_align1; - -/* Read versions supported for a command */ -#define EC_CMD_GET_CMD_VERSIONS 0x0008 - -/** - * struct ec_params_get_cmd_versions - Parameters for the get command versions. - * @cmd: Command to check. - */ -struct ec_params_get_cmd_versions { - uint8_t cmd; -} __ec_align1; - -/** - * struct ec_params_get_cmd_versions_v1 - Parameters for the get command - * versions (v1) - * @cmd: Command to check. - */ -struct ec_params_get_cmd_versions_v1 { - uint16_t cmd; -} __ec_align2; - -/** - * struct ec_response_get_cmd_version - Response to the get command versions. - * @version_mask: Mask of supported versions; use EC_VER_MASK() to compare with - * a desired version. - */ -struct ec_response_get_cmd_versions { - uint32_t version_mask; -} __ec_align4; - -/* - * Check EC communications status (busy). This is needed on i2c/spi but not - * on lpc since it has its own out-of-band busy indicator. - * - * lpc must read the status from the command register. Attempting this on - * lpc will overwrite the args/parameter space and corrupt its data. - */ -#define EC_CMD_GET_COMMS_STATUS 0x0009 - -/* Avoid using ec_status which is for return values */ -enum ec_comms_status { - EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */ -}; - -/** - * struct ec_response_get_comms_status - Response to the get comms status - * command. - * @flags: Mask of enum ec_comms_status. - */ -struct ec_response_get_comms_status { - uint32_t flags; /* Mask of enum ec_comms_status */ -} __ec_align4; - -/* Fake a variety of responses, purely for testing purposes. */ -#define EC_CMD_TEST_PROTOCOL 0x000A - -/* Tell the EC what to send back to us. */ -struct ec_params_test_protocol { - uint32_t ec_result; - uint32_t ret_len; - uint8_t buf[32]; -} __ec_align4; - -/* Here it comes... */ -struct ec_response_test_protocol { - uint8_t buf[32]; -} __ec_align4; - -/* Get protocol information */ -#define EC_CMD_GET_PROTOCOL_INFO 0x000B - -/* Flags for ec_response_get_protocol_info.flags */ -/* EC_RES_IN_PROGRESS may be returned if a command is slow */ -#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED BIT(0) - -/** - * struct ec_response_get_protocol_info - Response to the get protocol info. - * @protocol_versions: Bitmask of protocol versions supported (1 << n means - * version n). - * @max_request_packet_size: Maximum request packet size in bytes. - * @max_response_packet_size: Maximum response packet size in bytes. - * @flags: see EC_PROTOCOL_INFO_* - */ -struct ec_response_get_protocol_info { - /* Fields which exist if at least protocol version 3 supported */ - uint32_t protocol_versions; - uint16_t max_request_packet_size; - uint16_t max_response_packet_size; - uint32_t flags; -} __ec_align4; - - -/*****************************************************************************/ -/* Get/Set miscellaneous values */ - -/* The upper byte of .flags tells what to do (nothing means "get") */ -#define EC_GSV_SET 0x80000000 - -/* - * The lower three bytes of .flags identifies the parameter, if that has - * meaning for an individual command. - */ -#define EC_GSV_PARAM_MASK 0x00ffffff - -struct ec_params_get_set_value { - uint32_t flags; - uint32_t value; -} __ec_align4; - -struct ec_response_get_set_value { - uint32_t flags; - uint32_t value; -} __ec_align4; - -/* More than one command can use these structs to get/set parameters. */ -#define EC_CMD_GSV_PAUSE_IN_S5 0x000C - -/*****************************************************************************/ -/* List the features supported by the firmware */ -#define EC_CMD_GET_FEATURES 0x000D - -/* Supported features */ -enum ec_feature_code { - /* - * This image contains a limited set of features. Another image - * in RW partition may support more features. - */ - EC_FEATURE_LIMITED = 0, - /* - * Commands for probing/reading/writing/erasing the flash in the - * EC are present. - */ - EC_FEATURE_FLASH = 1, - /* - * Can control the fan speed directly. - */ - EC_FEATURE_PWM_FAN = 2, - /* - * Can control the intensity of the keyboard backlight. - */ - EC_FEATURE_PWM_KEYB = 3, - /* - * Support Google lightbar, introduced on Pixel. - */ - EC_FEATURE_LIGHTBAR = 4, - /* Control of LEDs */ - EC_FEATURE_LED = 5, - /* Exposes an interface to control gyro and sensors. - * The host goes through the EC to access these sensors. - * In addition, the EC may provide composite sensors, like lid angle. - */ - EC_FEATURE_MOTION_SENSE = 6, - /* The keyboard is controlled by the EC */ - EC_FEATURE_KEYB = 7, - /* The AP can use part of the EC flash as persistent storage. */ - EC_FEATURE_PSTORE = 8, - /* The EC monitors BIOS port 80h, and can return POST codes. */ - EC_FEATURE_PORT80 = 9, - /* - * Thermal management: include TMP specific commands. - * Higher level than direct fan control. - */ - EC_FEATURE_THERMAL = 10, - /* Can switch the screen backlight on/off */ - EC_FEATURE_BKLIGHT_SWITCH = 11, - /* Can switch the wifi module on/off */ - EC_FEATURE_WIFI_SWITCH = 12, - /* Monitor host events, through for example SMI or SCI */ - EC_FEATURE_HOST_EVENTS = 13, - /* The EC exposes GPIO commands to control/monitor connected devices. */ - EC_FEATURE_GPIO = 14, - /* The EC can send i2c messages to downstream devices. */ - EC_FEATURE_I2C = 15, - /* Command to control charger are included */ - EC_FEATURE_CHARGER = 16, - /* Simple battery support. */ - EC_FEATURE_BATTERY = 17, - /* - * Support Smart battery protocol - * (Common Smart Battery System Interface Specification) - */ - EC_FEATURE_SMART_BATTERY = 18, - /* EC can detect when the host hangs. */ - EC_FEATURE_HANG_DETECT = 19, - /* Report power information, for pit only */ - EC_FEATURE_PMU = 20, - /* Another Cros EC device is present downstream of this one */ - EC_FEATURE_SUB_MCU = 21, - /* Support USB Power delivery (PD) commands */ - EC_FEATURE_USB_PD = 22, - /* Control USB multiplexer, for audio through USB port for instance. */ - EC_FEATURE_USB_MUX = 23, - /* Motion Sensor code has an internal software FIFO */ - EC_FEATURE_MOTION_SENSE_FIFO = 24, - /* Support temporary secure vstore */ - EC_FEATURE_VSTORE = 25, - /* EC decides on USB-C SS mux state, muxes configured by host */ - EC_FEATURE_USBC_SS_MUX_VIRTUAL = 26, - /* EC has RTC feature that can be controlled by host commands */ - EC_FEATURE_RTC = 27, - /* The MCU exposes a Fingerprint sensor */ - EC_FEATURE_FINGERPRINT = 28, - /* The MCU exposes a Touchpad */ - EC_FEATURE_TOUCHPAD = 29, - /* The MCU has RWSIG task enabled */ - EC_FEATURE_RWSIG = 30, - /* EC has device events support */ - EC_FEATURE_DEVICE_EVENT = 31, - /* EC supports the unified wake masks for LPC/eSPI systems */ - EC_FEATURE_UNIFIED_WAKE_MASKS = 32, - /* EC supports 64-bit host events */ - EC_FEATURE_HOST_EVENT64 = 33, - /* EC runs code in RAM (not in place, a.k.a. XIP) */ - EC_FEATURE_EXEC_IN_RAM = 34, - /* EC supports CEC commands */ - EC_FEATURE_CEC = 35, - /* EC supports tight sensor timestamping. */ - EC_FEATURE_MOTION_SENSE_TIGHT_TIMESTAMPS = 36, - /* - * EC supports tablet mode detection aligned to Chrome and allows - * setting of threshold by host command using - * MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. - */ - EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37, - /* EC supports audio codec. */ - EC_FEATURE_AUDIO_CODEC = 38, - /* The MCU is a System Companion Processor (SCP). */ - EC_FEATURE_SCP = 39, - /* The MCU is an Integrated Sensor Hub */ - EC_FEATURE_ISH = 40, -}; - -#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) -#define EC_FEATURE_MASK_1(event_code) BIT(event_code - 32) - -struct ec_response_get_features { - uint32_t flags[2]; -} __ec_align4; - -/*****************************************************************************/ -/* Get the board's SKU ID from EC */ -#define EC_CMD_GET_SKU_ID 0x000E - -/* Set SKU ID from AP */ -#define EC_CMD_SET_SKU_ID 0x000F - -struct ec_sku_id_info { - uint32_t sku_id; -} __ec_align4; - -/*****************************************************************************/ -/* Flash commands */ - -/* Get flash info */ -#define EC_CMD_FLASH_INFO 0x0010 -#define EC_VER_FLASH_INFO 2 - -/** - * struct ec_response_flash_info - Response to the flash info command. - * @flash_size: Usable flash size in bytes. - * @write_block_size: Write block size. Write offset and size must be a - * multiple of this. - * @erase_block_size: Erase block size. Erase offset and size must be a - * multiple of this. - * @protect_block_size: Protection block size. Protection offset and size - * must be a multiple of this. - * - * Version 0 returns these fields. - */ -struct ec_response_flash_info { - uint32_t flash_size; - uint32_t write_block_size; - uint32_t erase_block_size; - uint32_t protect_block_size; -} __ec_align4; - -/* - * Flags for version 1+ flash info command - * EC flash erases bits to 0 instead of 1. - */ -#define EC_FLASH_INFO_ERASE_TO_0 BIT(0) - -/* - * Flash must be selected for read/write/erase operations to succeed. This may - * be necessary on a chip where write/erase can be corrupted by other board - * activity, or where the chip needs to enable some sort of programming voltage, - * or where the read/write/erase operations require cleanly suspending other - * chip functionality. - */ -#define EC_FLASH_INFO_SELECT_REQUIRED BIT(1) - -/** - * struct ec_response_flash_info_1 - Response to the flash info v1 command. - * @flash_size: Usable flash size in bytes. - * @write_block_size: Write block size. Write offset and size must be a - * multiple of this. - * @erase_block_size: Erase block size. Erase offset and size must be a - * multiple of this. - * @protect_block_size: Protection block size. Protection offset and size - * must be a multiple of this. - * @write_ideal_size: Ideal write size in bytes. Writes will be fastest if - * size is exactly this and offset is a multiple of this. - * For example, an EC may have a write buffer which can do - * half-page operations if data is aligned, and a slower - * word-at-a-time write mode. - * @flags: Flags; see EC_FLASH_INFO_* - * - * Version 1 returns the same initial fields as version 0, with additional - * fields following. - * - * gcc anonymous structs don't seem to get along with the __packed directive; - * if they did we'd define the version 0 structure as a sub-structure of this - * one. - * - * Version 2 supports flash banks of different sizes: - * The caller specified the number of banks it has preallocated - * (num_banks_desc) - * The EC returns the number of banks describing the flash memory. - * It adds banks descriptions up to num_banks_desc. - */ -struct ec_response_flash_info_1 { - /* Version 0 fields; see above for description */ - uint32_t flash_size; - uint32_t write_block_size; - uint32_t erase_block_size; - uint32_t protect_block_size; - - /* Version 1 adds these fields: */ - uint32_t write_ideal_size; - uint32_t flags; -} __ec_align4; - -struct ec_params_flash_info_2 { - /* Number of banks to describe */ - uint16_t num_banks_desc; - /* Reserved; set 0; ignore on read */ - uint8_t reserved[2]; -} __ec_align4; - -struct ec_flash_bank { - /* Number of sector is in this bank. */ - uint16_t count; - /* Size in power of 2 of each sector (8 --> 256 bytes) */ - uint8_t size_exp; - /* Minimal write size for the sectors in this bank */ - uint8_t write_size_exp; - /* Erase size for the sectors in this bank */ - uint8_t erase_size_exp; - /* Size for write protection, usually identical to erase size. */ - uint8_t protect_size_exp; - /* Reserved; set 0; ignore on read */ - uint8_t reserved[2]; -}; - -struct ec_response_flash_info_2 { - /* Total flash in the EC. */ - uint32_t flash_size; - /* Flags; see EC_FLASH_INFO_* */ - uint32_t flags; - /* Maximum size to use to send data to write to the EC. */ - uint32_t write_ideal_size; - /* Number of banks present in the EC. */ - uint16_t num_banks_total; - /* Number of banks described in banks array. */ - uint16_t num_banks_desc; - struct ec_flash_bank banks[0]; -} __ec_align4; - -/* - * Read flash - * - * Response is params.size bytes of data. - */ -#define EC_CMD_FLASH_READ 0x0011 - -/** - * struct ec_params_flash_read - Parameters for the flash read command. - * @offset: Byte offset to read. - * @size: Size to read in bytes. - */ -struct ec_params_flash_read { - uint32_t offset; - uint32_t size; -} __ec_align4; - -/* Write flash */ -#define EC_CMD_FLASH_WRITE 0x0012 -#define EC_VER_FLASH_WRITE 1 - -/* Version 0 of the flash command supported only 64 bytes of data */ -#define EC_FLASH_WRITE_VER0_SIZE 64 - -/** - * struct ec_params_flash_write - Parameters for the flash write command. - * @offset: Byte offset to write. - * @size: Size to write in bytes. - */ -struct ec_params_flash_write { - uint32_t offset; - uint32_t size; - /* Followed by data to write */ -} __ec_align4; - -/* Erase flash */ -#define EC_CMD_FLASH_ERASE 0x0013 - -/** - * struct ec_params_flash_erase - Parameters for the flash erase command, v0. - * @offset: Byte offset to erase. - * @size: Size to erase in bytes. - */ -struct ec_params_flash_erase { - uint32_t offset; - uint32_t size; -} __ec_align4; - -/* - * v1 add async erase: - * subcommands can returns: - * EC_RES_SUCCESS : erased (see ERASE_SECTOR_ASYNC case below). - * EC_RES_INVALID_PARAM : offset/size are not aligned on a erase boundary. - * EC_RES_ERROR : other errors. - * EC_RES_BUSY : an existing erase operation is in progress. - * EC_RES_ACCESS_DENIED: Trying to erase running image. - * - * When ERASE_SECTOR_ASYNC returns EC_RES_SUCCESS, the operation is just - * properly queued. The user must call ERASE_GET_RESULT subcommand to get - * the proper result. - * When ERASE_GET_RESULT returns EC_RES_BUSY, the caller must wait and send - * ERASE_GET_RESULT again to get the result of ERASE_SECTOR_ASYNC. - * ERASE_GET_RESULT command may timeout on EC where flash access is not - * permitted while erasing. (For instance, STM32F4). - */ -enum ec_flash_erase_cmd { - FLASH_ERASE_SECTOR, /* Erase and wait for result */ - FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */ - FLASH_ERASE_GET_RESULT, /* Ask for last erase result */ -}; - -/** - * struct ec_params_flash_erase_v1 - Parameters for the flash erase command, v1. - * @cmd: One of ec_flash_erase_cmd. - * @reserved: Pad byte; currently always contains 0. - * @flag: No flags defined yet; set to 0. - * @params: Same as v0 parameters. - */ -struct ec_params_flash_erase_v1 { - uint8_t cmd; - uint8_t reserved; - uint16_t flag; - struct ec_params_flash_erase params; -} __ec_align4; - -/* - * Get/set flash protection. - * - * If mask!=0, sets/clear the requested bits of flags. Depending on the - * firmware write protect GPIO, not all flags will take effect immediately; - * some flags require a subsequent hard reset to take effect. Check the - * returned flags bits to see what actually happened. - * - * If mask=0, simply returns the current flags state. - */ -#define EC_CMD_FLASH_PROTECT 0x0015 -#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */ - -/* Flags for flash protection */ -/* RO flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0) -/* - * RO flash code protected now. If this bit is set, at-boot status cannot - * be changed. - */ -#define EC_FLASH_PROTECT_RO_NOW BIT(1) -/* Entire flash code protected now, until reboot. */ -#define EC_FLASH_PROTECT_ALL_NOW BIT(2) -/* Flash write protect GPIO is asserted now */ -#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3) -/* Error - at least one bank of flash is stuck locked, and cannot be unlocked */ -#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4) -/* - * Error - flash protection is in inconsistent state. At least one bank of - * flash which should be protected is not protected. Usually fixed by - * re-requesting the desired flags, or by a hard reset if that fails. - */ -#define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5) -/* Entire flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6) -/* RW flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7) -/* RW flash code protected now. */ -#define EC_FLASH_PROTECT_RW_NOW BIT(8) -/* Rollback information flash region protected when the EC boots */ -#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9) -/* Rollback information flash region protected now */ -#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10) - - -/** - * struct ec_params_flash_protect - Parameters for the flash protect command. - * @mask: Bits in flags to apply. - * @flags: New flags to apply. - */ -struct ec_params_flash_protect { - uint32_t mask; - uint32_t flags; -} __ec_align4; - -/** - * struct ec_response_flash_protect - Response to the flash protect command. - * @flags: Current value of flash protect flags. - * @valid_flags: Flags which are valid on this platform. This allows the - * caller to distinguish between flags which aren't set vs. flags - * which can't be set on this platform. - * @writable_flags: Flags which can be changed given the current protection - * state. - */ -struct ec_response_flash_protect { - uint32_t flags; - uint32_t valid_flags; - uint32_t writable_flags; -} __ec_align4; - -/* - * Note: commands 0x14 - 0x19 version 0 were old commands to get/set flash - * write protect. These commands may be reused with version > 0. - */ - -/* Get the region offset/size */ -#define EC_CMD_FLASH_REGION_INFO 0x0016 -#define EC_VER_FLASH_REGION_INFO 1 - -enum ec_flash_region { - /* Region which holds read-only EC image */ - EC_FLASH_REGION_RO = 0, - /* - * Region which holds active RW image. 'Active' is different from - * 'running'. Active means 'scheduled-to-run'. Since RO image always - * scheduled to run, active/non-active applies only to RW images (for - * the same reason 'update' applies only to RW images. It's a state of - * an image on a flash. Running image can be RO, RW_A, RW_B but active - * image can only be RW_A or RW_B. In recovery mode, an active RW image - * doesn't enter 'running' state but it's still active on a flash. - */ - EC_FLASH_REGION_ACTIVE, - /* - * Region which should be write-protected in the factory (a superset of - * EC_FLASH_REGION_RO) - */ - EC_FLASH_REGION_WP_RO, - /* Region which holds updatable (non-active) RW image */ - EC_FLASH_REGION_UPDATE, - /* Number of regions */ - EC_FLASH_REGION_COUNT, -}; -/* - * 'RW' is vague if there are multiple RW images; we mean the active one, - * so the old constant is deprecated. - */ -#define EC_FLASH_REGION_RW EC_FLASH_REGION_ACTIVE - -/** - * struct ec_params_flash_region_info - Parameters for the flash region info - * command. - * @region: Flash region; see EC_FLASH_REGION_* - */ -struct ec_params_flash_region_info { - uint32_t region; -} __ec_align4; - -struct ec_response_flash_region_info { - uint32_t offset; - uint32_t size; -} __ec_align4; - -/* Read/write VbNvContext */ -#define EC_CMD_VBNV_CONTEXT 0x0017 -#define EC_VER_VBNV_CONTEXT 1 -#define EC_VBNV_BLOCK_SIZE 16 - -enum ec_vbnvcontext_op { - EC_VBNV_CONTEXT_OP_READ, - EC_VBNV_CONTEXT_OP_WRITE, -}; - -struct ec_params_vbnvcontext { - uint32_t op; - uint8_t block[EC_VBNV_BLOCK_SIZE]; -} __ec_align4; - -struct ec_response_vbnvcontext { - uint8_t block[EC_VBNV_BLOCK_SIZE]; -} __ec_align4; - - -/* Get SPI flash information */ -#define EC_CMD_FLASH_SPI_INFO 0x0018 - -struct ec_response_flash_spi_info { - /* JEDEC info from command 0x9F (manufacturer, memory type, size) */ - uint8_t jedec[3]; - - /* Pad byte; currently always contains 0 */ - uint8_t reserved0; - - /* Manufacturer / device ID from command 0x90 */ - uint8_t mfr_dev_id[2]; - - /* Status registers from command 0x05 and 0x35 */ - uint8_t sr1, sr2; -} __ec_align1; - - -/* Select flash during flash operations */ -#define EC_CMD_FLASH_SELECT 0x0019 - -/** - * struct ec_params_flash_select - Parameters for the flash select command. - * @select: 1 to select flash, 0 to deselect flash - */ -struct ec_params_flash_select { - uint8_t select; -} __ec_align4; - - -/*****************************************************************************/ -/* PWM commands */ - -/* Get fan target RPM */ -#define EC_CMD_PWM_GET_FAN_TARGET_RPM 0x0020 - -struct ec_response_pwm_get_fan_rpm { - uint32_t rpm; -} __ec_align4; - -/* Set target fan RPM */ -#define EC_CMD_PWM_SET_FAN_TARGET_RPM 0x0021 - -/* Version 0 of input params */ -struct ec_params_pwm_set_fan_target_rpm_v0 { - uint32_t rpm; -} __ec_align4; - -/* Version 1 of input params */ -struct ec_params_pwm_set_fan_target_rpm_v1 { - uint32_t rpm; - uint8_t fan_idx; -} __ec_align_size1; - -/* Get keyboard backlight */ -/* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ -#define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x0022 - -struct ec_response_pwm_get_keyboard_backlight { - uint8_t percent; - uint8_t enabled; -} __ec_align1; - -/* Set keyboard backlight */ -/* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ -#define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x0023 - -struct ec_params_pwm_set_keyboard_backlight { - uint8_t percent; -} __ec_align1; - -/* Set target fan PWM duty cycle */ -#define EC_CMD_PWM_SET_FAN_DUTY 0x0024 - -/* Version 0 of input params */ -struct ec_params_pwm_set_fan_duty_v0 { - uint32_t percent; -} __ec_align4; - -/* Version 1 of input params */ -struct ec_params_pwm_set_fan_duty_v1 { - uint32_t percent; - uint8_t fan_idx; -} __ec_align_size1; - -#define EC_CMD_PWM_SET_DUTY 0x0025 -/* 16 bit duty cycle, 0xffff = 100% */ -#define EC_PWM_MAX_DUTY 0xffff - -enum ec_pwm_type { - /* All types, indexed by board-specific enum pwm_channel */ - EC_PWM_TYPE_GENERIC = 0, - /* Keyboard backlight */ - EC_PWM_TYPE_KB_LIGHT, - /* Display backlight */ - EC_PWM_TYPE_DISPLAY_LIGHT, - EC_PWM_TYPE_COUNT, -}; - -struct ec_params_pwm_set_duty { - uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ - uint8_t pwm_type; /* ec_pwm_type */ - uint8_t index; /* Type-specific index, or 0 if unique */ -} __ec_align4; - -#define EC_CMD_PWM_GET_DUTY 0x0026 - -struct ec_params_pwm_get_duty { - uint8_t pwm_type; /* ec_pwm_type */ - uint8_t index; /* Type-specific index, or 0 if unique */ -} __ec_align1; - -struct ec_response_pwm_get_duty { - uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ -} __ec_align2; - -/*****************************************************************************/ -/* - * Lightbar commands. This looks worse than it is. Since we only use one HOST - * command to say "talk to the lightbar", we put the "and tell it to do X" part - * into a subcommand. We'll make separate structs for subcommands with - * different input args, so that we know how much to expect. - */ -#define EC_CMD_LIGHTBAR_CMD 0x0028 - -struct rgb_s { - uint8_t r, g, b; -} __ec_todo_unpacked; - -#define LB_BATTERY_LEVELS 4 - -/* - * List of tweakable parameters. NOTE: It's __packed so it can be sent in a - * host command, but the alignment is the same regardless. Keep it that way. - */ -struct lightbar_params_v0 { - /* Timing */ - int32_t google_ramp_up; - int32_t google_ramp_down; - int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ - int32_t s0s3_ramp_down; - int32_t s3_sleep_for; - int32_t s3_ramp_up; - int32_t s3_ramp_down; - - /* Oscillation */ - uint8_t new_s0; - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ - - /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ - - /* Battery level thresholds */ - uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; - - /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ - - /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ -} __ec_todo_packed; - -struct lightbar_params_v1 { - /* Timing */ - int32_t google_ramp_up; - int32_t google_ramp_down; - int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ - int32_t s0s3_ramp_down; - int32_t s3_sleep_for; - int32_t s3_ramp_up; - int32_t s3_ramp_down; - int32_t s5_ramp_up; - int32_t s5_ramp_down; - int32_t tap_tick_delay; - int32_t tap_gate_delay; - int32_t tap_display_time; - - /* Tap-for-battery params */ - uint8_t tap_pct_red; - uint8_t tap_pct_green; - uint8_t tap_seg_min_on; - uint8_t tap_seg_max_on; - uint8_t tap_seg_osc; - uint8_t tap_idx[3]; - - /* Oscillation */ - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ - - /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ - - /* Battery level thresholds */ - uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; - - /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ - - /* s5: single color pulse on inhibited power-up */ - uint8_t s5_idx; - - /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ -} __ec_todo_packed; - -/* Lightbar command params v2 - * crbug.com/467716 - * - * lightbar_parms_v1 was too big for i2c, therefore in v2, we split them up by - * logical groups to make it more manageable ( < 120 bytes). - * - * NOTE: Each of these groups must be less than 120 bytes. - */ - -struct lightbar_params_v2_timing { - /* Timing */ - int32_t google_ramp_up; - int32_t google_ramp_down; - int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ - int32_t s0s3_ramp_down; - int32_t s3_sleep_for; - int32_t s3_ramp_up; - int32_t s3_ramp_down; - int32_t s5_ramp_up; - int32_t s5_ramp_down; - int32_t tap_tick_delay; - int32_t tap_gate_delay; - int32_t tap_display_time; -} __ec_todo_packed; - -struct lightbar_params_v2_tap { - /* Tap-for-battery params */ - uint8_t tap_pct_red; - uint8_t tap_pct_green; - uint8_t tap_seg_min_on; - uint8_t tap_seg_max_on; - uint8_t tap_seg_osc; - uint8_t tap_idx[3]; -} __ec_todo_packed; - -struct lightbar_params_v2_oscillation { - /* Oscillation */ - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ -} __ec_todo_packed; - -struct lightbar_params_v2_brightness { - /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ -} __ec_todo_packed; - -struct lightbar_params_v2_thresholds { - /* Battery level thresholds */ - uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; -} __ec_todo_packed; - -struct lightbar_params_v2_colors { - /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ - - /* s5: single color pulse on inhibited power-up */ - uint8_t s5_idx; - - /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ -} __ec_todo_packed; - -/* Lightbar program. */ -#define EC_LB_PROG_LEN 192 -struct lightbar_program { - uint8_t size; - uint8_t data[EC_LB_PROG_LEN]; -} __ec_todo_unpacked; - -struct ec_params_lightbar { - uint8_t cmd; /* Command (see enum lightbar_command) */ - union { - /* - * The following commands have no args: - * - * dump, off, on, init, get_seq, get_params_v0, get_params_v1, - * version, get_brightness, get_demo, suspend, resume, - * get_params_v2_timing, get_params_v2_tap, get_params_v2_osc, - * get_params_v2_bright, get_params_v2_thlds, - * get_params_v2_colors - * - * Don't use an empty struct, because C++ hates that. - */ - - struct __ec_todo_unpacked { - uint8_t num; - } set_brightness, seq, demo; - - struct __ec_todo_unpacked { - uint8_t ctrl, reg, value; - } reg; - - struct __ec_todo_unpacked { - uint8_t led, red, green, blue; - } set_rgb; - - struct __ec_todo_unpacked { - uint8_t led; - } get_rgb; - - struct __ec_todo_unpacked { - uint8_t enable; - } manual_suspend_ctrl; - - struct lightbar_params_v0 set_params_v0; - struct lightbar_params_v1 set_params_v1; - - struct lightbar_params_v2_timing set_v2par_timing; - struct lightbar_params_v2_tap set_v2par_tap; - struct lightbar_params_v2_oscillation set_v2par_osc; - struct lightbar_params_v2_brightness set_v2par_bright; - struct lightbar_params_v2_thresholds set_v2par_thlds; - struct lightbar_params_v2_colors set_v2par_colors; - - struct lightbar_program set_program; - }; -} __ec_todo_packed; - -struct ec_response_lightbar { - union { - struct __ec_todo_unpacked { - struct __ec_todo_unpacked { - uint8_t reg; - uint8_t ic0; - uint8_t ic1; - } vals[23]; - } dump; - - struct __ec_todo_unpacked { - uint8_t num; - } get_seq, get_brightness, get_demo; - - struct lightbar_params_v0 get_params_v0; - struct lightbar_params_v1 get_params_v1; - - - struct lightbar_params_v2_timing get_params_v2_timing; - struct lightbar_params_v2_tap get_params_v2_tap; - struct lightbar_params_v2_oscillation get_params_v2_osc; - struct lightbar_params_v2_brightness get_params_v2_bright; - struct lightbar_params_v2_thresholds get_params_v2_thlds; - struct lightbar_params_v2_colors get_params_v2_colors; - - struct __ec_todo_unpacked { - uint32_t num; - uint32_t flags; - } version; - - struct __ec_todo_unpacked { - uint8_t red, green, blue; - } get_rgb; - - /* - * The following commands have no response: - * - * off, on, init, set_brightness, seq, reg, set_rgb, demo, - * set_params_v0, set_params_v1, set_program, - * manual_suspend_ctrl, suspend, resume, set_v2par_timing, - * set_v2par_tap, set_v2par_osc, set_v2par_bright, - * set_v2par_thlds, set_v2par_colors - */ - }; -} __ec_todo_packed; - -/* Lightbar commands */ -enum lightbar_command { - LIGHTBAR_CMD_DUMP = 0, - LIGHTBAR_CMD_OFF = 1, - LIGHTBAR_CMD_ON = 2, - LIGHTBAR_CMD_INIT = 3, - LIGHTBAR_CMD_SET_BRIGHTNESS = 4, - LIGHTBAR_CMD_SEQ = 5, - LIGHTBAR_CMD_REG = 6, - LIGHTBAR_CMD_SET_RGB = 7, - LIGHTBAR_CMD_GET_SEQ = 8, - LIGHTBAR_CMD_DEMO = 9, - LIGHTBAR_CMD_GET_PARAMS_V0 = 10, - LIGHTBAR_CMD_SET_PARAMS_V0 = 11, - LIGHTBAR_CMD_VERSION = 12, - LIGHTBAR_CMD_GET_BRIGHTNESS = 13, - LIGHTBAR_CMD_GET_RGB = 14, - LIGHTBAR_CMD_GET_DEMO = 15, - LIGHTBAR_CMD_GET_PARAMS_V1 = 16, - LIGHTBAR_CMD_SET_PARAMS_V1 = 17, - LIGHTBAR_CMD_SET_PROGRAM = 18, - LIGHTBAR_CMD_MANUAL_SUSPEND_CTRL = 19, - LIGHTBAR_CMD_SUSPEND = 20, - LIGHTBAR_CMD_RESUME = 21, - LIGHTBAR_CMD_GET_PARAMS_V2_TIMING = 22, - LIGHTBAR_CMD_SET_PARAMS_V2_TIMING = 23, - LIGHTBAR_CMD_GET_PARAMS_V2_TAP = 24, - LIGHTBAR_CMD_SET_PARAMS_V2_TAP = 25, - LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION = 26, - LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION = 27, - LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS = 28, - LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS = 29, - LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS = 30, - LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31, - LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32, - LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33, - LIGHTBAR_NUM_CMDS -}; - -/*****************************************************************************/ -/* LED control commands */ - -#define EC_CMD_LED_CONTROL 0x0029 - -enum ec_led_id { - /* LED to indicate battery state of charge */ - EC_LED_ID_BATTERY_LED = 0, - /* - * LED to indicate system power state (on or in suspend). - * May be on power button or on C-panel. - */ - EC_LED_ID_POWER_LED, - /* LED on power adapter or its plug */ - EC_LED_ID_ADAPTER_LED, - /* LED to indicate left side */ - EC_LED_ID_LEFT_LED, - /* LED to indicate right side */ - EC_LED_ID_RIGHT_LED, - /* LED to indicate recovery mode with HW_REINIT */ - EC_LED_ID_RECOVERY_HW_REINIT_LED, - /* LED to indicate sysrq debug mode. */ - EC_LED_ID_SYSRQ_DEBUG_LED, - - EC_LED_ID_COUNT -}; - -/* LED control flags */ -#define EC_LED_FLAGS_QUERY BIT(0) /* Query LED capability only */ -#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */ - -enum ec_led_colors { - EC_LED_COLOR_RED = 0, - EC_LED_COLOR_GREEN, - EC_LED_COLOR_BLUE, - EC_LED_COLOR_YELLOW, - EC_LED_COLOR_WHITE, - EC_LED_COLOR_AMBER, - - EC_LED_COLOR_COUNT -}; - -struct ec_params_led_control { - uint8_t led_id; /* Which LED to control */ - uint8_t flags; /* Control flags */ - - uint8_t brightness[EC_LED_COLOR_COUNT]; -} __ec_align1; - -struct ec_response_led_control { - /* - * Available brightness value range. - * - * Range 0 means color channel not present. - * Range 1 means on/off control. - * Other values means the LED is control by PWM. - */ - uint8_t brightness_range[EC_LED_COLOR_COUNT]; -} __ec_align1; - -/*****************************************************************************/ -/* Verified boot commands */ - -/* - * Note: command code 0x29 version 0 was VBOOT_CMD in Link EVT; it may be - * reused for other purposes with version > 0. - */ - -/* Verified boot hash command */ -#define EC_CMD_VBOOT_HASH 0x002A - -struct ec_params_vboot_hash { - uint8_t cmd; /* enum ec_vboot_hash_cmd */ - uint8_t hash_type; /* enum ec_vboot_hash_type */ - uint8_t nonce_size; /* Nonce size; may be 0 */ - uint8_t reserved0; /* Reserved; set 0 */ - uint32_t offset; /* Offset in flash to hash */ - uint32_t size; /* Number of bytes to hash */ - uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */ -} __ec_align4; - -struct ec_response_vboot_hash { - uint8_t status; /* enum ec_vboot_hash_status */ - uint8_t hash_type; /* enum ec_vboot_hash_type */ - uint8_t digest_size; /* Size of hash digest in bytes */ - uint8_t reserved0; /* Ignore; will be 0 */ - uint32_t offset; /* Offset in flash which was hashed */ - uint32_t size; /* Number of bytes hashed */ - uint8_t hash_digest[64]; /* Hash digest data */ -} __ec_align4; - -enum ec_vboot_hash_cmd { - EC_VBOOT_HASH_GET = 0, /* Get current hash status */ - EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */ - EC_VBOOT_HASH_START = 2, /* Start computing a new hash */ - EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */ -}; - -enum ec_vboot_hash_type { - EC_VBOOT_HASH_TYPE_SHA256 = 0, /* SHA-256 */ -}; - -enum ec_vboot_hash_status { - EC_VBOOT_HASH_STATUS_NONE = 0, /* No hash (not started, or aborted) */ - EC_VBOOT_HASH_STATUS_DONE = 1, /* Finished computing a hash */ - EC_VBOOT_HASH_STATUS_BUSY = 2, /* Busy computing a hash */ -}; - -/* - * Special values for offset for EC_VBOOT_HASH_START and EC_VBOOT_HASH_RECALC. - * If one of these is specified, the EC will automatically update offset and - * size to the correct values for the specified image (RO or RW). - */ -#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe -#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd -#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc - -/* - * 'RW' is vague if there are multiple RW images; we mean the active one, - * so the old constant is deprecated. - */ -#define EC_VBOOT_HASH_OFFSET_RW EC_VBOOT_HASH_OFFSET_ACTIVE - -/*****************************************************************************/ -/* - * Motion sense commands. We'll make separate structs for sub-commands with - * different input args, so that we know how much to expect. - */ -#define EC_CMD_MOTION_SENSE_CMD 0x002B - -/* Motion sense commands */ -enum motionsense_command { - /* - * Dump command returns all motion sensor data including motion sense - * module flags and individual sensor flags. - */ - MOTIONSENSE_CMD_DUMP = 0, - - /* - * Info command returns data describing the details of a given sensor, - * including enum motionsensor_type, enum motionsensor_location, and - * enum motionsensor_chip. - */ - MOTIONSENSE_CMD_INFO = 1, - - /* - * EC Rate command is a setter/getter command for the EC sampling rate - * in milliseconds. - * It is per sensor, the EC run sample task at the minimum of all - * sensors EC_RATE. - * For sensors without hardware FIFO, EC_RATE should be equals to 1/ODR - * to collect all the sensor samples. - * For sensor with hardware FIFO, EC_RATE is used as the maximal delay - * to process of all motion sensors in milliseconds. - */ - MOTIONSENSE_CMD_EC_RATE = 2, - - /* - * Sensor ODR command is a setter/getter command for the output data - * rate of a specific motion sensor in millihertz. - */ - MOTIONSENSE_CMD_SENSOR_ODR = 3, - - /* - * Sensor range command is a setter/getter command for the range of - * a specified motion sensor in +/-G's or +/- deg/s. - */ - MOTIONSENSE_CMD_SENSOR_RANGE = 4, - - /* - * Setter/getter command for the keyboard wake angle. When the lid - * angle is greater than this value, keyboard wake is disabled in S3, - * and when the lid angle goes less than this value, keyboard wake is - * enabled. Note, the lid angle measurement is an approximate, - * un-calibrated value, hence the wake angle isn't exact. - */ - MOTIONSENSE_CMD_KB_WAKE_ANGLE = 5, - - /* - * Returns a single sensor data. - */ - MOTIONSENSE_CMD_DATA = 6, - - /* - * Return sensor fifo info. - */ - MOTIONSENSE_CMD_FIFO_INFO = 7, - - /* - * Insert a flush element in the fifo and return sensor fifo info. - * The host can use that element to synchronize its operation. - */ - MOTIONSENSE_CMD_FIFO_FLUSH = 8, - - /* - * Return a portion of the fifo. - */ - MOTIONSENSE_CMD_FIFO_READ = 9, - - /* - * Perform low level calibration. - * On sensors that support it, ask to do offset calibration. - */ - MOTIONSENSE_CMD_PERFORM_CALIB = 10, - - /* - * Sensor Offset command is a setter/getter command for the offset - * used for calibration. - * The offsets can be calculated by the host, or via - * PERFORM_CALIB command. - */ - MOTIONSENSE_CMD_SENSOR_OFFSET = 11, - - /* - * List available activities for a MOTION sensor. - * Indicates if they are enabled or disabled. - */ - MOTIONSENSE_CMD_LIST_ACTIVITIES = 12, - - /* - * Activity management - * Enable/Disable activity recognition. - */ - MOTIONSENSE_CMD_SET_ACTIVITY = 13, - - /* - * Lid Angle - */ - MOTIONSENSE_CMD_LID_ANGLE = 14, - - /* - * Allow the FIFO to trigger interrupt via MKBP events. - * By default the FIFO does not send interrupt to process the FIFO - * until the AP is ready or it is coming from a wakeup sensor. - */ - MOTIONSENSE_CMD_FIFO_INT_ENABLE = 15, - - /* - * Spoof the readings of the sensors. The spoofed readings can be set - * to arbitrary values, or will lock to the last read actual values. - */ - MOTIONSENSE_CMD_SPOOF = 16, - - /* Set lid angle for tablet mode detection. */ - MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE = 17, - - /* - * Sensor Scale command is a setter/getter command for the calibration - * scale. - */ - MOTIONSENSE_CMD_SENSOR_SCALE = 18, - - /* Number of motionsense sub-commands. */ - MOTIONSENSE_NUM_CMDS -}; - -/* List of motion sensor types. */ -enum motionsensor_type { - MOTIONSENSE_TYPE_ACCEL = 0, - MOTIONSENSE_TYPE_GYRO = 1, - MOTIONSENSE_TYPE_MAG = 2, - MOTIONSENSE_TYPE_PROX = 3, - MOTIONSENSE_TYPE_LIGHT = 4, - MOTIONSENSE_TYPE_ACTIVITY = 5, - MOTIONSENSE_TYPE_BARO = 6, - MOTIONSENSE_TYPE_SYNC = 7, - MOTIONSENSE_TYPE_MAX, -}; - -/* List of motion sensor locations. */ -enum motionsensor_location { - MOTIONSENSE_LOC_BASE = 0, - MOTIONSENSE_LOC_LID = 1, - MOTIONSENSE_LOC_CAMERA = 2, - MOTIONSENSE_LOC_MAX, -}; - -/* List of motion sensor chips. */ -enum motionsensor_chip { - MOTIONSENSE_CHIP_KXCJ9 = 0, - MOTIONSENSE_CHIP_LSM6DS0 = 1, - MOTIONSENSE_CHIP_BMI160 = 2, - MOTIONSENSE_CHIP_SI1141 = 3, - MOTIONSENSE_CHIP_SI1142 = 4, - MOTIONSENSE_CHIP_SI1143 = 5, - MOTIONSENSE_CHIP_KX022 = 6, - MOTIONSENSE_CHIP_L3GD20H = 7, - MOTIONSENSE_CHIP_BMA255 = 8, - MOTIONSENSE_CHIP_BMP280 = 9, - MOTIONSENSE_CHIP_OPT3001 = 10, - MOTIONSENSE_CHIP_BH1730 = 11, - MOTIONSENSE_CHIP_GPIO = 12, - MOTIONSENSE_CHIP_LIS2DH = 13, - MOTIONSENSE_CHIP_LSM6DSM = 14, - MOTIONSENSE_CHIP_LIS2DE = 15, - MOTIONSENSE_CHIP_LIS2MDL = 16, - MOTIONSENSE_CHIP_LSM6DS3 = 17, - MOTIONSENSE_CHIP_LSM6DSO = 18, - MOTIONSENSE_CHIP_LNG2DM = 19, - MOTIONSENSE_CHIP_MAX, -}; - -/* List of orientation positions */ -enum motionsensor_orientation { - MOTIONSENSE_ORIENTATION_LANDSCAPE = 0, - MOTIONSENSE_ORIENTATION_PORTRAIT = 1, - MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_PORTRAIT = 2, - MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE = 3, - MOTIONSENSE_ORIENTATION_UNKNOWN = 4, -}; - -struct ec_response_motion_sensor_data { - /* Flags for each sensor. */ - uint8_t flags; - /* Sensor number the data comes from. */ - uint8_t sensor_num; - /* Each sensor is up to 3-axis. */ - union { - int16_t data[3]; - struct __ec_todo_packed { - uint16_t reserved; - uint32_t timestamp; - }; - struct __ec_todo_unpacked { - uint8_t activity; /* motionsensor_activity */ - uint8_t state; - int16_t add_info[2]; - }; - }; -} __ec_todo_packed; - -/* Note: used in ec_response_get_next_data */ -struct ec_response_motion_sense_fifo_info { - /* Size of the fifo */ - uint16_t size; - /* Amount of space used in the fifo */ - uint16_t count; - /* Timestamp recorded in us. - * aka accurate timestamp when host event was triggered. - */ - uint32_t timestamp; - /* Total amount of vector lost */ - uint16_t total_lost; - /* Lost events since the last fifo_info, per sensors */ - uint16_t lost[0]; -} __ec_todo_packed; - -struct ec_response_motion_sense_fifo_data { - uint32_t number_data; - struct ec_response_motion_sensor_data data[0]; -} __ec_todo_packed; - -/* List supported activity recognition */ -enum motionsensor_activity { - MOTIONSENSE_ACTIVITY_RESERVED = 0, - MOTIONSENSE_ACTIVITY_SIG_MOTION = 1, - MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2, - MOTIONSENSE_ACTIVITY_ORIENTATION = 3, -}; - -struct ec_motion_sense_activity { - uint8_t sensor_num; - uint8_t activity; /* one of enum motionsensor_activity */ - uint8_t enable; /* 1: enable, 0: disable */ - uint8_t reserved; - uint16_t parameters[3]; /* activity dependent parameters */ -} __ec_todo_unpacked; - -/* Module flag masks used for the dump sub-command. */ -#define MOTIONSENSE_MODULE_FLAG_ACTIVE BIT(0) - -/* Sensor flag masks used for the dump sub-command. */ -#define MOTIONSENSE_SENSOR_FLAG_PRESENT BIT(0) - -/* - * Flush entry for synchronization. - * data contains time stamp - */ -#define MOTIONSENSE_SENSOR_FLAG_FLUSH BIT(0) -#define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP BIT(1) -#define MOTIONSENSE_SENSOR_FLAG_WAKEUP BIT(2) -#define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE BIT(3) -#define MOTIONSENSE_SENSOR_FLAG_ODR BIT(4) - -/* - * Send this value for the data element to only perform a read. If you - * send any other value, the EC will interpret it as data to set and will - * return the actual value set. - */ -#define EC_MOTION_SENSE_NO_VALUE -1 - -#define EC_MOTION_SENSE_INVALID_CALIB_TEMP 0x8000 - -/* MOTIONSENSE_CMD_SENSOR_OFFSET subcommand flag */ -/* Set Calibration information */ -#define MOTION_SENSE_SET_OFFSET BIT(0) - -/* Default Scale value, factor 1. */ -#define MOTION_SENSE_DEFAULT_SCALE BIT(15) - -#define LID_ANGLE_UNRELIABLE 500 - -enum motionsense_spoof_mode { - /* Disable spoof mode. */ - MOTIONSENSE_SPOOF_MODE_DISABLE = 0, - - /* Enable spoof mode, but use provided component values. */ - MOTIONSENSE_SPOOF_MODE_CUSTOM, - - /* Enable spoof mode, but use the current sensor values. */ - MOTIONSENSE_SPOOF_MODE_LOCK_CURRENT, - - /* Query the current spoof mode status for the sensor. */ - MOTIONSENSE_SPOOF_MODE_QUERY, -}; - -struct ec_params_motion_sense { - uint8_t cmd; - union { - /* Used for MOTIONSENSE_CMD_DUMP. */ - struct __ec_todo_unpacked { - /* - * Maximal number of sensor the host is expecting. - * 0 means the host is only interested in the number - * of sensors controlled by the EC. - */ - uint8_t max_sensor_count; - } dump; - - /* - * Used for MOTIONSENSE_CMD_KB_WAKE_ANGLE. - */ - struct __ec_todo_unpacked { - /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. - * kb_wake_angle: angle to wakup AP. - */ - int16_t data; - } kb_wake_angle; - - /* - * Used for MOTIONSENSE_CMD_INFO, MOTIONSENSE_CMD_DATA - * and MOTIONSENSE_CMD_PERFORM_CALIB. - */ - struct __ec_todo_unpacked { - uint8_t sensor_num; - } info, info_3, data, fifo_flush, perform_calib, - list_activities; - - /* - * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR - * and MOTIONSENSE_CMD_SENSOR_RANGE. - */ - struct __ec_todo_unpacked { - uint8_t sensor_num; - - /* Rounding flag, true for round-up, false for down. */ - uint8_t roundup; - - uint16_t reserved; - - /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. */ - int32_t data; - } ec_rate, sensor_odr, sensor_range; - - /* Used for MOTIONSENSE_CMD_SENSOR_OFFSET */ - struct __ec_todo_packed { - uint8_t sensor_num; - - /* - * bit 0: If set (MOTION_SENSE_SET_OFFSET), set - * the calibration information in the EC. - * If unset, just retrieve calibration information. - */ - uint16_t flags; - - /* - * Temperature at calibration, in units of 0.01 C - * 0x8000: invalid / unknown. - * 0x0: 0C - * 0x7fff: +327.67C - */ - int16_t temp; - - /* - * Offset for calibration. - * Unit: - * Accelerometer: 1/1024 g - * Gyro: 1/1024 deg/s - * Compass: 1/16 uT - */ - int16_t offset[3]; - } sensor_offset; - - /* Used for MOTIONSENSE_CMD_SENSOR_SCALE */ - struct __ec_todo_packed { - uint8_t sensor_num; - - /* - * bit 0: If set (MOTION_SENSE_SET_OFFSET), set - * the calibration information in the EC. - * If unset, just retrieve calibration information. - */ - uint16_t flags; - - /* - * Temperature at calibration, in units of 0.01 C - * 0x8000: invalid / unknown. - * 0x0: 0C - * 0x7fff: +327.67C - */ - int16_t temp; - - /* - * Scale for calibration: - * By default scale is 1, it is encoded on 16bits: - * 1 = BIT(15) - * ~2 = 0xFFFF - * ~0 = 0. - */ - uint16_t scale[3]; - } sensor_scale; - - - /* Used for MOTIONSENSE_CMD_FIFO_INFO */ - /* (no params) */ - - /* Used for MOTIONSENSE_CMD_FIFO_READ */ - struct __ec_todo_unpacked { - /* - * Number of expected vector to return. - * EC may return less or 0 if none available. - */ - uint32_t max_data_vector; - } fifo_read; - - struct ec_motion_sense_activity set_activity; - - /* Used for MOTIONSENSE_CMD_LID_ANGLE */ - /* (no params) */ - - /* Used for MOTIONSENSE_CMD_FIFO_INT_ENABLE */ - struct __ec_todo_unpacked { - /* - * 1: enable, 0 disable fifo, - * EC_MOTION_SENSE_NO_VALUE return value. - */ - int8_t enable; - } fifo_int_enable; - - /* Used for MOTIONSENSE_CMD_SPOOF */ - struct __ec_todo_packed { - uint8_t sensor_id; - - /* See enum motionsense_spoof_mode. */ - uint8_t spoof_enable; - - /* Ignored, used for alignment. */ - uint8_t reserved; - - /* Individual component values to spoof. */ - int16_t components[3]; - } spoof; - - /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ - struct __ec_todo_unpacked { - /* - * Lid angle threshold for switching between tablet and - * clamshell mode. - */ - int16_t lid_angle; - - /* - * Hysteresis degree to prevent fluctuations between - * clamshell and tablet mode if lid angle keeps - * changing around the threshold. Lid motion driver will - * use lid_angle + hys_degree to trigger tablet mode and - * lid_angle - hys_degree to trigger clamshell mode. - */ - int16_t hys_degree; - } tablet_mode_threshold; - }; -} __ec_todo_packed; - -struct ec_response_motion_sense { - union { - /* Used for MOTIONSENSE_CMD_DUMP */ - struct __ec_todo_unpacked { - /* Flags representing the motion sensor module. */ - uint8_t module_flags; - - /* Number of sensors managed directly by the EC. */ - uint8_t sensor_count; - - /* - * Sensor data is truncated if response_max is too small - * for holding all the data. - */ - struct ec_response_motion_sensor_data sensor[0]; - } dump; - - /* Used for MOTIONSENSE_CMD_INFO. */ - struct __ec_todo_unpacked { - /* Should be element of enum motionsensor_type. */ - uint8_t type; - - /* Should be element of enum motionsensor_location. */ - uint8_t location; - - /* Should be element of enum motionsensor_chip. */ - uint8_t chip; - } info; - - /* Used for MOTIONSENSE_CMD_INFO version 3 */ - struct __ec_todo_unpacked { - /* Should be element of enum motionsensor_type. */ - uint8_t type; - - /* Should be element of enum motionsensor_location. */ - uint8_t location; - - /* Should be element of enum motionsensor_chip. */ - uint8_t chip; - - /* Minimum sensor sampling frequency */ - uint32_t min_frequency; - - /* Maximum sensor sampling frequency */ - uint32_t max_frequency; - - /* Max number of sensor events that could be in fifo */ - uint32_t fifo_max_event_count; - } info_3; - - /* Used for MOTIONSENSE_CMD_DATA */ - struct ec_response_motion_sensor_data data; - - /* - * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR, - * MOTIONSENSE_CMD_SENSOR_RANGE, - * MOTIONSENSE_CMD_KB_WAKE_ANGLE, - * MOTIONSENSE_CMD_FIFO_INT_ENABLE and - * MOTIONSENSE_CMD_SPOOF. - */ - struct __ec_todo_unpacked { - /* Current value of the parameter queried. */ - int32_t ret; - } ec_rate, sensor_odr, sensor_range, kb_wake_angle, - fifo_int_enable, spoof; - - /* - * Used for MOTIONSENSE_CMD_SENSOR_OFFSET, - * PERFORM_CALIB. - */ - struct __ec_todo_unpacked { - int16_t temp; - int16_t offset[3]; - } sensor_offset, perform_calib; - - /* Used for MOTIONSENSE_CMD_SENSOR_SCALE */ - struct __ec_todo_unpacked { - int16_t temp; - uint16_t scale[3]; - } sensor_scale; - - struct ec_response_motion_sense_fifo_info fifo_info, fifo_flush; - - struct ec_response_motion_sense_fifo_data fifo_read; - - struct __ec_todo_packed { - uint16_t reserved; - uint32_t enabled; - uint32_t disabled; - } list_activities; - - /* No params for set activity */ - - /* Used for MOTIONSENSE_CMD_LID_ANGLE */ - struct __ec_todo_unpacked { - /* - * Angle between 0 and 360 degree if available, - * LID_ANGLE_UNRELIABLE otherwise. - */ - uint16_t value; - } lid_angle; - - /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ - struct __ec_todo_unpacked { - /* - * Lid angle threshold for switching between tablet and - * clamshell mode. - */ - uint16_t lid_angle; - - /* Hysteresis degree. */ - uint16_t hys_degree; - } tablet_mode_threshold; - - }; -} __ec_todo_packed; - -/*****************************************************************************/ -/* Force lid open command */ - -/* Make lid event always open */ -#define EC_CMD_FORCE_LID_OPEN 0x002C - -struct ec_params_force_lid_open { - uint8_t enabled; -} __ec_align1; - -/*****************************************************************************/ -/* Configure the behavior of the power button */ -#define EC_CMD_CONFIG_POWER_BUTTON 0x002D - -enum ec_config_power_button_flags { - /* Enable/Disable power button pulses for x86 devices */ - EC_POWER_BUTTON_ENABLE_PULSE = BIT(0), -}; - -struct ec_params_config_power_button { - /* See enum ec_config_power_button_flags */ - uint8_t flags; -} __ec_align1; - -/*****************************************************************************/ -/* USB charging control commands */ - -/* Set USB port charging mode */ -#define EC_CMD_USB_CHARGE_SET_MODE 0x0030 - -struct ec_params_usb_charge_set_mode { - uint8_t usb_port_id; - uint8_t mode:7; - uint8_t inhibit_charge:1; -} __ec_align1; - -/*****************************************************************************/ -/* Persistent storage for host */ - -/* Maximum bytes that can be read/written in a single command */ -#define EC_PSTORE_SIZE_MAX 64 - -/* Get persistent storage info */ -#define EC_CMD_PSTORE_INFO 0x0040 - -struct ec_response_pstore_info { - /* Persistent storage size, in bytes */ - uint32_t pstore_size; - /* Access size; read/write offset and size must be a multiple of this */ - uint32_t access_size; -} __ec_align4; - -/* - * Read persistent storage - * - * Response is params.size bytes of data. - */ -#define EC_CMD_PSTORE_READ 0x0041 - -struct ec_params_pstore_read { - uint32_t offset; /* Byte offset to read */ - uint32_t size; /* Size to read in bytes */ -} __ec_align4; - -/* Write persistent storage */ -#define EC_CMD_PSTORE_WRITE 0x0042 - -struct ec_params_pstore_write { - uint32_t offset; /* Byte offset to write */ - uint32_t size; /* Size to write in bytes */ - uint8_t data[EC_PSTORE_SIZE_MAX]; -} __ec_align4; - -/*****************************************************************************/ -/* Real-time clock */ - -/* RTC params and response structures */ -struct ec_params_rtc { - uint32_t time; -} __ec_align4; - -struct ec_response_rtc { - uint32_t time; -} __ec_align4; - -/* These use ec_response_rtc */ -#define EC_CMD_RTC_GET_VALUE 0x0044 -#define EC_CMD_RTC_GET_ALARM 0x0045 - -/* These all use ec_params_rtc */ -#define EC_CMD_RTC_SET_VALUE 0x0046 -#define EC_CMD_RTC_SET_ALARM 0x0047 - -/* Pass as time param to SET_ALARM to clear the current alarm */ -#define EC_RTC_ALARM_CLEAR 0 - -/*****************************************************************************/ -/* Port80 log access */ - -/* Maximum entries that can be read/written in a single command */ -#define EC_PORT80_SIZE_MAX 32 - -/* Get last port80 code from previous boot */ -#define EC_CMD_PORT80_LAST_BOOT 0x0048 -#define EC_CMD_PORT80_READ 0x0048 - -enum ec_port80_subcmd { - EC_PORT80_GET_INFO = 0, - EC_PORT80_READ_BUFFER, -}; - -struct ec_params_port80_read { - uint16_t subcmd; - union { - struct __ec_todo_unpacked { - uint32_t offset; - uint32_t num_entries; - } read_buffer; - }; -} __ec_todo_packed; - -struct ec_response_port80_read { - union { - struct __ec_todo_unpacked { - uint32_t writes; - uint32_t history_size; - uint32_t last_boot; - } get_info; - struct __ec_todo_unpacked { - uint16_t codes[EC_PORT80_SIZE_MAX]; - } data; - }; -} __ec_todo_packed; - -struct ec_response_port80_last_boot { - uint16_t code; -} __ec_align2; - -/*****************************************************************************/ -/* Temporary secure storage for host verified boot use */ - -/* Number of bytes in a vstore slot */ -#define EC_VSTORE_SLOT_SIZE 64 - -/* Maximum number of vstore slots */ -#define EC_VSTORE_SLOT_MAX 32 - -/* Get persistent storage info */ -#define EC_CMD_VSTORE_INFO 0x0049 -struct ec_response_vstore_info { - /* Indicates which slots are locked */ - uint32_t slot_locked; - /* Total number of slots available */ - uint8_t slot_count; -} __ec_align_size1; - -/* - * Read temporary secure storage - * - * Response is EC_VSTORE_SLOT_SIZE bytes of data. - */ -#define EC_CMD_VSTORE_READ 0x004A - -struct ec_params_vstore_read { - uint8_t slot; /* Slot to read from */ -} __ec_align1; - -struct ec_response_vstore_read { - uint8_t data[EC_VSTORE_SLOT_SIZE]; -} __ec_align1; - -/* - * Write temporary secure storage and lock it. - */ -#define EC_CMD_VSTORE_WRITE 0x004B - -struct ec_params_vstore_write { - uint8_t slot; /* Slot to write to */ - uint8_t data[EC_VSTORE_SLOT_SIZE]; -} __ec_align1; - -/*****************************************************************************/ -/* Thermal engine commands. Note that there are two implementations. We'll - * reuse the command number, but the data and behavior is incompatible. - * Version 0 is what originally shipped on Link. - * Version 1 separates the CPU thermal limits from the fan control. - */ - -#define EC_CMD_THERMAL_SET_THRESHOLD 0x0050 -#define EC_CMD_THERMAL_GET_THRESHOLD 0x0051 - -/* The version 0 structs are opaque. You have to know what they are for - * the get/set commands to make any sense. - */ - -/* Version 0 - set */ -struct ec_params_thermal_set_threshold { - uint8_t sensor_type; - uint8_t threshold_id; - uint16_t value; -} __ec_align2; - -/* Version 0 - get */ -struct ec_params_thermal_get_threshold { - uint8_t sensor_type; - uint8_t threshold_id; -} __ec_align1; - -struct ec_response_thermal_get_threshold { - uint16_t value; -} __ec_align2; - - -/* The version 1 structs are visible. */ -enum ec_temp_thresholds { - EC_TEMP_THRESH_WARN = 0, - EC_TEMP_THRESH_HIGH, - EC_TEMP_THRESH_HALT, - - EC_TEMP_THRESH_COUNT -}; - -/* - * Thermal configuration for one temperature sensor. Temps are in degrees K. - * Zero values will be silently ignored by the thermal task. - * - * Set 'temp_host' value allows thermal task to trigger some event with 1 degree - * hysteresis. - * For example, - * temp_host[EC_TEMP_THRESH_HIGH] = 300 K - * temp_host_release[EC_TEMP_THRESH_HIGH] = 0 K - * EC will throttle ap when temperature >= 301 K, and release throttling when - * temperature <= 299 K. - * - * Set 'temp_host_release' value allows thermal task has a custom hysteresis. - * For example, - * temp_host[EC_TEMP_THRESH_HIGH] = 300 K - * temp_host_release[EC_TEMP_THRESH_HIGH] = 295 K - * EC will throttle ap when temperature >= 301 K, and release throttling when - * temperature <= 294 K. - * - * Note that this structure is a sub-structure of - * ec_params_thermal_set_threshold_v1, but maintains its alignment there. - */ -struct ec_thermal_config { - uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */ - uint32_t temp_host_release[EC_TEMP_THRESH_COUNT]; /* release levels */ - uint32_t temp_fan_off; /* no active cooling needed */ - uint32_t temp_fan_max; /* max active cooling needed */ -} __ec_align4; - -/* Version 1 - get config for one sensor. */ -struct ec_params_thermal_get_threshold_v1 { - uint32_t sensor_num; -} __ec_align4; -/* This returns a struct ec_thermal_config */ - -/* - * Version 1 - set config for one sensor. - * Use read-modify-write for best results! - */ -struct ec_params_thermal_set_threshold_v1 { - uint32_t sensor_num; - struct ec_thermal_config cfg; -} __ec_align4; -/* This returns no data */ - -/****************************************************************************/ - -/* Toggle automatic fan control */ -#define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x0052 - -/* Version 1 of input params */ -struct ec_params_auto_fan_ctrl_v1 { - uint8_t fan_idx; -} __ec_align1; - -/* Get/Set TMP006 calibration data */ -#define EC_CMD_TMP006_GET_CALIBRATION 0x0053 -#define EC_CMD_TMP006_SET_CALIBRATION 0x0054 - -/* - * The original TMP006 calibration only needed four params, but now we need - * more. Since the algorithm is nothing but magic numbers anyway, we'll leave - * the params opaque. The v1 "get" response will include the algorithm number - * and how many params it requires. That way we can change the EC code without - * needing to update this file. We can also use a different algorithm on each - * sensor. - */ - -/* This is the same struct for both v0 and v1. */ -struct ec_params_tmp006_get_calibration { - uint8_t index; -} __ec_align1; - -/* Version 0 */ -struct ec_response_tmp006_get_calibration_v0 { - float s0; - float b0; - float b1; - float b2; -} __ec_align4; - -struct ec_params_tmp006_set_calibration_v0 { - uint8_t index; - uint8_t reserved[3]; - float s0; - float b0; - float b1; - float b2; -} __ec_align4; - -/* Version 1 */ -struct ec_response_tmp006_get_calibration_v1 { - uint8_t algorithm; - uint8_t num_params; - uint8_t reserved[2]; - float val[0]; -} __ec_align4; - -struct ec_params_tmp006_set_calibration_v1 { - uint8_t index; - uint8_t algorithm; - uint8_t num_params; - uint8_t reserved; - float val[0]; -} __ec_align4; - - -/* Read raw TMP006 data */ -#define EC_CMD_TMP006_GET_RAW 0x0055 - -struct ec_params_tmp006_get_raw { - uint8_t index; -} __ec_align1; - -struct ec_response_tmp006_get_raw { - int32_t t; /* In 1/100 K */ - int32_t v; /* In nV */ -} __ec_align4; - -/*****************************************************************************/ -/* MKBP - Matrix KeyBoard Protocol */ - -/* - * Read key state - * - * Returns raw data for keyboard cols; see ec_response_mkbp_info.cols for - * expected response size. - * - * NOTE: This has been superseded by EC_CMD_MKBP_GET_NEXT_EVENT. If you wish - * to obtain the instantaneous state, use EC_CMD_MKBP_INFO with the type - * EC_MKBP_INFO_CURRENT and event EC_MKBP_EVENT_KEY_MATRIX. - */ -#define EC_CMD_MKBP_STATE 0x0060 - -/* - * Provide information about various MKBP things. See enum ec_mkbp_info_type. - */ -#define EC_CMD_MKBP_INFO 0x0061 - -struct ec_response_mkbp_info { - uint32_t rows; - uint32_t cols; - /* Formerly "switches", which was 0. */ - uint8_t reserved; -} __ec_align_size1; - -struct ec_params_mkbp_info { - uint8_t info_type; - uint8_t event_type; -} __ec_align1; - -enum ec_mkbp_info_type { - /* - * Info about the keyboard matrix: number of rows and columns. - * - * Returns struct ec_response_mkbp_info. - */ - EC_MKBP_INFO_KBD = 0, - - /* - * For buttons and switches, info about which specifically are - * supported. event_type must be set to one of the values in enum - * ec_mkbp_event. - * - * For EC_MKBP_EVENT_BUTTON and EC_MKBP_EVENT_SWITCH, returns a 4 byte - * bitmask indicating which buttons or switches are present. See the - * bit inidices below. - */ - EC_MKBP_INFO_SUPPORTED = 1, - - /* - * Instantaneous state of buttons and switches. - * - * event_type must be set to one of the values in enum ec_mkbp_event. - * - * For EC_MKBP_EVENT_KEY_MATRIX, returns uint8_t key_matrix[13] - * indicating the current state of the keyboard matrix. - * - * For EC_MKBP_EVENT_HOST_EVENT, return uint32_t host_event, the raw - * event state. - * - * For EC_MKBP_EVENT_BUTTON, returns uint32_t buttons, indicating the - * state of supported buttons. - * - * For EC_MKBP_EVENT_SWITCH, returns uint32_t switches, indicating the - * state of supported switches. - */ - EC_MKBP_INFO_CURRENT = 2, -}; - -/* Simulate key press */ -#define EC_CMD_MKBP_SIMULATE_KEY 0x0062 - -struct ec_params_mkbp_simulate_key { - uint8_t col; - uint8_t row; - uint8_t pressed; -} __ec_align1; - -#define EC_CMD_GET_KEYBOARD_ID 0x0063 - -struct ec_response_keyboard_id { - uint32_t keyboard_id; -} __ec_align4; - -enum keyboard_id { - KEYBOARD_ID_UNSUPPORTED = 0, - KEYBOARD_ID_UNREADABLE = 0xffffffff, -}; - -/* Configure keyboard scanning */ -#define EC_CMD_MKBP_SET_CONFIG 0x0064 -#define EC_CMD_MKBP_GET_CONFIG 0x0065 - -/* flags */ -enum mkbp_config_flags { - EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ -}; - -enum mkbp_config_valid { - EC_MKBP_VALID_SCAN_PERIOD = BIT(0), - EC_MKBP_VALID_POLL_TIMEOUT = BIT(1), - EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3), - EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4), - EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5), - EC_MKBP_VALID_DEBOUNCE_UP = BIT(6), - EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7), -}; - -/* - * Configuration for our key scanning algorithm. - * - * Note that this is used as a sub-structure of - * ec_{params/response}_mkbp_get_config. - */ -struct ec_mkbp_config { - uint32_t valid_mask; /* valid fields */ - uint8_t flags; /* some flags (enum mkbp_config_flags) */ - uint8_t valid_flags; /* which flags are valid */ - uint16_t scan_period_us; /* period between start of scans */ - /* revert to interrupt mode after no activity for this long */ - uint32_t poll_timeout_us; - /* - * minimum post-scan relax time. Once we finish a scan we check - * the time until we are due to start the next one. If this time is - * shorter this field, we use this instead. - */ - uint16_t min_post_scan_delay_us; - /* delay between setting up output and waiting for it to settle */ - uint16_t output_settle_us; - uint16_t debounce_down_us; /* time for debounce on key down */ - uint16_t debounce_up_us; /* time for debounce on key up */ - /* maximum depth to allow for fifo (0 = no keyscan output) */ - uint8_t fifo_max_depth; -} __ec_align_size1; - -struct ec_params_mkbp_set_config { - struct ec_mkbp_config config; -} __ec_align_size1; - -struct ec_response_mkbp_get_config { - struct ec_mkbp_config config; -} __ec_align_size1; - -/* Run the key scan emulation */ -#define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066 - -enum ec_keyscan_seq_cmd { - EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */ - EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */ - EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */ - EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */ - EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */ -}; - -enum ec_collect_flags { - /* - * Indicates this scan was processed by the EC. Due to timing, some - * scans may be skipped. - */ - EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0), -}; - -struct ec_collect_item { - uint8_t flags; /* some flags (enum ec_collect_flags) */ -} __ec_align1; - -struct ec_params_keyscan_seq_ctrl { - uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */ - union { - struct __ec_align1 { - uint8_t active; /* still active */ - uint8_t num_items; /* number of items */ - /* Current item being presented */ - uint8_t cur_item; - } status; - struct __ec_todo_unpacked { - /* - * Absolute time for this scan, measured from the - * start of the sequence. - */ - uint32_t time_us; - uint8_t scan[0]; /* keyscan data */ - } add; - struct __ec_align1 { - uint8_t start_item; /* First item to return */ - uint8_t num_items; /* Number of items to return */ - } collect; - }; -} __ec_todo_packed; - -struct ec_result_keyscan_seq_ctrl { - union { - struct __ec_todo_unpacked { - uint8_t num_items; /* Number of items */ - /* Data for each item */ - struct ec_collect_item item[0]; - } collect; - }; -} __ec_todo_packed; - -/* - * Get the next pending MKBP event. - * - * Returns EC_RES_UNAVAILABLE if there is no event pending. - */ -#define EC_CMD_GET_NEXT_EVENT 0x0067 - -#define EC_MKBP_HAS_MORE_EVENTS_SHIFT 7 - -/* - * We use the most significant bit of the event type to indicate to the host - * that the EC has more MKBP events available to provide. - */ -#define EC_MKBP_HAS_MORE_EVENTS BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) - -/* The mask to apply to get the raw event type */ -#define EC_MKBP_EVENT_TYPE_MASK (BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) - 1) - -enum ec_mkbp_event { - /* Keyboard matrix changed. The event data is the new matrix state. */ - EC_MKBP_EVENT_KEY_MATRIX = 0, - - /* New host event. The event data is 4 bytes of host event flags. */ - EC_MKBP_EVENT_HOST_EVENT = 1, - - /* New Sensor FIFO data. The event data is fifo_info structure. */ - EC_MKBP_EVENT_SENSOR_FIFO = 2, - - /* The state of the non-matrixed buttons have changed. */ - EC_MKBP_EVENT_BUTTON = 3, - - /* The state of the switches have changed. */ - EC_MKBP_EVENT_SWITCH = 4, - - /* New Fingerprint sensor event, the event data is fp_events bitmap. */ - EC_MKBP_EVENT_FINGERPRINT = 5, - - /* - * Sysrq event: send emulated sysrq. The event data is sysrq, - * corresponding to the key to be pressed. - */ - EC_MKBP_EVENT_SYSRQ = 6, - - /* - * New 64-bit host event. - * The event data is 8 bytes of host event flags. - */ - EC_MKBP_EVENT_HOST_EVENT64 = 7, - - /* Notify the AP that something happened on CEC */ - EC_MKBP_EVENT_CEC_EVENT = 8, - - /* Send an incoming CEC message to the AP */ - EC_MKBP_EVENT_CEC_MESSAGE = 9, - - /* Number of MKBP events */ - EC_MKBP_EVENT_COUNT, -}; -BUILD_ASSERT(EC_MKBP_EVENT_COUNT <= EC_MKBP_EVENT_TYPE_MASK); - -union __ec_align_offset1 ec_response_get_next_data { - uint8_t key_matrix[13]; - - /* Unaligned */ - uint32_t host_event; - uint64_t host_event64; - - struct __ec_todo_unpacked { - /* For aligning the fifo_info */ - uint8_t reserved[3]; - struct ec_response_motion_sense_fifo_info info; - } sensor_fifo; - - uint32_t buttons; - - uint32_t switches; - - uint32_t fp_events; - - uint32_t sysrq; - - /* CEC events from enum mkbp_cec_event */ - uint32_t cec_events; -}; - -union __ec_align_offset1 ec_response_get_next_data_v1 { - uint8_t key_matrix[16]; - - /* Unaligned */ - uint32_t host_event; - uint64_t host_event64; - - struct __ec_todo_unpacked { - /* For aligning the fifo_info */ - uint8_t reserved[3]; - struct ec_response_motion_sense_fifo_info info; - } sensor_fifo; - - uint32_t buttons; - - uint32_t switches; - - uint32_t fp_events; - - uint32_t sysrq; - - /* CEC events from enum mkbp_cec_event */ - uint32_t cec_events; - - uint8_t cec_message[16]; -}; -BUILD_ASSERT(sizeof(union ec_response_get_next_data_v1) == 16); - -struct ec_response_get_next_event { - uint8_t event_type; - /* Followed by event data if any */ - union ec_response_get_next_data data; -} __ec_align1; - -struct ec_response_get_next_event_v1 { - uint8_t event_type; - /* Followed by event data if any */ - union ec_response_get_next_data_v1 data; -} __ec_align1; - -/* Bit indices for buttons and switches.*/ -/* Buttons */ -#define EC_MKBP_POWER_BUTTON 0 -#define EC_MKBP_VOL_UP 1 -#define EC_MKBP_VOL_DOWN 2 -#define EC_MKBP_RECOVERY 3 - -/* Switches */ -#define EC_MKBP_LID_OPEN 0 -#define EC_MKBP_TABLET_MODE 1 -#define EC_MKBP_BASE_ATTACHED 2 - -/* Run keyboard factory test scanning */ -#define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068 - -struct ec_response_keyboard_factory_test { - uint16_t shorted; /* Keyboard pins are shorted */ -} __ec_align2; - -/* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */ -#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF) -#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events) & 0x0000000F) -#define EC_MKBP_FP_ENROLL_PROGRESS_OFFSET 4 -#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) (((fpe) & 0x00000FF0) \ - >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET) -#define EC_MKBP_FP_MATCH_IDX_OFFSET 12 -#define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000 -#define EC_MKBP_FP_MATCH_IDX(fpe) (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) \ - >> EC_MKBP_FP_MATCH_IDX_OFFSET) -#define EC_MKBP_FP_ENROLL BIT(27) -#define EC_MKBP_FP_MATCH BIT(28) -#define EC_MKBP_FP_FINGER_DOWN BIT(29) -#define EC_MKBP_FP_FINGER_UP BIT(30) -#define EC_MKBP_FP_IMAGE_READY BIT(31) -/* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_ENROLL is set */ -#define EC_MKBP_FP_ERR_ENROLL_OK 0 -#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1 -#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2 -#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3 -#define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5 -/* Can be used to detect if image was usable for enrollment or not. */ -#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1 -/* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_MATCH is set */ -#define EC_MKBP_FP_ERR_MATCH_NO 0 -#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6 -#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7 -#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2 -#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4 -#define EC_MKBP_FP_ERR_MATCH_YES 1 -#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3 -#define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5 - - -/*****************************************************************************/ -/* Temperature sensor commands */ - -/* Read temperature sensor info */ -#define EC_CMD_TEMP_SENSOR_GET_INFO 0x0070 - -struct ec_params_temp_sensor_get_info { - uint8_t id; -} __ec_align1; - -struct ec_response_temp_sensor_get_info { - char sensor_name[32]; - uint8_t sensor_type; -} __ec_align1; - -/*****************************************************************************/ - -/* - * Note: host commands 0x80 - 0x87 are reserved to avoid conflict with ACPI - * commands accidentally sent to the wrong interface. See the ACPI section - * below. - */ - -/*****************************************************************************/ -/* Host event commands */ - - -/* Obsolete. New implementation should use EC_CMD_HOST_EVENT instead */ -/* - * Host event mask params and response structures, shared by all of the host - * event commands below. - */ -struct ec_params_host_event_mask { - uint32_t mask; -} __ec_align4; - -struct ec_response_host_event_mask { - uint32_t mask; -} __ec_align4; - -/* These all use ec_response_host_event_mask */ -#define EC_CMD_HOST_EVENT_GET_B 0x0087 -#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088 -#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089 -#define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x008D - -/* These all use ec_params_host_event_mask */ -#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A -#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B -#define EC_CMD_HOST_EVENT_CLEAR 0x008C -#define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x008E -#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F - -/* - * Unified host event programming interface - Should be used by newer versions - * of BIOS/OS to program host events and masks - */ - -struct ec_params_host_event { - - /* Action requested by host - one of enum ec_host_event_action. */ - uint8_t action; - - /* - * Mask type that the host requested the action on - one of - * enum ec_host_event_mask_type. - */ - uint8_t mask_type; - - /* Set to 0, ignore on read */ - uint16_t reserved; - - /* Value to be used in case of set operations. */ - uint64_t value; -} __ec_align4; - -/* - * Response structure returned by EC_CMD_HOST_EVENT. - * Update the value on a GET request. Set to 0 on GET/CLEAR - */ - -struct ec_response_host_event { - - /* Mask value in case of get operation */ - uint64_t value; -} __ec_align4; - -enum ec_host_event_action { - /* - * params.value is ignored. Value of mask_type populated - * in response.value - */ - EC_HOST_EVENT_GET, - - /* Bits in params.value are set */ - EC_HOST_EVENT_SET, - - /* Bits in params.value are cleared */ - EC_HOST_EVENT_CLEAR, -}; - -enum ec_host_event_mask_type { - - /* Main host event copy */ - EC_HOST_EVENT_MAIN, - - /* Copy B of host events */ - EC_HOST_EVENT_B, - - /* SCI Mask */ - EC_HOST_EVENT_SCI_MASK, - - /* SMI Mask */ - EC_HOST_EVENT_SMI_MASK, - - /* Mask of events that should be always reported in hostevents */ - EC_HOST_EVENT_ALWAYS_REPORT_MASK, - - /* Active wake mask */ - EC_HOST_EVENT_ACTIVE_WAKE_MASK, - - /* Lazy wake mask for S0ix */ - EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX, - - /* Lazy wake mask for S3 */ - EC_HOST_EVENT_LAZY_WAKE_MASK_S3, - - /* Lazy wake mask for S5 */ - EC_HOST_EVENT_LAZY_WAKE_MASK_S5, -}; - -#define EC_CMD_HOST_EVENT 0x00A4 - -/*****************************************************************************/ -/* Switch commands */ - -/* Enable/disable LCD backlight */ -#define EC_CMD_SWITCH_ENABLE_BKLIGHT 0x0090 - -struct ec_params_switch_enable_backlight { - uint8_t enabled; -} __ec_align1; - -/* Enable/disable WLAN/Bluetooth */ -#define EC_CMD_SWITCH_ENABLE_WIRELESS 0x0091 -#define EC_VER_SWITCH_ENABLE_WIRELESS 1 - -/* Version 0 params; no response */ -struct ec_params_switch_enable_wireless_v0 { - uint8_t enabled; -} __ec_align1; - -/* Version 1 params */ -struct ec_params_switch_enable_wireless_v1 { - /* Flags to enable now */ - uint8_t now_flags; - - /* Which flags to copy from now_flags */ - uint8_t now_mask; - - /* - * Flags to leave enabled in S3, if they're on at the S0->S3 - * transition. (Other flags will be disabled by the S0->S3 - * transition.) - */ - uint8_t suspend_flags; - - /* Which flags to copy from suspend_flags */ - uint8_t suspend_mask; -} __ec_align1; - -/* Version 1 response */ -struct ec_response_switch_enable_wireless_v1 { - /* Flags to enable now */ - uint8_t now_flags; - - /* Flags to leave enabled in S3 */ - uint8_t suspend_flags; -} __ec_align1; - -/*****************************************************************************/ -/* GPIO commands. Only available on EC if write protect has been disabled. */ - -/* Set GPIO output value */ -#define EC_CMD_GPIO_SET 0x0092 - -struct ec_params_gpio_set { - char name[32]; - uint8_t val; -} __ec_align1; - -/* Get GPIO value */ -#define EC_CMD_GPIO_GET 0x0093 - -/* Version 0 of input params and response */ -struct ec_params_gpio_get { - char name[32]; -} __ec_align1; - -struct ec_response_gpio_get { - uint8_t val; -} __ec_align1; - -/* Version 1 of input params and response */ -struct ec_params_gpio_get_v1 { - uint8_t subcmd; - union { - struct __ec_align1 { - char name[32]; - } get_value_by_name; - struct __ec_align1 { - uint8_t index; - } get_info; - }; -} __ec_align1; - -struct ec_response_gpio_get_v1 { - union { - struct __ec_align1 { - uint8_t val; - } get_value_by_name, get_count; - struct __ec_todo_unpacked { - uint8_t val; - char name[32]; - uint32_t flags; - } get_info; - }; -} __ec_todo_packed; - -enum gpio_get_subcmd { - EC_GPIO_GET_BY_NAME = 0, - EC_GPIO_GET_COUNT = 1, - EC_GPIO_GET_INFO = 2, -}; - -/*****************************************************************************/ -/* I2C commands. Only available when flash write protect is unlocked. */ - -/* - * CAUTION: These commands are deprecated, and are not supported anymore in EC - * builds >= 8398.0.0 (see crosbug.com/p/23570). - * - * Use EC_CMD_I2C_PASSTHRU instead. - */ - -/* Read I2C bus */ -#define EC_CMD_I2C_READ 0x0094 - -struct ec_params_i2c_read { - uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ - uint8_t read_size; /* Either 8 or 16. */ - uint8_t port; - uint8_t offset; -} __ec_align_size1; - -struct ec_response_i2c_read { - uint16_t data; -} __ec_align2; - -/* Write I2C bus */ -#define EC_CMD_I2C_WRITE 0x0095 - -struct ec_params_i2c_write { - uint16_t data; - uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ - uint8_t write_size; /* Either 8 or 16. */ - uint8_t port; - uint8_t offset; -} __ec_align_size1; - -/*****************************************************************************/ -/* Charge state commands. Only available when flash write protect unlocked. */ - -/* Force charge state machine to stop charging the battery or force it to - * discharge the battery. - */ -#define EC_CMD_CHARGE_CONTROL 0x0096 -#define EC_VER_CHARGE_CONTROL 1 - -enum ec_charge_control_mode { - CHARGE_CONTROL_NORMAL = 0, - CHARGE_CONTROL_IDLE, - CHARGE_CONTROL_DISCHARGE, -}; - -struct ec_params_charge_control { - uint32_t mode; /* enum charge_control_mode */ -} __ec_align4; - -/*****************************************************************************/ - -/* Snapshot console output buffer for use by EC_CMD_CONSOLE_READ. */ -#define EC_CMD_CONSOLE_SNAPSHOT 0x0097 - -/* - * Read data from the saved snapshot. If the subcmd parameter is - * CONSOLE_READ_NEXT, this will return data starting from the beginning of - * the latest snapshot. If it is CONSOLE_READ_RECENT, it will start from the - * end of the previous snapshot. - * - * The params are only looked at in version >= 1 of this command. Prior - * versions will just default to CONSOLE_READ_NEXT behavior. - * - * Response is null-terminated string. Empty string, if there is no more - * remaining output. - */ -#define EC_CMD_CONSOLE_READ 0x0098 - -enum ec_console_read_subcmd { - CONSOLE_READ_NEXT = 0, - CONSOLE_READ_RECENT -}; - -struct ec_params_console_read_v1 { - uint8_t subcmd; /* enum ec_console_read_subcmd */ -} __ec_align1; - -/*****************************************************************************/ - -/* - * Cut off battery power immediately or after the host has shut down. - * - * return EC_RES_INVALID_COMMAND if unsupported by a board/battery. - * EC_RES_SUCCESS if the command was successful. - * EC_RES_ERROR if the cut off command failed. - */ -#define EC_CMD_BATTERY_CUT_OFF 0x0099 - -#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0) - -struct ec_params_battery_cutoff { - uint8_t flags; -} __ec_align1; - -/*****************************************************************************/ -/* USB port mux control. */ - -/* - * Switch USB mux or return to automatic switching. - */ -#define EC_CMD_USB_MUX 0x009A - -struct ec_params_usb_mux { - uint8_t mux; -} __ec_align1; - -/*****************************************************************************/ -/* LDOs / FETs control. */ - -enum ec_ldo_state { - EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */ - EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */ -}; - -/* - * Switch on/off a LDO. - */ -#define EC_CMD_LDO_SET 0x009B - -struct ec_params_ldo_set { - uint8_t index; - uint8_t state; -} __ec_align1; - -/* - * Get LDO state. - */ -#define EC_CMD_LDO_GET 0x009C - -struct ec_params_ldo_get { - uint8_t index; -} __ec_align1; - -struct ec_response_ldo_get { - uint8_t state; -} __ec_align1; - -/*****************************************************************************/ -/* Power info. */ - -/* - * Get power info. - */ -#define EC_CMD_POWER_INFO 0x009D - -struct ec_response_power_info { - uint32_t usb_dev_type; - uint16_t voltage_ac; - uint16_t voltage_system; - uint16_t current_system; - uint16_t usb_current_limit; -} __ec_align4; - -/*****************************************************************************/ -/* I2C passthru command */ - -#define EC_CMD_I2C_PASSTHRU 0x009E - -/* Read data; if not present, message is a write */ -#define EC_I2C_FLAG_READ BIT(15) - -/* Mask for address */ -#define EC_I2C_ADDR_MASK 0x3ff - -#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */ -#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */ - -/* Any error */ -#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) - -struct ec_params_i2c_passthru_msg { - uint16_t addr_flags; /* I2C slave address (7 or 10 bits) and flags */ - uint16_t len; /* Number of bytes to read or write */ -} __ec_align2; - -struct ec_params_i2c_passthru { - uint8_t port; /* I2C port number */ - uint8_t num_msgs; /* Number of messages */ - struct ec_params_i2c_passthru_msg msg[]; - /* Data to write for all messages is concatenated here */ -} __ec_align2; - -struct ec_response_i2c_passthru { - uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ - uint8_t num_msgs; /* Number of messages processed */ - uint8_t data[]; /* Data read by messages concatenated here */ -} __ec_align1; - -/*****************************************************************************/ -/* Power button hang detect */ - -#define EC_CMD_HANG_DETECT 0x009F - -/* Reasons to start hang detection timer */ -/* Power button pressed */ -#define EC_HANG_START_ON_POWER_PRESS BIT(0) - -/* Lid closed */ -#define EC_HANG_START_ON_LID_CLOSE BIT(1) - - /* Lid opened */ -#define EC_HANG_START_ON_LID_OPEN BIT(2) - -/* Start of AP S3->S0 transition (booting or resuming from suspend) */ -#define EC_HANG_START_ON_RESUME BIT(3) - -/* Reasons to cancel hang detection */ - -/* Power button released */ -#define EC_HANG_STOP_ON_POWER_RELEASE BIT(8) - -/* Any host command from AP received */ -#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9) - -/* Stop on end of AP S0->S3 transition (suspending or shutting down) */ -#define EC_HANG_STOP_ON_SUSPEND BIT(10) - -/* - * If this flag is set, all the other fields are ignored, and the hang detect - * timer is started. This provides the AP a way to start the hang timer - * without reconfiguring any of the other hang detect settings. Note that - * you must previously have configured the timeouts. - */ -#define EC_HANG_START_NOW BIT(30) - -/* - * If this flag is set, all the other fields are ignored (including - * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer - * without reconfiguring any of the other hang detect settings. - */ -#define EC_HANG_STOP_NOW BIT(31) - -struct ec_params_hang_detect { - /* Flags; see EC_HANG_* */ - uint32_t flags; - - /* Timeout in msec before generating host event, if enabled */ - uint16_t host_event_timeout_msec; - - /* Timeout in msec before generating warm reboot, if enabled */ - uint16_t warm_reboot_timeout_msec; -} __ec_align4; - -/*****************************************************************************/ -/* Commands for battery charging */ - -/* - * This is the single catch-all host command to exchange data regarding the - * charge state machine (v2 and up). - */ -#define EC_CMD_CHARGE_STATE 0x00A0 - -/* Subcommands for this host command */ -enum charge_state_command { - CHARGE_STATE_CMD_GET_STATE, - CHARGE_STATE_CMD_GET_PARAM, - CHARGE_STATE_CMD_SET_PARAM, - CHARGE_STATE_NUM_CMDS -}; - -/* - * Known param numbers are defined here. Ranges are reserved for board-specific - * params, which are handled by the particular implementations. - */ -enum charge_state_params { - CS_PARAM_CHG_VOLTAGE, /* charger voltage limit */ - CS_PARAM_CHG_CURRENT, /* charger current limit */ - CS_PARAM_CHG_INPUT_CURRENT, /* charger input current limit */ - CS_PARAM_CHG_STATUS, /* charger-specific status */ - CS_PARAM_CHG_OPTION, /* charger-specific options */ - CS_PARAM_LIMIT_POWER, /* - * Check if power is limited due to - * low battery and / or a weak external - * charger. READ ONLY. - */ - /* How many so far? */ - CS_NUM_BASE_PARAMS, - - /* Range for CONFIG_CHARGER_PROFILE_OVERRIDE params */ - CS_PARAM_CUSTOM_PROFILE_MIN = 0x10000, - CS_PARAM_CUSTOM_PROFILE_MAX = 0x1ffff, - - /* Range for CONFIG_CHARGE_STATE_DEBUG params */ - CS_PARAM_DEBUG_MIN = 0x20000, - CS_PARAM_DEBUG_CTL_MODE = 0x20000, - CS_PARAM_DEBUG_MANUAL_MODE, - CS_PARAM_DEBUG_SEEMS_DEAD, - CS_PARAM_DEBUG_SEEMS_DISCONNECTED, - CS_PARAM_DEBUG_BATT_REMOVED, - CS_PARAM_DEBUG_MANUAL_CURRENT, - CS_PARAM_DEBUG_MANUAL_VOLTAGE, - CS_PARAM_DEBUG_MAX = 0x2ffff, - - /* Other custom param ranges go here... */ -}; - -struct ec_params_charge_state { - uint8_t cmd; /* enum charge_state_command */ - union { - /* get_state has no args */ - - struct __ec_todo_unpacked { - uint32_t param; /* enum charge_state_param */ - } get_param; - - struct __ec_todo_unpacked { - uint32_t param; /* param to set */ - uint32_t value; /* value to set */ - } set_param; - }; -} __ec_todo_packed; - -struct ec_response_charge_state { - union { - struct __ec_align4 { - int ac; - int chg_voltage; - int chg_current; - int chg_input_current; - int batt_state_of_charge; - } get_state; - - struct __ec_align4 { - uint32_t value; - } get_param; - - /* set_param returns no args */ - }; -} __ec_align4; - - -/* - * Set maximum battery charging current. - */ -#define EC_CMD_CHARGE_CURRENT_LIMIT 0x00A1 - -struct ec_params_current_limit { - uint32_t limit; /* in mA */ -} __ec_align4; - -/* - * Set maximum external voltage / current. - */ -#define EC_CMD_EXTERNAL_POWER_LIMIT 0x00A2 - -/* Command v0 is used only on Spring and is obsolete + unsupported */ -struct ec_params_external_power_limit_v1 { - uint16_t current_lim; /* in mA, or EC_POWER_LIMIT_NONE to clear limit */ - uint16_t voltage_lim; /* in mV, or EC_POWER_LIMIT_NONE to clear limit */ -} __ec_align2; - -#define EC_POWER_LIMIT_NONE 0xffff - -/* - * Set maximum voltage & current of a dedicated charge port - */ -#define EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT 0x00A3 - -struct ec_params_dedicated_charger_limit { - uint16_t current_lim; /* in mA */ - uint16_t voltage_lim; /* in mV */ -} __ec_align2; - -/*****************************************************************************/ -/* Hibernate/Deep Sleep Commands */ - -/* Set the delay before going into hibernation. */ -#define EC_CMD_HIBERNATION_DELAY 0x00A8 - -struct ec_params_hibernation_delay { - /* - * Seconds to wait in G3 before hibernate. Pass in 0 to read the - * current settings without changing them. - */ - uint32_t seconds; -} __ec_align4; - -struct ec_response_hibernation_delay { - /* - * The current time in seconds in which the system has been in the G3 - * state. This value is reset if the EC transitions out of G3. - */ - uint32_t time_g3; - - /* - * The current time remaining in seconds until the EC should hibernate. - * This value is also reset if the EC transitions out of G3. - */ - uint32_t time_remaining; - - /* - * The current time in seconds that the EC should wait in G3 before - * hibernating. - */ - uint32_t hibernate_delay; -} __ec_align4; - -/* Inform the EC when entering a sleep state */ -#define EC_CMD_HOST_SLEEP_EVENT 0x00A9 - -enum host_sleep_event { - HOST_SLEEP_EVENT_S3_SUSPEND = 1, - HOST_SLEEP_EVENT_S3_RESUME = 2, - HOST_SLEEP_EVENT_S0IX_SUSPEND = 3, - HOST_SLEEP_EVENT_S0IX_RESUME = 4, - /* S3 suspend with additional enabled wake sources */ - HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5, -}; - -struct ec_params_host_sleep_event { - uint8_t sleep_event; -} __ec_align1; - -/* - * Use a default timeout value (CONFIG_SLEEP_TIMEOUT_MS) for detecting sleep - * transition failures - */ -#define EC_HOST_SLEEP_TIMEOUT_DEFAULT 0 - -/* Disable timeout detection for this sleep transition */ -#define EC_HOST_SLEEP_TIMEOUT_INFINITE 0xFFFF - -struct ec_params_host_sleep_event_v1 { - /* The type of sleep being entered or exited. */ - uint8_t sleep_event; - - /* Padding */ - uint8_t reserved; - union { - /* Parameters that apply for suspend messages. */ - struct { - /* - * The timeout in milliseconds between when this message - * is received and when the EC will declare sleep - * transition failure if the sleep signal is not - * asserted. - */ - uint16_t sleep_timeout_ms; - } suspend_params; - - /* No parameters for non-suspend messages. */ - }; -} __ec_align2; - -/* A timeout occurred when this bit is set */ -#define EC_HOST_RESUME_SLEEP_TIMEOUT 0x80000000 - -/* - * The mask defining which bits correspond to the number of sleep transitions, - * as well as the maximum number of suspend line transitions that will be - * reported back to the host. - */ -#define EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK 0x7FFFFFFF - -struct ec_response_host_sleep_event_v1 { - union { - /* Response fields that apply for resume messages. */ - struct { - /* - * The number of sleep power signal transitions that - * occurred since the suspend message. The high bit - * indicates a timeout occurred. - */ - uint32_t sleep_transitions; - } resume_response; - - /* No response fields for non-resume messages. */ - }; -} __ec_align4; - -/*****************************************************************************/ -/* Device events */ -#define EC_CMD_DEVICE_EVENT 0x00AA - -enum ec_device_event { - EC_DEVICE_EVENT_TRACKPAD, - EC_DEVICE_EVENT_DSP, - EC_DEVICE_EVENT_WIFI, -}; - -enum ec_device_event_param { - /* Get and clear pending device events */ - EC_DEVICE_EVENT_PARAM_GET_CURRENT_EVENTS, - /* Get device event mask */ - EC_DEVICE_EVENT_PARAM_GET_ENABLED_EVENTS, - /* Set device event mask */ - EC_DEVICE_EVENT_PARAM_SET_ENABLED_EVENTS, -}; - -#define EC_DEVICE_EVENT_MASK(event_code) BIT(event_code % 32) - -struct ec_params_device_event { - uint32_t event_mask; - uint8_t param; -} __ec_align_size1; - -struct ec_response_device_event { - uint32_t event_mask; -} __ec_align4; - -/*****************************************************************************/ -/* Smart battery pass-through */ - -/* Get / Set 16-bit smart battery registers */ -#define EC_CMD_SB_READ_WORD 0x00B0 -#define EC_CMD_SB_WRITE_WORD 0x00B1 - -/* Get / Set string smart battery parameters - * formatted as SMBUS "block". - */ -#define EC_CMD_SB_READ_BLOCK 0x00B2 -#define EC_CMD_SB_WRITE_BLOCK 0x00B3 - -struct ec_params_sb_rd { - uint8_t reg; -} __ec_align1; - -struct ec_response_sb_rd_word { - uint16_t value; -} __ec_align2; - -struct ec_params_sb_wr_word { - uint8_t reg; - uint16_t value; -} __ec_align1; - -struct ec_response_sb_rd_block { - uint8_t data[32]; -} __ec_align1; - -struct ec_params_sb_wr_block { - uint8_t reg; - uint16_t data[32]; -} __ec_align1; - -/*****************************************************************************/ -/* Battery vendor parameters - * - * Get or set vendor-specific parameters in the battery. Implementations may - * differ between boards or batteries. On a set operation, the response - * contains the actual value set, which may be rounded or clipped from the - * requested value. - */ - -#define EC_CMD_BATTERY_VENDOR_PARAM 0x00B4 - -enum ec_battery_vendor_param_mode { - BATTERY_VENDOR_PARAM_MODE_GET = 0, - BATTERY_VENDOR_PARAM_MODE_SET, -}; - -struct ec_params_battery_vendor_param { - uint32_t param; - uint32_t value; - uint8_t mode; -} __ec_align_size1; - -struct ec_response_battery_vendor_param { - uint32_t value; -} __ec_align4; - -/*****************************************************************************/ -/* - * Smart Battery Firmware Update Commands - */ -#define EC_CMD_SB_FW_UPDATE 0x00B5 - -enum ec_sb_fw_update_subcmd { - EC_SB_FW_UPDATE_PREPARE = 0x0, - EC_SB_FW_UPDATE_INFO = 0x1, /*query sb info */ - EC_SB_FW_UPDATE_BEGIN = 0x2, /*check if protected */ - EC_SB_FW_UPDATE_WRITE = 0x3, /*check if protected */ - EC_SB_FW_UPDATE_END = 0x4, - EC_SB_FW_UPDATE_STATUS = 0x5, - EC_SB_FW_UPDATE_PROTECT = 0x6, - EC_SB_FW_UPDATE_MAX = 0x7, -}; - -#define SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE 32 -#define SB_FW_UPDATE_CMD_STATUS_SIZE 2 -#define SB_FW_UPDATE_CMD_INFO_SIZE 8 - -struct ec_sb_fw_update_header { - uint16_t subcmd; /* enum ec_sb_fw_update_subcmd */ - uint16_t fw_id; /* firmware id */ -} __ec_align4; - -struct ec_params_sb_fw_update { - struct ec_sb_fw_update_header hdr; - union { - /* EC_SB_FW_UPDATE_PREPARE = 0x0 */ - /* EC_SB_FW_UPDATE_INFO = 0x1 */ - /* EC_SB_FW_UPDATE_BEGIN = 0x2 */ - /* EC_SB_FW_UPDATE_END = 0x4 */ - /* EC_SB_FW_UPDATE_STATUS = 0x5 */ - /* EC_SB_FW_UPDATE_PROTECT = 0x6 */ - /* Those have no args */ - - /* EC_SB_FW_UPDATE_WRITE = 0x3 */ - struct __ec_align4 { - uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE]; - } write; - }; -} __ec_align4; - -struct ec_response_sb_fw_update { - union { - /* EC_SB_FW_UPDATE_INFO = 0x1 */ - struct __ec_align1 { - uint8_t data[SB_FW_UPDATE_CMD_INFO_SIZE]; - } info; - - /* EC_SB_FW_UPDATE_STATUS = 0x5 */ - struct __ec_align1 { - uint8_t data[SB_FW_UPDATE_CMD_STATUS_SIZE]; - } status; - }; -} __ec_align1; - -/* - * Entering Verified Boot Mode Command - * Default mode is VBOOT_MODE_NORMAL if EC did not receive this command. - * Valid Modes are: normal, developer, and recovery. - */ -#define EC_CMD_ENTERING_MODE 0x00B6 - -struct ec_params_entering_mode { - int vboot_mode; -} __ec_align4; - -#define VBOOT_MODE_NORMAL 0 -#define VBOOT_MODE_DEVELOPER 1 -#define VBOOT_MODE_RECOVERY 2 - -/*****************************************************************************/ -/* - * I2C passthru protection command: Protects I2C tunnels against access on - * certain addresses (board-specific). - */ -#define EC_CMD_I2C_PASSTHRU_PROTECT 0x00B7 - -enum ec_i2c_passthru_protect_subcmd { - EC_CMD_I2C_PASSTHRU_PROTECT_STATUS = 0x0, - EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 0x1, -}; - -struct ec_params_i2c_passthru_protect { - uint8_t subcmd; - uint8_t port; /* I2C port number */ -} __ec_align1; - -struct ec_response_i2c_passthru_protect { - uint8_t status; /* Status flags (0: unlocked, 1: locked) */ -} __ec_align1; - - -/*****************************************************************************/ -/* - * HDMI CEC commands - * - * These commands are for sending and receiving message via HDMI CEC - */ - -#define MAX_CEC_MSG_LEN 16 - -/* CEC message from the AP to be written on the CEC bus */ -#define EC_CMD_CEC_WRITE_MSG 0x00B8 - -/** - * struct ec_params_cec_write - Message to write to the CEC bus - * @msg: message content to write to the CEC bus - */ -struct ec_params_cec_write { - uint8_t msg[MAX_CEC_MSG_LEN]; -} __ec_align1; - -/* Set various CEC parameters */ -#define EC_CMD_CEC_SET 0x00BA - -/** - * struct ec_params_cec_set - CEC parameters set - * @cmd: parameter type, can be CEC_CMD_ENABLE or CEC_CMD_LOGICAL_ADDRESS - * @val: in case cmd is CEC_CMD_ENABLE, this field can be 0 to disable CEC - * or 1 to enable CEC functionality, in case cmd is - * CEC_CMD_LOGICAL_ADDRESS, this field encodes the requested logical - * address between 0 and 15 or 0xff to unregister - */ -struct ec_params_cec_set { - uint8_t cmd; /* enum cec_command */ - uint8_t val; -} __ec_align1; - -/* Read various CEC parameters */ -#define EC_CMD_CEC_GET 0x00BB - -/** - * struct ec_params_cec_get - CEC parameters get - * @cmd: parameter type, can be CEC_CMD_ENABLE or CEC_CMD_LOGICAL_ADDRESS - */ -struct ec_params_cec_get { - uint8_t cmd; /* enum cec_command */ -} __ec_align1; - -/** - * struct ec_response_cec_get - CEC parameters get response - * @val: in case cmd was CEC_CMD_ENABLE, this field will 0 if CEC is - * disabled or 1 if CEC functionality is enabled, - * in case cmd was CEC_CMD_LOGICAL_ADDRESS, this will encode the - * configured logical address between 0 and 15 or 0xff if unregistered - */ -struct ec_response_cec_get { - uint8_t val; -} __ec_align1; - -/* CEC parameters command */ -enum cec_command { - /* CEC reading, writing and events enable */ - CEC_CMD_ENABLE, - /* CEC logical address */ - CEC_CMD_LOGICAL_ADDRESS, -}; - -/* Events from CEC to AP */ -enum mkbp_cec_event { - /* Outgoing message was acknowledged by a follower */ - EC_MKBP_CEC_SEND_OK = BIT(0), - /* Outgoing message was not acknowledged */ - EC_MKBP_CEC_SEND_FAILED = BIT(1), -}; - -/*****************************************************************************/ - -/* Commands for I2S recording on audio codec. */ - -#define EC_CMD_CODEC_I2S 0x00BC -#define EC_WOV_I2S_SAMPLE_RATE 48000 - -enum ec_codec_i2s_subcmd { - EC_CODEC_SET_SAMPLE_DEPTH = 0x0, - EC_CODEC_SET_GAIN = 0x1, - EC_CODEC_GET_GAIN = 0x2, - EC_CODEC_I2S_ENABLE = 0x3, - EC_CODEC_I2S_SET_CONFIG = 0x4, - EC_CODEC_I2S_SET_TDM_CONFIG = 0x5, - EC_CODEC_I2S_SET_BCLK = 0x6, - EC_CODEC_I2S_SUBCMD_COUNT = 0x7, -}; - -enum ec_sample_depth_value { - EC_CODEC_SAMPLE_DEPTH_16 = 0, - EC_CODEC_SAMPLE_DEPTH_24 = 1, -}; - -enum ec_i2s_config { - EC_DAI_FMT_I2S = 0, - EC_DAI_FMT_RIGHT_J = 1, - EC_DAI_FMT_LEFT_J = 2, - EC_DAI_FMT_PCM_A = 3, - EC_DAI_FMT_PCM_B = 4, - EC_DAI_FMT_PCM_TDM = 5, -}; - -/* - * For subcommand EC_CODEC_GET_GAIN. - */ -struct __ec_align1 ec_codec_i2s_gain { - uint8_t left; - uint8_t right; -}; - -struct __ec_todo_unpacked ec_param_codec_i2s_tdm { - int16_t ch0_delay; /* 0 to 496 */ - int16_t ch1_delay; /* -1 to 496 */ - uint8_t adjacent_to_ch0; - uint8_t adjacent_to_ch1; -}; - -struct __ec_todo_packed ec_param_codec_i2s { - /* enum ec_codec_i2s_subcmd */ - uint8_t cmd; - union { - /* - * EC_CODEC_SET_SAMPLE_DEPTH - * Value should be one of ec_sample_depth_value. - */ - uint8_t depth; - - /* - * EC_CODEC_SET_GAIN - * Value should be 0~43 for both channels. - */ - struct ec_codec_i2s_gain gain; - - /* - * EC_CODEC_I2S_ENABLE - * 1 to enable, 0 to disable. - */ - uint8_t i2s_enable; - - /* - * EC_CODEC_I2S_SET_CONFIG - * Value should be one of ec_i2s_config. - */ - uint8_t i2s_config; - - /* - * EC_CODEC_I2S_SET_TDM_CONFIG - * Value should be one of ec_i2s_config. - */ - struct ec_param_codec_i2s_tdm tdm_param; - - /* - * EC_CODEC_I2S_SET_BCLK - */ - uint32_t bclk; - }; -}; - - -/*****************************************************************************/ -/* System commands */ - -/* - * TODO(crosbug.com/p/23747): This is a confusing name, since it doesn't - * necessarily reboot the EC. Rename to "image" or something similar? - */ -#define EC_CMD_REBOOT_EC 0x00D2 - -/* Command */ -enum ec_reboot_cmd { - EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */ - EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */ - EC_REBOOT_JUMP_RW = 2, /* Jump to active RW without rebooting */ - /* (command 3 was jump to RW-B) */ - EC_REBOOT_COLD = 4, /* Cold-reboot */ - EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ - EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ - EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_OFF flag */ -}; - -/* Flags for ec_params_reboot_ec.reboot_flags */ -#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */ -#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */ -#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */ - -struct ec_params_reboot_ec { - uint8_t cmd; /* enum ec_reboot_cmd */ - uint8_t flags; /* See EC_REBOOT_FLAG_* */ -} __ec_align1; - -/* - * Get information on last EC panic. - * - * Returns variable-length platform-dependent panic information. See panic.h - * for details. - */ -#define EC_CMD_GET_PANIC_INFO 0x00D3 - -/*****************************************************************************/ -/* - * Special commands - * - * These do not follow the normal rules for commands. See each command for - * details. - */ - -/* - * Reboot NOW - * - * This command will work even when the EC LPC interface is busy, because the - * reboot command is processed at interrupt level. Note that when the EC - * reboots, the host will reboot too, so there is no response to this command. - * - * Use EC_CMD_REBOOT_EC to reboot the EC more politely. - */ -#define EC_CMD_REBOOT 0x00D1 /* Think "die" */ - -/* - * Resend last response (not supported on LPC). - * - * Returns EC_RES_UNAVAILABLE if there is no response available - for example, - * there was no previous command, or the previous command's response was too - * big to save. - */ -#define EC_CMD_RESEND_RESPONSE 0x00DB - -/* - * This header byte on a command indicate version 0. Any header byte less - * than this means that we are talking to an old EC which doesn't support - * versioning. In that case, we assume version 0. - * - * Header bytes greater than this indicate a later version. For example, - * EC_CMD_VERSION0 + 1 means we are using version 1. - * - * The old EC interface must not use commands 0xdc or higher. - */ -#define EC_CMD_VERSION0 0x00DC - -/*****************************************************************************/ -/* - * PD commands - * - * These commands are for PD MCU communication. - */ - -/* EC to PD MCU exchange status command */ -#define EC_CMD_PD_EXCHANGE_STATUS 0x0100 -#define EC_VER_PD_EXCHANGE_STATUS 2 - -enum pd_charge_state { - PD_CHARGE_NO_CHANGE = 0, /* Don't change charge state */ - PD_CHARGE_NONE, /* No charging allowed */ - PD_CHARGE_5V, /* 5V charging only */ - PD_CHARGE_MAX /* Charge at max voltage */ -}; - -/* Status of EC being sent to PD */ -#define EC_STATUS_HIBERNATING BIT(0) - -struct ec_params_pd_status { - uint8_t status; /* EC status */ - int8_t batt_soc; /* battery state of charge */ - uint8_t charge_state; /* charging state (from enum pd_charge_state) */ -} __ec_align1; - -/* Status of PD being sent back to EC */ -#define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */ -#define PD_STATUS_IN_RW BIT(1) /* Running RW image */ -#define PD_STATUS_JUMPED_TO_IMAGE BIT(2) /* Current image was jumped to */ -#define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */ -#define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */ -#define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */ -#define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */ -#define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \ - PD_STATUS_TCPC_ALERT_1 | \ - PD_STATUS_HOST_EVENT) -struct ec_response_pd_status { - uint32_t curr_lim_ma; /* input current limit */ - uint16_t status; /* PD MCU status */ - int8_t active_charge_port; /* active charging port */ -} __ec_align_size1; - -/* AP to PD MCU host event status command, cleared on read */ -#define EC_CMD_PD_HOST_EVENT_STATUS 0x0104 - -/* PD MCU host event status bits */ -#define PD_EVENT_UPDATE_DEVICE BIT(0) -#define PD_EVENT_POWER_CHANGE BIT(1) -#define PD_EVENT_IDENTITY_RECEIVED BIT(2) -#define PD_EVENT_DATA_SWAP BIT(3) -struct ec_response_host_event_status { - uint32_t status; /* PD MCU host event status */ -} __ec_align4; - -/* Set USB type-C port role and muxes */ -#define EC_CMD_USB_PD_CONTROL 0x0101 - -enum usb_pd_control_role { - USB_PD_CTRL_ROLE_NO_CHANGE = 0, - USB_PD_CTRL_ROLE_TOGGLE_ON = 1, /* == AUTO */ - USB_PD_CTRL_ROLE_TOGGLE_OFF = 2, - USB_PD_CTRL_ROLE_FORCE_SINK = 3, - USB_PD_CTRL_ROLE_FORCE_SOURCE = 4, - USB_PD_CTRL_ROLE_FREEZE = 5, - USB_PD_CTRL_ROLE_COUNT -}; - -enum usb_pd_control_mux { - USB_PD_CTRL_MUX_NO_CHANGE = 0, - USB_PD_CTRL_MUX_NONE = 1, - USB_PD_CTRL_MUX_USB = 2, - USB_PD_CTRL_MUX_DP = 3, - USB_PD_CTRL_MUX_DOCK = 4, - USB_PD_CTRL_MUX_AUTO = 5, - USB_PD_CTRL_MUX_COUNT -}; - -enum usb_pd_control_swap { - USB_PD_CTRL_SWAP_NONE = 0, - USB_PD_CTRL_SWAP_DATA = 1, - USB_PD_CTRL_SWAP_POWER = 2, - USB_PD_CTRL_SWAP_VCONN = 3, - USB_PD_CTRL_SWAP_COUNT -}; - -struct ec_params_usb_pd_control { - uint8_t port; - uint8_t role; - uint8_t mux; - uint8_t swap; -} __ec_align1; - -#define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */ -#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */ -#define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2) /* Partner is PD capable */ - -#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */ -#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */ -#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */ -#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */ -#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */ -#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */ -#define PD_CTRL_RESP_ROLE_EXT_POWERED BIT(6) /* Partner externally powerd */ - -struct ec_response_usb_pd_control { - uint8_t enabled; - uint8_t role; - uint8_t polarity; - uint8_t state; -} __ec_align1; - -struct ec_response_usb_pd_control_v1 { - uint8_t enabled; - uint8_t role; - uint8_t polarity; - char state[32]; -} __ec_align1; - -/* Values representing usbc PD CC state */ -#define USBC_PD_CC_NONE 0 /* No accessory connected */ -#define USBC_PD_CC_NO_UFP 1 /* No UFP accessory connected */ -#define USBC_PD_CC_AUDIO_ACC 2 /* Audio accessory connected */ -#define USBC_PD_CC_DEBUG_ACC 3 /* Debug accessory connected */ -#define USBC_PD_CC_UFP_ATTACHED 4 /* UFP attached to usbc */ -#define USBC_PD_CC_DFP_ATTACHED 5 /* DPF attached to usbc */ - -struct ec_response_usb_pd_control_v2 { - uint8_t enabled; - uint8_t role; - uint8_t polarity; - char state[32]; - uint8_t cc_state; /* USBC_PD_CC_*Encoded cc state */ - uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ - /* CL:1500994 Current cable type */ - uint8_t reserved_cable_type; -} __ec_align1; - -#define EC_CMD_USB_PD_PORTS 0x0102 - -/* Maximum number of PD ports on a device, num_ports will be <= this */ -#define EC_USB_PD_MAX_PORTS 8 - -struct ec_response_usb_pd_ports { - uint8_t num_ports; -} __ec_align1; - -#define EC_CMD_USB_PD_POWER_INFO 0x0103 - -#define PD_POWER_CHARGING_PORT 0xff -struct ec_params_usb_pd_power_info { - uint8_t port; -} __ec_align1; - -enum usb_chg_type { - USB_CHG_TYPE_NONE, - USB_CHG_TYPE_PD, - USB_CHG_TYPE_C, - USB_CHG_TYPE_PROPRIETARY, - USB_CHG_TYPE_BC12_DCP, - USB_CHG_TYPE_BC12_CDP, - USB_CHG_TYPE_BC12_SDP, - USB_CHG_TYPE_OTHER, - USB_CHG_TYPE_VBUS, - USB_CHG_TYPE_UNKNOWN, - USB_CHG_TYPE_DEDICATED, -}; -enum usb_power_roles { - USB_PD_PORT_POWER_DISCONNECTED, - USB_PD_PORT_POWER_SOURCE, - USB_PD_PORT_POWER_SINK, - USB_PD_PORT_POWER_SINK_NOT_CHARGING, -}; - -struct usb_chg_measures { - uint16_t voltage_max; - uint16_t voltage_now; - uint16_t current_max; - uint16_t current_lim; -} __ec_align2; - -struct ec_response_usb_pd_power_info { - uint8_t role; - uint8_t type; - uint8_t dualrole; - uint8_t reserved1; - struct usb_chg_measures meas; - uint32_t max_power; -} __ec_align4; - - -/* - * This command will return the number of USB PD charge port + the number - * of dedicated port present. - * EC_CMD_USB_PD_PORTS does NOT include the dedicated ports - */ -#define EC_CMD_CHARGE_PORT_COUNT 0x0105 -struct ec_response_charge_port_count { - uint8_t port_count; -} __ec_align1; - -/* Write USB-PD device FW */ -#define EC_CMD_USB_PD_FW_UPDATE 0x0110 - -enum usb_pd_fw_update_cmds { - USB_PD_FW_REBOOT, - USB_PD_FW_FLASH_ERASE, - USB_PD_FW_FLASH_WRITE, - USB_PD_FW_ERASE_SIG, -}; - -struct ec_params_usb_pd_fw_update { - uint16_t dev_id; - uint8_t cmd; - uint8_t port; - uint32_t size; /* Size to write in bytes */ - /* Followed by data to write */ -} __ec_align4; - -/* Write USB-PD Accessory RW_HASH table entry */ -#define EC_CMD_USB_PD_RW_HASH_ENTRY 0x0111 -/* RW hash is first 20 bytes of SHA-256 of RW section */ -#define PD_RW_HASH_SIZE 20 -struct ec_params_usb_pd_rw_hash_entry { - uint16_t dev_id; - uint8_t dev_rw_hash[PD_RW_HASH_SIZE]; - uint8_t reserved; /* - * For alignment of current_image - * TODO(rspangler) but it's not aligned! - * Should have been reserved[2]. - */ - uint32_t current_image; /* One of ec_current_image */ -} __ec_align1; - -/* Read USB-PD Accessory info */ -#define EC_CMD_USB_PD_DEV_INFO 0x0112 - -struct ec_params_usb_pd_info_request { - uint8_t port; -} __ec_align1; - -/* Read USB-PD Device discovery info */ -#define EC_CMD_USB_PD_DISCOVERY 0x0113 -struct ec_params_usb_pd_discovery_entry { - uint16_t vid; /* USB-IF VID */ - uint16_t pid; /* USB-IF PID */ - uint8_t ptype; /* product type (hub,periph,cable,ama) */ -} __ec_align_size1; - -/* Override default charge behavior */ -#define EC_CMD_PD_CHARGE_PORT_OVERRIDE 0x0114 - -/* Negative port parameters have special meaning */ -enum usb_pd_override_ports { - OVERRIDE_DONT_CHARGE = -2, - OVERRIDE_OFF = -1, - /* [0, CONFIG_USB_PD_PORT_COUNT): Port# */ -}; - -struct ec_params_charge_port_override { - int16_t override_port; /* Override port# */ -} __ec_align2; - -/* - * Read (and delete) one entry of PD event log. - * TODO(crbug.com/751742): Make this host command more generic to accommodate - * future non-PD logs that use the same internal EC event_log. - */ -#define EC_CMD_PD_GET_LOG_ENTRY 0x0115 - -struct ec_response_pd_log { - uint32_t timestamp; /* relative timestamp in milliseconds */ - uint8_t type; /* event type : see PD_EVENT_xx below */ - uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */ - uint16_t data; /* type-defined data payload */ - uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */ -} __ec_align4; - -/* The timestamp is the microsecond counter shifted to get about a ms. */ -#define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */ - -#define PD_LOG_SIZE_MASK 0x1f -#define PD_LOG_PORT_MASK 0xe0 -#define PD_LOG_PORT_SHIFT 5 -#define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \ - ((size) & PD_LOG_SIZE_MASK)) -#define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT) -#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK) - -/* PD event log : entry types */ -/* PD MCU events */ -#define PD_EVENT_MCU_BASE 0x00 -#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE+0) -#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE+1) -/* Reserved for custom board event */ -#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE+2) -/* PD generic accessory events */ -#define PD_EVENT_ACC_BASE 0x20 -#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE+0) -#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE+1) -/* PD power supply events */ -#define PD_EVENT_PS_BASE 0x40 -#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE+0) -/* PD video dongles events */ -#define PD_EVENT_VIDEO_BASE 0x60 -#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0) -#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE+1) -/* Returned in the "type" field, when there is no entry available */ -#define PD_EVENT_NO_ENTRY 0xff - -/* - * PD_EVENT_MCU_CHARGE event definition : - * the payload is "struct usb_chg_measures" - * the data field contains the port state flags as defined below : - */ -/* Port partner is a dual role device */ -#define CHARGE_FLAGS_DUAL_ROLE BIT(15) -/* Port is the pending override port */ -#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14) -/* Port is the override port */ -#define CHARGE_FLAGS_OVERRIDE BIT(13) -/* Charger type */ -#define CHARGE_FLAGS_TYPE_SHIFT 3 -#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT) -/* Power delivery role */ -#define CHARGE_FLAGS_ROLE_MASK (7 << 0) - -/* - * PD_EVENT_PS_FAULT data field flags definition : - */ -#define PS_FAULT_OCP 1 -#define PS_FAULT_FAST_OCP 2 -#define PS_FAULT_OVP 3 -#define PS_FAULT_DISCH 4 - -/* - * PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info". - */ -struct mcdp_version { - uint8_t major; - uint8_t minor; - uint16_t build; -} __ec_align4; - -struct mcdp_info { - uint8_t family[2]; - uint8_t chipid[2]; - struct mcdp_version irom; - struct mcdp_version fw; -} __ec_align4; - -/* struct mcdp_info field decoding */ -#define MCDP_CHIPID(chipid) ((chipid[0] << 8) | chipid[1]) -#define MCDP_FAMILY(family) ((family[0] << 8) | family[1]) - -/* Get/Set USB-PD Alternate mode info */ -#define EC_CMD_USB_PD_GET_AMODE 0x0116 -struct ec_params_usb_pd_get_mode_request { - uint16_t svid_idx; /* SVID index to get */ - uint8_t port; /* port */ -} __ec_align_size1; - -struct ec_params_usb_pd_get_mode_response { - uint16_t svid; /* SVID */ - uint16_t opos; /* Object Position */ - uint32_t vdo[6]; /* Mode VDOs */ -} __ec_align4; - -#define EC_CMD_USB_PD_SET_AMODE 0x0117 - -enum pd_mode_cmd { - PD_EXIT_MODE = 0, - PD_ENTER_MODE = 1, - /* Not a command. Do NOT remove. */ - PD_MODE_CMD_COUNT, -}; - -struct ec_params_usb_pd_set_mode_request { - uint32_t cmd; /* enum pd_mode_cmd */ - uint16_t svid; /* SVID to set */ - uint8_t opos; /* Object Position */ - uint8_t port; /* port */ -} __ec_align4; - -/* Ask the PD MCU to record a log of a requested type */ -#define EC_CMD_PD_WRITE_LOG_ENTRY 0x0118 - -struct ec_params_pd_write_log_entry { - uint8_t type; /* event type : see PD_EVENT_xx above */ - uint8_t port; /* port#, or 0 for events unrelated to a given port */ -} __ec_align1; - - -/* Control USB-PD chip */ -#define EC_CMD_PD_CONTROL 0x0119 - -enum ec_pd_control_cmd { - PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */ - PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */ - PD_RESET, /* Force reset the PD chip */ - PD_CONTROL_DISABLE, /* Disable further calls to this command */ - PD_CHIP_ON, /* Power on the PD chip */ -}; - -struct ec_params_pd_control { - uint8_t chip; /* chip id */ - uint8_t subcmd; -} __ec_align1; - -/* Get info about USB-C SS muxes */ -#define EC_CMD_USB_PD_MUX_INFO 0x011A - -struct ec_params_usb_pd_mux_info { - uint8_t port; /* USB-C port number */ -} __ec_align1; - -/* Flags representing mux state */ -#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ -#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ -#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ -#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ -#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ - -struct ec_response_usb_pd_mux_info { - uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ -} __ec_align1; - -#define EC_CMD_PD_CHIP_INFO 0x011B - -struct ec_params_pd_chip_info { - uint8_t port; /* USB-C port number */ - uint8_t renew; /* Force renewal */ -} __ec_align1; - -struct ec_response_pd_chip_info { - uint16_t vendor_id; - uint16_t product_id; - uint16_t device_id; - union { - uint8_t fw_version_string[8]; - uint64_t fw_version_number; - }; -} __ec_align2; - -struct ec_response_pd_chip_info_v1 { - uint16_t vendor_id; - uint16_t product_id; - uint16_t device_id; - union { - uint8_t fw_version_string[8]; - uint64_t fw_version_number; - }; - union { - uint8_t min_req_fw_version_string[8]; - uint64_t min_req_fw_version_number; - }; -} __ec_align2; - -/* Run RW signature verification and get status */ -#define EC_CMD_RWSIG_CHECK_STATUS 0x011C - -struct ec_response_rwsig_check_status { - uint32_t status; -} __ec_align4; - -/* For controlling RWSIG task */ -#define EC_CMD_RWSIG_ACTION 0x011D - -enum rwsig_action { - RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */ - RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */ -}; - -struct ec_params_rwsig_action { - uint32_t action; -} __ec_align4; - -/* Run verification on a slot */ -#define EC_CMD_EFS_VERIFY 0x011E - -struct ec_params_efs_verify { - uint8_t region; /* enum ec_flash_region */ -} __ec_align1; - -/* - * Retrieve info from Cros Board Info store. Response is based on the data - * type. Integers return a uint32. Strings return a string, using the response - * size to determine how big it is. - */ -#define EC_CMD_GET_CROS_BOARD_INFO 0x011F -/* - * Write info into Cros Board Info on EEPROM. Write fails if the board has - * hardware write-protect enabled. - */ -#define EC_CMD_SET_CROS_BOARD_INFO 0x0120 - -enum cbi_data_tag { - CBI_TAG_BOARD_VERSION = 0, /* uint32_t or smaller */ - CBI_TAG_OEM_ID = 1, /* uint32_t or smaller */ - CBI_TAG_SKU_ID = 2, /* uint32_t or smaller */ - CBI_TAG_DRAM_PART_NUM = 3, /* variable length ascii, nul terminated. */ - CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */ - CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ - CBI_TAG_COUNT, -}; - -/* - * Flags to control read operation - * - * RELOAD: Invalidate cache and read data from EEPROM. Useful to verify - * write was successful without reboot. - */ -#define CBI_GET_RELOAD BIT(0) - -struct ec_params_get_cbi { - uint32_t tag; /* enum cbi_data_tag */ - uint32_t flag; /* CBI_GET_* */ -} __ec_align4; - -/* - * Flags to control write behavior. - * - * NO_SYNC: Makes EC update data in RAM but skip writing to EEPROM. It's - * useful when writing multiple fields in a row. - * INIT: Need to be set when creating a new CBI from scratch. All fields - * will be initialized to zero first. - */ -#define CBI_SET_NO_SYNC BIT(0) -#define CBI_SET_INIT BIT(1) - -struct ec_params_set_cbi { - uint32_t tag; /* enum cbi_data_tag */ - uint32_t flag; /* CBI_SET_* */ - uint32_t size; /* Data size */ - uint8_t data[]; /* For string and raw data */ -} __ec_align1; - -/* - * Information about resets of the AP by the EC and the EC's own uptime. - */ -#define EC_CMD_GET_UPTIME_INFO 0x0121 - -struct ec_response_uptime_info { - /* - * Number of milliseconds since the last EC boot. Sysjump resets - * typically do not restart the EC's time_since_boot epoch. - * - * WARNING: The EC's sense of time is much less accurate than the AP's - * sense of time, in both phase and frequency. This timebase is similar - * to CLOCK_MONOTONIC_RAW, but with 1% or more frequency error. - */ - uint32_t time_since_ec_boot_ms; - - /* - * Number of times the AP was reset by the EC since the last EC boot. - * Note that the AP may be held in reset by the EC during the initial - * boot sequence, such that the very first AP boot may count as more - * than one here. - */ - uint32_t ap_resets_since_ec_boot; - - /* - * The set of flags which describe the EC's most recent reset. See - * include/system.h RESET_FLAG_* for details. - */ - uint32_t ec_reset_flags; - - /* Empty log entries have both the cause and timestamp set to zero. */ - struct ap_reset_log_entry { - /* - * See include/chipset.h: enum chipset_{reset,shutdown}_reason - * for details. - */ - uint16_t reset_cause; - - /* Reserved for protocol growth. */ - uint16_t reserved; - - /* - * The time of the reset's assertion, in milliseconds since the - * last EC boot, in the same epoch as time_since_ec_boot_ms. - * Set to zero if the log entry is empty. - */ - uint32_t reset_time_ms; - } recent_ap_reset[4]; -} __ec_align4; - -/* - * Add entropy to the device secret (stored in the rollback region). - * - * Depending on the chip, the operation may take a long time (e.g. to erase - * flash), so the commands are asynchronous. - */ -#define EC_CMD_ADD_ENTROPY 0x0122 - -enum add_entropy_action { - /* Add entropy to the current secret. */ - ADD_ENTROPY_ASYNC = 0, - /* - * Add entropy, and also make sure that the previous secret is erased. - * (this can be implemented by adding entropy multiple times until - * all rolback blocks have been overwritten). - */ - ADD_ENTROPY_RESET_ASYNC = 1, - /* Read back result from the previous operation. */ - ADD_ENTROPY_GET_RESULT = 2, -}; - -struct ec_params_rollback_add_entropy { - uint8_t action; -} __ec_align1; - -/* - * Perform a single read of a given ADC channel. - */ -#define EC_CMD_ADC_READ 0x0123 - -struct ec_params_adc_read { - uint8_t adc_channel; -} __ec_align1; - -struct ec_response_adc_read { - int32_t adc_value; -} __ec_align4; - -/* - * Read back rollback info - */ -#define EC_CMD_ROLLBACK_INFO 0x0124 - -struct ec_response_rollback_info { - int32_t id; /* Incrementing number to indicate which region to use. */ - int32_t rollback_min_version; - int32_t rw_rollback_version; -} __ec_align4; - - -/* Issue AP reset */ -#define EC_CMD_AP_RESET 0x0125 - -/*****************************************************************************/ -/* The command range 0x200-0x2FF is reserved for Rotor. */ - -/*****************************************************************************/ -/* - * Reserve a range of host commands for the CR51 firmware. - */ -#define EC_CMD_CR51_BASE 0x0300 -#define EC_CMD_CR51_LAST 0x03FF - -/*****************************************************************************/ -/* Fingerprint MCU commands: range 0x0400-0x040x */ - -/* Fingerprint SPI sensor passthru command: prototyping ONLY */ -#define EC_CMD_FP_PASSTHRU 0x0400 - -#define EC_FP_FLAG_NOT_COMPLETE 0x1 - -struct ec_params_fp_passthru { - uint16_t len; /* Number of bytes to write then read */ - uint16_t flags; /* EC_FP_FLAG_xxx */ - uint8_t data[]; /* Data to send */ -} __ec_align2; - -/* Configure the Fingerprint MCU behavior */ -#define EC_CMD_FP_MODE 0x0402 - -/* Put the sensor in its lowest power mode */ -#define FP_MODE_DEEPSLEEP BIT(0) -/* Wait to see a finger on the sensor */ -#define FP_MODE_FINGER_DOWN BIT(1) -/* Poll until the finger has left the sensor */ -#define FP_MODE_FINGER_UP BIT(2) -/* Capture the current finger image */ -#define FP_MODE_CAPTURE BIT(3) -/* Finger enrollment session on-going */ -#define FP_MODE_ENROLL_SESSION BIT(4) -/* Enroll the current finger image */ -#define FP_MODE_ENROLL_IMAGE BIT(5) -/* Try to match the current finger image */ -#define FP_MODE_MATCH BIT(6) -/* Reset and re-initialize the sensor. */ -#define FP_MODE_RESET_SENSOR BIT(7) -/* special value: don't change anything just read back current mode */ -#define FP_MODE_DONT_CHANGE BIT(31) - -#define FP_VALID_MODES (FP_MODE_DEEPSLEEP | \ - FP_MODE_FINGER_DOWN | \ - FP_MODE_FINGER_UP | \ - FP_MODE_CAPTURE | \ - FP_MODE_ENROLL_SESSION | \ - FP_MODE_ENROLL_IMAGE | \ - FP_MODE_MATCH | \ - FP_MODE_RESET_SENSOR | \ - FP_MODE_DONT_CHANGE) - -/* Capture types defined in bits [30..28] */ -#define FP_MODE_CAPTURE_TYPE_SHIFT 28 -#define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT) -/* - * This enum must remain ordered, if you add new values you must ensure that - * FP_CAPTURE_TYPE_MAX is still the last one. - */ -enum fp_capture_type { - /* Full blown vendor-defined capture (produces 'frame_size' bytes) */ - FP_CAPTURE_VENDOR_FORMAT = 0, - /* Simple raw image capture (produces width x height x bpp bits) */ - FP_CAPTURE_SIMPLE_IMAGE = 1, - /* Self test pattern (e.g. checkerboard) */ - FP_CAPTURE_PATTERN0 = 2, - /* Self test pattern (e.g. inverted checkerboard) */ - FP_CAPTURE_PATTERN1 = 3, - /* Capture for Quality test with fixed contrast */ - FP_CAPTURE_QUALITY_TEST = 4, - /* Capture for pixel reset value test */ - FP_CAPTURE_RESET_TEST = 5, - FP_CAPTURE_TYPE_MAX, -}; -/* Extracts the capture type from the sensor 'mode' word */ -#define FP_CAPTURE_TYPE(mode) (((mode) & FP_MODE_CAPTURE_TYPE_MASK) \ - >> FP_MODE_CAPTURE_TYPE_SHIFT) - -struct ec_params_fp_mode { - uint32_t mode; /* as defined by FP_MODE_ constants */ -} __ec_align4; - -struct ec_response_fp_mode { - uint32_t mode; /* as defined by FP_MODE_ constants */ -} __ec_align4; - -/* Retrieve Fingerprint sensor information */ -#define EC_CMD_FP_INFO 0x0403 - -/* Number of dead pixels detected on the last maintenance */ -#define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF) -/* Unknown number of dead pixels detected on the last maintenance */ -#define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF) -/* No interrupt from the sensor */ -#define FP_ERROR_NO_IRQ BIT(12) -/* SPI communication error */ -#define FP_ERROR_SPI_COMM BIT(13) -/* Invalid sensor Hardware ID */ -#define FP_ERROR_BAD_HWID BIT(14) -/* Sensor initialization failed */ -#define FP_ERROR_INIT_FAIL BIT(15) - -struct ec_response_fp_info_v0 { - /* Sensor identification */ - uint32_t vendor_id; - uint32_t product_id; - uint32_t model_id; - uint32_t version; - /* Image frame characteristics */ - uint32_t frame_size; - uint32_t pixel_format; /* using V4L2_PIX_FMT_ */ - uint16_t width; - uint16_t height; - uint16_t bpp; - uint16_t errors; /* see FP_ERROR_ flags above */ -} __ec_align4; - -struct ec_response_fp_info { - /* Sensor identification */ - uint32_t vendor_id; - uint32_t product_id; - uint32_t model_id; - uint32_t version; - /* Image frame characteristics */ - uint32_t frame_size; - uint32_t pixel_format; /* using V4L2_PIX_FMT_ */ - uint16_t width; - uint16_t height; - uint16_t bpp; - uint16_t errors; /* see FP_ERROR_ flags above */ - /* Template/finger current information */ - uint32_t template_size; /* max template size in bytes */ - uint16_t template_max; /* maximum number of fingers/templates */ - uint16_t template_valid; /* number of valid fingers/templates */ - uint32_t template_dirty; /* bitmap of templates with MCU side changes */ - uint32_t template_version; /* version of the template format */ -} __ec_align4; - -/* Get the last captured finger frame or a template content */ -#define EC_CMD_FP_FRAME 0x0404 - -/* constants defining the 'offset' field which also contains the frame index */ -#define FP_FRAME_INDEX_SHIFT 28 -/* Frame buffer where the captured image is stored */ -#define FP_FRAME_INDEX_RAW_IMAGE 0 -/* First frame buffer holding a template */ -#define FP_FRAME_INDEX_TEMPLATE 1 -#define FP_FRAME_GET_BUFFER_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT) -#define FP_FRAME_OFFSET_MASK 0x0FFFFFFF - -/* Version of the format of the encrypted templates. */ -#define FP_TEMPLATE_FORMAT_VERSION 3 - -/* Constants for encryption parameters */ -#define FP_CONTEXT_NONCE_BYTES 12 -#define FP_CONTEXT_USERID_WORDS (32 / sizeof(uint32_t)) -#define FP_CONTEXT_TAG_BYTES 16 -#define FP_CONTEXT_SALT_BYTES 16 -#define FP_CONTEXT_TPM_BYTES 32 - -struct ec_fp_template_encryption_metadata { - /* - * Version of the structure format (N=3). - */ - uint16_t struct_version; - /* Reserved bytes, set to 0. */ - uint16_t reserved; - /* - * The salt is *only* ever used for key derivation. The nonce is unique, - * a different one is used for every message. - */ - uint8_t nonce[FP_CONTEXT_NONCE_BYTES]; - uint8_t salt[FP_CONTEXT_SALT_BYTES]; - uint8_t tag[FP_CONTEXT_TAG_BYTES]; -}; - -struct ec_params_fp_frame { - /* - * The offset contains the template index or FP_FRAME_INDEX_RAW_IMAGE - * in the high nibble, and the real offset within the frame in - * FP_FRAME_OFFSET_MASK. - */ - uint32_t offset; - uint32_t size; -} __ec_align4; - -/* Load a template into the MCU */ -#define EC_CMD_FP_TEMPLATE 0x0405 - -/* Flag in the 'size' field indicating that the full template has been sent */ -#define FP_TEMPLATE_COMMIT 0x80000000 - -struct ec_params_fp_template { - uint32_t offset; - uint32_t size; - uint8_t data[]; -} __ec_align4; - -/* Clear the current fingerprint user context and set a new one */ -#define EC_CMD_FP_CONTEXT 0x0406 - -struct ec_params_fp_context { - uint32_t userid[FP_CONTEXT_USERID_WORDS]; -} __ec_align4; - -#define EC_CMD_FP_STATS 0x0407 - -#define FPSTATS_CAPTURE_INV BIT(0) -#define FPSTATS_MATCHING_INV BIT(1) - -struct ec_response_fp_stats { - uint32_t capture_time_us; - uint32_t matching_time_us; - uint32_t overall_time_us; - struct { - uint32_t lo; - uint32_t hi; - } overall_t0; - uint8_t timestamps_invalid; - int8_t template_matched; -} __ec_align2; - -#define EC_CMD_FP_SEED 0x0408 -struct ec_params_fp_seed { - /* - * Version of the structure format (N=3). - */ - uint16_t struct_version; - /* Reserved bytes, set to 0. */ - uint16_t reserved; - /* Seed from the TPM. */ - uint8_t seed[FP_CONTEXT_TPM_BYTES]; -} __ec_align4; - -/*****************************************************************************/ -/* Touchpad MCU commands: range 0x0500-0x05FF */ - -/* Perform touchpad self test */ -#define EC_CMD_TP_SELF_TEST 0x0500 - -/* Get number of frame types, and the size of each type */ -#define EC_CMD_TP_FRAME_INFO 0x0501 - -struct ec_response_tp_frame_info { - uint32_t n_frames; - uint32_t frame_sizes[0]; -} __ec_align4; - -/* Create a snapshot of current frame readings */ -#define EC_CMD_TP_FRAME_SNAPSHOT 0x0502 - -/* Read the frame */ -#define EC_CMD_TP_FRAME_GET 0x0503 - -struct ec_params_tp_frame_get { - uint32_t frame_index; - uint32_t offset; - uint32_t size; -} __ec_align4; - -/*****************************************************************************/ -/* EC-EC communication commands: range 0x0600-0x06FF */ - -#define EC_COMM_TEXT_MAX 8 - -/* - * Get battery static information, i.e. information that never changes, or - * very infrequently. - */ -#define EC_CMD_BATTERY_GET_STATIC 0x0600 - -/** - * struct ec_params_battery_static_info - Battery static info parameters - * @index: Battery index. - */ -struct ec_params_battery_static_info { - uint8_t index; -} __ec_align_size1; - -/** - * struct ec_response_battery_static_info - Battery static info response - * @design_capacity: Battery Design Capacity (mAh) - * @design_voltage: Battery Design Voltage (mV) - * @manufacturer: Battery Manufacturer String - * @model: Battery Model Number String - * @serial: Battery Serial Number String - * @type: Battery Type String - * @cycle_count: Battery Cycle Count - */ -struct ec_response_battery_static_info { - uint16_t design_capacity; - uint16_t design_voltage; - char manufacturer[EC_COMM_TEXT_MAX]; - char model[EC_COMM_TEXT_MAX]; - char serial[EC_COMM_TEXT_MAX]; - char type[EC_COMM_TEXT_MAX]; - /* TODO(crbug.com/795991): Consider moving to dynamic structure. */ - uint32_t cycle_count; -} __ec_align4; - -/* - * Get battery dynamic information, i.e. information that is likely to change - * every time it is read. - */ -#define EC_CMD_BATTERY_GET_DYNAMIC 0x0601 - -/** - * struct ec_params_battery_dynamic_info - Battery dynamic info parameters - * @index: Battery index. - */ -struct ec_params_battery_dynamic_info { - uint8_t index; -} __ec_align_size1; - -/** - * struct ec_response_battery_dynamic_info - Battery dynamic info response - * @actual_voltage: Battery voltage (mV) - * @actual_current: Battery current (mA); negative=discharging - * @remaining_capacity: Remaining capacity (mAh) - * @full_capacity: Capacity (mAh, might change occasionally) - * @flags: Flags, see EC_BATT_FLAG_* - * @desired_voltage: Charging voltage desired by battery (mV) - * @desired_current: Charging current desired by battery (mA) - */ -struct ec_response_battery_dynamic_info { - int16_t actual_voltage; - int16_t actual_current; - int16_t remaining_capacity; - int16_t full_capacity; - int16_t flags; - int16_t desired_voltage; - int16_t desired_current; -} __ec_align2; - -/* - * Control charger chip. Used to control charger chip on the slave. - */ -#define EC_CMD_CHARGER_CONTROL 0x0602 - -/** - * struct ec_params_charger_control - Charger control parameters - * @max_current: Charger current (mA). Positive to allow base to draw up to - * max_current and (possibly) charge battery, negative to request current - * from base (OTG). - * @otg_voltage: Voltage (mV) to use in OTG mode, ignored if max_current is - * >= 0. - * @allow_charging: Allow base battery charging (only makes sense if - * max_current > 0). - */ -struct ec_params_charger_control { - int16_t max_current; - uint16_t otg_voltage; - uint8_t allow_charging; -} __ec_align_size1; - -/*****************************************************************************/ -/* - * Reserve a range of host commands for board-specific, experimental, or - * special purpose features. These can be (re)used without updating this file. - * - * CAUTION: Don't go nuts with this. Shipping products should document ALL - * their EC commands for easier development, testing, debugging, and support. - * - * All commands MUST be #defined to be 4-digit UPPER CASE hex values - * (e.g., 0x00AB, not 0xab) for CONFIG_HOSTCMD_SECTION_SORTED to work. - * - * In your experimental code, you may want to do something like this: - * - * #define EC_CMD_MAGIC_FOO 0x0000 - * #define EC_CMD_MAGIC_BAR 0x0001 - * #define EC_CMD_MAGIC_HEY 0x0002 - * - * DECLARE_PRIVATE_HOST_COMMAND(EC_CMD_MAGIC_FOO, magic_foo_handler, - * EC_VER_MASK(0); - * - * DECLARE_PRIVATE_HOST_COMMAND(EC_CMD_MAGIC_BAR, magic_bar_handler, - * EC_VER_MASK(0); - * - * DECLARE_PRIVATE_HOST_COMMAND(EC_CMD_MAGIC_HEY, magic_hey_handler, - * EC_VER_MASK(0); - */ -#define EC_CMD_BOARD_SPECIFIC_BASE 0x3E00 -#define EC_CMD_BOARD_SPECIFIC_LAST 0x3FFF - -/* - * Given the private host command offset, calculate the true private host - * command value. - */ -#define EC_PRIVATE_HOST_COMMAND_VALUE(command) \ - (EC_CMD_BOARD_SPECIFIC_BASE + (command)) - -/*****************************************************************************/ -/* - * Passthru commands - * - * Some platforms have sub-processors chained to each other. For example. - * - * AP <--> EC <--> PD MCU - * - * The top 2 bits of the command number are used to indicate which device the - * command is intended for. Device 0 is always the device receiving the - * command; other device mapping is board-specific. - * - * When a device receives a command to be passed to a sub-processor, it passes - * it on with the device number set back to 0. This allows the sub-processor - * to remain blissfully unaware of whether the command originated on the next - * device up the chain, or was passed through from the AP. - * - * In the above example, if the AP wants to send command 0x0002 to the PD MCU, - * AP sends command 0x4002 to the EC - * EC sends command 0x0002 to the PD MCU - * EC forwards PD MCU response back to the AP - */ - -/* Offset and max command number for sub-device n */ -#define EC_CMD_PASSTHRU_OFFSET(n) (0x4000 * (n)) -#define EC_CMD_PASSTHRU_MAX(n) (EC_CMD_PASSTHRU_OFFSET(n) + 0x3fff) - -/*****************************************************************************/ -/* - * Deprecated constants. These constants have been renamed for clarity. The - * meaning and size has not changed. Programs that use the old names should - * switch to the new names soon, as the old names may not be carried forward - * forever. - */ -#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE -#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1 -#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE - - - -#endif /* __CROS_EC_COMMANDS_H */ diff --git a/include/linux/platform_data/cros_ec_chardev.h b/include/linux/platform_data/cros_ec_chardev.h index 6600b54f531c..973b2615aa02 100644 --- a/include/linux/platform_data/cros_ec_chardev.h +++ b/include/linux/platform_data/cros_ec_chardev.h @@ -12,7 +12,7 @@ #include #include -#include +#include #define CROS_EC_DEV_VERSION "1.0.0" diff --git a/include/linux/platform_data/cros_ec_commands.h b/include/linux/platform_data/cros_ec_commands.h new file mode 100644 index 000000000000..7ccb8757b79d --- /dev/null +++ b/include/linux/platform_data/cros_ec_commands.h @@ -0,0 +1,5713 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Host communication command constants for ChromeOS EC + * + * Copyright (C) 2012 Google, Inc + * + * NOTE: This file is auto-generated from ChromeOS EC Open Source code from + * https://chromium.googlesource.com/chromiumos/platform/ec/+/master/include/ec_commands.h + */ + +/* Host communication command constants for Chrome EC */ + +#ifndef __CROS_EC_COMMANDS_H +#define __CROS_EC_COMMANDS_H + + + + +#define BUILD_ASSERT(_cond) + +/* + * Current version of this protocol + * + * TODO(crosbug.com/p/11223): This is effectively useless; protocol is + * determined in other ways. Remove this once the kernel code no longer + * depends on it. + */ +#define EC_PROTO_VERSION 0x00000002 + +/* Command version mask */ +#define EC_VER_MASK(version) BIT(version) + +/* I/O addresses for ACPI commands */ +#define EC_LPC_ADDR_ACPI_DATA 0x62 +#define EC_LPC_ADDR_ACPI_CMD 0x66 + +/* I/O addresses for host command */ +#define EC_LPC_ADDR_HOST_DATA 0x200 +#define EC_LPC_ADDR_HOST_CMD 0x204 + +/* I/O addresses for host command args and params */ +/* Protocol version 2 */ +#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ +#define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is + * EC_PROTO2_MAX_PARAM_SIZE + */ +/* Protocol version 3 */ +#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ +#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ + +/* + * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff + * and they tell the kernel that so we have to think of it as two parts. + */ +#define EC_HOST_CMD_REGION0 0x800 +#define EC_HOST_CMD_REGION1 0x880 +#define EC_HOST_CMD_REGION_SIZE 0x80 + +/* EC command register bit functions */ +#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */ +#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */ +#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */ +#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */ +#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */ +#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */ +#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */ + +#define EC_LPC_ADDR_MEMMAP 0x900 +#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ +#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */ + +/* The offset address of each type of data in mapped memory. */ +#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */ +#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */ +#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */ +#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */ +#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ +#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ +#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ +#define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */ +#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ +#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */ +/* Unused 0x28 - 0x2f */ +#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */ +/* Unused 0x31 - 0x33 */ +#define EC_MEMMAP_HOST_EVENTS 0x34 /* 64 bits */ +/* Battery values are all 32 bits, unless otherwise noted. */ +#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ +#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ +#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ +#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, see below (8-bit) */ +#define EC_MEMMAP_BATT_COUNT 0x4d /* Battery Count (8-bit) */ +#define EC_MEMMAP_BATT_INDEX 0x4e /* Current Battery Data Index (8-bit) */ +/* Unused 0x4f */ +#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */ +#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ +#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ +#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ +/* Strings are all 8 bytes (EC_MEMMAP_TEXT_MAX) */ +#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ +#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ +#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ +#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ +#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */ +/* Unused 0x84 - 0x8f */ +#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/ +/* Unused 0x91 */ +#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */ +/* 0x92: Lid Angle if available, LID_ANGLE_UNRELIABLE otherwise */ +/* 0x94 - 0x99: 1st Accelerometer */ +/* 0x9a - 0x9f: 2nd Accelerometer */ +#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ +/* Unused 0xa6 - 0xdf */ + +/* + * ACPI is unable to access memory mapped data at or above this offset due to + * limitations of the ACPI protocol. Do not place data in the range 0xe0 - 0xfe + * which might be needed by ACPI. + */ +#define EC_MEMMAP_NO_ACPI 0xe0 + +/* Define the format of the accelerometer mapped memory status byte. */ +#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f +#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4) +#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7) + +/* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */ +#define EC_TEMP_SENSOR_ENTRIES 16 +/* + * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B. + * + * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2. + */ +#define EC_TEMP_SENSOR_B_ENTRIES 8 + +/* Special values for mapped temperature sensors */ +#define EC_TEMP_SENSOR_NOT_PRESENT 0xff +#define EC_TEMP_SENSOR_ERROR 0xfe +#define EC_TEMP_SENSOR_NOT_POWERED 0xfd +#define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc +/* + * The offset of temperature value stored in mapped memory. This allows + * reporting a temperature range of 200K to 454K = -73C to 181C. + */ +#define EC_TEMP_SENSOR_OFFSET 200 + +/* + * Number of ALS readings at EC_MEMMAP_ALS + */ +#define EC_ALS_ENTRIES 2 + +/* + * The default value a temperature sensor will return when it is present but + * has not been read this boot. This is a reasonable number to avoid + * triggering alarms on the host. + */ +#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET) + +#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ +#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ +#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */ + +/* Battery bit flags at EC_MEMMAP_BATT_FLAG. */ +#define EC_BATT_FLAG_AC_PRESENT 0x01 +#define EC_BATT_FLAG_BATT_PRESENT 0x02 +#define EC_BATT_FLAG_DISCHARGING 0x04 +#define EC_BATT_FLAG_CHARGING 0x08 +#define EC_BATT_FLAG_LEVEL_CRITICAL 0x10 +/* Set if some of the static/dynamic data is invalid (or outdated). */ +#define EC_BATT_FLAG_INVALID_DATA 0x20 + +/* Switch flags at EC_MEMMAP_SWITCHES */ +#define EC_SWITCH_LID_OPEN 0x01 +#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 +#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04 +/* Was recovery requested via keyboard; now unused. */ +#define EC_SWITCH_IGNORE1 0x08 +/* Recovery requested via dedicated signal (from servo board) */ +#define EC_SWITCH_DEDICATED_RECOVERY 0x10 +/* Was fake developer mode switch; now unused. Remove in next refactor. */ +#define EC_SWITCH_IGNORE0 0x20 + +/* Host command interface flags */ +/* Host command interface supports LPC args (LPC interface only) */ +#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 +/* Host command interface supports version 3 protocol */ +#define EC_HOST_CMD_FLAG_VERSION_3 0x02 + +/* Wireless switch flags */ +#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */ +#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */ +#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */ +#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */ +#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */ + +/*****************************************************************************/ +/* + * ACPI commands + * + * These are valid ONLY on the ACPI command/data port. + */ + +/* + * ACPI Read Embedded Controller + * + * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*). + * + * Use the following sequence: + * + * - Write EC_CMD_ACPI_READ to EC_LPC_ADDR_ACPI_CMD + * - Wait for EC_LPC_CMDR_PENDING bit to clear + * - Write address to EC_LPC_ADDR_ACPI_DATA + * - Wait for EC_LPC_CMDR_DATA bit to set + * - Read value from EC_LPC_ADDR_ACPI_DATA + */ +#define EC_CMD_ACPI_READ 0x0080 + +/* + * ACPI Write Embedded Controller + * + * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*). + * + * Use the following sequence: + * + * - Write EC_CMD_ACPI_WRITE to EC_LPC_ADDR_ACPI_CMD + * - Wait for EC_LPC_CMDR_PENDING bit to clear + * - Write address to EC_LPC_ADDR_ACPI_DATA + * - Wait for EC_LPC_CMDR_PENDING bit to clear + * - Write value to EC_LPC_ADDR_ACPI_DATA + */ +#define EC_CMD_ACPI_WRITE 0x0081 + +/* + * ACPI Burst Enable Embedded Controller + * + * This enables burst mode on the EC to allow the host to issue several + * commands back-to-back. While in this mode, writes to mapped multi-byte + * data are locked out to ensure data consistency. + */ +#define EC_CMD_ACPI_BURST_ENABLE 0x0082 + +/* + * ACPI Burst Disable Embedded Controller + * + * This disables burst mode on the EC and stops preventing EC writes to mapped + * multi-byte data. + */ +#define EC_CMD_ACPI_BURST_DISABLE 0x0083 + +/* + * ACPI Query Embedded Controller + * + * This clears the lowest-order bit in the currently pending host events, and + * sets the result code to the 1-based index of the bit (event 0x00000001 = 1, + * event 0x80000000 = 32), or 0 if no event was pending. + */ +#define EC_CMD_ACPI_QUERY_EVENT 0x0084 + +/* Valid addresses in ACPI memory space, for read/write commands */ + +/* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */ +#define EC_ACPI_MEM_VERSION 0x00 +/* + * Test location; writing value here updates test compliment byte to (0xff - + * value). + */ +#define EC_ACPI_MEM_TEST 0x01 +/* Test compliment; writes here are ignored. */ +#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 + +/* Keyboard backlight brightness percent (0 - 100) */ +#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03 +/* DPTF Target Fan Duty (0-100, 0xff for auto/none) */ +#define EC_ACPI_MEM_FAN_DUTY 0x04 + +/* + * DPTF temp thresholds. Any of the EC's temp sensors can have up to two + * independent thresholds attached to them. The current value of the ID + * register determines which sensor is affected by the THRESHOLD and COMMIT + * registers. The THRESHOLD register uses the same EC_TEMP_SENSOR_OFFSET scheme + * as the memory-mapped sensors. The COMMIT register applies those settings. + * + * The spec does not mandate any way to read back the threshold settings + * themselves, but when a threshold is crossed the AP needs a way to determine + * which sensor(s) are responsible. Each reading of the ID register clears and + * returns one sensor ID that has crossed one of its threshold (in either + * direction) since the last read. A value of 0xFF means "no new thresholds + * have tripped". Setting or enabling the thresholds for a sensor will clear + * the unread event count for that sensor. + */ +#define EC_ACPI_MEM_TEMP_ID 0x05 +#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06 +#define EC_ACPI_MEM_TEMP_COMMIT 0x07 +/* + * Here are the bits for the COMMIT register: + * bit 0 selects the threshold index for the chosen sensor (0/1) + * bit 1 enables/disables the selected threshold (0 = off, 1 = on) + * Each write to the commit register affects one threshold. + */ +#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK BIT(0) +#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK BIT(1) +/* + * Example: + * + * Set the thresholds for sensor 2 to 50 C and 60 C: + * write 2 to [0x05] -- select temp sensor 2 + * write 0x7b to [0x06] -- C_TO_K(50) - EC_TEMP_SENSOR_OFFSET + * write 0x2 to [0x07] -- enable threshold 0 with this value + * write 0x85 to [0x06] -- C_TO_K(60) - EC_TEMP_SENSOR_OFFSET + * write 0x3 to [0x07] -- enable threshold 1 with this value + * + * Disable the 60 C threshold, leaving the 50 C threshold unchanged: + * write 2 to [0x05] -- select temp sensor 2 + * write 0x1 to [0x07] -- disable threshold 1 + */ + +/* DPTF battery charging current limit */ +#define EC_ACPI_MEM_CHARGING_LIMIT 0x08 + +/* Charging limit is specified in 64 mA steps */ +#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64 +/* Value to disable DPTF battery charging limit */ +#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff + +/* + * Report device orientation + * Bits Definition + * 3:1 Device DPTF Profile Number (DDPN) + * 0 = Reserved for backward compatibility (indicates no valid + * profile number. Host should fall back to using TBMD). + * 1..7 = DPTF Profile number to indicate to host which table needs + * to be loaded. + * 0 Tablet Mode Device Indicator (TBMD) + */ +#define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09 +#define EC_ACPI_MEM_TBMD_SHIFT 0 +#define EC_ACPI_MEM_TBMD_MASK 0x1 +#define EC_ACPI_MEM_DDPN_SHIFT 1 +#define EC_ACPI_MEM_DDPN_MASK 0x7 + +/* + * Report device features. Uses the same format as the host command, except: + * + * bit 0 (EC_FEATURE_LIMITED) changes meaning from "EC code has a limited set + * of features", which is of limited interest when the system is already + * interpreting ACPI bytecode, to "EC_FEATURES[0-7] is not supported". Since + * these are supported, it defaults to 0. + * This allows detecting the presence of this field since older versions of + * the EC codebase would simply return 0xff to that unknown address. Check + * FEATURES0 != 0xff (or FEATURES0[0] == 0) to make sure that the other bits + * are valid. + */ +#define EC_ACPI_MEM_DEVICE_FEATURES0 0x0a +#define EC_ACPI_MEM_DEVICE_FEATURES1 0x0b +#define EC_ACPI_MEM_DEVICE_FEATURES2 0x0c +#define EC_ACPI_MEM_DEVICE_FEATURES3 0x0d +#define EC_ACPI_MEM_DEVICE_FEATURES4 0x0e +#define EC_ACPI_MEM_DEVICE_FEATURES5 0x0f +#define EC_ACPI_MEM_DEVICE_FEATURES6 0x10 +#define EC_ACPI_MEM_DEVICE_FEATURES7 0x11 + +#define EC_ACPI_MEM_BATTERY_INDEX 0x12 + +/* + * USB Port Power. Each bit indicates whether the corresponding USB ports' power + * is enabled (1) or disabled (0). + * bit 0 USB port ID 0 + * ... + * bit 7 USB port ID 7 + */ +#define EC_ACPI_MEM_USB_PORT_POWER 0x13 + +/* + * ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf. This data + * is read-only from the AP. Added in EC_ACPI_MEM_VERSION 2. + */ +#define EC_ACPI_MEM_MAPPED_BEGIN 0x20 +#define EC_ACPI_MEM_MAPPED_SIZE 0xe0 + +/* Current version of ACPI memory address space */ +#define EC_ACPI_MEM_VERSION_CURRENT 2 + + +/* + * This header file is used in coreboot both in C and ACPI code. The ACPI code + * is pre-processed to handle constants but the ASL compiler is unable to + * handle actual C code so keep it separate. + */ + + +/* + * Attributes for EC request and response packets. Just defining __packed + * results in inefficient assembly code on ARM, if the structure is actually + * 32-bit aligned, as it should be for all buffers. + * + * Be very careful when adding these to existing structures. They will round + * up the structure size to the specified boundary. + * + * Also be very careful to make that if a structure is included in some other + * parent structure that the alignment will still be true given the packing of + * the parent structure. This is particularly important if the sub-structure + * will be passed as a pointer to another function, since that function will + * not know about the misaligment caused by the parent structure's packing. + * + * Also be very careful using __packed - particularly when nesting non-packed + * structures inside packed ones. In fact, DO NOT use __packed directly; + * always use one of these attributes. + * + * Once everything is annotated properly, the following search strings should + * not return ANY matches in this file other than right here: + * + * "__packed" - generates inefficient code; all sub-structs must also be packed + * + * "struct [^_]" - all structs should be annotated, except for structs that are + * members of other structs/unions (and their original declarations should be + * annotated). + */ + +/* + * Packed structures make no assumption about alignment, so they do inefficient + * byte-wise reads. + */ +#define __ec_align1 __packed +#define __ec_align2 __packed +#define __ec_align4 __packed +#define __ec_align_size1 __packed +#define __ec_align_offset1 __packed +#define __ec_align_offset2 __packed +#define __ec_todo_packed __packed +#define __ec_todo_unpacked + + +/* LPC command status byte masks */ +/* EC has written a byte in the data register and host hasn't read it yet */ +#define EC_LPC_STATUS_TO_HOST 0x01 +/* Host has written a command/data byte and the EC hasn't read it yet */ +#define EC_LPC_STATUS_FROM_HOST 0x02 +/* EC is processing a command */ +#define EC_LPC_STATUS_PROCESSING 0x04 +/* Last write to EC was a command, not data */ +#define EC_LPC_STATUS_LAST_CMD 0x08 +/* EC is in burst mode */ +#define EC_LPC_STATUS_BURST_MODE 0x10 +/* SCI event is pending (requesting SCI query) */ +#define EC_LPC_STATUS_SCI_PENDING 0x20 +/* SMI event is pending (requesting SMI query) */ +#define EC_LPC_STATUS_SMI_PENDING 0x40 +/* (reserved) */ +#define EC_LPC_STATUS_RESERVED 0x80 + +/* + * EC is busy. This covers both the EC processing a command, and the host has + * written a new command but the EC hasn't picked it up yet. + */ +#define EC_LPC_STATUS_BUSY_MASK \ + (EC_LPC_STATUS_FROM_HOST | EC_LPC_STATUS_PROCESSING) + +/* + * Host command response codes (16-bit). Note that response codes should be + * stored in a uint16_t rather than directly in a value of this type. + */ +enum ec_status { + EC_RES_SUCCESS = 0, + EC_RES_INVALID_COMMAND = 1, + EC_RES_ERROR = 2, + EC_RES_INVALID_PARAM = 3, + EC_RES_ACCESS_DENIED = 4, + EC_RES_INVALID_RESPONSE = 5, + EC_RES_INVALID_VERSION = 6, + EC_RES_INVALID_CHECKSUM = 7, + EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */ + EC_RES_UNAVAILABLE = 9, /* No response available */ + EC_RES_TIMEOUT = 10, /* We got a timeout */ + EC_RES_OVERFLOW = 11, /* Table / data overflow */ + EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ + EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ + EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */ + EC_RES_BUS_ERROR = 15, /* Communications bus error */ + EC_RES_BUSY = 16, /* Up but too busy. Should retry */ + EC_RES_INVALID_HEADER_VERSION = 17, /* Header version invalid */ + EC_RES_INVALID_HEADER_CRC = 18, /* Header CRC invalid */ + EC_RES_INVALID_DATA_CRC = 19, /* Data CRC invalid */ + EC_RES_DUP_UNAVAILABLE = 20, /* Can't resend response */ +}; + +/* + * Host event codes. Note these are 1-based, not 0-based, because ACPI query + * EC command uses code 0 to mean "no event pending". We explicitly specify + * each value in the enum listing so they won't change if we delete/insert an + * item or rearrange the list (it needs to be stable across platforms, not + * just within a single compiled instance). + */ +enum host_event_code { + EC_HOST_EVENT_LID_CLOSED = 1, + EC_HOST_EVENT_LID_OPEN = 2, + EC_HOST_EVENT_POWER_BUTTON = 3, + EC_HOST_EVENT_AC_CONNECTED = 4, + EC_HOST_EVENT_AC_DISCONNECTED = 5, + EC_HOST_EVENT_BATTERY_LOW = 6, + EC_HOST_EVENT_BATTERY_CRITICAL = 7, + EC_HOST_EVENT_BATTERY = 8, + EC_HOST_EVENT_THERMAL_THRESHOLD = 9, + /* Event generated by a device attached to the EC */ + EC_HOST_EVENT_DEVICE = 10, + EC_HOST_EVENT_THERMAL = 11, + EC_HOST_EVENT_USB_CHARGER = 12, + EC_HOST_EVENT_KEY_PRESSED = 13, + /* + * EC has finished initializing the host interface. The host can check + * for this event following sending a EC_CMD_REBOOT_EC command to + * determine when the EC is ready to accept subsequent commands. + */ + EC_HOST_EVENT_INTERFACE_READY = 14, + /* Keyboard recovery combo has been pressed */ + EC_HOST_EVENT_KEYBOARD_RECOVERY = 15, + + /* Shutdown due to thermal overload */ + EC_HOST_EVENT_THERMAL_SHUTDOWN = 16, + /* Shutdown due to battery level too low */ + EC_HOST_EVENT_BATTERY_SHUTDOWN = 17, + + /* Suggest that the AP throttle itself */ + EC_HOST_EVENT_THROTTLE_START = 18, + /* Suggest that the AP resume normal speed */ + EC_HOST_EVENT_THROTTLE_STOP = 19, + + /* Hang detect logic detected a hang and host event timeout expired */ + EC_HOST_EVENT_HANG_DETECT = 20, + /* Hang detect logic detected a hang and warm rebooted the AP */ + EC_HOST_EVENT_HANG_REBOOT = 21, + + /* PD MCU triggering host event */ + EC_HOST_EVENT_PD_MCU = 22, + + /* Battery Status flags have changed */ + EC_HOST_EVENT_BATTERY_STATUS = 23, + + /* EC encountered a panic, triggering a reset */ + EC_HOST_EVENT_PANIC = 24, + + /* Keyboard fastboot combo has been pressed */ + EC_HOST_EVENT_KEYBOARD_FASTBOOT = 25, + + /* EC RTC event occurred */ + EC_HOST_EVENT_RTC = 26, + + /* Emulate MKBP event */ + EC_HOST_EVENT_MKBP = 27, + + /* EC desires to change state of host-controlled USB mux */ + EC_HOST_EVENT_USB_MUX = 28, + + /* TABLET/LAPTOP mode or detachable base attach/detach event */ + EC_HOST_EVENT_MODE_CHANGE = 29, + + /* Keyboard recovery combo with hardware reinitialization */ + EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT = 30, + + /* + * The high bit of the event mask is not used as a host event code. If + * it reads back as set, then the entire event mask should be + * considered invalid by the host. This can happen when reading the + * raw event status via EC_MEMMAP_HOST_EVENTS but the LPC interface is + * not initialized on the EC, or improperly configured on the host. + */ + EC_HOST_EVENT_INVALID = 32 +}; +/* Host event mask */ +#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1) + +/** + * struct ec_lpc_host_args - Arguments at EC_LPC_ADDR_HOST_ARGS + * @flags: The host argument flags. + * @command_version: Command version. + * @data_size: The length of data. + * @checksum: Checksum; sum of command + flags + command_version + data_size + + * all params/response data bytes. + */ +struct ec_lpc_host_args { + uint8_t flags; + uint8_t command_version; + uint8_t data_size; + uint8_t checksum; +} __ec_align4; + +/* Flags for ec_lpc_host_args.flags */ +/* + * Args are from host. Data area at EC_LPC_ADDR_HOST_PARAM contains command + * params. + * + * If EC gets a command and this flag is not set, this is an old-style command. + * Command version is 0 and params from host are at EC_LPC_ADDR_OLD_PARAM with + * unknown length. EC must respond with an old-style response (that is, + * without setting EC_HOST_ARGS_FLAG_TO_HOST). + */ +#define EC_HOST_ARGS_FLAG_FROM_HOST 0x01 +/* + * Args are from EC. Data area at EC_LPC_ADDR_HOST_PARAM contains response. + * + * If EC responds to a command and this flag is not set, this is an old-style + * response. Command version is 0 and response data from EC is at + * EC_LPC_ADDR_OLD_PARAM with unknown length. + */ +#define EC_HOST_ARGS_FLAG_TO_HOST 0x02 + +/*****************************************************************************/ +/* + * Byte codes returned by EC over SPI interface. + * + * These can be used by the AP to debug the EC interface, and to determine + * when the EC is not in a state where it will ever get around to responding + * to the AP. + * + * Example of sequence of bytes read from EC for a current good transfer: + * 1. - - AP asserts chip select (CS#) + * 2. EC_SPI_OLD_READY - AP sends first byte(s) of request + * 3. - - EC starts handling CS# interrupt + * 4. EC_SPI_RECEIVING - AP sends remaining byte(s) of request + * 5. EC_SPI_PROCESSING - EC starts processing request; AP is clocking in + * bytes looking for EC_SPI_FRAME_START + * 6. - - EC finishes processing and sets up response + * 7. EC_SPI_FRAME_START - AP reads frame byte + * 8. (response packet) - AP reads response packet + * 9. EC_SPI_PAST_END - Any additional bytes read by AP + * 10 - - AP deasserts chip select + * 11 - - EC processes CS# interrupt and sets up DMA for + * next request + * + * If the AP is waiting for EC_SPI_FRAME_START and sees any value other than + * the following byte values: + * EC_SPI_OLD_READY + * EC_SPI_RX_READY + * EC_SPI_RECEIVING + * EC_SPI_PROCESSING + * + * Then the EC found an error in the request, or was not ready for the request + * and lost data. The AP should give up waiting for EC_SPI_FRAME_START, + * because the EC is unable to tell when the AP is done sending its request. + */ + +/* + * Framing byte which precedes a response packet from the EC. After sending a + * request, the AP will clock in bytes until it sees the framing byte, then + * clock in the response packet. + */ +#define EC_SPI_FRAME_START 0xec + +/* + * Padding bytes which are clocked out after the end of a response packet. + */ +#define EC_SPI_PAST_END 0xed + +/* + * EC is ready to receive, and has ignored the byte sent by the AP. EC expects + * that the AP will send a valid packet header (starting with + * EC_COMMAND_PROTOCOL_3) in the next 32 bytes. + */ +#define EC_SPI_RX_READY 0xf8 + +/* + * EC has started receiving the request from the AP, but hasn't started + * processing it yet. + */ +#define EC_SPI_RECEIVING 0xf9 + +/* EC has received the entire request from the AP and is processing it. */ +#define EC_SPI_PROCESSING 0xfa + +/* + * EC received bad data from the AP, such as a packet header with an invalid + * length. EC will ignore all data until chip select deasserts. + */ +#define EC_SPI_RX_BAD_DATA 0xfb + +/* + * EC received data from the AP before it was ready. That is, the AP asserted + * chip select and started clocking data before the EC was ready to receive it. + * EC will ignore all data until chip select deasserts. + */ +#define EC_SPI_NOT_READY 0xfc + +/* + * EC was ready to receive a request from the AP. EC has treated the byte sent + * by the AP as part of a request packet, or (for old-style ECs) is processing + * a fully received packet but is not ready to respond yet. + */ +#define EC_SPI_OLD_READY 0xfd + +/*****************************************************************************/ + +/* + * Protocol version 2 for I2C and SPI send a request this way: + * + * 0 EC_CMD_VERSION0 + (command version) + * 1 Command number + * 2 Length of params = N + * 3..N+2 Params, if any + * N+3 8-bit checksum of bytes 0..N+2 + * + * The corresponding response is: + * + * 0 Result code (EC_RES_*) + * 1 Length of params = M + * 2..M+1 Params, if any + * M+2 8-bit checksum of bytes 0..M+1 + */ +#define EC_PROTO2_REQUEST_HEADER_BYTES 3 +#define EC_PROTO2_REQUEST_TRAILER_BYTES 1 +#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \ + EC_PROTO2_REQUEST_TRAILER_BYTES) + +#define EC_PROTO2_RESPONSE_HEADER_BYTES 2 +#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1 +#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \ + EC_PROTO2_RESPONSE_TRAILER_BYTES) + +/* Parameter length was limited by the LPC interface */ +#define EC_PROTO2_MAX_PARAM_SIZE 0xfc + +/* Maximum request and response packet sizes for protocol version 2 */ +#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \ + EC_PROTO2_MAX_PARAM_SIZE) +#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \ + EC_PROTO2_MAX_PARAM_SIZE) + +/*****************************************************************************/ + +/* + * Value written to legacy command port / prefix byte to indicate protocol + * 3+ structs are being used. Usage is bus-dependent. + */ +#define EC_COMMAND_PROTOCOL_3 0xda + +#define EC_HOST_REQUEST_VERSION 3 + +/** + * struct ec_host_request - Version 3 request from host. + * @struct_version: Should be 3. The EC will return EC_RES_INVALID_HEADER if it + * receives a header with a version it doesn't know how to + * parse. + * @checksum: Checksum of request and data; sum of all bytes including checksum + * should total to 0. + * @command: Command to send (EC_CMD_...) + * @command_version: Command version. + * @reserved: Unused byte in current protocol version; set to 0. + * @data_len: Length of data which follows this header. + */ +struct ec_host_request { + uint8_t struct_version; + uint8_t checksum; + uint16_t command; + uint8_t command_version; + uint8_t reserved; + uint16_t data_len; +} __ec_align4; + +#define EC_HOST_RESPONSE_VERSION 3 + +/** + * struct ec_host_response - Version 3 response from EC. + * @struct_version: Struct version (=3). + * @checksum: Checksum of response and data; sum of all bytes including + * checksum should total to 0. + * @result: EC's response to the command (separate from communication failure) + * @data_len: Length of data which follows this header. + * @reserved: Unused bytes in current protocol version; set to 0. + */ +struct ec_host_response { + uint8_t struct_version; + uint8_t checksum; + uint16_t result; + uint16_t data_len; + uint16_t reserved; +} __ec_align4; + +/*****************************************************************************/ + +/* + * Host command protocol V4. + * + * Packets always start with a request or response header. They are followed + * by data_len bytes of data. If the data_crc_present flag is set, the data + * bytes are followed by a CRC-8 of that data, using using x^8 + x^2 + x + 1 + * polynomial. + * + * Host algorithm when sending a request q: + * + * 101) tries_left=(some value, e.g. 3); + * 102) q.seq_num++ + * 103) q.seq_dup=0 + * 104) Calculate q.header_crc. + * 105) Send request q to EC. + * 106) Wait for response r. Go to 201 if received or 301 if timeout. + * + * 201) If r.struct_version != 4, go to 301. + * 202) If r.header_crc mismatches calculated CRC for r header, go to 301. + * 203) If r.data_crc_present and r.data_crc mismatches, go to 301. + * 204) If r.seq_num != q.seq_num, go to 301. + * 205) If r.seq_dup == q.seq_dup, return success. + * 207) If r.seq_dup == 1, go to 301. + * 208) Return error. + * + * 301) If --tries_left <= 0, return error. + * 302) If q.seq_dup == 1, go to 105. + * 303) q.seq_dup = 1 + * 304) Go to 104. + * + * EC algorithm when receiving a request q. + * EC has response buffer r, error buffer e. + * + * 101) If q.struct_version != 4, set e.result = EC_RES_INVALID_HEADER_VERSION + * and go to 301 + * 102) If q.header_crc mismatches calculated CRC, set e.result = + * EC_RES_INVALID_HEADER_CRC and go to 301 + * 103) If q.data_crc_present, calculate data CRC. If that mismatches the CRC + * byte at the end of the packet, set e.result = EC_RES_INVALID_DATA_CRC + * and go to 301. + * 104) If q.seq_dup == 0, go to 201. + * 105) If q.seq_num != r.seq_num, go to 201. + * 106) If q.seq_dup == r.seq_dup, go to 205, else go to 203. + * + * 201) Process request q into response r. + * 202) r.seq_num = q.seq_num + * 203) r.seq_dup = q.seq_dup + * 204) Calculate r.header_crc + * 205) If r.data_len > 0 and data is no longer available, set e.result = + * EC_RES_DUP_UNAVAILABLE and go to 301. + * 206) Send response r. + * + * 301) e.seq_num = q.seq_num + * 302) e.seq_dup = q.seq_dup + * 303) Calculate e.header_crc. + * 304) Send error response e. + */ + +/* Version 4 request from host */ +struct ec_host_request4 { + /* + * bits 0-3: struct_version: Structure version (=4) + * bit 4: is_response: Is response (=0) + * bits 5-6: seq_num: Sequence number + * bit 7: seq_dup: Sequence duplicate flag + */ + uint8_t fields0; + + /* + * bits 0-4: command_version: Command version + * bits 5-6: Reserved (set 0, ignore on read) + * bit 7: data_crc_present: Is data CRC present after data + */ + uint8_t fields1; + + /* Command code (EC_CMD_*) */ + uint16_t command; + + /* Length of data which follows this header (not including data CRC) */ + uint16_t data_len; + + /* Reserved (set 0, ignore on read) */ + uint8_t reserved; + + /* CRC-8 of above fields, using x^8 + x^2 + x + 1 polynomial */ + uint8_t header_crc; +} __ec_align4; + +/* Version 4 response from EC */ +struct ec_host_response4 { + /* + * bits 0-3: struct_version: Structure version (=4) + * bit 4: is_response: Is response (=1) + * bits 5-6: seq_num: Sequence number + * bit 7: seq_dup: Sequence duplicate flag + */ + uint8_t fields0; + + /* + * bits 0-6: Reserved (set 0, ignore on read) + * bit 7: data_crc_present: Is data CRC present after data + */ + uint8_t fields1; + + /* Result code (EC_RES_*) */ + uint16_t result; + + /* Length of data which follows this header (not including data CRC) */ + uint16_t data_len; + + /* Reserved (set 0, ignore on read) */ + uint8_t reserved; + + /* CRC-8 of above fields, using x^8 + x^2 + x + 1 polynomial */ + uint8_t header_crc; +} __ec_align4; + +/* Fields in fields0 byte */ +#define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f +#define EC_PACKET4_0_IS_RESPONSE_MASK 0x10 +#define EC_PACKET4_0_SEQ_NUM_SHIFT 5 +#define EC_PACKET4_0_SEQ_NUM_MASK 0x60 +#define EC_PACKET4_0_SEQ_DUP_MASK 0x80 + +/* Fields in fields1 byte */ +#define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f /* (request only) */ +#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80 + +/*****************************************************************************/ +/* + * Notes on commands: + * + * Each command is an 16-bit command value. Commands which take params or + * return response data specify structures for that data. If no structure is + * specified, the command does not input or output data, respectively. + * Parameter/response length is implicit in the structs. Some underlying + * communication protocols (I2C, SPI) may add length or checksum headers, but + * those are implementation-dependent and not defined here. + * + * All commands MUST be #defined to be 4-digit UPPER CASE hex values + * (e.g., 0x00AB, not 0xab) for CONFIG_HOSTCMD_SECTION_SORTED to work. + */ + +/*****************************************************************************/ +/* General / test commands */ + +/* + * Get protocol version, used to deal with non-backward compatible protocol + * changes. + */ +#define EC_CMD_PROTO_VERSION 0x0000 + +/** + * struct ec_response_proto_version - Response to the proto version command. + * @version: The protocol version. + */ +struct ec_response_proto_version { + uint32_t version; +} __ec_align4; + +/* + * Hello. This is a simple command to test the EC is responsive to + * commands. + */ +#define EC_CMD_HELLO 0x0001 + +/** + * struct ec_params_hello - Parameters to the hello command. + * @in_data: Pass anything here. + */ +struct ec_params_hello { + uint32_t in_data; +} __ec_align4; + +/** + * struct ec_response_hello - Response to the hello command. + * @out_data: Output will be in_data + 0x01020304. + */ +struct ec_response_hello { + uint32_t out_data; +} __ec_align4; + +/* Get version number */ +#define EC_CMD_GET_VERSION 0x0002 + +enum ec_current_image { + EC_IMAGE_UNKNOWN = 0, + EC_IMAGE_RO, + EC_IMAGE_RW +}; + +/** + * struct ec_response_get_version - Response to the get version command. + * @version_string_ro: Null-terminated RO firmware version string. + * @version_string_rw: Null-terminated RW firmware version string. + * @reserved: Unused bytes; was previously RW-B firmware version string. + * @current_image: One of ec_current_image. + */ +struct ec_response_get_version { + char version_string_ro[32]; + char version_string_rw[32]; + char reserved[32]; + uint32_t current_image; +} __ec_align4; + +/* Read test */ +#define EC_CMD_READ_TEST 0x0003 + +/** + * struct ec_params_read_test - Parameters for the read test command. + * @offset: Starting value for read buffer. + * @size: Size to read in bytes. + */ +struct ec_params_read_test { + uint32_t offset; + uint32_t size; +} __ec_align4; + +/** + * struct ec_response_read_test - Response to the read test command. + * @data: Data returned by the read test command. + */ +struct ec_response_read_test { + uint32_t data[32]; +} __ec_align4; + +/* + * Get build information + * + * Response is null-terminated string. + */ +#define EC_CMD_GET_BUILD_INFO 0x0004 + +/* Get chip info */ +#define EC_CMD_GET_CHIP_INFO 0x0005 + +/** + * struct ec_response_get_chip_info - Response to the get chip info command. + * @vendor: Null-terminated string for chip vendor. + * @name: Null-terminated string for chip name. + * @revision: Null-terminated string for chip mask version. + */ +struct ec_response_get_chip_info { + char vendor[32]; + char name[32]; + char revision[32]; +} __ec_align4; + +/* Get board HW version */ +#define EC_CMD_GET_BOARD_VERSION 0x0006 + +/** + * struct ec_response_board_version - Response to the board version command. + * @board_version: A monotonously incrementing number. + */ +struct ec_response_board_version { + uint16_t board_version; +} __ec_align2; + +/* + * Read memory-mapped data. + * + * This is an alternate interface to memory-mapped data for bus protocols + * which don't support direct-mapped memory - I2C, SPI, etc. + * + * Response is params.size bytes of data. + */ +#define EC_CMD_READ_MEMMAP 0x0007 + +/** + * struct ec_params_read_memmap - Parameters for the read memory map command. + * @offset: Offset in memmap (EC_MEMMAP_*). + * @size: Size to read in bytes. + */ +struct ec_params_read_memmap { + uint8_t offset; + uint8_t size; +} __ec_align1; + +/* Read versions supported for a command */ +#define EC_CMD_GET_CMD_VERSIONS 0x0008 + +/** + * struct ec_params_get_cmd_versions - Parameters for the get command versions. + * @cmd: Command to check. + */ +struct ec_params_get_cmd_versions { + uint8_t cmd; +} __ec_align1; + +/** + * struct ec_params_get_cmd_versions_v1 - Parameters for the get command + * versions (v1) + * @cmd: Command to check. + */ +struct ec_params_get_cmd_versions_v1 { + uint16_t cmd; +} __ec_align2; + +/** + * struct ec_response_get_cmd_version - Response to the get command versions. + * @version_mask: Mask of supported versions; use EC_VER_MASK() to compare with + * a desired version. + */ +struct ec_response_get_cmd_versions { + uint32_t version_mask; +} __ec_align4; + +/* + * Check EC communications status (busy). This is needed on i2c/spi but not + * on lpc since it has its own out-of-band busy indicator. + * + * lpc must read the status from the command register. Attempting this on + * lpc will overwrite the args/parameter space and corrupt its data. + */ +#define EC_CMD_GET_COMMS_STATUS 0x0009 + +/* Avoid using ec_status which is for return values */ +enum ec_comms_status { + EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */ +}; + +/** + * struct ec_response_get_comms_status - Response to the get comms status + * command. + * @flags: Mask of enum ec_comms_status. + */ +struct ec_response_get_comms_status { + uint32_t flags; /* Mask of enum ec_comms_status */ +} __ec_align4; + +/* Fake a variety of responses, purely for testing purposes. */ +#define EC_CMD_TEST_PROTOCOL 0x000A + +/* Tell the EC what to send back to us. */ +struct ec_params_test_protocol { + uint32_t ec_result; + uint32_t ret_len; + uint8_t buf[32]; +} __ec_align4; + +/* Here it comes... */ +struct ec_response_test_protocol { + uint8_t buf[32]; +} __ec_align4; + +/* Get protocol information */ +#define EC_CMD_GET_PROTOCOL_INFO 0x000B + +/* Flags for ec_response_get_protocol_info.flags */ +/* EC_RES_IN_PROGRESS may be returned if a command is slow */ +#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED BIT(0) + +/** + * struct ec_response_get_protocol_info - Response to the get protocol info. + * @protocol_versions: Bitmask of protocol versions supported (1 << n means + * version n). + * @max_request_packet_size: Maximum request packet size in bytes. + * @max_response_packet_size: Maximum response packet size in bytes. + * @flags: see EC_PROTOCOL_INFO_* + */ +struct ec_response_get_protocol_info { + /* Fields which exist if at least protocol version 3 supported */ + uint32_t protocol_versions; + uint16_t max_request_packet_size; + uint16_t max_response_packet_size; + uint32_t flags; +} __ec_align4; + + +/*****************************************************************************/ +/* Get/Set miscellaneous values */ + +/* The upper byte of .flags tells what to do (nothing means "get") */ +#define EC_GSV_SET 0x80000000 + +/* + * The lower three bytes of .flags identifies the parameter, if that has + * meaning for an individual command. + */ +#define EC_GSV_PARAM_MASK 0x00ffffff + +struct ec_params_get_set_value { + uint32_t flags; + uint32_t value; +} __ec_align4; + +struct ec_response_get_set_value { + uint32_t flags; + uint32_t value; +} __ec_align4; + +/* More than one command can use these structs to get/set parameters. */ +#define EC_CMD_GSV_PAUSE_IN_S5 0x000C + +/*****************************************************************************/ +/* List the features supported by the firmware */ +#define EC_CMD_GET_FEATURES 0x000D + +/* Supported features */ +enum ec_feature_code { + /* + * This image contains a limited set of features. Another image + * in RW partition may support more features. + */ + EC_FEATURE_LIMITED = 0, + /* + * Commands for probing/reading/writing/erasing the flash in the + * EC are present. + */ + EC_FEATURE_FLASH = 1, + /* + * Can control the fan speed directly. + */ + EC_FEATURE_PWM_FAN = 2, + /* + * Can control the intensity of the keyboard backlight. + */ + EC_FEATURE_PWM_KEYB = 3, + /* + * Support Google lightbar, introduced on Pixel. + */ + EC_FEATURE_LIGHTBAR = 4, + /* Control of LEDs */ + EC_FEATURE_LED = 5, + /* Exposes an interface to control gyro and sensors. + * The host goes through the EC to access these sensors. + * In addition, the EC may provide composite sensors, like lid angle. + */ + EC_FEATURE_MOTION_SENSE = 6, + /* The keyboard is controlled by the EC */ + EC_FEATURE_KEYB = 7, + /* The AP can use part of the EC flash as persistent storage. */ + EC_FEATURE_PSTORE = 8, + /* The EC monitors BIOS port 80h, and can return POST codes. */ + EC_FEATURE_PORT80 = 9, + /* + * Thermal management: include TMP specific commands. + * Higher level than direct fan control. + */ + EC_FEATURE_THERMAL = 10, + /* Can switch the screen backlight on/off */ + EC_FEATURE_BKLIGHT_SWITCH = 11, + /* Can switch the wifi module on/off */ + EC_FEATURE_WIFI_SWITCH = 12, + /* Monitor host events, through for example SMI or SCI */ + EC_FEATURE_HOST_EVENTS = 13, + /* The EC exposes GPIO commands to control/monitor connected devices. */ + EC_FEATURE_GPIO = 14, + /* The EC can send i2c messages to downstream devices. */ + EC_FEATURE_I2C = 15, + /* Command to control charger are included */ + EC_FEATURE_CHARGER = 16, + /* Simple battery support. */ + EC_FEATURE_BATTERY = 17, + /* + * Support Smart battery protocol + * (Common Smart Battery System Interface Specification) + */ + EC_FEATURE_SMART_BATTERY = 18, + /* EC can detect when the host hangs. */ + EC_FEATURE_HANG_DETECT = 19, + /* Report power information, for pit only */ + EC_FEATURE_PMU = 20, + /* Another Cros EC device is present downstream of this one */ + EC_FEATURE_SUB_MCU = 21, + /* Support USB Power delivery (PD) commands */ + EC_FEATURE_USB_PD = 22, + /* Control USB multiplexer, for audio through USB port for instance. */ + EC_FEATURE_USB_MUX = 23, + /* Motion Sensor code has an internal software FIFO */ + EC_FEATURE_MOTION_SENSE_FIFO = 24, + /* Support temporary secure vstore */ + EC_FEATURE_VSTORE = 25, + /* EC decides on USB-C SS mux state, muxes configured by host */ + EC_FEATURE_USBC_SS_MUX_VIRTUAL = 26, + /* EC has RTC feature that can be controlled by host commands */ + EC_FEATURE_RTC = 27, + /* The MCU exposes a Fingerprint sensor */ + EC_FEATURE_FINGERPRINT = 28, + /* The MCU exposes a Touchpad */ + EC_FEATURE_TOUCHPAD = 29, + /* The MCU has RWSIG task enabled */ + EC_FEATURE_RWSIG = 30, + /* EC has device events support */ + EC_FEATURE_DEVICE_EVENT = 31, + /* EC supports the unified wake masks for LPC/eSPI systems */ + EC_FEATURE_UNIFIED_WAKE_MASKS = 32, + /* EC supports 64-bit host events */ + EC_FEATURE_HOST_EVENT64 = 33, + /* EC runs code in RAM (not in place, a.k.a. XIP) */ + EC_FEATURE_EXEC_IN_RAM = 34, + /* EC supports CEC commands */ + EC_FEATURE_CEC = 35, + /* EC supports tight sensor timestamping. */ + EC_FEATURE_MOTION_SENSE_TIGHT_TIMESTAMPS = 36, + /* + * EC supports tablet mode detection aligned to Chrome and allows + * setting of threshold by host command using + * MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. + */ + EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37, + /* EC supports audio codec. */ + EC_FEATURE_AUDIO_CODEC = 38, + /* The MCU is a System Companion Processor (SCP). */ + EC_FEATURE_SCP = 39, + /* The MCU is an Integrated Sensor Hub */ + EC_FEATURE_ISH = 40, +}; + +#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) +#define EC_FEATURE_MASK_1(event_code) BIT(event_code - 32) + +struct ec_response_get_features { + uint32_t flags[2]; +} __ec_align4; + +/*****************************************************************************/ +/* Get the board's SKU ID from EC */ +#define EC_CMD_GET_SKU_ID 0x000E + +/* Set SKU ID from AP */ +#define EC_CMD_SET_SKU_ID 0x000F + +struct ec_sku_id_info { + uint32_t sku_id; +} __ec_align4; + +/*****************************************************************************/ +/* Flash commands */ + +/* Get flash info */ +#define EC_CMD_FLASH_INFO 0x0010 +#define EC_VER_FLASH_INFO 2 + +/** + * struct ec_response_flash_info - Response to the flash info command. + * @flash_size: Usable flash size in bytes. + * @write_block_size: Write block size. Write offset and size must be a + * multiple of this. + * @erase_block_size: Erase block size. Erase offset and size must be a + * multiple of this. + * @protect_block_size: Protection block size. Protection offset and size + * must be a multiple of this. + * + * Version 0 returns these fields. + */ +struct ec_response_flash_info { + uint32_t flash_size; + uint32_t write_block_size; + uint32_t erase_block_size; + uint32_t protect_block_size; +} __ec_align4; + +/* + * Flags for version 1+ flash info command + * EC flash erases bits to 0 instead of 1. + */ +#define EC_FLASH_INFO_ERASE_TO_0 BIT(0) + +/* + * Flash must be selected for read/write/erase operations to succeed. This may + * be necessary on a chip where write/erase can be corrupted by other board + * activity, or where the chip needs to enable some sort of programming voltage, + * or where the read/write/erase operations require cleanly suspending other + * chip functionality. + */ +#define EC_FLASH_INFO_SELECT_REQUIRED BIT(1) + +/** + * struct ec_response_flash_info_1 - Response to the flash info v1 command. + * @flash_size: Usable flash size in bytes. + * @write_block_size: Write block size. Write offset and size must be a + * multiple of this. + * @erase_block_size: Erase block size. Erase offset and size must be a + * multiple of this. + * @protect_block_size: Protection block size. Protection offset and size + * must be a multiple of this. + * @write_ideal_size: Ideal write size in bytes. Writes will be fastest if + * size is exactly this and offset is a multiple of this. + * For example, an EC may have a write buffer which can do + * half-page operations if data is aligned, and a slower + * word-at-a-time write mode. + * @flags: Flags; see EC_FLASH_INFO_* + * + * Version 1 returns the same initial fields as version 0, with additional + * fields following. + * + * gcc anonymous structs don't seem to get along with the __packed directive; + * if they did we'd define the version 0 structure as a sub-structure of this + * one. + * + * Version 2 supports flash banks of different sizes: + * The caller specified the number of banks it has preallocated + * (num_banks_desc) + * The EC returns the number of banks describing the flash memory. + * It adds banks descriptions up to num_banks_desc. + */ +struct ec_response_flash_info_1 { + /* Version 0 fields; see above for description */ + uint32_t flash_size; + uint32_t write_block_size; + uint32_t erase_block_size; + uint32_t protect_block_size; + + /* Version 1 adds these fields: */ + uint32_t write_ideal_size; + uint32_t flags; +} __ec_align4; + +struct ec_params_flash_info_2 { + /* Number of banks to describe */ + uint16_t num_banks_desc; + /* Reserved; set 0; ignore on read */ + uint8_t reserved[2]; +} __ec_align4; + +struct ec_flash_bank { + /* Number of sector is in this bank. */ + uint16_t count; + /* Size in power of 2 of each sector (8 --> 256 bytes) */ + uint8_t size_exp; + /* Minimal write size for the sectors in this bank */ + uint8_t write_size_exp; + /* Erase size for the sectors in this bank */ + uint8_t erase_size_exp; + /* Size for write protection, usually identical to erase size. */ + uint8_t protect_size_exp; + /* Reserved; set 0; ignore on read */ + uint8_t reserved[2]; +}; + +struct ec_response_flash_info_2 { + /* Total flash in the EC. */ + uint32_t flash_size; + /* Flags; see EC_FLASH_INFO_* */ + uint32_t flags; + /* Maximum size to use to send data to write to the EC. */ + uint32_t write_ideal_size; + /* Number of banks present in the EC. */ + uint16_t num_banks_total; + /* Number of banks described in banks array. */ + uint16_t num_banks_desc; + struct ec_flash_bank banks[0]; +} __ec_align4; + +/* + * Read flash + * + * Response is params.size bytes of data. + */ +#define EC_CMD_FLASH_READ 0x0011 + +/** + * struct ec_params_flash_read - Parameters for the flash read command. + * @offset: Byte offset to read. + * @size: Size to read in bytes. + */ +struct ec_params_flash_read { + uint32_t offset; + uint32_t size; +} __ec_align4; + +/* Write flash */ +#define EC_CMD_FLASH_WRITE 0x0012 +#define EC_VER_FLASH_WRITE 1 + +/* Version 0 of the flash command supported only 64 bytes of data */ +#define EC_FLASH_WRITE_VER0_SIZE 64 + +/** + * struct ec_params_flash_write - Parameters for the flash write command. + * @offset: Byte offset to write. + * @size: Size to write in bytes. + */ +struct ec_params_flash_write { + uint32_t offset; + uint32_t size; + /* Followed by data to write */ +} __ec_align4; + +/* Erase flash */ +#define EC_CMD_FLASH_ERASE 0x0013 + +/** + * struct ec_params_flash_erase - Parameters for the flash erase command, v0. + * @offset: Byte offset to erase. + * @size: Size to erase in bytes. + */ +struct ec_params_flash_erase { + uint32_t offset; + uint32_t size; +} __ec_align4; + +/* + * v1 add async erase: + * subcommands can returns: + * EC_RES_SUCCESS : erased (see ERASE_SECTOR_ASYNC case below). + * EC_RES_INVALID_PARAM : offset/size are not aligned on a erase boundary. + * EC_RES_ERROR : other errors. + * EC_RES_BUSY : an existing erase operation is in progress. + * EC_RES_ACCESS_DENIED: Trying to erase running image. + * + * When ERASE_SECTOR_ASYNC returns EC_RES_SUCCESS, the operation is just + * properly queued. The user must call ERASE_GET_RESULT subcommand to get + * the proper result. + * When ERASE_GET_RESULT returns EC_RES_BUSY, the caller must wait and send + * ERASE_GET_RESULT again to get the result of ERASE_SECTOR_ASYNC. + * ERASE_GET_RESULT command may timeout on EC where flash access is not + * permitted while erasing. (For instance, STM32F4). + */ +enum ec_flash_erase_cmd { + FLASH_ERASE_SECTOR, /* Erase and wait for result */ + FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */ + FLASH_ERASE_GET_RESULT, /* Ask for last erase result */ +}; + +/** + * struct ec_params_flash_erase_v1 - Parameters for the flash erase command, v1. + * @cmd: One of ec_flash_erase_cmd. + * @reserved: Pad byte; currently always contains 0. + * @flag: No flags defined yet; set to 0. + * @params: Same as v0 parameters. + */ +struct ec_params_flash_erase_v1 { + uint8_t cmd; + uint8_t reserved; + uint16_t flag; + struct ec_params_flash_erase params; +} __ec_align4; + +/* + * Get/set flash protection. + * + * If mask!=0, sets/clear the requested bits of flags. Depending on the + * firmware write protect GPIO, not all flags will take effect immediately; + * some flags require a subsequent hard reset to take effect. Check the + * returned flags bits to see what actually happened. + * + * If mask=0, simply returns the current flags state. + */ +#define EC_CMD_FLASH_PROTECT 0x0015 +#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */ + +/* Flags for flash protection */ +/* RO flash code protected when the EC boots */ +#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0) +/* + * RO flash code protected now. If this bit is set, at-boot status cannot + * be changed. + */ +#define EC_FLASH_PROTECT_RO_NOW BIT(1) +/* Entire flash code protected now, until reboot. */ +#define EC_FLASH_PROTECT_ALL_NOW BIT(2) +/* Flash write protect GPIO is asserted now */ +#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3) +/* Error - at least one bank of flash is stuck locked, and cannot be unlocked */ +#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4) +/* + * Error - flash protection is in inconsistent state. At least one bank of + * flash which should be protected is not protected. Usually fixed by + * re-requesting the desired flags, or by a hard reset if that fails. + */ +#define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5) +/* Entire flash code protected when the EC boots */ +#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6) +/* RW flash code protected when the EC boots */ +#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7) +/* RW flash code protected now. */ +#define EC_FLASH_PROTECT_RW_NOW BIT(8) +/* Rollback information flash region protected when the EC boots */ +#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9) +/* Rollback information flash region protected now */ +#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10) + + +/** + * struct ec_params_flash_protect - Parameters for the flash protect command. + * @mask: Bits in flags to apply. + * @flags: New flags to apply. + */ +struct ec_params_flash_protect { + uint32_t mask; + uint32_t flags; +} __ec_align4; + +/** + * struct ec_response_flash_protect - Response to the flash protect command. + * @flags: Current value of flash protect flags. + * @valid_flags: Flags which are valid on this platform. This allows the + * caller to distinguish between flags which aren't set vs. flags + * which can't be set on this platform. + * @writable_flags: Flags which can be changed given the current protection + * state. + */ +struct ec_response_flash_protect { + uint32_t flags; + uint32_t valid_flags; + uint32_t writable_flags; +} __ec_align4; + +/* + * Note: commands 0x14 - 0x19 version 0 were old commands to get/set flash + * write protect. These commands may be reused with version > 0. + */ + +/* Get the region offset/size */ +#define EC_CMD_FLASH_REGION_INFO 0x0016 +#define EC_VER_FLASH_REGION_INFO 1 + +enum ec_flash_region { + /* Region which holds read-only EC image */ + EC_FLASH_REGION_RO = 0, + /* + * Region which holds active RW image. 'Active' is different from + * 'running'. Active means 'scheduled-to-run'. Since RO image always + * scheduled to run, active/non-active applies only to RW images (for + * the same reason 'update' applies only to RW images. It's a state of + * an image on a flash. Running image can be RO, RW_A, RW_B but active + * image can only be RW_A or RW_B. In recovery mode, an active RW image + * doesn't enter 'running' state but it's still active on a flash. + */ + EC_FLASH_REGION_ACTIVE, + /* + * Region which should be write-protected in the factory (a superset of + * EC_FLASH_REGION_RO) + */ + EC_FLASH_REGION_WP_RO, + /* Region which holds updatable (non-active) RW image */ + EC_FLASH_REGION_UPDATE, + /* Number of regions */ + EC_FLASH_REGION_COUNT, +}; +/* + * 'RW' is vague if there are multiple RW images; we mean the active one, + * so the old constant is deprecated. + */ +#define EC_FLASH_REGION_RW EC_FLASH_REGION_ACTIVE + +/** + * struct ec_params_flash_region_info - Parameters for the flash region info + * command. + * @region: Flash region; see EC_FLASH_REGION_* + */ +struct ec_params_flash_region_info { + uint32_t region; +} __ec_align4; + +struct ec_response_flash_region_info { + uint32_t offset; + uint32_t size; +} __ec_align4; + +/* Read/write VbNvContext */ +#define EC_CMD_VBNV_CONTEXT 0x0017 +#define EC_VER_VBNV_CONTEXT 1 +#define EC_VBNV_BLOCK_SIZE 16 + +enum ec_vbnvcontext_op { + EC_VBNV_CONTEXT_OP_READ, + EC_VBNV_CONTEXT_OP_WRITE, +}; + +struct ec_params_vbnvcontext { + uint32_t op; + uint8_t block[EC_VBNV_BLOCK_SIZE]; +} __ec_align4; + +struct ec_response_vbnvcontext { + uint8_t block[EC_VBNV_BLOCK_SIZE]; +} __ec_align4; + + +/* Get SPI flash information */ +#define EC_CMD_FLASH_SPI_INFO 0x0018 + +struct ec_response_flash_spi_info { + /* JEDEC info from command 0x9F (manufacturer, memory type, size) */ + uint8_t jedec[3]; + + /* Pad byte; currently always contains 0 */ + uint8_t reserved0; + + /* Manufacturer / device ID from command 0x90 */ + uint8_t mfr_dev_id[2]; + + /* Status registers from command 0x05 and 0x35 */ + uint8_t sr1, sr2; +} __ec_align1; + + +/* Select flash during flash operations */ +#define EC_CMD_FLASH_SELECT 0x0019 + +/** + * struct ec_params_flash_select - Parameters for the flash select command. + * @select: 1 to select flash, 0 to deselect flash + */ +struct ec_params_flash_select { + uint8_t select; +} __ec_align4; + + +/*****************************************************************************/ +/* PWM commands */ + +/* Get fan target RPM */ +#define EC_CMD_PWM_GET_FAN_TARGET_RPM 0x0020 + +struct ec_response_pwm_get_fan_rpm { + uint32_t rpm; +} __ec_align4; + +/* Set target fan RPM */ +#define EC_CMD_PWM_SET_FAN_TARGET_RPM 0x0021 + +/* Version 0 of input params */ +struct ec_params_pwm_set_fan_target_rpm_v0 { + uint32_t rpm; +} __ec_align4; + +/* Version 1 of input params */ +struct ec_params_pwm_set_fan_target_rpm_v1 { + uint32_t rpm; + uint8_t fan_idx; +} __ec_align_size1; + +/* Get keyboard backlight */ +/* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ +#define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x0022 + +struct ec_response_pwm_get_keyboard_backlight { + uint8_t percent; + uint8_t enabled; +} __ec_align1; + +/* Set keyboard backlight */ +/* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ +#define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x0023 + +struct ec_params_pwm_set_keyboard_backlight { + uint8_t percent; +} __ec_align1; + +/* Set target fan PWM duty cycle */ +#define EC_CMD_PWM_SET_FAN_DUTY 0x0024 + +/* Version 0 of input params */ +struct ec_params_pwm_set_fan_duty_v0 { + uint32_t percent; +} __ec_align4; + +/* Version 1 of input params */ +struct ec_params_pwm_set_fan_duty_v1 { + uint32_t percent; + uint8_t fan_idx; +} __ec_align_size1; + +#define EC_CMD_PWM_SET_DUTY 0x0025 +/* 16 bit duty cycle, 0xffff = 100% */ +#define EC_PWM_MAX_DUTY 0xffff + +enum ec_pwm_type { + /* All types, indexed by board-specific enum pwm_channel */ + EC_PWM_TYPE_GENERIC = 0, + /* Keyboard backlight */ + EC_PWM_TYPE_KB_LIGHT, + /* Display backlight */ + EC_PWM_TYPE_DISPLAY_LIGHT, + EC_PWM_TYPE_COUNT, +}; + +struct ec_params_pwm_set_duty { + uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ + uint8_t pwm_type; /* ec_pwm_type */ + uint8_t index; /* Type-specific index, or 0 if unique */ +} __ec_align4; + +#define EC_CMD_PWM_GET_DUTY 0x0026 + +struct ec_params_pwm_get_duty { + uint8_t pwm_type; /* ec_pwm_type */ + uint8_t index; /* Type-specific index, or 0 if unique */ +} __ec_align1; + +struct ec_response_pwm_get_duty { + uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ +} __ec_align2; + +/*****************************************************************************/ +/* + * Lightbar commands. This looks worse than it is. Since we only use one HOST + * command to say "talk to the lightbar", we put the "and tell it to do X" part + * into a subcommand. We'll make separate structs for subcommands with + * different input args, so that we know how much to expect. + */ +#define EC_CMD_LIGHTBAR_CMD 0x0028 + +struct rgb_s { + uint8_t r, g, b; +} __ec_todo_unpacked; + +#define LB_BATTERY_LEVELS 4 + +/* + * List of tweakable parameters. NOTE: It's __packed so it can be sent in a + * host command, but the alignment is the same regardless. Keep it that way. + */ +struct lightbar_params_v0 { + /* Timing */ + int32_t google_ramp_up; + int32_t google_ramp_down; + int32_t s3s0_ramp_up; + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0s3_ramp_down; + int32_t s3_sleep_for; + int32_t s3_ramp_up; + int32_t s3_ramp_down; + + /* Oscillation */ + uint8_t new_s0; + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ + + /* Brightness limits based on the backlight and AC. */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ + + /* Battery level thresholds */ + uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; + + /* Map [AC][battery_level] to color index */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + + /* Color palette */ + struct rgb_s color[8]; /* 0-3 are Google colors */ +} __ec_todo_packed; + +struct lightbar_params_v1 { + /* Timing */ + int32_t google_ramp_up; + int32_t google_ramp_down; + int32_t s3s0_ramp_up; + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0s3_ramp_down; + int32_t s3_sleep_for; + int32_t s3_ramp_up; + int32_t s3_ramp_down; + int32_t s5_ramp_up; + int32_t s5_ramp_down; + int32_t tap_tick_delay; + int32_t tap_gate_delay; + int32_t tap_display_time; + + /* Tap-for-battery params */ + uint8_t tap_pct_red; + uint8_t tap_pct_green; + uint8_t tap_seg_min_on; + uint8_t tap_seg_max_on; + uint8_t tap_seg_osc; + uint8_t tap_idx[3]; + + /* Oscillation */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ + + /* Brightness limits based on the backlight and AC. */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ + + /* Battery level thresholds */ + uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; + + /* Map [AC][battery_level] to color index */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + + /* s5: single color pulse on inhibited power-up */ + uint8_t s5_idx; + + /* Color palette */ + struct rgb_s color[8]; /* 0-3 are Google colors */ +} __ec_todo_packed; + +/* Lightbar command params v2 + * crbug.com/467716 + * + * lightbar_parms_v1 was too big for i2c, therefore in v2, we split them up by + * logical groups to make it more manageable ( < 120 bytes). + * + * NOTE: Each of these groups must be less than 120 bytes. + */ + +struct lightbar_params_v2_timing { + /* Timing */ + int32_t google_ramp_up; + int32_t google_ramp_down; + int32_t s3s0_ramp_up; + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0s3_ramp_down; + int32_t s3_sleep_for; + int32_t s3_ramp_up; + int32_t s3_ramp_down; + int32_t s5_ramp_up; + int32_t s5_ramp_down; + int32_t tap_tick_delay; + int32_t tap_gate_delay; + int32_t tap_display_time; +} __ec_todo_packed; + +struct lightbar_params_v2_tap { + /* Tap-for-battery params */ + uint8_t tap_pct_red; + uint8_t tap_pct_green; + uint8_t tap_seg_min_on; + uint8_t tap_seg_max_on; + uint8_t tap_seg_osc; + uint8_t tap_idx[3]; +} __ec_todo_packed; + +struct lightbar_params_v2_oscillation { + /* Oscillation */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ +} __ec_todo_packed; + +struct lightbar_params_v2_brightness { + /* Brightness limits based on the backlight and AC. */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ +} __ec_todo_packed; + +struct lightbar_params_v2_thresholds { + /* Battery level thresholds */ + uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; +} __ec_todo_packed; + +struct lightbar_params_v2_colors { + /* Map [AC][battery_level] to color index */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + + /* s5: single color pulse on inhibited power-up */ + uint8_t s5_idx; + + /* Color palette */ + struct rgb_s color[8]; /* 0-3 are Google colors */ +} __ec_todo_packed; + +/* Lightbar program. */ +#define EC_LB_PROG_LEN 192 +struct lightbar_program { + uint8_t size; + uint8_t data[EC_LB_PROG_LEN]; +} __ec_todo_unpacked; + +struct ec_params_lightbar { + uint8_t cmd; /* Command (see enum lightbar_command) */ + union { + /* + * The following commands have no args: + * + * dump, off, on, init, get_seq, get_params_v0, get_params_v1, + * version, get_brightness, get_demo, suspend, resume, + * get_params_v2_timing, get_params_v2_tap, get_params_v2_osc, + * get_params_v2_bright, get_params_v2_thlds, + * get_params_v2_colors + * + * Don't use an empty struct, because C++ hates that. + */ + + struct __ec_todo_unpacked { + uint8_t num; + } set_brightness, seq, demo; + + struct __ec_todo_unpacked { + uint8_t ctrl, reg, value; + } reg; + + struct __ec_todo_unpacked { + uint8_t led, red, green, blue; + } set_rgb; + + struct __ec_todo_unpacked { + uint8_t led; + } get_rgb; + + struct __ec_todo_unpacked { + uint8_t enable; + } manual_suspend_ctrl; + + struct lightbar_params_v0 set_params_v0; + struct lightbar_params_v1 set_params_v1; + + struct lightbar_params_v2_timing set_v2par_timing; + struct lightbar_params_v2_tap set_v2par_tap; + struct lightbar_params_v2_oscillation set_v2par_osc; + struct lightbar_params_v2_brightness set_v2par_bright; + struct lightbar_params_v2_thresholds set_v2par_thlds; + struct lightbar_params_v2_colors set_v2par_colors; + + struct lightbar_program set_program; + }; +} __ec_todo_packed; + +struct ec_response_lightbar { + union { + struct __ec_todo_unpacked { + struct __ec_todo_unpacked { + uint8_t reg; + uint8_t ic0; + uint8_t ic1; + } vals[23]; + } dump; + + struct __ec_todo_unpacked { + uint8_t num; + } get_seq, get_brightness, get_demo; + + struct lightbar_params_v0 get_params_v0; + struct lightbar_params_v1 get_params_v1; + + + struct lightbar_params_v2_timing get_params_v2_timing; + struct lightbar_params_v2_tap get_params_v2_tap; + struct lightbar_params_v2_oscillation get_params_v2_osc; + struct lightbar_params_v2_brightness get_params_v2_bright; + struct lightbar_params_v2_thresholds get_params_v2_thlds; + struct lightbar_params_v2_colors get_params_v2_colors; + + struct __ec_todo_unpacked { + uint32_t num; + uint32_t flags; + } version; + + struct __ec_todo_unpacked { + uint8_t red, green, blue; + } get_rgb; + + /* + * The following commands have no response: + * + * off, on, init, set_brightness, seq, reg, set_rgb, demo, + * set_params_v0, set_params_v1, set_program, + * manual_suspend_ctrl, suspend, resume, set_v2par_timing, + * set_v2par_tap, set_v2par_osc, set_v2par_bright, + * set_v2par_thlds, set_v2par_colors + */ + }; +} __ec_todo_packed; + +/* Lightbar commands */ +enum lightbar_command { + LIGHTBAR_CMD_DUMP = 0, + LIGHTBAR_CMD_OFF = 1, + LIGHTBAR_CMD_ON = 2, + LIGHTBAR_CMD_INIT = 3, + LIGHTBAR_CMD_SET_BRIGHTNESS = 4, + LIGHTBAR_CMD_SEQ = 5, + LIGHTBAR_CMD_REG = 6, + LIGHTBAR_CMD_SET_RGB = 7, + LIGHTBAR_CMD_GET_SEQ = 8, + LIGHTBAR_CMD_DEMO = 9, + LIGHTBAR_CMD_GET_PARAMS_V0 = 10, + LIGHTBAR_CMD_SET_PARAMS_V0 = 11, + LIGHTBAR_CMD_VERSION = 12, + LIGHTBAR_CMD_GET_BRIGHTNESS = 13, + LIGHTBAR_CMD_GET_RGB = 14, + LIGHTBAR_CMD_GET_DEMO = 15, + LIGHTBAR_CMD_GET_PARAMS_V1 = 16, + LIGHTBAR_CMD_SET_PARAMS_V1 = 17, + LIGHTBAR_CMD_SET_PROGRAM = 18, + LIGHTBAR_CMD_MANUAL_SUSPEND_CTRL = 19, + LIGHTBAR_CMD_SUSPEND = 20, + LIGHTBAR_CMD_RESUME = 21, + LIGHTBAR_CMD_GET_PARAMS_V2_TIMING = 22, + LIGHTBAR_CMD_SET_PARAMS_V2_TIMING = 23, + LIGHTBAR_CMD_GET_PARAMS_V2_TAP = 24, + LIGHTBAR_CMD_SET_PARAMS_V2_TAP = 25, + LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION = 26, + LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION = 27, + LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS = 28, + LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS = 29, + LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS = 30, + LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31, + LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32, + LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33, + LIGHTBAR_NUM_CMDS +}; + +/*****************************************************************************/ +/* LED control commands */ + +#define EC_CMD_LED_CONTROL 0x0029 + +enum ec_led_id { + /* LED to indicate battery state of charge */ + EC_LED_ID_BATTERY_LED = 0, + /* + * LED to indicate system power state (on or in suspend). + * May be on power button or on C-panel. + */ + EC_LED_ID_POWER_LED, + /* LED on power adapter or its plug */ + EC_LED_ID_ADAPTER_LED, + /* LED to indicate left side */ + EC_LED_ID_LEFT_LED, + /* LED to indicate right side */ + EC_LED_ID_RIGHT_LED, + /* LED to indicate recovery mode with HW_REINIT */ + EC_LED_ID_RECOVERY_HW_REINIT_LED, + /* LED to indicate sysrq debug mode. */ + EC_LED_ID_SYSRQ_DEBUG_LED, + + EC_LED_ID_COUNT +}; + +/* LED control flags */ +#define EC_LED_FLAGS_QUERY BIT(0) /* Query LED capability only */ +#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */ + +enum ec_led_colors { + EC_LED_COLOR_RED = 0, + EC_LED_COLOR_GREEN, + EC_LED_COLOR_BLUE, + EC_LED_COLOR_YELLOW, + EC_LED_COLOR_WHITE, + EC_LED_COLOR_AMBER, + + EC_LED_COLOR_COUNT +}; + +struct ec_params_led_control { + uint8_t led_id; /* Which LED to control */ + uint8_t flags; /* Control flags */ + + uint8_t brightness[EC_LED_COLOR_COUNT]; +} __ec_align1; + +struct ec_response_led_control { + /* + * Available brightness value range. + * + * Range 0 means color channel not present. + * Range 1 means on/off control. + * Other values means the LED is control by PWM. + */ + uint8_t brightness_range[EC_LED_COLOR_COUNT]; +} __ec_align1; + +/*****************************************************************************/ +/* Verified boot commands */ + +/* + * Note: command code 0x29 version 0 was VBOOT_CMD in Link EVT; it may be + * reused for other purposes with version > 0. + */ + +/* Verified boot hash command */ +#define EC_CMD_VBOOT_HASH 0x002A + +struct ec_params_vboot_hash { + uint8_t cmd; /* enum ec_vboot_hash_cmd */ + uint8_t hash_type; /* enum ec_vboot_hash_type */ + uint8_t nonce_size; /* Nonce size; may be 0 */ + uint8_t reserved0; /* Reserved; set 0 */ + uint32_t offset; /* Offset in flash to hash */ + uint32_t size; /* Number of bytes to hash */ + uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */ +} __ec_align4; + +struct ec_response_vboot_hash { + uint8_t status; /* enum ec_vboot_hash_status */ + uint8_t hash_type; /* enum ec_vboot_hash_type */ + uint8_t digest_size; /* Size of hash digest in bytes */ + uint8_t reserved0; /* Ignore; will be 0 */ + uint32_t offset; /* Offset in flash which was hashed */ + uint32_t size; /* Number of bytes hashed */ + uint8_t hash_digest[64]; /* Hash digest data */ +} __ec_align4; + +enum ec_vboot_hash_cmd { + EC_VBOOT_HASH_GET = 0, /* Get current hash status */ + EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */ + EC_VBOOT_HASH_START = 2, /* Start computing a new hash */ + EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */ +}; + +enum ec_vboot_hash_type { + EC_VBOOT_HASH_TYPE_SHA256 = 0, /* SHA-256 */ +}; + +enum ec_vboot_hash_status { + EC_VBOOT_HASH_STATUS_NONE = 0, /* No hash (not started, or aborted) */ + EC_VBOOT_HASH_STATUS_DONE = 1, /* Finished computing a hash */ + EC_VBOOT_HASH_STATUS_BUSY = 2, /* Busy computing a hash */ +}; + +/* + * Special values for offset for EC_VBOOT_HASH_START and EC_VBOOT_HASH_RECALC. + * If one of these is specified, the EC will automatically update offset and + * size to the correct values for the specified image (RO or RW). + */ +#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe +#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd +#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc + +/* + * 'RW' is vague if there are multiple RW images; we mean the active one, + * so the old constant is deprecated. + */ +#define EC_VBOOT_HASH_OFFSET_RW EC_VBOOT_HASH_OFFSET_ACTIVE + +/*****************************************************************************/ +/* + * Motion sense commands. We'll make separate structs for sub-commands with + * different input args, so that we know how much to expect. + */ +#define EC_CMD_MOTION_SENSE_CMD 0x002B + +/* Motion sense commands */ +enum motionsense_command { + /* + * Dump command returns all motion sensor data including motion sense + * module flags and individual sensor flags. + */ + MOTIONSENSE_CMD_DUMP = 0, + + /* + * Info command returns data describing the details of a given sensor, + * including enum motionsensor_type, enum motionsensor_location, and + * enum motionsensor_chip. + */ + MOTIONSENSE_CMD_INFO = 1, + + /* + * EC Rate command is a setter/getter command for the EC sampling rate + * in milliseconds. + * It is per sensor, the EC run sample task at the minimum of all + * sensors EC_RATE. + * For sensors without hardware FIFO, EC_RATE should be equals to 1/ODR + * to collect all the sensor samples. + * For sensor with hardware FIFO, EC_RATE is used as the maximal delay + * to process of all motion sensors in milliseconds. + */ + MOTIONSENSE_CMD_EC_RATE = 2, + + /* + * Sensor ODR command is a setter/getter command for the output data + * rate of a specific motion sensor in millihertz. + */ + MOTIONSENSE_CMD_SENSOR_ODR = 3, + + /* + * Sensor range command is a setter/getter command for the range of + * a specified motion sensor in +/-G's or +/- deg/s. + */ + MOTIONSENSE_CMD_SENSOR_RANGE = 4, + + /* + * Setter/getter command for the keyboard wake angle. When the lid + * angle is greater than this value, keyboard wake is disabled in S3, + * and when the lid angle goes less than this value, keyboard wake is + * enabled. Note, the lid angle measurement is an approximate, + * un-calibrated value, hence the wake angle isn't exact. + */ + MOTIONSENSE_CMD_KB_WAKE_ANGLE = 5, + + /* + * Returns a single sensor data. + */ + MOTIONSENSE_CMD_DATA = 6, + + /* + * Return sensor fifo info. + */ + MOTIONSENSE_CMD_FIFO_INFO = 7, + + /* + * Insert a flush element in the fifo and return sensor fifo info. + * The host can use that element to synchronize its operation. + */ + MOTIONSENSE_CMD_FIFO_FLUSH = 8, + + /* + * Return a portion of the fifo. + */ + MOTIONSENSE_CMD_FIFO_READ = 9, + + /* + * Perform low level calibration. + * On sensors that support it, ask to do offset calibration. + */ + MOTIONSENSE_CMD_PERFORM_CALIB = 10, + + /* + * Sensor Offset command is a setter/getter command for the offset + * used for calibration. + * The offsets can be calculated by the host, or via + * PERFORM_CALIB command. + */ + MOTIONSENSE_CMD_SENSOR_OFFSET = 11, + + /* + * List available activities for a MOTION sensor. + * Indicates if they are enabled or disabled. + */ + MOTIONSENSE_CMD_LIST_ACTIVITIES = 12, + + /* + * Activity management + * Enable/Disable activity recognition. + */ + MOTIONSENSE_CMD_SET_ACTIVITY = 13, + + /* + * Lid Angle + */ + MOTIONSENSE_CMD_LID_ANGLE = 14, + + /* + * Allow the FIFO to trigger interrupt via MKBP events. + * By default the FIFO does not send interrupt to process the FIFO + * until the AP is ready or it is coming from a wakeup sensor. + */ + MOTIONSENSE_CMD_FIFO_INT_ENABLE = 15, + + /* + * Spoof the readings of the sensors. The spoofed readings can be set + * to arbitrary values, or will lock to the last read actual values. + */ + MOTIONSENSE_CMD_SPOOF = 16, + + /* Set lid angle for tablet mode detection. */ + MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE = 17, + + /* + * Sensor Scale command is a setter/getter command for the calibration + * scale. + */ + MOTIONSENSE_CMD_SENSOR_SCALE = 18, + + /* Number of motionsense sub-commands. */ + MOTIONSENSE_NUM_CMDS +}; + +/* List of motion sensor types. */ +enum motionsensor_type { + MOTIONSENSE_TYPE_ACCEL = 0, + MOTIONSENSE_TYPE_GYRO = 1, + MOTIONSENSE_TYPE_MAG = 2, + MOTIONSENSE_TYPE_PROX = 3, + MOTIONSENSE_TYPE_LIGHT = 4, + MOTIONSENSE_TYPE_ACTIVITY = 5, + MOTIONSENSE_TYPE_BARO = 6, + MOTIONSENSE_TYPE_SYNC = 7, + MOTIONSENSE_TYPE_MAX, +}; + +/* List of motion sensor locations. */ +enum motionsensor_location { + MOTIONSENSE_LOC_BASE = 0, + MOTIONSENSE_LOC_LID = 1, + MOTIONSENSE_LOC_CAMERA = 2, + MOTIONSENSE_LOC_MAX, +}; + +/* List of motion sensor chips. */ +enum motionsensor_chip { + MOTIONSENSE_CHIP_KXCJ9 = 0, + MOTIONSENSE_CHIP_LSM6DS0 = 1, + MOTIONSENSE_CHIP_BMI160 = 2, + MOTIONSENSE_CHIP_SI1141 = 3, + MOTIONSENSE_CHIP_SI1142 = 4, + MOTIONSENSE_CHIP_SI1143 = 5, + MOTIONSENSE_CHIP_KX022 = 6, + MOTIONSENSE_CHIP_L3GD20H = 7, + MOTIONSENSE_CHIP_BMA255 = 8, + MOTIONSENSE_CHIP_BMP280 = 9, + MOTIONSENSE_CHIP_OPT3001 = 10, + MOTIONSENSE_CHIP_BH1730 = 11, + MOTIONSENSE_CHIP_GPIO = 12, + MOTIONSENSE_CHIP_LIS2DH = 13, + MOTIONSENSE_CHIP_LSM6DSM = 14, + MOTIONSENSE_CHIP_LIS2DE = 15, + MOTIONSENSE_CHIP_LIS2MDL = 16, + MOTIONSENSE_CHIP_LSM6DS3 = 17, + MOTIONSENSE_CHIP_LSM6DSO = 18, + MOTIONSENSE_CHIP_LNG2DM = 19, + MOTIONSENSE_CHIP_MAX, +}; + +/* List of orientation positions */ +enum motionsensor_orientation { + MOTIONSENSE_ORIENTATION_LANDSCAPE = 0, + MOTIONSENSE_ORIENTATION_PORTRAIT = 1, + MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_PORTRAIT = 2, + MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE = 3, + MOTIONSENSE_ORIENTATION_UNKNOWN = 4, +}; + +struct ec_response_motion_sensor_data { + /* Flags for each sensor. */ + uint8_t flags; + /* Sensor number the data comes from. */ + uint8_t sensor_num; + /* Each sensor is up to 3-axis. */ + union { + int16_t data[3]; + struct __ec_todo_packed { + uint16_t reserved; + uint32_t timestamp; + }; + struct __ec_todo_unpacked { + uint8_t activity; /* motionsensor_activity */ + uint8_t state; + int16_t add_info[2]; + }; + }; +} __ec_todo_packed; + +/* Note: used in ec_response_get_next_data */ +struct ec_response_motion_sense_fifo_info { + /* Size of the fifo */ + uint16_t size; + /* Amount of space used in the fifo */ + uint16_t count; + /* Timestamp recorded in us. + * aka accurate timestamp when host event was triggered. + */ + uint32_t timestamp; + /* Total amount of vector lost */ + uint16_t total_lost; + /* Lost events since the last fifo_info, per sensors */ + uint16_t lost[0]; +} __ec_todo_packed; + +struct ec_response_motion_sense_fifo_data { + uint32_t number_data; + struct ec_response_motion_sensor_data data[0]; +} __ec_todo_packed; + +/* List supported activity recognition */ +enum motionsensor_activity { + MOTIONSENSE_ACTIVITY_RESERVED = 0, + MOTIONSENSE_ACTIVITY_SIG_MOTION = 1, + MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2, + MOTIONSENSE_ACTIVITY_ORIENTATION = 3, +}; + +struct ec_motion_sense_activity { + uint8_t sensor_num; + uint8_t activity; /* one of enum motionsensor_activity */ + uint8_t enable; /* 1: enable, 0: disable */ + uint8_t reserved; + uint16_t parameters[3]; /* activity dependent parameters */ +} __ec_todo_unpacked; + +/* Module flag masks used for the dump sub-command. */ +#define MOTIONSENSE_MODULE_FLAG_ACTIVE BIT(0) + +/* Sensor flag masks used for the dump sub-command. */ +#define MOTIONSENSE_SENSOR_FLAG_PRESENT BIT(0) + +/* + * Flush entry for synchronization. + * data contains time stamp + */ +#define MOTIONSENSE_SENSOR_FLAG_FLUSH BIT(0) +#define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP BIT(1) +#define MOTIONSENSE_SENSOR_FLAG_WAKEUP BIT(2) +#define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE BIT(3) +#define MOTIONSENSE_SENSOR_FLAG_ODR BIT(4) + +/* + * Send this value for the data element to only perform a read. If you + * send any other value, the EC will interpret it as data to set and will + * return the actual value set. + */ +#define EC_MOTION_SENSE_NO_VALUE -1 + +#define EC_MOTION_SENSE_INVALID_CALIB_TEMP 0x8000 + +/* MOTIONSENSE_CMD_SENSOR_OFFSET subcommand flag */ +/* Set Calibration information */ +#define MOTION_SENSE_SET_OFFSET BIT(0) + +/* Default Scale value, factor 1. */ +#define MOTION_SENSE_DEFAULT_SCALE BIT(15) + +#define LID_ANGLE_UNRELIABLE 500 + +enum motionsense_spoof_mode { + /* Disable spoof mode. */ + MOTIONSENSE_SPOOF_MODE_DISABLE = 0, + + /* Enable spoof mode, but use provided component values. */ + MOTIONSENSE_SPOOF_MODE_CUSTOM, + + /* Enable spoof mode, but use the current sensor values. */ + MOTIONSENSE_SPOOF_MODE_LOCK_CURRENT, + + /* Query the current spoof mode status for the sensor. */ + MOTIONSENSE_SPOOF_MODE_QUERY, +}; + +struct ec_params_motion_sense { + uint8_t cmd; + union { + /* Used for MOTIONSENSE_CMD_DUMP. */ + struct __ec_todo_unpacked { + /* + * Maximal number of sensor the host is expecting. + * 0 means the host is only interested in the number + * of sensors controlled by the EC. + */ + uint8_t max_sensor_count; + } dump; + + /* + * Used for MOTIONSENSE_CMD_KB_WAKE_ANGLE. + */ + struct __ec_todo_unpacked { + /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. + * kb_wake_angle: angle to wakup AP. + */ + int16_t data; + } kb_wake_angle; + + /* + * Used for MOTIONSENSE_CMD_INFO, MOTIONSENSE_CMD_DATA + * and MOTIONSENSE_CMD_PERFORM_CALIB. + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + } info, info_3, data, fifo_flush, perform_calib, + list_activities; + + /* + * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR + * and MOTIONSENSE_CMD_SENSOR_RANGE. + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + + /* Rounding flag, true for round-up, false for down. */ + uint8_t roundup; + + uint16_t reserved; + + /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. */ + int32_t data; + } ec_rate, sensor_odr, sensor_range; + + /* Used for MOTIONSENSE_CMD_SENSOR_OFFSET */ + struct __ec_todo_packed { + uint8_t sensor_num; + + /* + * bit 0: If set (MOTION_SENSE_SET_OFFSET), set + * the calibration information in the EC. + * If unset, just retrieve calibration information. + */ + uint16_t flags; + + /* + * Temperature at calibration, in units of 0.01 C + * 0x8000: invalid / unknown. + * 0x0: 0C + * 0x7fff: +327.67C + */ + int16_t temp; + + /* + * Offset for calibration. + * Unit: + * Accelerometer: 1/1024 g + * Gyro: 1/1024 deg/s + * Compass: 1/16 uT + */ + int16_t offset[3]; + } sensor_offset; + + /* Used for MOTIONSENSE_CMD_SENSOR_SCALE */ + struct __ec_todo_packed { + uint8_t sensor_num; + + /* + * bit 0: If set (MOTION_SENSE_SET_OFFSET), set + * the calibration information in the EC. + * If unset, just retrieve calibration information. + */ + uint16_t flags; + + /* + * Temperature at calibration, in units of 0.01 C + * 0x8000: invalid / unknown. + * 0x0: 0C + * 0x7fff: +327.67C + */ + int16_t temp; + + /* + * Scale for calibration: + * By default scale is 1, it is encoded on 16bits: + * 1 = BIT(15) + * ~2 = 0xFFFF + * ~0 = 0. + */ + uint16_t scale[3]; + } sensor_scale; + + + /* Used for MOTIONSENSE_CMD_FIFO_INFO */ + /* (no params) */ + + /* Used for MOTIONSENSE_CMD_FIFO_READ */ + struct __ec_todo_unpacked { + /* + * Number of expected vector to return. + * EC may return less or 0 if none available. + */ + uint32_t max_data_vector; + } fifo_read; + + struct ec_motion_sense_activity set_activity; + + /* Used for MOTIONSENSE_CMD_LID_ANGLE */ + /* (no params) */ + + /* Used for MOTIONSENSE_CMD_FIFO_INT_ENABLE */ + struct __ec_todo_unpacked { + /* + * 1: enable, 0 disable fifo, + * EC_MOTION_SENSE_NO_VALUE return value. + */ + int8_t enable; + } fifo_int_enable; + + /* Used for MOTIONSENSE_CMD_SPOOF */ + struct __ec_todo_packed { + uint8_t sensor_id; + + /* See enum motionsense_spoof_mode. */ + uint8_t spoof_enable; + + /* Ignored, used for alignment. */ + uint8_t reserved; + + /* Individual component values to spoof. */ + int16_t components[3]; + } spoof; + + /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ + struct __ec_todo_unpacked { + /* + * Lid angle threshold for switching between tablet and + * clamshell mode. + */ + int16_t lid_angle; + + /* + * Hysteresis degree to prevent fluctuations between + * clamshell and tablet mode if lid angle keeps + * changing around the threshold. Lid motion driver will + * use lid_angle + hys_degree to trigger tablet mode and + * lid_angle - hys_degree to trigger clamshell mode. + */ + int16_t hys_degree; + } tablet_mode_threshold; + }; +} __ec_todo_packed; + +struct ec_response_motion_sense { + union { + /* Used for MOTIONSENSE_CMD_DUMP */ + struct __ec_todo_unpacked { + /* Flags representing the motion sensor module. */ + uint8_t module_flags; + + /* Number of sensors managed directly by the EC. */ + uint8_t sensor_count; + + /* + * Sensor data is truncated if response_max is too small + * for holding all the data. + */ + struct ec_response_motion_sensor_data sensor[0]; + } dump; + + /* Used for MOTIONSENSE_CMD_INFO. */ + struct __ec_todo_unpacked { + /* Should be element of enum motionsensor_type. */ + uint8_t type; + + /* Should be element of enum motionsensor_location. */ + uint8_t location; + + /* Should be element of enum motionsensor_chip. */ + uint8_t chip; + } info; + + /* Used for MOTIONSENSE_CMD_INFO version 3 */ + struct __ec_todo_unpacked { + /* Should be element of enum motionsensor_type. */ + uint8_t type; + + /* Should be element of enum motionsensor_location. */ + uint8_t location; + + /* Should be element of enum motionsensor_chip. */ + uint8_t chip; + + /* Minimum sensor sampling frequency */ + uint32_t min_frequency; + + /* Maximum sensor sampling frequency */ + uint32_t max_frequency; + + /* Max number of sensor events that could be in fifo */ + uint32_t fifo_max_event_count; + } info_3; + + /* Used for MOTIONSENSE_CMD_DATA */ + struct ec_response_motion_sensor_data data; + + /* + * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR, + * MOTIONSENSE_CMD_SENSOR_RANGE, + * MOTIONSENSE_CMD_KB_WAKE_ANGLE, + * MOTIONSENSE_CMD_FIFO_INT_ENABLE and + * MOTIONSENSE_CMD_SPOOF. + */ + struct __ec_todo_unpacked { + /* Current value of the parameter queried. */ + int32_t ret; + } ec_rate, sensor_odr, sensor_range, kb_wake_angle, + fifo_int_enable, spoof; + + /* + * Used for MOTIONSENSE_CMD_SENSOR_OFFSET, + * PERFORM_CALIB. + */ + struct __ec_todo_unpacked { + int16_t temp; + int16_t offset[3]; + } sensor_offset, perform_calib; + + /* Used for MOTIONSENSE_CMD_SENSOR_SCALE */ + struct __ec_todo_unpacked { + int16_t temp; + uint16_t scale[3]; + } sensor_scale; + + struct ec_response_motion_sense_fifo_info fifo_info, fifo_flush; + + struct ec_response_motion_sense_fifo_data fifo_read; + + struct __ec_todo_packed { + uint16_t reserved; + uint32_t enabled; + uint32_t disabled; + } list_activities; + + /* No params for set activity */ + + /* Used for MOTIONSENSE_CMD_LID_ANGLE */ + struct __ec_todo_unpacked { + /* + * Angle between 0 and 360 degree if available, + * LID_ANGLE_UNRELIABLE otherwise. + */ + uint16_t value; + } lid_angle; + + /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ + struct __ec_todo_unpacked { + /* + * Lid angle threshold for switching between tablet and + * clamshell mode. + */ + uint16_t lid_angle; + + /* Hysteresis degree. */ + uint16_t hys_degree; + } tablet_mode_threshold; + + }; +} __ec_todo_packed; + +/*****************************************************************************/ +/* Force lid open command */ + +/* Make lid event always open */ +#define EC_CMD_FORCE_LID_OPEN 0x002C + +struct ec_params_force_lid_open { + uint8_t enabled; +} __ec_align1; + +/*****************************************************************************/ +/* Configure the behavior of the power button */ +#define EC_CMD_CONFIG_POWER_BUTTON 0x002D + +enum ec_config_power_button_flags { + /* Enable/Disable power button pulses for x86 devices */ + EC_POWER_BUTTON_ENABLE_PULSE = BIT(0), +}; + +struct ec_params_config_power_button { + /* See enum ec_config_power_button_flags */ + uint8_t flags; +} __ec_align1; + +/*****************************************************************************/ +/* USB charging control commands */ + +/* Set USB port charging mode */ +#define EC_CMD_USB_CHARGE_SET_MODE 0x0030 + +struct ec_params_usb_charge_set_mode { + uint8_t usb_port_id; + uint8_t mode:7; + uint8_t inhibit_charge:1; +} __ec_align1; + +/*****************************************************************************/ +/* Persistent storage for host */ + +/* Maximum bytes that can be read/written in a single command */ +#define EC_PSTORE_SIZE_MAX 64 + +/* Get persistent storage info */ +#define EC_CMD_PSTORE_INFO 0x0040 + +struct ec_response_pstore_info { + /* Persistent storage size, in bytes */ + uint32_t pstore_size; + /* Access size; read/write offset and size must be a multiple of this */ + uint32_t access_size; +} __ec_align4; + +/* + * Read persistent storage + * + * Response is params.size bytes of data. + */ +#define EC_CMD_PSTORE_READ 0x0041 + +struct ec_params_pstore_read { + uint32_t offset; /* Byte offset to read */ + uint32_t size; /* Size to read in bytes */ +} __ec_align4; + +/* Write persistent storage */ +#define EC_CMD_PSTORE_WRITE 0x0042 + +struct ec_params_pstore_write { + uint32_t offset; /* Byte offset to write */ + uint32_t size; /* Size to write in bytes */ + uint8_t data[EC_PSTORE_SIZE_MAX]; +} __ec_align4; + +/*****************************************************************************/ +/* Real-time clock */ + +/* RTC params and response structures */ +struct ec_params_rtc { + uint32_t time; +} __ec_align4; + +struct ec_response_rtc { + uint32_t time; +} __ec_align4; + +/* These use ec_response_rtc */ +#define EC_CMD_RTC_GET_VALUE 0x0044 +#define EC_CMD_RTC_GET_ALARM 0x0045 + +/* These all use ec_params_rtc */ +#define EC_CMD_RTC_SET_VALUE 0x0046 +#define EC_CMD_RTC_SET_ALARM 0x0047 + +/* Pass as time param to SET_ALARM to clear the current alarm */ +#define EC_RTC_ALARM_CLEAR 0 + +/*****************************************************************************/ +/* Port80 log access */ + +/* Maximum entries that can be read/written in a single command */ +#define EC_PORT80_SIZE_MAX 32 + +/* Get last port80 code from previous boot */ +#define EC_CMD_PORT80_LAST_BOOT 0x0048 +#define EC_CMD_PORT80_READ 0x0048 + +enum ec_port80_subcmd { + EC_PORT80_GET_INFO = 0, + EC_PORT80_READ_BUFFER, +}; + +struct ec_params_port80_read { + uint16_t subcmd; + union { + struct __ec_todo_unpacked { + uint32_t offset; + uint32_t num_entries; + } read_buffer; + }; +} __ec_todo_packed; + +struct ec_response_port80_read { + union { + struct __ec_todo_unpacked { + uint32_t writes; + uint32_t history_size; + uint32_t last_boot; + } get_info; + struct __ec_todo_unpacked { + uint16_t codes[EC_PORT80_SIZE_MAX]; + } data; + }; +} __ec_todo_packed; + +struct ec_response_port80_last_boot { + uint16_t code; +} __ec_align2; + +/*****************************************************************************/ +/* Temporary secure storage for host verified boot use */ + +/* Number of bytes in a vstore slot */ +#define EC_VSTORE_SLOT_SIZE 64 + +/* Maximum number of vstore slots */ +#define EC_VSTORE_SLOT_MAX 32 + +/* Get persistent storage info */ +#define EC_CMD_VSTORE_INFO 0x0049 +struct ec_response_vstore_info { + /* Indicates which slots are locked */ + uint32_t slot_locked; + /* Total number of slots available */ + uint8_t slot_count; +} __ec_align_size1; + +/* + * Read temporary secure storage + * + * Response is EC_VSTORE_SLOT_SIZE bytes of data. + */ +#define EC_CMD_VSTORE_READ 0x004A + +struct ec_params_vstore_read { + uint8_t slot; /* Slot to read from */ +} __ec_align1; + +struct ec_response_vstore_read { + uint8_t data[EC_VSTORE_SLOT_SIZE]; +} __ec_align1; + +/* + * Write temporary secure storage and lock it. + */ +#define EC_CMD_VSTORE_WRITE 0x004B + +struct ec_params_vstore_write { + uint8_t slot; /* Slot to write to */ + uint8_t data[EC_VSTORE_SLOT_SIZE]; +} __ec_align1; + +/*****************************************************************************/ +/* Thermal engine commands. Note that there are two implementations. We'll + * reuse the command number, but the data and behavior is incompatible. + * Version 0 is what originally shipped on Link. + * Version 1 separates the CPU thermal limits from the fan control. + */ + +#define EC_CMD_THERMAL_SET_THRESHOLD 0x0050 +#define EC_CMD_THERMAL_GET_THRESHOLD 0x0051 + +/* The version 0 structs are opaque. You have to know what they are for + * the get/set commands to make any sense. + */ + +/* Version 0 - set */ +struct ec_params_thermal_set_threshold { + uint8_t sensor_type; + uint8_t threshold_id; + uint16_t value; +} __ec_align2; + +/* Version 0 - get */ +struct ec_params_thermal_get_threshold { + uint8_t sensor_type; + uint8_t threshold_id; +} __ec_align1; + +struct ec_response_thermal_get_threshold { + uint16_t value; +} __ec_align2; + + +/* The version 1 structs are visible. */ +enum ec_temp_thresholds { + EC_TEMP_THRESH_WARN = 0, + EC_TEMP_THRESH_HIGH, + EC_TEMP_THRESH_HALT, + + EC_TEMP_THRESH_COUNT +}; + +/* + * Thermal configuration for one temperature sensor. Temps are in degrees K. + * Zero values will be silently ignored by the thermal task. + * + * Set 'temp_host' value allows thermal task to trigger some event with 1 degree + * hysteresis. + * For example, + * temp_host[EC_TEMP_THRESH_HIGH] = 300 K + * temp_host_release[EC_TEMP_THRESH_HIGH] = 0 K + * EC will throttle ap when temperature >= 301 K, and release throttling when + * temperature <= 299 K. + * + * Set 'temp_host_release' value allows thermal task has a custom hysteresis. + * For example, + * temp_host[EC_TEMP_THRESH_HIGH] = 300 K + * temp_host_release[EC_TEMP_THRESH_HIGH] = 295 K + * EC will throttle ap when temperature >= 301 K, and release throttling when + * temperature <= 294 K. + * + * Note that this structure is a sub-structure of + * ec_params_thermal_set_threshold_v1, but maintains its alignment there. + */ +struct ec_thermal_config { + uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */ + uint32_t temp_host_release[EC_TEMP_THRESH_COUNT]; /* release levels */ + uint32_t temp_fan_off; /* no active cooling needed */ + uint32_t temp_fan_max; /* max active cooling needed */ +} __ec_align4; + +/* Version 1 - get config for one sensor. */ +struct ec_params_thermal_get_threshold_v1 { + uint32_t sensor_num; +} __ec_align4; +/* This returns a struct ec_thermal_config */ + +/* + * Version 1 - set config for one sensor. + * Use read-modify-write for best results! + */ +struct ec_params_thermal_set_threshold_v1 { + uint32_t sensor_num; + struct ec_thermal_config cfg; +} __ec_align4; +/* This returns no data */ + +/****************************************************************************/ + +/* Toggle automatic fan control */ +#define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x0052 + +/* Version 1 of input params */ +struct ec_params_auto_fan_ctrl_v1 { + uint8_t fan_idx; +} __ec_align1; + +/* Get/Set TMP006 calibration data */ +#define EC_CMD_TMP006_GET_CALIBRATION 0x0053 +#define EC_CMD_TMP006_SET_CALIBRATION 0x0054 + +/* + * The original TMP006 calibration only needed four params, but now we need + * more. Since the algorithm is nothing but magic numbers anyway, we'll leave + * the params opaque. The v1 "get" response will include the algorithm number + * and how many params it requires. That way we can change the EC code without + * needing to update this file. We can also use a different algorithm on each + * sensor. + */ + +/* This is the same struct for both v0 and v1. */ +struct ec_params_tmp006_get_calibration { + uint8_t index; +} __ec_align1; + +/* Version 0 */ +struct ec_response_tmp006_get_calibration_v0 { + float s0; + float b0; + float b1; + float b2; +} __ec_align4; + +struct ec_params_tmp006_set_calibration_v0 { + uint8_t index; + uint8_t reserved[3]; + float s0; + float b0; + float b1; + float b2; +} __ec_align4; + +/* Version 1 */ +struct ec_response_tmp006_get_calibration_v1 { + uint8_t algorithm; + uint8_t num_params; + uint8_t reserved[2]; + float val[0]; +} __ec_align4; + +struct ec_params_tmp006_set_calibration_v1 { + uint8_t index; + uint8_t algorithm; + uint8_t num_params; + uint8_t reserved; + float val[0]; +} __ec_align4; + + +/* Read raw TMP006 data */ +#define EC_CMD_TMP006_GET_RAW 0x0055 + +struct ec_params_tmp006_get_raw { + uint8_t index; +} __ec_align1; + +struct ec_response_tmp006_get_raw { + int32_t t; /* In 1/100 K */ + int32_t v; /* In nV */ +} __ec_align4; + +/*****************************************************************************/ +/* MKBP - Matrix KeyBoard Protocol */ + +/* + * Read key state + * + * Returns raw data for keyboard cols; see ec_response_mkbp_info.cols for + * expected response size. + * + * NOTE: This has been superseded by EC_CMD_MKBP_GET_NEXT_EVENT. If you wish + * to obtain the instantaneous state, use EC_CMD_MKBP_INFO with the type + * EC_MKBP_INFO_CURRENT and event EC_MKBP_EVENT_KEY_MATRIX. + */ +#define EC_CMD_MKBP_STATE 0x0060 + +/* + * Provide information about various MKBP things. See enum ec_mkbp_info_type. + */ +#define EC_CMD_MKBP_INFO 0x0061 + +struct ec_response_mkbp_info { + uint32_t rows; + uint32_t cols; + /* Formerly "switches", which was 0. */ + uint8_t reserved; +} __ec_align_size1; + +struct ec_params_mkbp_info { + uint8_t info_type; + uint8_t event_type; +} __ec_align1; + +enum ec_mkbp_info_type { + /* + * Info about the keyboard matrix: number of rows and columns. + * + * Returns struct ec_response_mkbp_info. + */ + EC_MKBP_INFO_KBD = 0, + + /* + * For buttons and switches, info about which specifically are + * supported. event_type must be set to one of the values in enum + * ec_mkbp_event. + * + * For EC_MKBP_EVENT_BUTTON and EC_MKBP_EVENT_SWITCH, returns a 4 byte + * bitmask indicating which buttons or switches are present. See the + * bit inidices below. + */ + EC_MKBP_INFO_SUPPORTED = 1, + + /* + * Instantaneous state of buttons and switches. + * + * event_type must be set to one of the values in enum ec_mkbp_event. + * + * For EC_MKBP_EVENT_KEY_MATRIX, returns uint8_t key_matrix[13] + * indicating the current state of the keyboard matrix. + * + * For EC_MKBP_EVENT_HOST_EVENT, return uint32_t host_event, the raw + * event state. + * + * For EC_MKBP_EVENT_BUTTON, returns uint32_t buttons, indicating the + * state of supported buttons. + * + * For EC_MKBP_EVENT_SWITCH, returns uint32_t switches, indicating the + * state of supported switches. + */ + EC_MKBP_INFO_CURRENT = 2, +}; + +/* Simulate key press */ +#define EC_CMD_MKBP_SIMULATE_KEY 0x0062 + +struct ec_params_mkbp_simulate_key { + uint8_t col; + uint8_t row; + uint8_t pressed; +} __ec_align1; + +#define EC_CMD_GET_KEYBOARD_ID 0x0063 + +struct ec_response_keyboard_id { + uint32_t keyboard_id; +} __ec_align4; + +enum keyboard_id { + KEYBOARD_ID_UNSUPPORTED = 0, + KEYBOARD_ID_UNREADABLE = 0xffffffff, +}; + +/* Configure keyboard scanning */ +#define EC_CMD_MKBP_SET_CONFIG 0x0064 +#define EC_CMD_MKBP_GET_CONFIG 0x0065 + +/* flags */ +enum mkbp_config_flags { + EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ +}; + +enum mkbp_config_valid { + EC_MKBP_VALID_SCAN_PERIOD = BIT(0), + EC_MKBP_VALID_POLL_TIMEOUT = BIT(1), + EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3), + EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4), + EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5), + EC_MKBP_VALID_DEBOUNCE_UP = BIT(6), + EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7), +}; + +/* + * Configuration for our key scanning algorithm. + * + * Note that this is used as a sub-structure of + * ec_{params/response}_mkbp_get_config. + */ +struct ec_mkbp_config { + uint32_t valid_mask; /* valid fields */ + uint8_t flags; /* some flags (enum mkbp_config_flags) */ + uint8_t valid_flags; /* which flags are valid */ + uint16_t scan_period_us; /* period between start of scans */ + /* revert to interrupt mode after no activity for this long */ + uint32_t poll_timeout_us; + /* + * minimum post-scan relax time. Once we finish a scan we check + * the time until we are due to start the next one. If this time is + * shorter this field, we use this instead. + */ + uint16_t min_post_scan_delay_us; + /* delay between setting up output and waiting for it to settle */ + uint16_t output_settle_us; + uint16_t debounce_down_us; /* time for debounce on key down */ + uint16_t debounce_up_us; /* time for debounce on key up */ + /* maximum depth to allow for fifo (0 = no keyscan output) */ + uint8_t fifo_max_depth; +} __ec_align_size1; + +struct ec_params_mkbp_set_config { + struct ec_mkbp_config config; +} __ec_align_size1; + +struct ec_response_mkbp_get_config { + struct ec_mkbp_config config; +} __ec_align_size1; + +/* Run the key scan emulation */ +#define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066 + +enum ec_keyscan_seq_cmd { + EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */ + EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */ + EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */ + EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */ + EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */ +}; + +enum ec_collect_flags { + /* + * Indicates this scan was processed by the EC. Due to timing, some + * scans may be skipped. + */ + EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0), +}; + +struct ec_collect_item { + uint8_t flags; /* some flags (enum ec_collect_flags) */ +} __ec_align1; + +struct ec_params_keyscan_seq_ctrl { + uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */ + union { + struct __ec_align1 { + uint8_t active; /* still active */ + uint8_t num_items; /* number of items */ + /* Current item being presented */ + uint8_t cur_item; + } status; + struct __ec_todo_unpacked { + /* + * Absolute time for this scan, measured from the + * start of the sequence. + */ + uint32_t time_us; + uint8_t scan[0]; /* keyscan data */ + } add; + struct __ec_align1 { + uint8_t start_item; /* First item to return */ + uint8_t num_items; /* Number of items to return */ + } collect; + }; +} __ec_todo_packed; + +struct ec_result_keyscan_seq_ctrl { + union { + struct __ec_todo_unpacked { + uint8_t num_items; /* Number of items */ + /* Data for each item */ + struct ec_collect_item item[0]; + } collect; + }; +} __ec_todo_packed; + +/* + * Get the next pending MKBP event. + * + * Returns EC_RES_UNAVAILABLE if there is no event pending. + */ +#define EC_CMD_GET_NEXT_EVENT 0x0067 + +#define EC_MKBP_HAS_MORE_EVENTS_SHIFT 7 + +/* + * We use the most significant bit of the event type to indicate to the host + * that the EC has more MKBP events available to provide. + */ +#define EC_MKBP_HAS_MORE_EVENTS BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) + +/* The mask to apply to get the raw event type */ +#define EC_MKBP_EVENT_TYPE_MASK (BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) - 1) + +enum ec_mkbp_event { + /* Keyboard matrix changed. The event data is the new matrix state. */ + EC_MKBP_EVENT_KEY_MATRIX = 0, + + /* New host event. The event data is 4 bytes of host event flags. */ + EC_MKBP_EVENT_HOST_EVENT = 1, + + /* New Sensor FIFO data. The event data is fifo_info structure. */ + EC_MKBP_EVENT_SENSOR_FIFO = 2, + + /* The state of the non-matrixed buttons have changed. */ + EC_MKBP_EVENT_BUTTON = 3, + + /* The state of the switches have changed. */ + EC_MKBP_EVENT_SWITCH = 4, + + /* New Fingerprint sensor event, the event data is fp_events bitmap. */ + EC_MKBP_EVENT_FINGERPRINT = 5, + + /* + * Sysrq event: send emulated sysrq. The event data is sysrq, + * corresponding to the key to be pressed. + */ + EC_MKBP_EVENT_SYSRQ = 6, + + /* + * New 64-bit host event. + * The event data is 8 bytes of host event flags. + */ + EC_MKBP_EVENT_HOST_EVENT64 = 7, + + /* Notify the AP that something happened on CEC */ + EC_MKBP_EVENT_CEC_EVENT = 8, + + /* Send an incoming CEC message to the AP */ + EC_MKBP_EVENT_CEC_MESSAGE = 9, + + /* Number of MKBP events */ + EC_MKBP_EVENT_COUNT, +}; +BUILD_ASSERT(EC_MKBP_EVENT_COUNT <= EC_MKBP_EVENT_TYPE_MASK); + +union __ec_align_offset1 ec_response_get_next_data { + uint8_t key_matrix[13]; + + /* Unaligned */ + uint32_t host_event; + uint64_t host_event64; + + struct __ec_todo_unpacked { + /* For aligning the fifo_info */ + uint8_t reserved[3]; + struct ec_response_motion_sense_fifo_info info; + } sensor_fifo; + + uint32_t buttons; + + uint32_t switches; + + uint32_t fp_events; + + uint32_t sysrq; + + /* CEC events from enum mkbp_cec_event */ + uint32_t cec_events; +}; + +union __ec_align_offset1 ec_response_get_next_data_v1 { + uint8_t key_matrix[16]; + + /* Unaligned */ + uint32_t host_event; + uint64_t host_event64; + + struct __ec_todo_unpacked { + /* For aligning the fifo_info */ + uint8_t reserved[3]; + struct ec_response_motion_sense_fifo_info info; + } sensor_fifo; + + uint32_t buttons; + + uint32_t switches; + + uint32_t fp_events; + + uint32_t sysrq; + + /* CEC events from enum mkbp_cec_event */ + uint32_t cec_events; + + uint8_t cec_message[16]; +}; +BUILD_ASSERT(sizeof(union ec_response_get_next_data_v1) == 16); + +struct ec_response_get_next_event { + uint8_t event_type; + /* Followed by event data if any */ + union ec_response_get_next_data data; +} __ec_align1; + +struct ec_response_get_next_event_v1 { + uint8_t event_type; + /* Followed by event data if any */ + union ec_response_get_next_data_v1 data; +} __ec_align1; + +/* Bit indices for buttons and switches.*/ +/* Buttons */ +#define EC_MKBP_POWER_BUTTON 0 +#define EC_MKBP_VOL_UP 1 +#define EC_MKBP_VOL_DOWN 2 +#define EC_MKBP_RECOVERY 3 + +/* Switches */ +#define EC_MKBP_LID_OPEN 0 +#define EC_MKBP_TABLET_MODE 1 +#define EC_MKBP_BASE_ATTACHED 2 + +/* Run keyboard factory test scanning */ +#define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068 + +struct ec_response_keyboard_factory_test { + uint16_t shorted; /* Keyboard pins are shorted */ +} __ec_align2; + +/* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */ +#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF) +#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events) & 0x0000000F) +#define EC_MKBP_FP_ENROLL_PROGRESS_OFFSET 4 +#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) (((fpe) & 0x00000FF0) \ + >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET) +#define EC_MKBP_FP_MATCH_IDX_OFFSET 12 +#define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000 +#define EC_MKBP_FP_MATCH_IDX(fpe) (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) \ + >> EC_MKBP_FP_MATCH_IDX_OFFSET) +#define EC_MKBP_FP_ENROLL BIT(27) +#define EC_MKBP_FP_MATCH BIT(28) +#define EC_MKBP_FP_FINGER_DOWN BIT(29) +#define EC_MKBP_FP_FINGER_UP BIT(30) +#define EC_MKBP_FP_IMAGE_READY BIT(31) +/* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_ENROLL is set */ +#define EC_MKBP_FP_ERR_ENROLL_OK 0 +#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1 +#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2 +#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3 +#define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5 +/* Can be used to detect if image was usable for enrollment or not. */ +#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1 +/* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_MATCH is set */ +#define EC_MKBP_FP_ERR_MATCH_NO 0 +#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6 +#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7 +#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2 +#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4 +#define EC_MKBP_FP_ERR_MATCH_YES 1 +#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3 +#define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5 + + +/*****************************************************************************/ +/* Temperature sensor commands */ + +/* Read temperature sensor info */ +#define EC_CMD_TEMP_SENSOR_GET_INFO 0x0070 + +struct ec_params_temp_sensor_get_info { + uint8_t id; +} __ec_align1; + +struct ec_response_temp_sensor_get_info { + char sensor_name[32]; + uint8_t sensor_type; +} __ec_align1; + +/*****************************************************************************/ + +/* + * Note: host commands 0x80 - 0x87 are reserved to avoid conflict with ACPI + * commands accidentally sent to the wrong interface. See the ACPI section + * below. + */ + +/*****************************************************************************/ +/* Host event commands */ + + +/* Obsolete. New implementation should use EC_CMD_HOST_EVENT instead */ +/* + * Host event mask params and response structures, shared by all of the host + * event commands below. + */ +struct ec_params_host_event_mask { + uint32_t mask; +} __ec_align4; + +struct ec_response_host_event_mask { + uint32_t mask; +} __ec_align4; + +/* These all use ec_response_host_event_mask */ +#define EC_CMD_HOST_EVENT_GET_B 0x0087 +#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088 +#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089 +#define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x008D + +/* These all use ec_params_host_event_mask */ +#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A +#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B +#define EC_CMD_HOST_EVENT_CLEAR 0x008C +#define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x008E +#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F + +/* + * Unified host event programming interface - Should be used by newer versions + * of BIOS/OS to program host events and masks + */ + +struct ec_params_host_event { + + /* Action requested by host - one of enum ec_host_event_action. */ + uint8_t action; + + /* + * Mask type that the host requested the action on - one of + * enum ec_host_event_mask_type. + */ + uint8_t mask_type; + + /* Set to 0, ignore on read */ + uint16_t reserved; + + /* Value to be used in case of set operations. */ + uint64_t value; +} __ec_align4; + +/* + * Response structure returned by EC_CMD_HOST_EVENT. + * Update the value on a GET request. Set to 0 on GET/CLEAR + */ + +struct ec_response_host_event { + + /* Mask value in case of get operation */ + uint64_t value; +} __ec_align4; + +enum ec_host_event_action { + /* + * params.value is ignored. Value of mask_type populated + * in response.value + */ + EC_HOST_EVENT_GET, + + /* Bits in params.value are set */ + EC_HOST_EVENT_SET, + + /* Bits in params.value are cleared */ + EC_HOST_EVENT_CLEAR, +}; + +enum ec_host_event_mask_type { + + /* Main host event copy */ + EC_HOST_EVENT_MAIN, + + /* Copy B of host events */ + EC_HOST_EVENT_B, + + /* SCI Mask */ + EC_HOST_EVENT_SCI_MASK, + + /* SMI Mask */ + EC_HOST_EVENT_SMI_MASK, + + /* Mask of events that should be always reported in hostevents */ + EC_HOST_EVENT_ALWAYS_REPORT_MASK, + + /* Active wake mask */ + EC_HOST_EVENT_ACTIVE_WAKE_MASK, + + /* Lazy wake mask for S0ix */ + EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX, + + /* Lazy wake mask for S3 */ + EC_HOST_EVENT_LAZY_WAKE_MASK_S3, + + /* Lazy wake mask for S5 */ + EC_HOST_EVENT_LAZY_WAKE_MASK_S5, +}; + +#define EC_CMD_HOST_EVENT 0x00A4 + +/*****************************************************************************/ +/* Switch commands */ + +/* Enable/disable LCD backlight */ +#define EC_CMD_SWITCH_ENABLE_BKLIGHT 0x0090 + +struct ec_params_switch_enable_backlight { + uint8_t enabled; +} __ec_align1; + +/* Enable/disable WLAN/Bluetooth */ +#define EC_CMD_SWITCH_ENABLE_WIRELESS 0x0091 +#define EC_VER_SWITCH_ENABLE_WIRELESS 1 + +/* Version 0 params; no response */ +struct ec_params_switch_enable_wireless_v0 { + uint8_t enabled; +} __ec_align1; + +/* Version 1 params */ +struct ec_params_switch_enable_wireless_v1 { + /* Flags to enable now */ + uint8_t now_flags; + + /* Which flags to copy from now_flags */ + uint8_t now_mask; + + /* + * Flags to leave enabled in S3, if they're on at the S0->S3 + * transition. (Other flags will be disabled by the S0->S3 + * transition.) + */ + uint8_t suspend_flags; + + /* Which flags to copy from suspend_flags */ + uint8_t suspend_mask; +} __ec_align1; + +/* Version 1 response */ +struct ec_response_switch_enable_wireless_v1 { + /* Flags to enable now */ + uint8_t now_flags; + + /* Flags to leave enabled in S3 */ + uint8_t suspend_flags; +} __ec_align1; + +/*****************************************************************************/ +/* GPIO commands. Only available on EC if write protect has been disabled. */ + +/* Set GPIO output value */ +#define EC_CMD_GPIO_SET 0x0092 + +struct ec_params_gpio_set { + char name[32]; + uint8_t val; +} __ec_align1; + +/* Get GPIO value */ +#define EC_CMD_GPIO_GET 0x0093 + +/* Version 0 of input params and response */ +struct ec_params_gpio_get { + char name[32]; +} __ec_align1; + +struct ec_response_gpio_get { + uint8_t val; +} __ec_align1; + +/* Version 1 of input params and response */ +struct ec_params_gpio_get_v1 { + uint8_t subcmd; + union { + struct __ec_align1 { + char name[32]; + } get_value_by_name; + struct __ec_align1 { + uint8_t index; + } get_info; + }; +} __ec_align1; + +struct ec_response_gpio_get_v1 { + union { + struct __ec_align1 { + uint8_t val; + } get_value_by_name, get_count; + struct __ec_todo_unpacked { + uint8_t val; + char name[32]; + uint32_t flags; + } get_info; + }; +} __ec_todo_packed; + +enum gpio_get_subcmd { + EC_GPIO_GET_BY_NAME = 0, + EC_GPIO_GET_COUNT = 1, + EC_GPIO_GET_INFO = 2, +}; + +/*****************************************************************************/ +/* I2C commands. Only available when flash write protect is unlocked. */ + +/* + * CAUTION: These commands are deprecated, and are not supported anymore in EC + * builds >= 8398.0.0 (see crosbug.com/p/23570). + * + * Use EC_CMD_I2C_PASSTHRU instead. + */ + +/* Read I2C bus */ +#define EC_CMD_I2C_READ 0x0094 + +struct ec_params_i2c_read { + uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ + uint8_t read_size; /* Either 8 or 16. */ + uint8_t port; + uint8_t offset; +} __ec_align_size1; + +struct ec_response_i2c_read { + uint16_t data; +} __ec_align2; + +/* Write I2C bus */ +#define EC_CMD_I2C_WRITE 0x0095 + +struct ec_params_i2c_write { + uint16_t data; + uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ + uint8_t write_size; /* Either 8 or 16. */ + uint8_t port; + uint8_t offset; +} __ec_align_size1; + +/*****************************************************************************/ +/* Charge state commands. Only available when flash write protect unlocked. */ + +/* Force charge state machine to stop charging the battery or force it to + * discharge the battery. + */ +#define EC_CMD_CHARGE_CONTROL 0x0096 +#define EC_VER_CHARGE_CONTROL 1 + +enum ec_charge_control_mode { + CHARGE_CONTROL_NORMAL = 0, + CHARGE_CONTROL_IDLE, + CHARGE_CONTROL_DISCHARGE, +}; + +struct ec_params_charge_control { + uint32_t mode; /* enum charge_control_mode */ +} __ec_align4; + +/*****************************************************************************/ + +/* Snapshot console output buffer for use by EC_CMD_CONSOLE_READ. */ +#define EC_CMD_CONSOLE_SNAPSHOT 0x0097 + +/* + * Read data from the saved snapshot. If the subcmd parameter is + * CONSOLE_READ_NEXT, this will return data starting from the beginning of + * the latest snapshot. If it is CONSOLE_READ_RECENT, it will start from the + * end of the previous snapshot. + * + * The params are only looked at in version >= 1 of this command. Prior + * versions will just default to CONSOLE_READ_NEXT behavior. + * + * Response is null-terminated string. Empty string, if there is no more + * remaining output. + */ +#define EC_CMD_CONSOLE_READ 0x0098 + +enum ec_console_read_subcmd { + CONSOLE_READ_NEXT = 0, + CONSOLE_READ_RECENT +}; + +struct ec_params_console_read_v1 { + uint8_t subcmd; /* enum ec_console_read_subcmd */ +} __ec_align1; + +/*****************************************************************************/ + +/* + * Cut off battery power immediately or after the host has shut down. + * + * return EC_RES_INVALID_COMMAND if unsupported by a board/battery. + * EC_RES_SUCCESS if the command was successful. + * EC_RES_ERROR if the cut off command failed. + */ +#define EC_CMD_BATTERY_CUT_OFF 0x0099 + +#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0) + +struct ec_params_battery_cutoff { + uint8_t flags; +} __ec_align1; + +/*****************************************************************************/ +/* USB port mux control. */ + +/* + * Switch USB mux or return to automatic switching. + */ +#define EC_CMD_USB_MUX 0x009A + +struct ec_params_usb_mux { + uint8_t mux; +} __ec_align1; + +/*****************************************************************************/ +/* LDOs / FETs control. */ + +enum ec_ldo_state { + EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */ + EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */ +}; + +/* + * Switch on/off a LDO. + */ +#define EC_CMD_LDO_SET 0x009B + +struct ec_params_ldo_set { + uint8_t index; + uint8_t state; +} __ec_align1; + +/* + * Get LDO state. + */ +#define EC_CMD_LDO_GET 0x009C + +struct ec_params_ldo_get { + uint8_t index; +} __ec_align1; + +struct ec_response_ldo_get { + uint8_t state; +} __ec_align1; + +/*****************************************************************************/ +/* Power info. */ + +/* + * Get power info. + */ +#define EC_CMD_POWER_INFO 0x009D + +struct ec_response_power_info { + uint32_t usb_dev_type; + uint16_t voltage_ac; + uint16_t voltage_system; + uint16_t current_system; + uint16_t usb_current_limit; +} __ec_align4; + +/*****************************************************************************/ +/* I2C passthru command */ + +#define EC_CMD_I2C_PASSTHRU 0x009E + +/* Read data; if not present, message is a write */ +#define EC_I2C_FLAG_READ BIT(15) + +/* Mask for address */ +#define EC_I2C_ADDR_MASK 0x3ff + +#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */ +#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */ + +/* Any error */ +#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) + +struct ec_params_i2c_passthru_msg { + uint16_t addr_flags; /* I2C slave address (7 or 10 bits) and flags */ + uint16_t len; /* Number of bytes to read or write */ +} __ec_align2; + +struct ec_params_i2c_passthru { + uint8_t port; /* I2C port number */ + uint8_t num_msgs; /* Number of messages */ + struct ec_params_i2c_passthru_msg msg[]; + /* Data to write for all messages is concatenated here */ +} __ec_align2; + +struct ec_response_i2c_passthru { + uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ + uint8_t num_msgs; /* Number of messages processed */ + uint8_t data[]; /* Data read by messages concatenated here */ +} __ec_align1; + +/*****************************************************************************/ +/* Power button hang detect */ + +#define EC_CMD_HANG_DETECT 0x009F + +/* Reasons to start hang detection timer */ +/* Power button pressed */ +#define EC_HANG_START_ON_POWER_PRESS BIT(0) + +/* Lid closed */ +#define EC_HANG_START_ON_LID_CLOSE BIT(1) + + /* Lid opened */ +#define EC_HANG_START_ON_LID_OPEN BIT(2) + +/* Start of AP S3->S0 transition (booting or resuming from suspend) */ +#define EC_HANG_START_ON_RESUME BIT(3) + +/* Reasons to cancel hang detection */ + +/* Power button released */ +#define EC_HANG_STOP_ON_POWER_RELEASE BIT(8) + +/* Any host command from AP received */ +#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9) + +/* Stop on end of AP S0->S3 transition (suspending or shutting down) */ +#define EC_HANG_STOP_ON_SUSPEND BIT(10) + +/* + * If this flag is set, all the other fields are ignored, and the hang detect + * timer is started. This provides the AP a way to start the hang timer + * without reconfiguring any of the other hang detect settings. Note that + * you must previously have configured the timeouts. + */ +#define EC_HANG_START_NOW BIT(30) + +/* + * If this flag is set, all the other fields are ignored (including + * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer + * without reconfiguring any of the other hang detect settings. + */ +#define EC_HANG_STOP_NOW BIT(31) + +struct ec_params_hang_detect { + /* Flags; see EC_HANG_* */ + uint32_t flags; + + /* Timeout in msec before generating host event, if enabled */ + uint16_t host_event_timeout_msec; + + /* Timeout in msec before generating warm reboot, if enabled */ + uint16_t warm_reboot_timeout_msec; +} __ec_align4; + +/*****************************************************************************/ +/* Commands for battery charging */ + +/* + * This is the single catch-all host command to exchange data regarding the + * charge state machine (v2 and up). + */ +#define EC_CMD_CHARGE_STATE 0x00A0 + +/* Subcommands for this host command */ +enum charge_state_command { + CHARGE_STATE_CMD_GET_STATE, + CHARGE_STATE_CMD_GET_PARAM, + CHARGE_STATE_CMD_SET_PARAM, + CHARGE_STATE_NUM_CMDS +}; + +/* + * Known param numbers are defined here. Ranges are reserved for board-specific + * params, which are handled by the particular implementations. + */ +enum charge_state_params { + CS_PARAM_CHG_VOLTAGE, /* charger voltage limit */ + CS_PARAM_CHG_CURRENT, /* charger current limit */ + CS_PARAM_CHG_INPUT_CURRENT, /* charger input current limit */ + CS_PARAM_CHG_STATUS, /* charger-specific status */ + CS_PARAM_CHG_OPTION, /* charger-specific options */ + CS_PARAM_LIMIT_POWER, /* + * Check if power is limited due to + * low battery and / or a weak external + * charger. READ ONLY. + */ + /* How many so far? */ + CS_NUM_BASE_PARAMS, + + /* Range for CONFIG_CHARGER_PROFILE_OVERRIDE params */ + CS_PARAM_CUSTOM_PROFILE_MIN = 0x10000, + CS_PARAM_CUSTOM_PROFILE_MAX = 0x1ffff, + + /* Range for CONFIG_CHARGE_STATE_DEBUG params */ + CS_PARAM_DEBUG_MIN = 0x20000, + CS_PARAM_DEBUG_CTL_MODE = 0x20000, + CS_PARAM_DEBUG_MANUAL_MODE, + CS_PARAM_DEBUG_SEEMS_DEAD, + CS_PARAM_DEBUG_SEEMS_DISCONNECTED, + CS_PARAM_DEBUG_BATT_REMOVED, + CS_PARAM_DEBUG_MANUAL_CURRENT, + CS_PARAM_DEBUG_MANUAL_VOLTAGE, + CS_PARAM_DEBUG_MAX = 0x2ffff, + + /* Other custom param ranges go here... */ +}; + +struct ec_params_charge_state { + uint8_t cmd; /* enum charge_state_command */ + union { + /* get_state has no args */ + + struct __ec_todo_unpacked { + uint32_t param; /* enum charge_state_param */ + } get_param; + + struct __ec_todo_unpacked { + uint32_t param; /* param to set */ + uint32_t value; /* value to set */ + } set_param; + }; +} __ec_todo_packed; + +struct ec_response_charge_state { + union { + struct __ec_align4 { + int ac; + int chg_voltage; + int chg_current; + int chg_input_current; + int batt_state_of_charge; + } get_state; + + struct __ec_align4 { + uint32_t value; + } get_param; + + /* set_param returns no args */ + }; +} __ec_align4; + + +/* + * Set maximum battery charging current. + */ +#define EC_CMD_CHARGE_CURRENT_LIMIT 0x00A1 + +struct ec_params_current_limit { + uint32_t limit; /* in mA */ +} __ec_align4; + +/* + * Set maximum external voltage / current. + */ +#define EC_CMD_EXTERNAL_POWER_LIMIT 0x00A2 + +/* Command v0 is used only on Spring and is obsolete + unsupported */ +struct ec_params_external_power_limit_v1 { + uint16_t current_lim; /* in mA, or EC_POWER_LIMIT_NONE to clear limit */ + uint16_t voltage_lim; /* in mV, or EC_POWER_LIMIT_NONE to clear limit */ +} __ec_align2; + +#define EC_POWER_LIMIT_NONE 0xffff + +/* + * Set maximum voltage & current of a dedicated charge port + */ +#define EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT 0x00A3 + +struct ec_params_dedicated_charger_limit { + uint16_t current_lim; /* in mA */ + uint16_t voltage_lim; /* in mV */ +} __ec_align2; + +/*****************************************************************************/ +/* Hibernate/Deep Sleep Commands */ + +/* Set the delay before going into hibernation. */ +#define EC_CMD_HIBERNATION_DELAY 0x00A8 + +struct ec_params_hibernation_delay { + /* + * Seconds to wait in G3 before hibernate. Pass in 0 to read the + * current settings without changing them. + */ + uint32_t seconds; +} __ec_align4; + +struct ec_response_hibernation_delay { + /* + * The current time in seconds in which the system has been in the G3 + * state. This value is reset if the EC transitions out of G3. + */ + uint32_t time_g3; + + /* + * The current time remaining in seconds until the EC should hibernate. + * This value is also reset if the EC transitions out of G3. + */ + uint32_t time_remaining; + + /* + * The current time in seconds that the EC should wait in G3 before + * hibernating. + */ + uint32_t hibernate_delay; +} __ec_align4; + +/* Inform the EC when entering a sleep state */ +#define EC_CMD_HOST_SLEEP_EVENT 0x00A9 + +enum host_sleep_event { + HOST_SLEEP_EVENT_S3_SUSPEND = 1, + HOST_SLEEP_EVENT_S3_RESUME = 2, + HOST_SLEEP_EVENT_S0IX_SUSPEND = 3, + HOST_SLEEP_EVENT_S0IX_RESUME = 4, + /* S3 suspend with additional enabled wake sources */ + HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5, +}; + +struct ec_params_host_sleep_event { + uint8_t sleep_event; +} __ec_align1; + +/* + * Use a default timeout value (CONFIG_SLEEP_TIMEOUT_MS) for detecting sleep + * transition failures + */ +#define EC_HOST_SLEEP_TIMEOUT_DEFAULT 0 + +/* Disable timeout detection for this sleep transition */ +#define EC_HOST_SLEEP_TIMEOUT_INFINITE 0xFFFF + +struct ec_params_host_sleep_event_v1 { + /* The type of sleep being entered or exited. */ + uint8_t sleep_event; + + /* Padding */ + uint8_t reserved; + union { + /* Parameters that apply for suspend messages. */ + struct { + /* + * The timeout in milliseconds between when this message + * is received and when the EC will declare sleep + * transition failure if the sleep signal is not + * asserted. + */ + uint16_t sleep_timeout_ms; + } suspend_params; + + /* No parameters for non-suspend messages. */ + }; +} __ec_align2; + +/* A timeout occurred when this bit is set */ +#define EC_HOST_RESUME_SLEEP_TIMEOUT 0x80000000 + +/* + * The mask defining which bits correspond to the number of sleep transitions, + * as well as the maximum number of suspend line transitions that will be + * reported back to the host. + */ +#define EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK 0x7FFFFFFF + +struct ec_response_host_sleep_event_v1 { + union { + /* Response fields that apply for resume messages. */ + struct { + /* + * The number of sleep power signal transitions that + * occurred since the suspend message. The high bit + * indicates a timeout occurred. + */ + uint32_t sleep_transitions; + } resume_response; + + /* No response fields for non-resume messages. */ + }; +} __ec_align4; + +/*****************************************************************************/ +/* Device events */ +#define EC_CMD_DEVICE_EVENT 0x00AA + +enum ec_device_event { + EC_DEVICE_EVENT_TRACKPAD, + EC_DEVICE_EVENT_DSP, + EC_DEVICE_EVENT_WIFI, +}; + +enum ec_device_event_param { + /* Get and clear pending device events */ + EC_DEVICE_EVENT_PARAM_GET_CURRENT_EVENTS, + /* Get device event mask */ + EC_DEVICE_EVENT_PARAM_GET_ENABLED_EVENTS, + /* Set device event mask */ + EC_DEVICE_EVENT_PARAM_SET_ENABLED_EVENTS, +}; + +#define EC_DEVICE_EVENT_MASK(event_code) BIT(event_code % 32) + +struct ec_params_device_event { + uint32_t event_mask; + uint8_t param; +} __ec_align_size1; + +struct ec_response_device_event { + uint32_t event_mask; +} __ec_align4; + +/*****************************************************************************/ +/* Smart battery pass-through */ + +/* Get / Set 16-bit smart battery registers */ +#define EC_CMD_SB_READ_WORD 0x00B0 +#define EC_CMD_SB_WRITE_WORD 0x00B1 + +/* Get / Set string smart battery parameters + * formatted as SMBUS "block". + */ +#define EC_CMD_SB_READ_BLOCK 0x00B2 +#define EC_CMD_SB_WRITE_BLOCK 0x00B3 + +struct ec_params_sb_rd { + uint8_t reg; +} __ec_align1; + +struct ec_response_sb_rd_word { + uint16_t value; +} __ec_align2; + +struct ec_params_sb_wr_word { + uint8_t reg; + uint16_t value; +} __ec_align1; + +struct ec_response_sb_rd_block { + uint8_t data[32]; +} __ec_align1; + +struct ec_params_sb_wr_block { + uint8_t reg; + uint16_t data[32]; +} __ec_align1; + +/*****************************************************************************/ +/* Battery vendor parameters + * + * Get or set vendor-specific parameters in the battery. Implementations may + * differ between boards or batteries. On a set operation, the response + * contains the actual value set, which may be rounded or clipped from the + * requested value. + */ + +#define EC_CMD_BATTERY_VENDOR_PARAM 0x00B4 + +enum ec_battery_vendor_param_mode { + BATTERY_VENDOR_PARAM_MODE_GET = 0, + BATTERY_VENDOR_PARAM_MODE_SET, +}; + +struct ec_params_battery_vendor_param { + uint32_t param; + uint32_t value; + uint8_t mode; +} __ec_align_size1; + +struct ec_response_battery_vendor_param { + uint32_t value; +} __ec_align4; + +/*****************************************************************************/ +/* + * Smart Battery Firmware Update Commands + */ +#define EC_CMD_SB_FW_UPDATE 0x00B5 + +enum ec_sb_fw_update_subcmd { + EC_SB_FW_UPDATE_PREPARE = 0x0, + EC_SB_FW_UPDATE_INFO = 0x1, /*query sb info */ + EC_SB_FW_UPDATE_BEGIN = 0x2, /*check if protected */ + EC_SB_FW_UPDATE_WRITE = 0x3, /*check if protected */ + EC_SB_FW_UPDATE_END = 0x4, + EC_SB_FW_UPDATE_STATUS = 0x5, + EC_SB_FW_UPDATE_PROTECT = 0x6, + EC_SB_FW_UPDATE_MAX = 0x7, +}; + +#define SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE 32 +#define SB_FW_UPDATE_CMD_STATUS_SIZE 2 +#define SB_FW_UPDATE_CMD_INFO_SIZE 8 + +struct ec_sb_fw_update_header { + uint16_t subcmd; /* enum ec_sb_fw_update_subcmd */ + uint16_t fw_id; /* firmware id */ +} __ec_align4; + +struct ec_params_sb_fw_update { + struct ec_sb_fw_update_header hdr; + union { + /* EC_SB_FW_UPDATE_PREPARE = 0x0 */ + /* EC_SB_FW_UPDATE_INFO = 0x1 */ + /* EC_SB_FW_UPDATE_BEGIN = 0x2 */ + /* EC_SB_FW_UPDATE_END = 0x4 */ + /* EC_SB_FW_UPDATE_STATUS = 0x5 */ + /* EC_SB_FW_UPDATE_PROTECT = 0x6 */ + /* Those have no args */ + + /* EC_SB_FW_UPDATE_WRITE = 0x3 */ + struct __ec_align4 { + uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE]; + } write; + }; +} __ec_align4; + +struct ec_response_sb_fw_update { + union { + /* EC_SB_FW_UPDATE_INFO = 0x1 */ + struct __ec_align1 { + uint8_t data[SB_FW_UPDATE_CMD_INFO_SIZE]; + } info; + + /* EC_SB_FW_UPDATE_STATUS = 0x5 */ + struct __ec_align1 { + uint8_t data[SB_FW_UPDATE_CMD_STATUS_SIZE]; + } status; + }; +} __ec_align1; + +/* + * Entering Verified Boot Mode Command + * Default mode is VBOOT_MODE_NORMAL if EC did not receive this command. + * Valid Modes are: normal, developer, and recovery. + */ +#define EC_CMD_ENTERING_MODE 0x00B6 + +struct ec_params_entering_mode { + int vboot_mode; +} __ec_align4; + +#define VBOOT_MODE_NORMAL 0 +#define VBOOT_MODE_DEVELOPER 1 +#define VBOOT_MODE_RECOVERY 2 + +/*****************************************************************************/ +/* + * I2C passthru protection command: Protects I2C tunnels against access on + * certain addresses (board-specific). + */ +#define EC_CMD_I2C_PASSTHRU_PROTECT 0x00B7 + +enum ec_i2c_passthru_protect_subcmd { + EC_CMD_I2C_PASSTHRU_PROTECT_STATUS = 0x0, + EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 0x1, +}; + +struct ec_params_i2c_passthru_protect { + uint8_t subcmd; + uint8_t port; /* I2C port number */ +} __ec_align1; + +struct ec_response_i2c_passthru_protect { + uint8_t status; /* Status flags (0: unlocked, 1: locked) */ +} __ec_align1; + + +/*****************************************************************************/ +/* + * HDMI CEC commands + * + * These commands are for sending and receiving message via HDMI CEC + */ + +#define MAX_CEC_MSG_LEN 16 + +/* CEC message from the AP to be written on the CEC bus */ +#define EC_CMD_CEC_WRITE_MSG 0x00B8 + +/** + * struct ec_params_cec_write - Message to write to the CEC bus + * @msg: message content to write to the CEC bus + */ +struct ec_params_cec_write { + uint8_t msg[MAX_CEC_MSG_LEN]; +} __ec_align1; + +/* Set various CEC parameters */ +#define EC_CMD_CEC_SET 0x00BA + +/** + * struct ec_params_cec_set - CEC parameters set + * @cmd: parameter type, can be CEC_CMD_ENABLE or CEC_CMD_LOGICAL_ADDRESS + * @val: in case cmd is CEC_CMD_ENABLE, this field can be 0 to disable CEC + * or 1 to enable CEC functionality, in case cmd is + * CEC_CMD_LOGICAL_ADDRESS, this field encodes the requested logical + * address between 0 and 15 or 0xff to unregister + */ +struct ec_params_cec_set { + uint8_t cmd; /* enum cec_command */ + uint8_t val; +} __ec_align1; + +/* Read various CEC parameters */ +#define EC_CMD_CEC_GET 0x00BB + +/** + * struct ec_params_cec_get - CEC parameters get + * @cmd: parameter type, can be CEC_CMD_ENABLE or CEC_CMD_LOGICAL_ADDRESS + */ +struct ec_params_cec_get { + uint8_t cmd; /* enum cec_command */ +} __ec_align1; + +/** + * struct ec_response_cec_get - CEC parameters get response + * @val: in case cmd was CEC_CMD_ENABLE, this field will 0 if CEC is + * disabled or 1 if CEC functionality is enabled, + * in case cmd was CEC_CMD_LOGICAL_ADDRESS, this will encode the + * configured logical address between 0 and 15 or 0xff if unregistered + */ +struct ec_response_cec_get { + uint8_t val; +} __ec_align1; + +/* CEC parameters command */ +enum cec_command { + /* CEC reading, writing and events enable */ + CEC_CMD_ENABLE, + /* CEC logical address */ + CEC_CMD_LOGICAL_ADDRESS, +}; + +/* Events from CEC to AP */ +enum mkbp_cec_event { + /* Outgoing message was acknowledged by a follower */ + EC_MKBP_CEC_SEND_OK = BIT(0), + /* Outgoing message was not acknowledged */ + EC_MKBP_CEC_SEND_FAILED = BIT(1), +}; + +/*****************************************************************************/ + +/* Commands for I2S recording on audio codec. */ + +#define EC_CMD_CODEC_I2S 0x00BC +#define EC_WOV_I2S_SAMPLE_RATE 48000 + +enum ec_codec_i2s_subcmd { + EC_CODEC_SET_SAMPLE_DEPTH = 0x0, + EC_CODEC_SET_GAIN = 0x1, + EC_CODEC_GET_GAIN = 0x2, + EC_CODEC_I2S_ENABLE = 0x3, + EC_CODEC_I2S_SET_CONFIG = 0x4, + EC_CODEC_I2S_SET_TDM_CONFIG = 0x5, + EC_CODEC_I2S_SET_BCLK = 0x6, + EC_CODEC_I2S_SUBCMD_COUNT = 0x7, +}; + +enum ec_sample_depth_value { + EC_CODEC_SAMPLE_DEPTH_16 = 0, + EC_CODEC_SAMPLE_DEPTH_24 = 1, +}; + +enum ec_i2s_config { + EC_DAI_FMT_I2S = 0, + EC_DAI_FMT_RIGHT_J = 1, + EC_DAI_FMT_LEFT_J = 2, + EC_DAI_FMT_PCM_A = 3, + EC_DAI_FMT_PCM_B = 4, + EC_DAI_FMT_PCM_TDM = 5, +}; + +/* + * For subcommand EC_CODEC_GET_GAIN. + */ +struct __ec_align1 ec_codec_i2s_gain { + uint8_t left; + uint8_t right; +}; + +struct __ec_todo_unpacked ec_param_codec_i2s_tdm { + int16_t ch0_delay; /* 0 to 496 */ + int16_t ch1_delay; /* -1 to 496 */ + uint8_t adjacent_to_ch0; + uint8_t adjacent_to_ch1; +}; + +struct __ec_todo_packed ec_param_codec_i2s { + /* enum ec_codec_i2s_subcmd */ + uint8_t cmd; + union { + /* + * EC_CODEC_SET_SAMPLE_DEPTH + * Value should be one of ec_sample_depth_value. + */ + uint8_t depth; + + /* + * EC_CODEC_SET_GAIN + * Value should be 0~43 for both channels. + */ + struct ec_codec_i2s_gain gain; + + /* + * EC_CODEC_I2S_ENABLE + * 1 to enable, 0 to disable. + */ + uint8_t i2s_enable; + + /* + * EC_CODEC_I2S_SET_CONFIG + * Value should be one of ec_i2s_config. + */ + uint8_t i2s_config; + + /* + * EC_CODEC_I2S_SET_TDM_CONFIG + * Value should be one of ec_i2s_config. + */ + struct ec_param_codec_i2s_tdm tdm_param; + + /* + * EC_CODEC_I2S_SET_BCLK + */ + uint32_t bclk; + }; +}; + + +/*****************************************************************************/ +/* System commands */ + +/* + * TODO(crosbug.com/p/23747): This is a confusing name, since it doesn't + * necessarily reboot the EC. Rename to "image" or something similar? + */ +#define EC_CMD_REBOOT_EC 0x00D2 + +/* Command */ +enum ec_reboot_cmd { + EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */ + EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */ + EC_REBOOT_JUMP_RW = 2, /* Jump to active RW without rebooting */ + /* (command 3 was jump to RW-B) */ + EC_REBOOT_COLD = 4, /* Cold-reboot */ + EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ + EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ + EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_OFF flag */ +}; + +/* Flags for ec_params_reboot_ec.reboot_flags */ +#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */ +#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */ +#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */ + +struct ec_params_reboot_ec { + uint8_t cmd; /* enum ec_reboot_cmd */ + uint8_t flags; /* See EC_REBOOT_FLAG_* */ +} __ec_align1; + +/* + * Get information on last EC panic. + * + * Returns variable-length platform-dependent panic information. See panic.h + * for details. + */ +#define EC_CMD_GET_PANIC_INFO 0x00D3 + +/*****************************************************************************/ +/* + * Special commands + * + * These do not follow the normal rules for commands. See each command for + * details. + */ + +/* + * Reboot NOW + * + * This command will work even when the EC LPC interface is busy, because the + * reboot command is processed at interrupt level. Note that when the EC + * reboots, the host will reboot too, so there is no response to this command. + * + * Use EC_CMD_REBOOT_EC to reboot the EC more politely. + */ +#define EC_CMD_REBOOT 0x00D1 /* Think "die" */ + +/* + * Resend last response (not supported on LPC). + * + * Returns EC_RES_UNAVAILABLE if there is no response available - for example, + * there was no previous command, or the previous command's response was too + * big to save. + */ +#define EC_CMD_RESEND_RESPONSE 0x00DB + +/* + * This header byte on a command indicate version 0. Any header byte less + * than this means that we are talking to an old EC which doesn't support + * versioning. In that case, we assume version 0. + * + * Header bytes greater than this indicate a later version. For example, + * EC_CMD_VERSION0 + 1 means we are using version 1. + * + * The old EC interface must not use commands 0xdc or higher. + */ +#define EC_CMD_VERSION0 0x00DC + +/*****************************************************************************/ +/* + * PD commands + * + * These commands are for PD MCU communication. + */ + +/* EC to PD MCU exchange status command */ +#define EC_CMD_PD_EXCHANGE_STATUS 0x0100 +#define EC_VER_PD_EXCHANGE_STATUS 2 + +enum pd_charge_state { + PD_CHARGE_NO_CHANGE = 0, /* Don't change charge state */ + PD_CHARGE_NONE, /* No charging allowed */ + PD_CHARGE_5V, /* 5V charging only */ + PD_CHARGE_MAX /* Charge at max voltage */ +}; + +/* Status of EC being sent to PD */ +#define EC_STATUS_HIBERNATING BIT(0) + +struct ec_params_pd_status { + uint8_t status; /* EC status */ + int8_t batt_soc; /* battery state of charge */ + uint8_t charge_state; /* charging state (from enum pd_charge_state) */ +} __ec_align1; + +/* Status of PD being sent back to EC */ +#define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */ +#define PD_STATUS_IN_RW BIT(1) /* Running RW image */ +#define PD_STATUS_JUMPED_TO_IMAGE BIT(2) /* Current image was jumped to */ +#define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */ +#define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */ +#define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */ +#define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */ +#define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \ + PD_STATUS_TCPC_ALERT_1 | \ + PD_STATUS_HOST_EVENT) +struct ec_response_pd_status { + uint32_t curr_lim_ma; /* input current limit */ + uint16_t status; /* PD MCU status */ + int8_t active_charge_port; /* active charging port */ +} __ec_align_size1; + +/* AP to PD MCU host event status command, cleared on read */ +#define EC_CMD_PD_HOST_EVENT_STATUS 0x0104 + +/* PD MCU host event status bits */ +#define PD_EVENT_UPDATE_DEVICE BIT(0) +#define PD_EVENT_POWER_CHANGE BIT(1) +#define PD_EVENT_IDENTITY_RECEIVED BIT(2) +#define PD_EVENT_DATA_SWAP BIT(3) +struct ec_response_host_event_status { + uint32_t status; /* PD MCU host event status */ +} __ec_align4; + +/* Set USB type-C port role and muxes */ +#define EC_CMD_USB_PD_CONTROL 0x0101 + +enum usb_pd_control_role { + USB_PD_CTRL_ROLE_NO_CHANGE = 0, + USB_PD_CTRL_ROLE_TOGGLE_ON = 1, /* == AUTO */ + USB_PD_CTRL_ROLE_TOGGLE_OFF = 2, + USB_PD_CTRL_ROLE_FORCE_SINK = 3, + USB_PD_CTRL_ROLE_FORCE_SOURCE = 4, + USB_PD_CTRL_ROLE_FREEZE = 5, + USB_PD_CTRL_ROLE_COUNT +}; + +enum usb_pd_control_mux { + USB_PD_CTRL_MUX_NO_CHANGE = 0, + USB_PD_CTRL_MUX_NONE = 1, + USB_PD_CTRL_MUX_USB = 2, + USB_PD_CTRL_MUX_DP = 3, + USB_PD_CTRL_MUX_DOCK = 4, + USB_PD_CTRL_MUX_AUTO = 5, + USB_PD_CTRL_MUX_COUNT +}; + +enum usb_pd_control_swap { + USB_PD_CTRL_SWAP_NONE = 0, + USB_PD_CTRL_SWAP_DATA = 1, + USB_PD_CTRL_SWAP_POWER = 2, + USB_PD_CTRL_SWAP_VCONN = 3, + USB_PD_CTRL_SWAP_COUNT +}; + +struct ec_params_usb_pd_control { + uint8_t port; + uint8_t role; + uint8_t mux; + uint8_t swap; +} __ec_align1; + +#define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */ +#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */ +#define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2) /* Partner is PD capable */ + +#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */ +#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */ +#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */ +#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */ +#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */ +#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */ +#define PD_CTRL_RESP_ROLE_EXT_POWERED BIT(6) /* Partner externally powerd */ + +struct ec_response_usb_pd_control { + uint8_t enabled; + uint8_t role; + uint8_t polarity; + uint8_t state; +} __ec_align1; + +struct ec_response_usb_pd_control_v1 { + uint8_t enabled; + uint8_t role; + uint8_t polarity; + char state[32]; +} __ec_align1; + +/* Values representing usbc PD CC state */ +#define USBC_PD_CC_NONE 0 /* No accessory connected */ +#define USBC_PD_CC_NO_UFP 1 /* No UFP accessory connected */ +#define USBC_PD_CC_AUDIO_ACC 2 /* Audio accessory connected */ +#define USBC_PD_CC_DEBUG_ACC 3 /* Debug accessory connected */ +#define USBC_PD_CC_UFP_ATTACHED 4 /* UFP attached to usbc */ +#define USBC_PD_CC_DFP_ATTACHED 5 /* DPF attached to usbc */ + +struct ec_response_usb_pd_control_v2 { + uint8_t enabled; + uint8_t role; + uint8_t polarity; + char state[32]; + uint8_t cc_state; /* USBC_PD_CC_*Encoded cc state */ + uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ + /* CL:1500994 Current cable type */ + uint8_t reserved_cable_type; +} __ec_align1; + +#define EC_CMD_USB_PD_PORTS 0x0102 + +/* Maximum number of PD ports on a device, num_ports will be <= this */ +#define EC_USB_PD_MAX_PORTS 8 + +struct ec_response_usb_pd_ports { + uint8_t num_ports; +} __ec_align1; + +#define EC_CMD_USB_PD_POWER_INFO 0x0103 + +#define PD_POWER_CHARGING_PORT 0xff +struct ec_params_usb_pd_power_info { + uint8_t port; +} __ec_align1; + +enum usb_chg_type { + USB_CHG_TYPE_NONE, + USB_CHG_TYPE_PD, + USB_CHG_TYPE_C, + USB_CHG_TYPE_PROPRIETARY, + USB_CHG_TYPE_BC12_DCP, + USB_CHG_TYPE_BC12_CDP, + USB_CHG_TYPE_BC12_SDP, + USB_CHG_TYPE_OTHER, + USB_CHG_TYPE_VBUS, + USB_CHG_TYPE_UNKNOWN, + USB_CHG_TYPE_DEDICATED, +}; +enum usb_power_roles { + USB_PD_PORT_POWER_DISCONNECTED, + USB_PD_PORT_POWER_SOURCE, + USB_PD_PORT_POWER_SINK, + USB_PD_PORT_POWER_SINK_NOT_CHARGING, +}; + +struct usb_chg_measures { + uint16_t voltage_max; + uint16_t voltage_now; + uint16_t current_max; + uint16_t current_lim; +} __ec_align2; + +struct ec_response_usb_pd_power_info { + uint8_t role; + uint8_t type; + uint8_t dualrole; + uint8_t reserved1; + struct usb_chg_measures meas; + uint32_t max_power; +} __ec_align4; + + +/* + * This command will return the number of USB PD charge port + the number + * of dedicated port present. + * EC_CMD_USB_PD_PORTS does NOT include the dedicated ports + */ +#define EC_CMD_CHARGE_PORT_COUNT 0x0105 +struct ec_response_charge_port_count { + uint8_t port_count; +} __ec_align1; + +/* Write USB-PD device FW */ +#define EC_CMD_USB_PD_FW_UPDATE 0x0110 + +enum usb_pd_fw_update_cmds { + USB_PD_FW_REBOOT, + USB_PD_FW_FLASH_ERASE, + USB_PD_FW_FLASH_WRITE, + USB_PD_FW_ERASE_SIG, +}; + +struct ec_params_usb_pd_fw_update { + uint16_t dev_id; + uint8_t cmd; + uint8_t port; + uint32_t size; /* Size to write in bytes */ + /* Followed by data to write */ +} __ec_align4; + +/* Write USB-PD Accessory RW_HASH table entry */ +#define EC_CMD_USB_PD_RW_HASH_ENTRY 0x0111 +/* RW hash is first 20 bytes of SHA-256 of RW section */ +#define PD_RW_HASH_SIZE 20 +struct ec_params_usb_pd_rw_hash_entry { + uint16_t dev_id; + uint8_t dev_rw_hash[PD_RW_HASH_SIZE]; + uint8_t reserved; /* + * For alignment of current_image + * TODO(rspangler) but it's not aligned! + * Should have been reserved[2]. + */ + uint32_t current_image; /* One of ec_current_image */ +} __ec_align1; + +/* Read USB-PD Accessory info */ +#define EC_CMD_USB_PD_DEV_INFO 0x0112 + +struct ec_params_usb_pd_info_request { + uint8_t port; +} __ec_align1; + +/* Read USB-PD Device discovery info */ +#define EC_CMD_USB_PD_DISCOVERY 0x0113 +struct ec_params_usb_pd_discovery_entry { + uint16_t vid; /* USB-IF VID */ + uint16_t pid; /* USB-IF PID */ + uint8_t ptype; /* product type (hub,periph,cable,ama) */ +} __ec_align_size1; + +/* Override default charge behavior */ +#define EC_CMD_PD_CHARGE_PORT_OVERRIDE 0x0114 + +/* Negative port parameters have special meaning */ +enum usb_pd_override_ports { + OVERRIDE_DONT_CHARGE = -2, + OVERRIDE_OFF = -1, + /* [0, CONFIG_USB_PD_PORT_COUNT): Port# */ +}; + +struct ec_params_charge_port_override { + int16_t override_port; /* Override port# */ +} __ec_align2; + +/* + * Read (and delete) one entry of PD event log. + * TODO(crbug.com/751742): Make this host command more generic to accommodate + * future non-PD logs that use the same internal EC event_log. + */ +#define EC_CMD_PD_GET_LOG_ENTRY 0x0115 + +struct ec_response_pd_log { + uint32_t timestamp; /* relative timestamp in milliseconds */ + uint8_t type; /* event type : see PD_EVENT_xx below */ + uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */ + uint16_t data; /* type-defined data payload */ + uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */ +} __ec_align4; + +/* The timestamp is the microsecond counter shifted to get about a ms. */ +#define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */ + +#define PD_LOG_SIZE_MASK 0x1f +#define PD_LOG_PORT_MASK 0xe0 +#define PD_LOG_PORT_SHIFT 5 +#define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \ + ((size) & PD_LOG_SIZE_MASK)) +#define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT) +#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK) + +/* PD event log : entry types */ +/* PD MCU events */ +#define PD_EVENT_MCU_BASE 0x00 +#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE+0) +#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE+1) +/* Reserved for custom board event */ +#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE+2) +/* PD generic accessory events */ +#define PD_EVENT_ACC_BASE 0x20 +#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE+0) +#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE+1) +/* PD power supply events */ +#define PD_EVENT_PS_BASE 0x40 +#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE+0) +/* PD video dongles events */ +#define PD_EVENT_VIDEO_BASE 0x60 +#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0) +#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE+1) +/* Returned in the "type" field, when there is no entry available */ +#define PD_EVENT_NO_ENTRY 0xff + +/* + * PD_EVENT_MCU_CHARGE event definition : + * the payload is "struct usb_chg_measures" + * the data field contains the port state flags as defined below : + */ +/* Port partner is a dual role device */ +#define CHARGE_FLAGS_DUAL_ROLE BIT(15) +/* Port is the pending override port */ +#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14) +/* Port is the override port */ +#define CHARGE_FLAGS_OVERRIDE BIT(13) +/* Charger type */ +#define CHARGE_FLAGS_TYPE_SHIFT 3 +#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT) +/* Power delivery role */ +#define CHARGE_FLAGS_ROLE_MASK (7 << 0) + +/* + * PD_EVENT_PS_FAULT data field flags definition : + */ +#define PS_FAULT_OCP 1 +#define PS_FAULT_FAST_OCP 2 +#define PS_FAULT_OVP 3 +#define PS_FAULT_DISCH 4 + +/* + * PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info". + */ +struct mcdp_version { + uint8_t major; + uint8_t minor; + uint16_t build; +} __ec_align4; + +struct mcdp_info { + uint8_t family[2]; + uint8_t chipid[2]; + struct mcdp_version irom; + struct mcdp_version fw; +} __ec_align4; + +/* struct mcdp_info field decoding */ +#define MCDP_CHIPID(chipid) ((chipid[0] << 8) | chipid[1]) +#define MCDP_FAMILY(family) ((family[0] << 8) | family[1]) + +/* Get/Set USB-PD Alternate mode info */ +#define EC_CMD_USB_PD_GET_AMODE 0x0116 +struct ec_params_usb_pd_get_mode_request { + uint16_t svid_idx; /* SVID index to get */ + uint8_t port; /* port */ +} __ec_align_size1; + +struct ec_params_usb_pd_get_mode_response { + uint16_t svid; /* SVID */ + uint16_t opos; /* Object Position */ + uint32_t vdo[6]; /* Mode VDOs */ +} __ec_align4; + +#define EC_CMD_USB_PD_SET_AMODE 0x0117 + +enum pd_mode_cmd { + PD_EXIT_MODE = 0, + PD_ENTER_MODE = 1, + /* Not a command. Do NOT remove. */ + PD_MODE_CMD_COUNT, +}; + +struct ec_params_usb_pd_set_mode_request { + uint32_t cmd; /* enum pd_mode_cmd */ + uint16_t svid; /* SVID to set */ + uint8_t opos; /* Object Position */ + uint8_t port; /* port */ +} __ec_align4; + +/* Ask the PD MCU to record a log of a requested type */ +#define EC_CMD_PD_WRITE_LOG_ENTRY 0x0118 + +struct ec_params_pd_write_log_entry { + uint8_t type; /* event type : see PD_EVENT_xx above */ + uint8_t port; /* port#, or 0 for events unrelated to a given port */ +} __ec_align1; + + +/* Control USB-PD chip */ +#define EC_CMD_PD_CONTROL 0x0119 + +enum ec_pd_control_cmd { + PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */ + PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */ + PD_RESET, /* Force reset the PD chip */ + PD_CONTROL_DISABLE, /* Disable further calls to this command */ + PD_CHIP_ON, /* Power on the PD chip */ +}; + +struct ec_params_pd_control { + uint8_t chip; /* chip id */ + uint8_t subcmd; +} __ec_align1; + +/* Get info about USB-C SS muxes */ +#define EC_CMD_USB_PD_MUX_INFO 0x011A + +struct ec_params_usb_pd_mux_info { + uint8_t port; /* USB-C port number */ +} __ec_align1; + +/* Flags representing mux state */ +#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ +#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ +#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ +#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ +#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ + +struct ec_response_usb_pd_mux_info { + uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ +} __ec_align1; + +#define EC_CMD_PD_CHIP_INFO 0x011B + +struct ec_params_pd_chip_info { + uint8_t port; /* USB-C port number */ + uint8_t renew; /* Force renewal */ +} __ec_align1; + +struct ec_response_pd_chip_info { + uint16_t vendor_id; + uint16_t product_id; + uint16_t device_id; + union { + uint8_t fw_version_string[8]; + uint64_t fw_version_number; + }; +} __ec_align2; + +struct ec_response_pd_chip_info_v1 { + uint16_t vendor_id; + uint16_t product_id; + uint16_t device_id; + union { + uint8_t fw_version_string[8]; + uint64_t fw_version_number; + }; + union { + uint8_t min_req_fw_version_string[8]; + uint64_t min_req_fw_version_number; + }; +} __ec_align2; + +/* Run RW signature verification and get status */ +#define EC_CMD_RWSIG_CHECK_STATUS 0x011C + +struct ec_response_rwsig_check_status { + uint32_t status; +} __ec_align4; + +/* For controlling RWSIG task */ +#define EC_CMD_RWSIG_ACTION 0x011D + +enum rwsig_action { + RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */ + RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */ +}; + +struct ec_params_rwsig_action { + uint32_t action; +} __ec_align4; + +/* Run verification on a slot */ +#define EC_CMD_EFS_VERIFY 0x011E + +struct ec_params_efs_verify { + uint8_t region; /* enum ec_flash_region */ +} __ec_align1; + +/* + * Retrieve info from Cros Board Info store. Response is based on the data + * type. Integers return a uint32. Strings return a string, using the response + * size to determine how big it is. + */ +#define EC_CMD_GET_CROS_BOARD_INFO 0x011F +/* + * Write info into Cros Board Info on EEPROM. Write fails if the board has + * hardware write-protect enabled. + */ +#define EC_CMD_SET_CROS_BOARD_INFO 0x0120 + +enum cbi_data_tag { + CBI_TAG_BOARD_VERSION = 0, /* uint32_t or smaller */ + CBI_TAG_OEM_ID = 1, /* uint32_t or smaller */ + CBI_TAG_SKU_ID = 2, /* uint32_t or smaller */ + CBI_TAG_DRAM_PART_NUM = 3, /* variable length ascii, nul terminated. */ + CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */ + CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ + CBI_TAG_COUNT, +}; + +/* + * Flags to control read operation + * + * RELOAD: Invalidate cache and read data from EEPROM. Useful to verify + * write was successful without reboot. + */ +#define CBI_GET_RELOAD BIT(0) + +struct ec_params_get_cbi { + uint32_t tag; /* enum cbi_data_tag */ + uint32_t flag; /* CBI_GET_* */ +} __ec_align4; + +/* + * Flags to control write behavior. + * + * NO_SYNC: Makes EC update data in RAM but skip writing to EEPROM. It's + * useful when writing multiple fields in a row. + * INIT: Need to be set when creating a new CBI from scratch. All fields + * will be initialized to zero first. + */ +#define CBI_SET_NO_SYNC BIT(0) +#define CBI_SET_INIT BIT(1) + +struct ec_params_set_cbi { + uint32_t tag; /* enum cbi_data_tag */ + uint32_t flag; /* CBI_SET_* */ + uint32_t size; /* Data size */ + uint8_t data[]; /* For string and raw data */ +} __ec_align1; + +/* + * Information about resets of the AP by the EC and the EC's own uptime. + */ +#define EC_CMD_GET_UPTIME_INFO 0x0121 + +struct ec_response_uptime_info { + /* + * Number of milliseconds since the last EC boot. Sysjump resets + * typically do not restart the EC's time_since_boot epoch. + * + * WARNING: The EC's sense of time is much less accurate than the AP's + * sense of time, in both phase and frequency. This timebase is similar + * to CLOCK_MONOTONIC_RAW, but with 1% or more frequency error. + */ + uint32_t time_since_ec_boot_ms; + + /* + * Number of times the AP was reset by the EC since the last EC boot. + * Note that the AP may be held in reset by the EC during the initial + * boot sequence, such that the very first AP boot may count as more + * than one here. + */ + uint32_t ap_resets_since_ec_boot; + + /* + * The set of flags which describe the EC's most recent reset. See + * include/system.h RESET_FLAG_* for details. + */ + uint32_t ec_reset_flags; + + /* Empty log entries have both the cause and timestamp set to zero. */ + struct ap_reset_log_entry { + /* + * See include/chipset.h: enum chipset_{reset,shutdown}_reason + * for details. + */ + uint16_t reset_cause; + + /* Reserved for protocol growth. */ + uint16_t reserved; + + /* + * The time of the reset's assertion, in milliseconds since the + * last EC boot, in the same epoch as time_since_ec_boot_ms. + * Set to zero if the log entry is empty. + */ + uint32_t reset_time_ms; + } recent_ap_reset[4]; +} __ec_align4; + +/* + * Add entropy to the device secret (stored in the rollback region). + * + * Depending on the chip, the operation may take a long time (e.g. to erase + * flash), so the commands are asynchronous. + */ +#define EC_CMD_ADD_ENTROPY 0x0122 + +enum add_entropy_action { + /* Add entropy to the current secret. */ + ADD_ENTROPY_ASYNC = 0, + /* + * Add entropy, and also make sure that the previous secret is erased. + * (this can be implemented by adding entropy multiple times until + * all rolback blocks have been overwritten). + */ + ADD_ENTROPY_RESET_ASYNC = 1, + /* Read back result from the previous operation. */ + ADD_ENTROPY_GET_RESULT = 2, +}; + +struct ec_params_rollback_add_entropy { + uint8_t action; +} __ec_align1; + +/* + * Perform a single read of a given ADC channel. + */ +#define EC_CMD_ADC_READ 0x0123 + +struct ec_params_adc_read { + uint8_t adc_channel; +} __ec_align1; + +struct ec_response_adc_read { + int32_t adc_value; +} __ec_align4; + +/* + * Read back rollback info + */ +#define EC_CMD_ROLLBACK_INFO 0x0124 + +struct ec_response_rollback_info { + int32_t id; /* Incrementing number to indicate which region to use. */ + int32_t rollback_min_version; + int32_t rw_rollback_version; +} __ec_align4; + + +/* Issue AP reset */ +#define EC_CMD_AP_RESET 0x0125 + +/*****************************************************************************/ +/* The command range 0x200-0x2FF is reserved for Rotor. */ + +/*****************************************************************************/ +/* + * Reserve a range of host commands for the CR51 firmware. + */ +#define EC_CMD_CR51_BASE 0x0300 +#define EC_CMD_CR51_LAST 0x03FF + +/*****************************************************************************/ +/* Fingerprint MCU commands: range 0x0400-0x040x */ + +/* Fingerprint SPI sensor passthru command: prototyping ONLY */ +#define EC_CMD_FP_PASSTHRU 0x0400 + +#define EC_FP_FLAG_NOT_COMPLETE 0x1 + +struct ec_params_fp_passthru { + uint16_t len; /* Number of bytes to write then read */ + uint16_t flags; /* EC_FP_FLAG_xxx */ + uint8_t data[]; /* Data to send */ +} __ec_align2; + +/* Configure the Fingerprint MCU behavior */ +#define EC_CMD_FP_MODE 0x0402 + +/* Put the sensor in its lowest power mode */ +#define FP_MODE_DEEPSLEEP BIT(0) +/* Wait to see a finger on the sensor */ +#define FP_MODE_FINGER_DOWN BIT(1) +/* Poll until the finger has left the sensor */ +#define FP_MODE_FINGER_UP BIT(2) +/* Capture the current finger image */ +#define FP_MODE_CAPTURE BIT(3) +/* Finger enrollment session on-going */ +#define FP_MODE_ENROLL_SESSION BIT(4) +/* Enroll the current finger image */ +#define FP_MODE_ENROLL_IMAGE BIT(5) +/* Try to match the current finger image */ +#define FP_MODE_MATCH BIT(6) +/* Reset and re-initialize the sensor. */ +#define FP_MODE_RESET_SENSOR BIT(7) +/* special value: don't change anything just read back current mode */ +#define FP_MODE_DONT_CHANGE BIT(31) + +#define FP_VALID_MODES (FP_MODE_DEEPSLEEP | \ + FP_MODE_FINGER_DOWN | \ + FP_MODE_FINGER_UP | \ + FP_MODE_CAPTURE | \ + FP_MODE_ENROLL_SESSION | \ + FP_MODE_ENROLL_IMAGE | \ + FP_MODE_MATCH | \ + FP_MODE_RESET_SENSOR | \ + FP_MODE_DONT_CHANGE) + +/* Capture types defined in bits [30..28] */ +#define FP_MODE_CAPTURE_TYPE_SHIFT 28 +#define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT) +/* + * This enum must remain ordered, if you add new values you must ensure that + * FP_CAPTURE_TYPE_MAX is still the last one. + */ +enum fp_capture_type { + /* Full blown vendor-defined capture (produces 'frame_size' bytes) */ + FP_CAPTURE_VENDOR_FORMAT = 0, + /* Simple raw image capture (produces width x height x bpp bits) */ + FP_CAPTURE_SIMPLE_IMAGE = 1, + /* Self test pattern (e.g. checkerboard) */ + FP_CAPTURE_PATTERN0 = 2, + /* Self test pattern (e.g. inverted checkerboard) */ + FP_CAPTURE_PATTERN1 = 3, + /* Capture for Quality test with fixed contrast */ + FP_CAPTURE_QUALITY_TEST = 4, + /* Capture for pixel reset value test */ + FP_CAPTURE_RESET_TEST = 5, + FP_CAPTURE_TYPE_MAX, +}; +/* Extracts the capture type from the sensor 'mode' word */ +#define FP_CAPTURE_TYPE(mode) (((mode) & FP_MODE_CAPTURE_TYPE_MASK) \ + >> FP_MODE_CAPTURE_TYPE_SHIFT) + +struct ec_params_fp_mode { + uint32_t mode; /* as defined by FP_MODE_ constants */ +} __ec_align4; + +struct ec_response_fp_mode { + uint32_t mode; /* as defined by FP_MODE_ constants */ +} __ec_align4; + +/* Retrieve Fingerprint sensor information */ +#define EC_CMD_FP_INFO 0x0403 + +/* Number of dead pixels detected on the last maintenance */ +#define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF) +/* Unknown number of dead pixels detected on the last maintenance */ +#define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF) +/* No interrupt from the sensor */ +#define FP_ERROR_NO_IRQ BIT(12) +/* SPI communication error */ +#define FP_ERROR_SPI_COMM BIT(13) +/* Invalid sensor Hardware ID */ +#define FP_ERROR_BAD_HWID BIT(14) +/* Sensor initialization failed */ +#define FP_ERROR_INIT_FAIL BIT(15) + +struct ec_response_fp_info_v0 { + /* Sensor identification */ + uint32_t vendor_id; + uint32_t product_id; + uint32_t model_id; + uint32_t version; + /* Image frame characteristics */ + uint32_t frame_size; + uint32_t pixel_format; /* using V4L2_PIX_FMT_ */ + uint16_t width; + uint16_t height; + uint16_t bpp; + uint16_t errors; /* see FP_ERROR_ flags above */ +} __ec_align4; + +struct ec_response_fp_info { + /* Sensor identification */ + uint32_t vendor_id; + uint32_t product_id; + uint32_t model_id; + uint32_t version; + /* Image frame characteristics */ + uint32_t frame_size; + uint32_t pixel_format; /* using V4L2_PIX_FMT_ */ + uint16_t width; + uint16_t height; + uint16_t bpp; + uint16_t errors; /* see FP_ERROR_ flags above */ + /* Template/finger current information */ + uint32_t template_size; /* max template size in bytes */ + uint16_t template_max; /* maximum number of fingers/templates */ + uint16_t template_valid; /* number of valid fingers/templates */ + uint32_t template_dirty; /* bitmap of templates with MCU side changes */ + uint32_t template_version; /* version of the template format */ +} __ec_align4; + +/* Get the last captured finger frame or a template content */ +#define EC_CMD_FP_FRAME 0x0404 + +/* constants defining the 'offset' field which also contains the frame index */ +#define FP_FRAME_INDEX_SHIFT 28 +/* Frame buffer where the captured image is stored */ +#define FP_FRAME_INDEX_RAW_IMAGE 0 +/* First frame buffer holding a template */ +#define FP_FRAME_INDEX_TEMPLATE 1 +#define FP_FRAME_GET_BUFFER_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT) +#define FP_FRAME_OFFSET_MASK 0x0FFFFFFF + +/* Version of the format of the encrypted templates. */ +#define FP_TEMPLATE_FORMAT_VERSION 3 + +/* Constants for encryption parameters */ +#define FP_CONTEXT_NONCE_BYTES 12 +#define FP_CONTEXT_USERID_WORDS (32 / sizeof(uint32_t)) +#define FP_CONTEXT_TAG_BYTES 16 +#define FP_CONTEXT_SALT_BYTES 16 +#define FP_CONTEXT_TPM_BYTES 32 + +struct ec_fp_template_encryption_metadata { + /* + * Version of the structure format (N=3). + */ + uint16_t struct_version; + /* Reserved bytes, set to 0. */ + uint16_t reserved; + /* + * The salt is *only* ever used for key derivation. The nonce is unique, + * a different one is used for every message. + */ + uint8_t nonce[FP_CONTEXT_NONCE_BYTES]; + uint8_t salt[FP_CONTEXT_SALT_BYTES]; + uint8_t tag[FP_CONTEXT_TAG_BYTES]; +}; + +struct ec_params_fp_frame { + /* + * The offset contains the template index or FP_FRAME_INDEX_RAW_IMAGE + * in the high nibble, and the real offset within the frame in + * FP_FRAME_OFFSET_MASK. + */ + uint32_t offset; + uint32_t size; +} __ec_align4; + +/* Load a template into the MCU */ +#define EC_CMD_FP_TEMPLATE 0x0405 + +/* Flag in the 'size' field indicating that the full template has been sent */ +#define FP_TEMPLATE_COMMIT 0x80000000 + +struct ec_params_fp_template { + uint32_t offset; + uint32_t size; + uint8_t data[]; +} __ec_align4; + +/* Clear the current fingerprint user context and set a new one */ +#define EC_CMD_FP_CONTEXT 0x0406 + +struct ec_params_fp_context { + uint32_t userid[FP_CONTEXT_USERID_WORDS]; +} __ec_align4; + +#define EC_CMD_FP_STATS 0x0407 + +#define FPSTATS_CAPTURE_INV BIT(0) +#define FPSTATS_MATCHING_INV BIT(1) + +struct ec_response_fp_stats { + uint32_t capture_time_us; + uint32_t matching_time_us; + uint32_t overall_time_us; + struct { + uint32_t lo; + uint32_t hi; + } overall_t0; + uint8_t timestamps_invalid; + int8_t template_matched; +} __ec_align2; + +#define EC_CMD_FP_SEED 0x0408 +struct ec_params_fp_seed { + /* + * Version of the structure format (N=3). + */ + uint16_t struct_version; + /* Reserved bytes, set to 0. */ + uint16_t reserved; + /* Seed from the TPM. */ + uint8_t seed[FP_CONTEXT_TPM_BYTES]; +} __ec_align4; + +/*****************************************************************************/ +/* Touchpad MCU commands: range 0x0500-0x05FF */ + +/* Perform touchpad self test */ +#define EC_CMD_TP_SELF_TEST 0x0500 + +/* Get number of frame types, and the size of each type */ +#define EC_CMD_TP_FRAME_INFO 0x0501 + +struct ec_response_tp_frame_info { + uint32_t n_frames; + uint32_t frame_sizes[0]; +} __ec_align4; + +/* Create a snapshot of current frame readings */ +#define EC_CMD_TP_FRAME_SNAPSHOT 0x0502 + +/* Read the frame */ +#define EC_CMD_TP_FRAME_GET 0x0503 + +struct ec_params_tp_frame_get { + uint32_t frame_index; + uint32_t offset; + uint32_t size; +} __ec_align4; + +/*****************************************************************************/ +/* EC-EC communication commands: range 0x0600-0x06FF */ + +#define EC_COMM_TEXT_MAX 8 + +/* + * Get battery static information, i.e. information that never changes, or + * very infrequently. + */ +#define EC_CMD_BATTERY_GET_STATIC 0x0600 + +/** + * struct ec_params_battery_static_info - Battery static info parameters + * @index: Battery index. + */ +struct ec_params_battery_static_info { + uint8_t index; +} __ec_align_size1; + +/** + * struct ec_response_battery_static_info - Battery static info response + * @design_capacity: Battery Design Capacity (mAh) + * @design_voltage: Battery Design Voltage (mV) + * @manufacturer: Battery Manufacturer String + * @model: Battery Model Number String + * @serial: Battery Serial Number String + * @type: Battery Type String + * @cycle_count: Battery Cycle Count + */ +struct ec_response_battery_static_info { + uint16_t design_capacity; + uint16_t design_voltage; + char manufacturer[EC_COMM_TEXT_MAX]; + char model[EC_COMM_TEXT_MAX]; + char serial[EC_COMM_TEXT_MAX]; + char type[EC_COMM_TEXT_MAX]; + /* TODO(crbug.com/795991): Consider moving to dynamic structure. */ + uint32_t cycle_count; +} __ec_align4; + +/* + * Get battery dynamic information, i.e. information that is likely to change + * every time it is read. + */ +#define EC_CMD_BATTERY_GET_DYNAMIC 0x0601 + +/** + * struct ec_params_battery_dynamic_info - Battery dynamic info parameters + * @index: Battery index. + */ +struct ec_params_battery_dynamic_info { + uint8_t index; +} __ec_align_size1; + +/** + * struct ec_response_battery_dynamic_info - Battery dynamic info response + * @actual_voltage: Battery voltage (mV) + * @actual_current: Battery current (mA); negative=discharging + * @remaining_capacity: Remaining capacity (mAh) + * @full_capacity: Capacity (mAh, might change occasionally) + * @flags: Flags, see EC_BATT_FLAG_* + * @desired_voltage: Charging voltage desired by battery (mV) + * @desired_current: Charging current desired by battery (mA) + */ +struct ec_response_battery_dynamic_info { + int16_t actual_voltage; + int16_t actual_current; + int16_t remaining_capacity; + int16_t full_capacity; + int16_t flags; + int16_t desired_voltage; + int16_t desired_current; +} __ec_align2; + +/* + * Control charger chip. Used to control charger chip on the slave. + */ +#define EC_CMD_CHARGER_CONTROL 0x0602 + +/** + * struct ec_params_charger_control - Charger control parameters + * @max_current: Charger current (mA). Positive to allow base to draw up to + * max_current and (possibly) charge battery, negative to request current + * from base (OTG). + * @otg_voltage: Voltage (mV) to use in OTG mode, ignored if max_current is + * >= 0. + * @allow_charging: Allow base battery charging (only makes sense if + * max_current > 0). + */ +struct ec_params_charger_control { + int16_t max_current; + uint16_t otg_voltage; + uint8_t allow_charging; +} __ec_align_size1; + +/*****************************************************************************/ +/* + * Reserve a range of host commands for board-specific, experimental, or + * special purpose features. These can be (re)used without updating this file. + * + * CAUTION: Don't go nuts with this. Shipping products should document ALL + * their EC commands for easier development, testing, debugging, and support. + * + * All commands MUST be #defined to be 4-digit UPPER CASE hex values + * (e.g., 0x00AB, not 0xab) for CONFIG_HOSTCMD_SECTION_SORTED to work. + * + * In your experimental code, you may want to do something like this: + * + * #define EC_CMD_MAGIC_FOO 0x0000 + * #define EC_CMD_MAGIC_BAR 0x0001 + * #define EC_CMD_MAGIC_HEY 0x0002 + * + * DECLARE_PRIVATE_HOST_COMMAND(EC_CMD_MAGIC_FOO, magic_foo_handler, + * EC_VER_MASK(0); + * + * DECLARE_PRIVATE_HOST_COMMAND(EC_CMD_MAGIC_BAR, magic_bar_handler, + * EC_VER_MASK(0); + * + * DECLARE_PRIVATE_HOST_COMMAND(EC_CMD_MAGIC_HEY, magic_hey_handler, + * EC_VER_MASK(0); + */ +#define EC_CMD_BOARD_SPECIFIC_BASE 0x3E00 +#define EC_CMD_BOARD_SPECIFIC_LAST 0x3FFF + +/* + * Given the private host command offset, calculate the true private host + * command value. + */ +#define EC_PRIVATE_HOST_COMMAND_VALUE(command) \ + (EC_CMD_BOARD_SPECIFIC_BASE + (command)) + +/*****************************************************************************/ +/* + * Passthru commands + * + * Some platforms have sub-processors chained to each other. For example. + * + * AP <--> EC <--> PD MCU + * + * The top 2 bits of the command number are used to indicate which device the + * command is intended for. Device 0 is always the device receiving the + * command; other device mapping is board-specific. + * + * When a device receives a command to be passed to a sub-processor, it passes + * it on with the device number set back to 0. This allows the sub-processor + * to remain blissfully unaware of whether the command originated on the next + * device up the chain, or was passed through from the AP. + * + * In the above example, if the AP wants to send command 0x0002 to the PD MCU, + * AP sends command 0x4002 to the EC + * EC sends command 0x0002 to the PD MCU + * EC forwards PD MCU response back to the AP + */ + +/* Offset and max command number for sub-device n */ +#define EC_CMD_PASSTHRU_OFFSET(n) (0x4000 * (n)) +#define EC_CMD_PASSTHRU_MAX(n) (EC_CMD_PASSTHRU_OFFSET(n) + 0x3fff) + +/*****************************************************************************/ +/* + * Deprecated constants. These constants have been renamed for clarity. The + * meaning and size has not changed. Programs that use the old names should + * switch to the new names soon, as the old names may not be carried forward + * forever. + */ +#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE +#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1 +#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE + + + +#endif /* __CROS_EC_COMMANDS_H */ diff --git a/include/linux/platform_data/cros_ec_proto.h b/include/linux/platform_data/cros_ec_proto.h new file mode 100644 index 000000000000..eab7036cda09 --- /dev/null +++ b/include/linux/platform_data/cros_ec_proto.h @@ -0,0 +1,319 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * ChromeOS Embedded Controller protocol interface. + * + * Copyright (C) 2012 Google, Inc + */ + +#ifndef __LINUX_CROS_EC_PROTO_H +#define __LINUX_CROS_EC_PROTO_H + +#include +#include +#include + +#include + +#define CROS_EC_DEV_NAME "cros_ec" +#define CROS_EC_DEV_FP_NAME "cros_fp" +#define CROS_EC_DEV_ISH_NAME "cros_ish" +#define CROS_EC_DEV_PD_NAME "cros_pd" +#define CROS_EC_DEV_SCP_NAME "cros_scp" +#define CROS_EC_DEV_TP_NAME "cros_tp" + +/* + * The EC is unresponsive for a time after a reboot command. Add a + * simple delay to make sure that the bus stays locked. + */ +#define EC_REBOOT_DELAY_MS 50 + +/* + * Max bus-specific overhead incurred by request/responses. + * I2C requires 1 additional byte for requests. + * I2C requires 2 additional bytes for responses. + * SPI requires up to 32 additional bytes for responses. + */ +#define EC_PROTO_VERSION_UNKNOWN 0 +#define EC_MAX_REQUEST_OVERHEAD 1 +#define EC_MAX_RESPONSE_OVERHEAD 32 + +/* + * Command interface between EC and AP, for LPC, I2C and SPI interfaces. + */ +enum { + EC_MSG_TX_HEADER_BYTES = 3, + EC_MSG_TX_TRAILER_BYTES = 1, + EC_MSG_TX_PROTO_BYTES = EC_MSG_TX_HEADER_BYTES + + EC_MSG_TX_TRAILER_BYTES, + EC_MSG_RX_PROTO_BYTES = 3, + + /* Max length of messages for proto 2*/ + EC_PROTO2_MSG_BYTES = EC_PROTO2_MAX_PARAM_SIZE + + EC_MSG_TX_PROTO_BYTES, + + EC_MAX_MSG_BYTES = 64 * 1024, +}; + +/** + * struct cros_ec_command - Information about a ChromeOS EC command. + * @version: Command version number (often 0). + * @command: Command to send (EC_CMD_...). + * @outsize: Outgoing length in bytes. + * @insize: Max number of bytes to accept from the EC. + * @result: EC's response to the command (separate from communication failure). + * @data: Where to put the incoming data from EC and outgoing data to EC. + */ +struct cros_ec_command { + uint32_t version; + uint32_t command; + uint32_t outsize; + uint32_t insize; + uint32_t result; + uint8_t data[0]; +}; + +/** + * struct cros_ec_device - Information about a ChromeOS EC device. + * @phys_name: Name of physical comms layer (e.g. 'i2c-4'). + * @dev: Device pointer for physical comms device + * @was_wake_device: True if this device was set to wake the system from + * sleep at the last suspend. + * @cros_class: The class structure for this device. + * @cmd_readmem: Direct read of the EC memory-mapped region, if supported. + * @offset: Is within EC_LPC_ADDR_MEMMAP region. + * @bytes: Number of bytes to read. zero means "read a string" (including + * the trailing '\0'). At most only EC_MEMMAP_SIZE bytes can be + * read. Caller must ensure that the buffer is large enough for the + * result when reading a string. + * @max_request: Max size of message requested. + * @max_response: Max size of message response. + * @max_passthru: Max sice of passthru message. + * @proto_version: The protocol version used for this device. + * @priv: Private data. + * @irq: Interrupt to use. + * @id: Device id. + * @din: Input buffer (for data from EC). This buffer will always be + * dword-aligned and include enough space for up to 7 word-alignment + * bytes also, so we can ensure that the body of the message is always + * dword-aligned (64-bit). We use this alignment to keep ARM and x86 + * happy. Probably word alignment would be OK, there might be a small + * performance advantage to using dword. + * @dout: Output buffer (for data to EC). This buffer will always be + * dword-aligned and include enough space for up to 7 word-alignment + * bytes also, so we can ensure that the body of the message is always + * dword-aligned (64-bit). We use this alignment to keep ARM and x86 + * happy. Probably word alignment would be OK, there might be a small + * performance advantage to using dword. + * @din_size: Size of din buffer to allocate (zero to use static din). + * @dout_size: Size of dout buffer to allocate (zero to use static dout). + * @wake_enabled: True if this device can wake the system from sleep. + * @suspended: True if this device had been suspended. + * @cmd_xfer: Send command to EC and get response. + * Returns the number of bytes received if the communication + * succeeded, but that doesn't mean the EC was happy with the + * command. The caller should check msg.result for the EC's result + * code. + * @pkt_xfer: Send packet to EC and get response. + * @lock: One transaction at a time. + * @mkbp_event_supported: True if this EC supports the MKBP event protocol. + * @host_sleep_v1: True if this EC supports the sleep v1 command. + * @event_notifier: Interrupt event notifier for transport devices. + * @event_data: Raw payload transferred with the MKBP event. + * @event_size: Size in bytes of the event data. + * @host_event_wake_mask: Mask of host events that cause wake from suspend. + * @ec: The platform_device used by the mfd driver to interface with the + * main EC. + * @pd: The platform_device used by the mfd driver to interface with the + * PD behind an EC. + */ +struct cros_ec_device { + /* These are used by other drivers that want to talk to the EC */ + const char *phys_name; + struct device *dev; + bool was_wake_device; + struct class *cros_class; + int (*cmd_readmem)(struct cros_ec_device *ec, unsigned int offset, + unsigned int bytes, void *dest); + + /* These are used to implement the platform-specific interface */ + u16 max_request; + u16 max_response; + u16 max_passthru; + u16 proto_version; + void *priv; + int irq; + u8 *din; + u8 *dout; + int din_size; + int dout_size; + bool wake_enabled; + bool suspended; + int (*cmd_xfer)(struct cros_ec_device *ec, + struct cros_ec_command *msg); + int (*pkt_xfer)(struct cros_ec_device *ec, + struct cros_ec_command *msg); + struct mutex lock; + bool mkbp_event_supported; + bool host_sleep_v1; + struct blocking_notifier_head event_notifier; + + struct ec_response_get_next_event_v1 event_data; + int event_size; + u32 host_event_wake_mask; + u32 last_resume_result; + + /* The platform devices used by the mfd driver */ + struct platform_device *ec; + struct platform_device *pd; +}; + +/** + * struct cros_ec_sensor_platform - ChromeOS EC sensor platform information. + * @sensor_num: Id of the sensor, as reported by the EC. + */ +struct cros_ec_sensor_platform { + u8 sensor_num; +}; + +/** + * struct cros_ec_platform - ChromeOS EC platform information. + * @ec_name: Name of EC device (e.g. 'cros-ec', 'cros-pd', ...) + * used in /dev/ and sysfs. + * @cmd_offset: Offset to apply for each command. Set when + * registering a device behind another one. + */ +struct cros_ec_platform { + const char *ec_name; + u16 cmd_offset; +}; + +/** + * cros_ec_suspend() - Handle a suspend operation for the ChromeOS EC device. + * @ec_dev: Device to suspend. + * + * This can be called by drivers to handle a suspend event. + * + * Return: 0 on success or negative error code. + */ +int cros_ec_suspend(struct cros_ec_device *ec_dev); + +/** + * cros_ec_resume() - Handle a resume operation for the ChromeOS EC device. + * @ec_dev: Device to resume. + * + * This can be called by drivers to handle a resume event. + * + * Return: 0 on success or negative error code. + */ +int cros_ec_resume(struct cros_ec_device *ec_dev); + +/** + * cros_ec_prepare_tx() - Prepare an outgoing message in the output buffer. + * @ec_dev: Device to register. + * @msg: Message to write. + * + * This is intended to be used by all ChromeOS EC drivers, but at present + * only SPI uses it. Once LPC uses the same protocol it can start using it. + * I2C could use it now, with a refactor of the existing code. + * + * Return: 0 on success or negative error code. + */ +int cros_ec_prepare_tx(struct cros_ec_device *ec_dev, + struct cros_ec_command *msg); + +/** + * cros_ec_check_result() - Check ec_msg->result. + * @ec_dev: EC device. + * @msg: Message to check. + * + * This is used by ChromeOS EC drivers to check the ec_msg->result for + * errors and to warn about them. + * + * Return: 0 on success or negative error code. + */ +int cros_ec_check_result(struct cros_ec_device *ec_dev, + struct cros_ec_command *msg); + +/** + * cros_ec_cmd_xfer() - Send a command to the ChromeOS EC. + * @ec_dev: EC device. + * @msg: Message to write. + * + * Call this to send a command to the ChromeOS EC. This should be used + * instead of calling the EC's cmd_xfer() callback directly. + * + * Return: 0 on success or negative error code. + */ +int cros_ec_cmd_xfer(struct cros_ec_device *ec_dev, + struct cros_ec_command *msg); + +/** + * cros_ec_cmd_xfer_status() - Send a command to the ChromeOS EC. + * @ec_dev: EC device. + * @msg: Message to write. + * + * This function is identical to cros_ec_cmd_xfer, except it returns success + * status only if both the command was transmitted successfully and the EC + * replied with success status. It's not necessary to check msg->result when + * using this function. + * + * Return: The number of bytes transferred on success or negative error code. + */ +int cros_ec_cmd_xfer_status(struct cros_ec_device *ec_dev, + struct cros_ec_command *msg); + +/** + * cros_ec_register() - Register a new ChromeOS EC, using the provided info. + * @ec_dev: Device to register. + * + * Before calling this, allocate a pointer to a new device and then fill + * in all the fields up to the --private-- marker. + * + * Return: 0 on success or negative error code. + */ +int cros_ec_register(struct cros_ec_device *ec_dev); + +/** + * cros_ec_unregister() - Remove a ChromeOS EC. + * @ec_dev: Device to unregister. + * + * Call this to deregister a ChromeOS EC, then clean up any private data. + * + * Return: 0 on success or negative error code. + */ +int cros_ec_unregister(struct cros_ec_device *ec_dev); + +/** + * cros_ec_query_all() - Query the protocol version supported by the + * ChromeOS EC. + * @ec_dev: Device to register. + * + * Return: 0 on success or negative error code. + */ +int cros_ec_query_all(struct cros_ec_device *ec_dev); + +/** + * cros_ec_get_next_event() - Fetch next event from the ChromeOS EC. + * @ec_dev: Device to fetch event from. + * @wake_event: Pointer to a bool set to true upon return if the event might be + * treated as a wake event. Ignored if null. + * + * Return: negative error code on errors; 0 for no data; or else number of + * bytes received (i.e., an event was retrieved successfully). Event types are + * written out to @ec_dev->event_data.event_type on success. + */ +int cros_ec_get_next_event(struct cros_ec_device *ec_dev, bool *wake_event); + +/** + * cros_ec_get_host_event() - Return a mask of event set by the ChromeOS EC. + * @ec_dev: Device to fetch event from. + * + * When MKBP is supported, when the EC raises an interrupt, we collect the + * events raised and call the functions in the ec notifier. This function + * is a helper to know which events are raised. + * + * Return: 0 on error or non-zero bitmask of one or more EC_HOST_EVENT_*. + */ +u32 cros_ec_get_host_event(struct cros_ec_device *ec_dev); + +#endif /* __LINUX_CROS_EC_PROTO_H */ diff --git a/sound/soc/codecs/cros_ec_codec.c b/sound/soc/codecs/cros_ec_codec.c index 85beef265cc8..3c1bd24a1057 100644 --- a/sound/soc/codecs/cros_ec_codec.c +++ b/sound/soc/codecs/cros_ec_codec.c @@ -9,9 +9,9 @@ #include #include #include -#include -#include #include +#include +#include #include #include #include -- cgit v1.2.3-71-gd317 From 74ded38a8e185b57a4362787815c353ac595013c Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Sat, 31 Aug 2019 10:26:21 +0200 Subject: w1: add 1-wire master driver for IP block found in SGI ASICs Starting with SGI Origin machines nearly every new SGI ASIC contains an 1-Wire master. They are used for attaching One-Wire prom devices, which contain information about part numbers, revision numbers, serial number etc. and MAC addresses for ethernet interfaces. This patch adds a master driver to support this IP block. It also adds an extra field dev_id to struct w1_bus_master, which could be in used in slave drivers for creating unique device names. Signed-off-by: Thomas Bogendoerfer Link: https://lore.kernel.org/r/20190831082623.15627-2-tbogendoerfer@suse.de Signed-off-by: Greg Kroah-Hartman --- drivers/w1/masters/Kconfig | 9 +++ drivers/w1/masters/Makefile | 1 + drivers/w1/masters/sgi_w1.c | 130 +++++++++++++++++++++++++++++++++++ include/linux/platform_data/sgi-w1.h | 13 ++++ include/linux/w1.h | 5 ++ 5 files changed, 158 insertions(+) create mode 100644 drivers/w1/masters/sgi_w1.c create mode 100644 include/linux/platform_data/sgi-w1.h (limited to 'include/linux/platform_data') diff --git a/drivers/w1/masters/Kconfig b/drivers/w1/masters/Kconfig index 7ae260577901..24b9a8e05f64 100644 --- a/drivers/w1/masters/Kconfig +++ b/drivers/w1/masters/Kconfig @@ -65,5 +65,14 @@ config HDQ_MASTER_OMAP Say Y here if you want support for the 1-wire or HDQ Interface on an OMAP processor. +config W1_MASTER_SGI + tristate "SGI ASIC driver" + help + Say Y here if you want support for your 1-wire devices using + SGI ASIC 1-Wire interface + + This support is also available as a module. If so, the module + will be called sgi_w1. + endmenu diff --git a/drivers/w1/masters/Makefile b/drivers/w1/masters/Makefile index 18954cae4256..dae629b7ab49 100644 --- a/drivers/w1/masters/Makefile +++ b/drivers/w1/masters/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_W1_MASTER_MXC) += mxc_w1.o obj-$(CONFIG_W1_MASTER_DS1WM) += ds1wm.o obj-$(CONFIG_W1_MASTER_GPIO) += w1-gpio.o obj-$(CONFIG_HDQ_MASTER_OMAP) += omap_hdq.o +obj-$(CONFIG_W1_MASTER_SGI) += sgi_w1.o diff --git a/drivers/w1/masters/sgi_w1.c b/drivers/w1/masters/sgi_w1.c new file mode 100644 index 000000000000..1b2d96b945be --- /dev/null +++ b/drivers/w1/masters/sgi_w1.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * sgi_w1.c - w1 master driver for one wire support in SGI ASICs + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define MCR_RD_DATA BIT(0) +#define MCR_DONE BIT(1) + +#define MCR_PACK(pulse, sample) (((pulse) << 10) | ((sample) << 2)) + +struct sgi_w1_device { + u32 __iomem *mcr; + struct w1_bus_master bus_master; + char dev_id[64]; +}; + +static u8 sgi_w1_wait(u32 __iomem *mcr) +{ + u32 mcr_val; + + do { + mcr_val = readl(mcr); + } while (!(mcr_val & MCR_DONE)); + + return (mcr_val & MCR_RD_DATA) ? 1 : 0; +} + +/* + * this is the low level routine to + * reset the device on the One Wire interface + * on the hardware + */ +static u8 sgi_w1_reset_bus(void *data) +{ + struct sgi_w1_device *dev = data; + u8 ret; + + writel(MCR_PACK(520, 65), dev->mcr); + ret = sgi_w1_wait(dev->mcr); + udelay(500); /* recovery time */ + return ret; +} + +/* + * this is the low level routine to read/write a bit on the One Wire + * interface on the hardware. It does write 0 if parameter bit is set + * to 0, otherwise a write 1/read. + */ +static u8 sgi_w1_touch_bit(void *data, u8 bit) +{ + struct sgi_w1_device *dev = data; + u8 ret; + + if (bit) + writel(MCR_PACK(6, 13), dev->mcr); + else + writel(MCR_PACK(80, 30), dev->mcr); + + ret = sgi_w1_wait(dev->mcr); + if (bit) + udelay(100); /* recovery */ + return ret; +} + +static int sgi_w1_probe(struct platform_device *pdev) +{ + struct sgi_w1_device *sdev; + struct sgi_w1_platform_data *pdata; + struct resource *res; + + sdev = devm_kzalloc(&pdev->dev, sizeof(struct sgi_w1_device), + GFP_KERNEL); + if (!sdev) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + sdev->mcr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(sdev->mcr)) + return PTR_ERR(sdev->mcr); + + sdev->bus_master.data = sdev; + sdev->bus_master.reset_bus = sgi_w1_reset_bus; + sdev->bus_master.touch_bit = sgi_w1_touch_bit; + + pdata = dev_get_platdata(&pdev->dev); + if (pdata) { + strlcpy(sdev->dev_id, pdata->dev_id, sizeof(sdev->dev_id)); + sdev->bus_master.dev_id = sdev->dev_id; + } + + platform_set_drvdata(pdev, sdev); + + return w1_add_master_device(&sdev->bus_master); +} + +/* + * disassociate the w1 device from the driver + */ +static int sgi_w1_remove(struct platform_device *pdev) +{ + struct sgi_w1_device *sdev = platform_get_drvdata(pdev); + + w1_remove_master_device(&sdev->bus_master); + + return 0; +} + +static struct platform_driver sgi_w1_driver = { + .driver = { + .name = "sgi_w1", + }, + .probe = sgi_w1_probe, + .remove = sgi_w1_remove, +}; +module_platform_driver(sgi_w1_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Thomas Bogendoerfer"); +MODULE_DESCRIPTION("Driver for One-Wire IP in SGI ASICs"); diff --git a/include/linux/platform_data/sgi-w1.h b/include/linux/platform_data/sgi-w1.h new file mode 100644 index 000000000000..e28c8a90ff84 --- /dev/null +++ b/include/linux/platform_data/sgi-w1.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SGI One-Wire (W1) IP + */ + +#ifndef PLATFORM_DATA_SGI_W1_H +#define PLATFORM_DATA_SGI_W1_H + +struct sgi_w1_platform_data { + char dev_id[64]; +}; + +#endif /* PLATFORM_DATA_SGI_W1_H */ diff --git a/include/linux/w1.h b/include/linux/w1.h index e0b5156f78fd..7da0c7588e04 100644 --- a/include/linux/w1.h +++ b/include/linux/w1.h @@ -118,6 +118,9 @@ typedef void (*w1_slave_found_callback)(struct w1_master *, u64); * w1_master* is passed to the slave found callback. * u8 is search_type, W1_SEARCH or W1_ALARM_SEARCH * + * @dev_id: Optional device id string, which w1 slaves could use for + * creating names, which then give a connection to the w1 master + * * Note: read_bit and write_bit are very low level functions and should only * be used with hardware that doesn't really support 1-wire operations, * like a parallel/serial port. @@ -150,6 +153,8 @@ struct w1_bus_master { void (*search)(void *, struct w1_master *, u8, w1_slave_found_callback); + + char *dev_id; }; /** -- cgit v1.2.3-71-gd317 From 305e503b14a879e619974b8e82236d5f32d0921e Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 22:27:35 +0200 Subject: spi: remove w90x900 driver The ARM w90x900 platform is getting removed, so this driver is obsolete. Link: https://lore.kernel.org/r/20190809202749.742267-8-arnd@arndb.de Signed-off-by: Arnd Bergmann Acked-by: Mark Brown Signed-off-by: Arnd Bergmann --- drivers/spi/Kconfig | 7 - drivers/spi/Makefile | 1 - drivers/spi/spi-nuc900.c | 429 ------------------------------- include/Kbuild | 1 - include/linux/platform_data/spi-nuc900.h | 29 --- 5 files changed, 467 deletions(-) delete mode 100644 drivers/spi/spi-nuc900.c delete mode 100644 include/linux/platform_data/spi-nuc900.h (limited to 'include/linux/platform_data') diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3a1d8f1170de..949b18ed9d6b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -440,13 +440,6 @@ config SPI_NPCM_PSPI This driver provides support for Nuvoton NPCM BMC Peripheral SPI controller in master mode. -config SPI_NUC900 - tristate "Nuvoton NUC900 series SPI" - depends on ARCH_W90X900 - select SPI_BITBANG - help - SPI driver for Nuvoton NUC900 series ARM SoCs - config SPI_LANTIQ_SSC tristate "Lantiq SSC SPI controller" depends on LANTIQ || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 63dcab552bcb..b1131809a294 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -64,7 +64,6 @@ obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o obj-$(CONFIG_SPI_MXIC) += spi-mxic.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o obj-$(CONFIG_SPI_NPCM_PSPI) += spi-npcm-pspi.o -obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o spi-octeon-objs := spi-cavium.o spi-cavium-octeon.o diff --git a/drivers/spi/spi-nuc900.c b/drivers/spi/spi-nuc900.c deleted file mode 100644 index 37e2034ad4d5..000000000000 --- a/drivers/spi/spi-nuc900.c +++ /dev/null @@ -1,429 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2009 Nuvoton technology. - * Wan ZongShun - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -/* usi registers offset */ -#define USI_CNT 0x00 -#define USI_DIV 0x04 -#define USI_SSR 0x08 -#define USI_RX0 0x10 -#define USI_TX0 0x10 - -/* usi register bit */ -#define ENINT (0x01 << 17) -#define ENFLG (0x01 << 16) -#define SLEEP (0x0f << 12) -#define TXNUM (0x03 << 8) -#define TXBITLEN (0x1f << 3) -#define TXNEG (0x01 << 2) -#define RXNEG (0x01 << 1) -#define LSB (0x01 << 10) -#define SELECTLEV (0x01 << 2) -#define SELECTPOL (0x01 << 31) -#define SELECTSLAVE 0x01 -#define GOBUSY 0x01 - -struct nuc900_spi { - struct spi_bitbang bitbang; - struct completion done; - void __iomem *regs; - int irq; - int len; - int count; - const unsigned char *tx; - unsigned char *rx; - struct clk *clk; - struct spi_master *master; - struct nuc900_spi_info *pdata; - spinlock_t lock; -}; - -static inline struct nuc900_spi *to_hw(struct spi_device *sdev) -{ - return spi_master_get_devdata(sdev->master); -} - -static void nuc900_slave_select(struct spi_device *spi, unsigned int ssr) -{ - struct nuc900_spi *hw = to_hw(spi); - unsigned int val; - unsigned int cs = spi->mode & SPI_CS_HIGH ? 1 : 0; - unsigned int cpol = spi->mode & SPI_CPOL ? 1 : 0; - unsigned long flags; - - spin_lock_irqsave(&hw->lock, flags); - - val = __raw_readl(hw->regs + USI_SSR); - - if (!cs) - val &= ~SELECTLEV; - else - val |= SELECTLEV; - - if (!ssr) - val &= ~SELECTSLAVE; - else - val |= SELECTSLAVE; - - __raw_writel(val, hw->regs + USI_SSR); - - val = __raw_readl(hw->regs + USI_CNT); - - if (!cpol) - val &= ~SELECTPOL; - else - val |= SELECTPOL; - - __raw_writel(val, hw->regs + USI_CNT); - - spin_unlock_irqrestore(&hw->lock, flags); -} - -static void nuc900_spi_chipsel(struct spi_device *spi, int value) -{ - switch (value) { - case BITBANG_CS_INACTIVE: - nuc900_slave_select(spi, 0); - break; - - case BITBANG_CS_ACTIVE: - nuc900_slave_select(spi, 1); - break; - } -} - -static void nuc900_spi_setup_txnum(struct nuc900_spi *hw, unsigned int txnum) -{ - unsigned int val; - unsigned long flags; - - spin_lock_irqsave(&hw->lock, flags); - - val = __raw_readl(hw->regs + USI_CNT) & ~TXNUM; - - if (txnum) - val |= txnum << 0x08; - - __raw_writel(val, hw->regs + USI_CNT); - - spin_unlock_irqrestore(&hw->lock, flags); - -} - -static void nuc900_spi_setup_txbitlen(struct nuc900_spi *hw, - unsigned int txbitlen) -{ - unsigned int val; - unsigned long flags; - - spin_lock_irqsave(&hw->lock, flags); - - val = __raw_readl(hw->regs + USI_CNT) & ~TXBITLEN; - - val |= (txbitlen << 0x03); - - __raw_writel(val, hw->regs + USI_CNT); - - spin_unlock_irqrestore(&hw->lock, flags); -} - -static void nuc900_spi_gobusy(struct nuc900_spi *hw) -{ - unsigned int val; - unsigned long flags; - - spin_lock_irqsave(&hw->lock, flags); - - val = __raw_readl(hw->regs + USI_CNT); - - val |= GOBUSY; - - __raw_writel(val, hw->regs + USI_CNT); - - spin_unlock_irqrestore(&hw->lock, flags); -} - -static inline unsigned int hw_txbyte(struct nuc900_spi *hw, int count) -{ - return hw->tx ? hw->tx[count] : 0; -} - -static int nuc900_spi_txrx(struct spi_device *spi, struct spi_transfer *t) -{ - struct nuc900_spi *hw = to_hw(spi); - - hw->tx = t->tx_buf; - hw->rx = t->rx_buf; - hw->len = t->len; - hw->count = 0; - - __raw_writel(hw_txbyte(hw, 0x0), hw->regs + USI_TX0); - - nuc900_spi_gobusy(hw); - - wait_for_completion(&hw->done); - - return hw->count; -} - -static irqreturn_t nuc900_spi_irq(int irq, void *dev) -{ - struct nuc900_spi *hw = dev; - unsigned int status; - unsigned int count = hw->count; - - status = __raw_readl(hw->regs + USI_CNT); - __raw_writel(status, hw->regs + USI_CNT); - - if (status & ENFLG) { - hw->count++; - - if (hw->rx) - hw->rx[count] = __raw_readl(hw->regs + USI_RX0); - count++; - - if (count < hw->len) { - __raw_writel(hw_txbyte(hw, count), hw->regs + USI_TX0); - nuc900_spi_gobusy(hw); - } else { - complete(&hw->done); - } - - return IRQ_HANDLED; - } - - complete(&hw->done); - return IRQ_HANDLED; -} - -static void nuc900_tx_edge(struct nuc900_spi *hw, unsigned int edge) -{ - unsigned int val; - unsigned long flags; - - spin_lock_irqsave(&hw->lock, flags); - - val = __raw_readl(hw->regs + USI_CNT); - - if (edge) - val |= TXNEG; - else - val &= ~TXNEG; - __raw_writel(val, hw->regs + USI_CNT); - - spin_unlock_irqrestore(&hw->lock, flags); -} - -static void nuc900_rx_edge(struct nuc900_spi *hw, unsigned int edge) -{ - unsigned int val; - unsigned long flags; - - spin_lock_irqsave(&hw->lock, flags); - - val = __raw_readl(hw->regs + USI_CNT); - - if (edge) - val |= RXNEG; - else - val &= ~RXNEG; - __raw_writel(val, hw->regs + USI_CNT); - - spin_unlock_irqrestore(&hw->lock, flags); -} - -static void nuc900_send_first(struct nuc900_spi *hw, unsigned int lsb) -{ - unsigned int val; - unsigned long flags; - - spin_lock_irqsave(&hw->lock, flags); - - val = __raw_readl(hw->regs + USI_CNT); - - if (lsb) - val |= LSB; - else - val &= ~LSB; - __raw_writel(val, hw->regs + USI_CNT); - - spin_unlock_irqrestore(&hw->lock, flags); -} - -static void nuc900_set_sleep(struct nuc900_spi *hw, unsigned int sleep) -{ - unsigned int val; - unsigned long flags; - - spin_lock_irqsave(&hw->lock, flags); - - val = __raw_readl(hw->regs + USI_CNT) & ~SLEEP; - - if (sleep) - val |= (sleep << 12); - - __raw_writel(val, hw->regs + USI_CNT); - - spin_unlock_irqrestore(&hw->lock, flags); -} - -static void nuc900_enable_int(struct nuc900_spi *hw) -{ - unsigned int val; - unsigned long flags; - - spin_lock_irqsave(&hw->lock, flags); - - val = __raw_readl(hw->regs + USI_CNT); - - val |= ENINT; - - __raw_writel(val, hw->regs + USI_CNT); - - spin_unlock_irqrestore(&hw->lock, flags); -} - -static void nuc900_set_divider(struct nuc900_spi *hw) -{ - __raw_writel(hw->pdata->divider, hw->regs + USI_DIV); -} - -static void nuc900_init_spi(struct nuc900_spi *hw) -{ - clk_enable(hw->clk); - spin_lock_init(&hw->lock); - - nuc900_tx_edge(hw, hw->pdata->txneg); - nuc900_rx_edge(hw, hw->pdata->rxneg); - nuc900_send_first(hw, hw->pdata->lsb); - nuc900_set_sleep(hw, hw->pdata->sleep); - nuc900_spi_setup_txbitlen(hw, hw->pdata->txbitlen); - nuc900_spi_setup_txnum(hw, hw->pdata->txnum); - nuc900_set_divider(hw); - nuc900_enable_int(hw); -} - -static int nuc900_spi_probe(struct platform_device *pdev) -{ - struct nuc900_spi *hw; - struct spi_master *master; - struct resource *res; - int err = 0; - - master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi)); - if (master == NULL) { - dev_err(&pdev->dev, "No memory for spi_master\n"); - return -ENOMEM; - } - - hw = spi_master_get_devdata(master); - hw->master = master; - hw->pdata = dev_get_platdata(&pdev->dev); - - if (hw->pdata == NULL) { - dev_err(&pdev->dev, "No platform data supplied\n"); - err = -ENOENT; - goto err_pdata; - } - - platform_set_drvdata(pdev, hw); - init_completion(&hw->done); - - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; - if (hw->pdata->lsb) - master->mode_bits |= SPI_LSB_FIRST; - master->num_chipselect = hw->pdata->num_cs; - master->bus_num = hw->pdata->bus_num; - hw->bitbang.master = hw->master; - hw->bitbang.chipselect = nuc900_spi_chipsel; - hw->bitbang.txrx_bufs = nuc900_spi_txrx; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - hw->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(hw->regs)) { - err = PTR_ERR(hw->regs); - goto err_pdata; - } - - hw->irq = platform_get_irq(pdev, 0); - if (hw->irq < 0) { - dev_err(&pdev->dev, "No IRQ specified\n"); - err = -ENOENT; - goto err_pdata; - } - - err = devm_request_irq(&pdev->dev, hw->irq, nuc900_spi_irq, 0, - pdev->name, hw); - if (err) { - dev_err(&pdev->dev, "Cannot claim IRQ\n"); - goto err_pdata; - } - - hw->clk = devm_clk_get(&pdev->dev, "spi"); - if (IS_ERR(hw->clk)) { - dev_err(&pdev->dev, "No clock for device\n"); - err = PTR_ERR(hw->clk); - goto err_pdata; - } - - mfp_set_groupg(&pdev->dev, NULL); - nuc900_init_spi(hw); - - err = spi_bitbang_start(&hw->bitbang); - if (err) { - dev_err(&pdev->dev, "Failed to register SPI master\n"); - goto err_register; - } - - return 0; - -err_register: - clk_disable(hw->clk); -err_pdata: - spi_master_put(hw->master); - return err; -} - -static int nuc900_spi_remove(struct platform_device *dev) -{ - struct nuc900_spi *hw = platform_get_drvdata(dev); - - spi_bitbang_stop(&hw->bitbang); - clk_disable(hw->clk); - spi_master_put(hw->master); - return 0; -} - -static struct platform_driver nuc900_spi_driver = { - .probe = nuc900_spi_probe, - .remove = nuc900_spi_remove, - .driver = { - .name = "nuc900-spi", - }, -}; -module_platform_driver(nuc900_spi_driver); - -MODULE_AUTHOR("Wan ZongShun "); -MODULE_DESCRIPTION("nuc900 spi driver!"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:nuc900-spi"); diff --git a/include/Kbuild b/include/Kbuild index c38f0d46b267..5e0642d79dce 100644 --- a/include/Kbuild +++ b/include/Kbuild @@ -550,7 +550,6 @@ header-test- += linux/platform_data/sky81452-backlight.h header-test- += linux/platform_data/spi-davinci.h header-test- += linux/platform_data/spi-ep93xx.h header-test- += linux/platform_data/spi-mt65xx.h -header-test- += linux/platform_data/spi-nuc900.h header-test- += linux/platform_data/st_sensors_pdata.h header-test- += linux/platform_data/ti-sysc.h header-test- += linux/platform_data/timer-ixp4xx.h diff --git a/include/linux/platform_data/spi-nuc900.h b/include/linux/platform_data/spi-nuc900.h deleted file mode 100644 index ca3510877000..000000000000 --- a/include/linux/platform_data/spi-nuc900.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2009 Nuvoton technology corporation. - * - * Wan ZongShun - */ - -#ifndef __SPI_NUC900_H -#define __SPI_NUC900_H - -extern void mfp_set_groupg(struct device *dev, const char *subname); - -struct nuc900_spi_info { - unsigned int num_cs; - unsigned int lsb; - unsigned int txneg; - unsigned int rxneg; - unsigned int divider; - unsigned int sleep; - unsigned int txnum; - unsigned int txbitlen; - int bus_num; -}; - -struct nuc900_spi_chip { - unsigned char bits_per_word; -}; - -#endif /* __SPI_NUC900_H */ -- cgit v1.2.3-71-gd317 From c7b46e0c33c594623a279db4e1725d7ae477280f Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 22:27:37 +0200 Subject: fbdev: remove w90x900/nuc900 platform drivers The ARM w90x900 platform is getting removed, so this driver is obsolete. Link: https://lore.kernel.org/r/20190809202749.742267-10-arnd@arndb.de Signed-off-by: Arnd Bergmann Acked-by: Bartlomiej Zolnierkiewicz Signed-off-by: Arnd Bergmann --- drivers/video/fbdev/Kconfig | 14 - drivers/video/fbdev/Makefile | 1 - drivers/video/fbdev/nuc900fb.c | 760 --------------------------- drivers/video/fbdev/nuc900fb.h | 51 -- include/Kbuild | 1 - include/linux/platform_data/video-nuc900fb.h | 79 --- 6 files changed, 906 deletions(-) delete mode 100644 drivers/video/fbdev/nuc900fb.c delete mode 100644 drivers/video/fbdev/nuc900fb.h delete mode 100644 include/linux/platform_data/video-nuc900fb.h (limited to 'include/linux/platform_data') diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig index 6b2de93bd302..5f83cd715387 100644 --- a/drivers/video/fbdev/Kconfig +++ b/drivers/video/fbdev/Kconfig @@ -1924,20 +1924,6 @@ config FB_S3C2410_DEBUG Turn on debugging messages. Note that you can set/unset at run time through sysfs -config FB_NUC900 - tristate "NUC900 LCD framebuffer support" - depends on FB && ARCH_W90X900 - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - ---help--- - Frame buffer driver for the built-in LCD controller in the Nuvoton - NUC900 processor - -config GPM1040A0_320X240 - bool "Giantplus Technology GPM1040A0 320x240 Color TFT LCD" - depends on FB_NUC900 - config FB_SM501 tristate "Silicon Motion SM501 framebuffer support" depends on FB && MFD_SM501 diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile index 7dc4861a93e6..aab7155884ea 100644 --- a/drivers/video/fbdev/Makefile +++ b/drivers/video/fbdev/Makefile @@ -116,7 +116,6 @@ obj-y += omap2/ obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o obj-$(CONFIG_FB_CARMINE) += carminefb.o obj-$(CONFIG_FB_MB862XX) += mb862xx/ -obj-$(CONFIG_FB_NUC900) += nuc900fb.o obj-$(CONFIG_FB_JZ4740) += jz4740_fb.o obj-$(CONFIG_FB_PUV3_UNIGFX) += fb-puv3.o obj-$(CONFIG_FB_HYPERV) += hyperv_fb.o diff --git a/drivers/video/fbdev/nuc900fb.c b/drivers/video/fbdev/nuc900fb.c deleted file mode 100644 index 4fd851598584..000000000000 --- a/drivers/video/fbdev/nuc900fb.c +++ /dev/null @@ -1,760 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * - * Copyright (c) 2009 Nuvoton technology corporation - * All rights reserved. - * - * Description: - * Nuvoton LCD Controller Driver - * Author: - * Wang Qiang (rurality.linux@gmail.com) 2009/12/11 - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "nuc900fb.h" - - -/* - * Initialize the nuc900 video (dual) buffer address - */ -static void nuc900fb_set_lcdaddr(struct fb_info *info) -{ - struct nuc900fb_info *fbi = info->par; - void __iomem *regs = fbi->io; - unsigned long vbaddr1, vbaddr2; - - vbaddr1 = info->fix.smem_start; - vbaddr2 = info->fix.smem_start; - vbaddr2 += info->fix.line_length * info->var.yres; - - /* set frambuffer start phy addr*/ - writel(vbaddr1, regs + REG_LCM_VA_BADDR0); - writel(vbaddr2, regs + REG_LCM_VA_BADDR1); - - writel(fbi->regs.lcd_va_fbctrl, regs + REG_LCM_VA_FBCTRL); - writel(fbi->regs.lcd_va_scale, regs + REG_LCM_VA_SCALE); -} - -/* - * calculate divider for lcd div - */ -static unsigned int nuc900fb_calc_pixclk(struct nuc900fb_info *fbi, - unsigned long pixclk) -{ - unsigned long clk = fbi->clk_rate; - unsigned long long div; - - /* pixclk is in picseconds. our clock is in Hz*/ - /* div = (clk * pixclk)/10^12 */ - div = (unsigned long long)clk * pixclk; - div >>= 12; - do_div(div, 625 * 625UL * 625); - - dev_dbg(fbi->dev, "pixclk %ld, divisor is %lld\n", pixclk, div); - - return div; -} - -/* - * Check the video params of 'var'. - */ -static int nuc900fb_check_var(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct nuc900fb_info *fbi = info->par; - struct nuc900fb_mach_info *mach_info = dev_get_platdata(fbi->dev); - struct nuc900fb_display *display = NULL; - struct nuc900fb_display *default_display = mach_info->displays + - mach_info->default_display; - int i; - - dev_dbg(fbi->dev, "check_var(var=%p, info=%p)\n", var, info); - - /* validate x/y resolution */ - /* choose default mode if possible */ - if (var->xres == default_display->xres && - var->yres == default_display->yres && - var->bits_per_pixel == default_display->bpp) - display = default_display; - else - for (i = 0; i < mach_info->num_displays; i++) - if (var->xres == mach_info->displays[i].xres && - var->yres == mach_info->displays[i].yres && - var->bits_per_pixel == mach_info->displays[i].bpp) { - display = mach_info->displays + i; - break; - } - - if (display == NULL) { - printk(KERN_ERR "wrong resolution or depth %dx%d at %d bit per pixel\n", - var->xres, var->yres, var->bits_per_pixel); - return -EINVAL; - } - - /* it should be the same size as the display */ - var->xres_virtual = display->xres; - var->yres_virtual = display->yres; - var->height = display->height; - var->width = display->width; - - /* copy lcd settings */ - var->pixclock = display->pixclock; - var->left_margin = display->left_margin; - var->right_margin = display->right_margin; - var->upper_margin = display->upper_margin; - var->lower_margin = display->lower_margin; - var->vsync_len = display->vsync_len; - var->hsync_len = display->hsync_len; - - var->transp.offset = 0; - var->transp.length = 0; - - fbi->regs.lcd_dccs = display->dccs; - fbi->regs.lcd_device_ctrl = display->devctl; - fbi->regs.lcd_va_fbctrl = display->fbctrl; - fbi->regs.lcd_va_scale = display->scale; - - /* set R/G/B possions */ - switch (var->bits_per_pixel) { - case 1: - case 2: - case 4: - case 8: - default: - var->red.offset = 0; - var->red.length = var->bits_per_pixel; - var->green = var->red; - var->blue = var->red; - break; - case 12: - var->red.length = 4; - var->green.length = 4; - var->blue.length = 4; - var->red.offset = 8; - var->green.offset = 4; - var->blue.offset = 0; - break; - case 16: - var->red.length = 5; - var->green.length = 6; - var->blue.length = 5; - var->red.offset = 11; - var->green.offset = 5; - var->blue.offset = 0; - break; - case 18: - var->red.length = 6; - var->green.length = 6; - var->blue.length = 6; - var->red.offset = 12; - var->green.offset = 6; - var->blue.offset = 0; - break; - case 32: - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->red.offset = 16; - var->green.offset = 8; - var->blue.offset = 0; - break; - } - - return 0; -} - -/* - * Calculate lcd register values from var setting & save into hw - */ -static void nuc900fb_calculate_lcd_regs(const struct fb_info *info, - struct nuc900fb_hw *regs) -{ - const struct fb_var_screeninfo *var = &info->var; - int vtt = var->height + var->upper_margin + var->lower_margin; - int htt = var->width + var->left_margin + var->right_margin; - int hsync = var->width + var->right_margin; - int vsync = var->height + var->lower_margin; - - regs->lcd_crtc_size = LCM_CRTC_SIZE_VTTVAL(vtt) | - LCM_CRTC_SIZE_HTTVAL(htt); - regs->lcd_crtc_dend = LCM_CRTC_DEND_VDENDVAL(var->height) | - LCM_CRTC_DEND_HDENDVAL(var->width); - regs->lcd_crtc_hr = LCM_CRTC_HR_EVAL(var->width + 5) | - LCM_CRTC_HR_SVAL(var->width + 1); - regs->lcd_crtc_hsync = LCM_CRTC_HSYNC_EVAL(hsync + var->hsync_len) | - LCM_CRTC_HSYNC_SVAL(hsync); - regs->lcd_crtc_vr = LCM_CRTC_VR_EVAL(vsync + var->vsync_len) | - LCM_CRTC_VR_SVAL(vsync); - -} - -/* - * Activate (set) the controller from the given framebuffer - * information - */ -static void nuc900fb_activate_var(struct fb_info *info) -{ - struct nuc900fb_info *fbi = info->par; - void __iomem *regs = fbi->io; - struct fb_var_screeninfo *var = &info->var; - int clkdiv; - - clkdiv = nuc900fb_calc_pixclk(fbi, var->pixclock) - 1; - if (clkdiv < 0) - clkdiv = 0; - - nuc900fb_calculate_lcd_regs(info, &fbi->regs); - - /* set the new lcd registers*/ - - dev_dbg(fbi->dev, "new lcd register set:\n"); - dev_dbg(fbi->dev, "dccs = 0x%08x\n", fbi->regs.lcd_dccs); - dev_dbg(fbi->dev, "dev_ctl = 0x%08x\n", fbi->regs.lcd_device_ctrl); - dev_dbg(fbi->dev, "crtc_size = 0x%08x\n", fbi->regs.lcd_crtc_size); - dev_dbg(fbi->dev, "crtc_dend = 0x%08x\n", fbi->regs.lcd_crtc_dend); - dev_dbg(fbi->dev, "crtc_hr = 0x%08x\n", fbi->regs.lcd_crtc_hr); - dev_dbg(fbi->dev, "crtc_hsync = 0x%08x\n", fbi->regs.lcd_crtc_hsync); - dev_dbg(fbi->dev, "crtc_vr = 0x%08x\n", fbi->regs.lcd_crtc_vr); - - writel(fbi->regs.lcd_device_ctrl, regs + REG_LCM_DEV_CTRL); - writel(fbi->regs.lcd_crtc_size, regs + REG_LCM_CRTC_SIZE); - writel(fbi->regs.lcd_crtc_dend, regs + REG_LCM_CRTC_DEND); - writel(fbi->regs.lcd_crtc_hr, regs + REG_LCM_CRTC_HR); - writel(fbi->regs.lcd_crtc_hsync, regs + REG_LCM_CRTC_HSYNC); - writel(fbi->regs.lcd_crtc_vr, regs + REG_LCM_CRTC_VR); - - /* set lcd address pointers */ - nuc900fb_set_lcdaddr(info); - - writel(fbi->regs.lcd_dccs, regs + REG_LCM_DCCS); -} - -/* - * Alters the hardware state. - * - */ -static int nuc900fb_set_par(struct fb_info *info) -{ - struct fb_var_screeninfo *var = &info->var; - - switch (var->bits_per_pixel) { - case 32: - case 24: - case 18: - case 16: - case 12: - info->fix.visual = FB_VISUAL_TRUECOLOR; - break; - case 1: - info->fix.visual = FB_VISUAL_MONO01; - break; - default: - info->fix.visual = FB_VISUAL_PSEUDOCOLOR; - break; - } - - info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8; - - /* activate this new configuration */ - nuc900fb_activate_var(info); - return 0; -} - -static inline unsigned int chan_to_field(unsigned int chan, - struct fb_bitfield *bf) -{ - chan &= 0xffff; - chan >>= 16 - bf->length; - return chan << bf->offset; -} - -static int nuc900fb_setcolreg(unsigned regno, - unsigned red, unsigned green, unsigned blue, - unsigned transp, struct fb_info *info) -{ - unsigned int val; - - switch (info->fix.visual) { - case FB_VISUAL_TRUECOLOR: - /* true-colour, use pseuo-palette */ - if (regno < 16) { - u32 *pal = info->pseudo_palette; - - val = chan_to_field(red, &info->var.red); - val |= chan_to_field(green, &info->var.green); - val |= chan_to_field(blue, &info->var.blue); - pal[regno] = val; - } - break; - - default: - return 1; /* unknown type */ - } - return 0; -} - -/** - * nuc900fb_blank - * - */ -static int nuc900fb_blank(int blank_mode, struct fb_info *info) -{ - - return 0; -} - -static struct fb_ops nuc900fb_ops = { - .owner = THIS_MODULE, - .fb_check_var = nuc900fb_check_var, - .fb_set_par = nuc900fb_set_par, - .fb_blank = nuc900fb_blank, - .fb_setcolreg = nuc900fb_setcolreg, - .fb_fillrect = cfb_fillrect, - .fb_copyarea = cfb_copyarea, - .fb_imageblit = cfb_imageblit, -}; - - -static inline void modify_gpio(void __iomem *reg, - unsigned long set, unsigned long mask) -{ - unsigned long tmp; - tmp = readl(reg) & ~mask; - writel(tmp | set, reg); -} - -/* - * Initialise LCD-related registers - */ -static int nuc900fb_init_registers(struct fb_info *info) -{ - struct nuc900fb_info *fbi = info->par; - struct nuc900fb_mach_info *mach_info = dev_get_platdata(fbi->dev); - void __iomem *regs = fbi->io; - - /*reset the display engine*/ - writel(0, regs + REG_LCM_DCCS); - writel(readl(regs + REG_LCM_DCCS) | LCM_DCCS_ENG_RST, - regs + REG_LCM_DCCS); - ndelay(100); - writel(readl(regs + REG_LCM_DCCS) & (~LCM_DCCS_ENG_RST), - regs + REG_LCM_DCCS); - ndelay(100); - - writel(0, regs + REG_LCM_DEV_CTRL); - - /* config gpio output */ - modify_gpio(W90X900_VA_GPIO + 0x54, mach_info->gpio_dir, - mach_info->gpio_dir_mask); - modify_gpio(W90X900_VA_GPIO + 0x58, mach_info->gpio_data, - mach_info->gpio_data_mask); - - return 0; -} - - -/* - * Alloc the SDRAM region of NUC900 for the frame buffer. - * The buffer should be a non-cached, non-buffered, memory region - * to allow palette and pixel writes without flushing the cache. - */ -static int nuc900fb_map_video_memory(struct fb_info *info) -{ - struct nuc900fb_info *fbi = info->par; - dma_addr_t map_dma; - unsigned long map_size = PAGE_ALIGN(info->fix.smem_len); - - dev_dbg(fbi->dev, "nuc900fb_map_video_memory(fbi=%p) map_size %lu\n", - fbi, map_size); - - info->screen_base = dma_alloc_wc(fbi->dev, map_size, &map_dma, - GFP_KERNEL); - - if (!info->screen_base) - return -ENOMEM; - - memset(info->screen_base, 0x00, map_size); - info->fix.smem_start = map_dma; - - return 0; -} - -static inline void nuc900fb_unmap_video_memory(struct fb_info *info) -{ - struct nuc900fb_info *fbi = info->par; - dma_free_wc(fbi->dev, PAGE_ALIGN(info->fix.smem_len), - info->screen_base, info->fix.smem_start); -} - -static irqreturn_t nuc900fb_irqhandler(int irq, void *dev_id) -{ - struct nuc900fb_info *fbi = dev_id; - void __iomem *regs = fbi->io; - void __iomem *irq_base = fbi->irq_base; - unsigned long lcdirq = readl(regs + REG_LCM_INT_CS); - - if (lcdirq & LCM_INT_CS_DISP_F_STATUS) { - writel(readl(irq_base) | 1<<30, irq_base); - - /* wait VA_EN low */ - if ((readl(regs + REG_LCM_DCCS) & - LCM_DCCS_SINGLE) == LCM_DCCS_SINGLE) - while ((readl(regs + REG_LCM_DCCS) & - LCM_DCCS_VA_EN) == LCM_DCCS_VA_EN) - ; - /* display_out-enable */ - writel(readl(regs + REG_LCM_DCCS) | LCM_DCCS_DISP_OUT_EN, - regs + REG_LCM_DCCS); - /* va-enable*/ - writel(readl(regs + REG_LCM_DCCS) | LCM_DCCS_VA_EN, - regs + REG_LCM_DCCS); - } else if (lcdirq & LCM_INT_CS_UNDERRUN_INT) { - writel(readl(irq_base) | LCM_INT_CS_UNDERRUN_INT, irq_base); - } else if (lcdirq & LCM_INT_CS_BUS_ERROR_INT) { - writel(readl(irq_base) | LCM_INT_CS_BUS_ERROR_INT, irq_base); - } - - return IRQ_HANDLED; -} - -#ifdef CONFIG_CPU_FREQ - -static int nuc900fb_cpufreq_transition(struct notifier_block *nb, - unsigned long val, void *data) -{ - struct nuc900fb_info *info; - struct fb_info *fbinfo; - long delta_f; - info = container_of(nb, struct nuc900fb_info, freq_transition); - fbinfo = dev_get_drvdata(info->dev); - - delta_f = info->clk_rate - clk_get_rate(info->clk); - - if ((val == CPUFREQ_POSTCHANGE && delta_f > 0) || - (val == CPUFREQ_PRECHANGE && delta_f < 0)) { - info->clk_rate = clk_get_rate(info->clk); - nuc900fb_activate_var(fbinfo); - } - - return 0; -} - -static inline int nuc900fb_cpufreq_register(struct nuc900fb_info *fbi) -{ - fbi->freq_transition.notifier_call = nuc900fb_cpufreq_transition; - return cpufreq_register_notifier(&fbi->freq_transition, - CPUFREQ_TRANSITION_NOTIFIER); -} - -static inline void nuc900fb_cpufreq_deregister(struct nuc900fb_info *fbi) -{ - cpufreq_unregister_notifier(&fbi->freq_transition, - CPUFREQ_TRANSITION_NOTIFIER); -} -#else -static inline int nuc900fb_cpufreq_transition(struct notifier_block *nb, - unsigned long val, void *data) -{ - return 0; -} - -static inline int nuc900fb_cpufreq_register(struct nuc900fb_info *fbi) -{ - return 0; -} - -static inline void nuc900fb_cpufreq_deregister(struct nuc900fb_info *info) -{ -} -#endif - -static char driver_name[] = "nuc900fb"; - -static int nuc900fb_probe(struct platform_device *pdev) -{ - struct nuc900fb_info *fbi; - struct nuc900fb_display *display; - struct fb_info *fbinfo; - struct nuc900fb_mach_info *mach_info; - struct resource *res; - int ret; - int irq; - int i; - int size; - - dev_dbg(&pdev->dev, "devinit\n"); - mach_info = dev_get_platdata(&pdev->dev); - if (mach_info == NULL) { - dev_err(&pdev->dev, - "no platform data for lcd, cannot attach\n"); - return -EINVAL; - } - - if (mach_info->default_display > mach_info->num_displays) { - dev_err(&pdev->dev, - "default display No. is %d but only %d displays \n", - mach_info->default_display, mach_info->num_displays); - return -EINVAL; - } - - - display = mach_info->displays + mach_info->default_display; - - irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(&pdev->dev, "no irq for device\n"); - return -ENOENT; - } - - fbinfo = framebuffer_alloc(sizeof(struct nuc900fb_info), &pdev->dev); - if (!fbinfo) - return -ENOMEM; - - platform_set_drvdata(pdev, fbinfo); - - fbi = fbinfo->par; - fbi->dev = &pdev->dev; - -#ifdef CONFIG_CPU_NUC950 - fbi->drv_type = LCDDRV_NUC950; -#endif - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - size = resource_size(res); - fbi->mem = request_mem_region(res->start, size, pdev->name); - if (fbi->mem == NULL) { - dev_err(&pdev->dev, "failed to alloc memory region\n"); - ret = -ENOENT; - goto free_fb; - } - - fbi->io = ioremap(res->start, size); - if (fbi->io == NULL) { - dev_err(&pdev->dev, "ioremap() of lcd registers failed\n"); - ret = -ENXIO; - goto release_mem_region; - } - - fbi->irq_base = fbi->io + REG_LCM_INT_CS; - - - /* Stop the LCD */ - writel(0, fbi->io + REG_LCM_DCCS); - - /* fill the fbinfo*/ - strcpy(fbinfo->fix.id, driver_name); - fbinfo->fix.type = FB_TYPE_PACKED_PIXELS; - fbinfo->fix.type_aux = 0; - fbinfo->fix.xpanstep = 0; - fbinfo->fix.ypanstep = 0; - fbinfo->fix.ywrapstep = 0; - fbinfo->fix.accel = FB_ACCEL_NONE; - fbinfo->var.nonstd = 0; - fbinfo->var.activate = FB_ACTIVATE_NOW; - fbinfo->var.accel_flags = 0; - fbinfo->var.vmode = FB_VMODE_NONINTERLACED; - fbinfo->fbops = &nuc900fb_ops; - fbinfo->flags = FBINFO_FLAG_DEFAULT; - fbinfo->pseudo_palette = &fbi->pseudo_pal; - - ret = request_irq(irq, nuc900fb_irqhandler, 0, pdev->name, fbi); - if (ret) { - dev_err(&pdev->dev, "cannot register irq handler %d -err %d\n", - irq, ret); - ret = -EBUSY; - goto release_regs; - } - - fbi->clk = clk_get(&pdev->dev, NULL); - if (IS_ERR(fbi->clk)) { - printk(KERN_ERR "nuc900-lcd:failed to get lcd clock source\n"); - ret = PTR_ERR(fbi->clk); - goto release_irq; - } - - clk_enable(fbi->clk); - dev_dbg(&pdev->dev, "got and enabled clock\n"); - - fbi->clk_rate = clk_get_rate(fbi->clk); - - /* calutate the video buffer size */ - for (i = 0; i < mach_info->num_displays; i++) { - unsigned long smem_len = mach_info->displays[i].xres; - smem_len *= mach_info->displays[i].yres; - smem_len *= mach_info->displays[i].bpp; - smem_len >>= 3; - if (fbinfo->fix.smem_len < smem_len) - fbinfo->fix.smem_len = smem_len; - } - - /* Initialize Video Memory */ - ret = nuc900fb_map_video_memory(fbinfo); - if (ret) { - printk(KERN_ERR "Failed to allocate video RAM: %x\n", ret); - goto release_clock; - } - - dev_dbg(&pdev->dev, "got video memory\n"); - - fbinfo->var.xres = display->xres; - fbinfo->var.yres = display->yres; - fbinfo->var.bits_per_pixel = display->bpp; - - nuc900fb_init_registers(fbinfo); - - nuc900fb_check_var(&fbinfo->var, fbinfo); - - ret = nuc900fb_cpufreq_register(fbi); - if (ret < 0) { - dev_err(&pdev->dev, "Failed to register cpufreq\n"); - goto free_video_memory; - } - - ret = register_framebuffer(fbinfo); - if (ret) { - printk(KERN_ERR "failed to register framebuffer device: %d\n", - ret); - goto free_cpufreq; - } - - fb_info(fbinfo, "%s frame buffer device\n", fbinfo->fix.id); - - return 0; - -free_cpufreq: - nuc900fb_cpufreq_deregister(fbi); -free_video_memory: - nuc900fb_unmap_video_memory(fbinfo); -release_clock: - clk_disable(fbi->clk); - clk_put(fbi->clk); -release_irq: - free_irq(irq, fbi); -release_regs: - iounmap(fbi->io); -release_mem_region: - release_mem_region(res->start, size); -free_fb: - framebuffer_release(fbinfo); - return ret; -} - -/* - * shutdown the lcd controller - */ -static void nuc900fb_stop_lcd(struct fb_info *info) -{ - struct nuc900fb_info *fbi = info->par; - void __iomem *regs = fbi->io; - - writel((~LCM_DCCS_DISP_INT_EN) | (~LCM_DCCS_VA_EN) | (~LCM_DCCS_OSD_EN), - regs + REG_LCM_DCCS); -} - -/* - * Cleanup - */ -static int nuc900fb_remove(struct platform_device *pdev) -{ - struct fb_info *fbinfo = platform_get_drvdata(pdev); - struct nuc900fb_info *fbi = fbinfo->par; - int irq; - - nuc900fb_stop_lcd(fbinfo); - msleep(1); - - unregister_framebuffer(fbinfo); - nuc900fb_cpufreq_deregister(fbi); - nuc900fb_unmap_video_memory(fbinfo); - - iounmap(fbi->io); - - irq = platform_get_irq(pdev, 0); - free_irq(irq, fbi); - - release_resource(fbi->mem); - kfree(fbi->mem); - - framebuffer_release(fbinfo); - - return 0; -} - -#ifdef CONFIG_PM - -/* - * suspend and resume support for the lcd controller - */ - -static int nuc900fb_suspend(struct platform_device *dev, pm_message_t state) -{ - struct fb_info *fbinfo = platform_get_drvdata(dev); - struct nuc900fb_info *info = fbinfo->par; - - nuc900fb_stop_lcd(fbinfo); - msleep(1); - clk_disable(info->clk); - return 0; -} - -static int nuc900fb_resume(struct platform_device *dev) -{ - struct fb_info *fbinfo = platform_get_drvdata(dev); - struct nuc900fb_info *fbi = fbinfo->par; - - printk(KERN_INFO "nuc900fb resume\n"); - - clk_enable(fbi->clk); - msleep(1); - - nuc900fb_init_registers(fbinfo); - nuc900fb_activate_var(fbinfo); - - return 0; -} - -#else -#define nuc900fb_suspend NULL -#define nuc900fb_resume NULL -#endif - -static struct platform_driver nuc900fb_driver = { - .probe = nuc900fb_probe, - .remove = nuc900fb_remove, - .suspend = nuc900fb_suspend, - .resume = nuc900fb_resume, - .driver = { - .name = "nuc900-lcd", - }, -}; - -module_platform_driver(nuc900fb_driver); - -MODULE_DESCRIPTION("Framebuffer driver for the NUC900"); -MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/nuc900fb.h b/drivers/video/fbdev/nuc900fb.h deleted file mode 100644 index 055ae9297931..000000000000 --- a/drivers/video/fbdev/nuc900fb.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * - * Copyright (c) 2009 Nuvoton technology corporation - * All rights reserved. - * - * Author: - * Wang Qiang(rurality.linux@gmail.com) 2009/12/16 - */ - -#ifndef __NUC900FB_H -#define __NUC900FB_H - -#include -#include - -enum nuc900_lcddrv_type { - LCDDRV_NUC910, - LCDDRV_NUC930, - LCDDRV_NUC932, - LCDDRV_NUC950, - LCDDRV_NUC960, -}; - - -#define PALETTE_BUFFER_SIZE 256 -#define PALETTE_BUFF_CLEAR (0x80000000) /* entry is clear/invalid */ - -struct nuc900fb_info { - struct device *dev; - struct clk *clk; - - struct resource *mem; - void __iomem *io; - void __iomem *irq_base; - int drv_type; - struct nuc900fb_hw regs; - unsigned long clk_rate; - -#ifdef CONFIG_CPU_FREQ - struct notifier_block freq_transition; -#endif - - /* keep these registers in case we need to re-write palette */ - u32 palette_buffer[PALETTE_BUFFER_SIZE]; - u32 pseudo_pal[16]; -}; - -int nuc900fb_init(void); - -#endif /* __NUC900FB_H */ diff --git a/include/Kbuild b/include/Kbuild index 5e0642d79dce..4d5a03a81fb5 100644 --- a/include/Kbuild +++ b/include/Kbuild @@ -568,7 +568,6 @@ header-test- += linux/platform_data/usb3503.h header-test- += linux/platform_data/ux500_wdt.h header-test- += linux/platform_data/video-clcd-versatile.h header-test- += linux/platform_data/video-imxfb.h -header-test- += linux/platform_data/video-nuc900fb.h header-test- += linux/platform_data/video-pxafb.h header-test- += linux/platform_data/video_s3c.h header-test- += linux/platform_data/voltage-omap.h diff --git a/include/linux/platform_data/video-nuc900fb.h b/include/linux/platform_data/video-nuc900fb.h deleted file mode 100644 index 3da504460c91..000000000000 --- a/include/linux/platform_data/video-nuc900fb.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* linux/include/asm/arch-nuc900/fb.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Changelog: - * - * 2008/08/26 vincen.zswan modify this file for LCD. - */ - -#ifndef __ASM_ARM_FB_H -#define __ASM_ARM_FB_H - - - -/* LCD Controller Hardware Desc */ -struct nuc900fb_hw { - unsigned int lcd_dccs; - unsigned int lcd_device_ctrl; - unsigned int lcd_mpulcd_cmd; - unsigned int lcd_int_cs; - unsigned int lcd_crtc_size; - unsigned int lcd_crtc_dend; - unsigned int lcd_crtc_hr; - unsigned int lcd_crtc_hsync; - unsigned int lcd_crtc_vr; - unsigned int lcd_va_baddr0; - unsigned int lcd_va_baddr1; - unsigned int lcd_va_fbctrl; - unsigned int lcd_va_scale; - unsigned int lcd_va_test; - unsigned int lcd_va_win; - unsigned int lcd_va_stuff; -}; - -/* LCD Display Description */ -struct nuc900fb_display { - /* LCD Image type */ - unsigned type; - - /* LCD Screen Size */ - unsigned short width; - unsigned short height; - - /* LCD Screen Info */ - unsigned short xres; - unsigned short yres; - unsigned short bpp; - - unsigned long pixclock; - unsigned short left_margin; - unsigned short right_margin; - unsigned short hsync_len; - unsigned short upper_margin; - unsigned short lower_margin; - unsigned short vsync_len; - - /* hardware special register value */ - unsigned int dccs; - unsigned int devctl; - unsigned int fbctrl; - unsigned int scale; -}; - -struct nuc900fb_mach_info { - struct nuc900fb_display *displays; - unsigned num_displays; - unsigned default_display; - /* GPIO Setting Info */ - unsigned gpio_dir; - unsigned gpio_dir_mask; - unsigned gpio_data; - unsigned gpio_data_mask; -}; - -extern void __init nuc900_fb_set_platdata(struct nuc900fb_mach_info *); - -#endif /* __ASM_ARM_FB_H */ -- cgit v1.2.3-71-gd317 From 7c28503db19cfa28e394a394aca61c79fbf3f969 Mon Sep 17 00:00:00 2001 From: Kristian Klausen Date: Mon, 9 Sep 2019 19:31:26 +0200 Subject: platform/x86: asus-wmi: Reorder ASUS_WMI_CHARGE_THRESHOLD At the same time add a comment explaining what it is used for. Signed-off-by: Kristian Klausen Signed-off-by: Andy Shevchenko --- include/linux/platform_data/x86/asus-wmi.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include/linux/platform_data') diff --git a/include/linux/platform_data/x86/asus-wmi.h b/include/linux/platform_data/x86/asus-wmi.h index 53934ef38d98..21f0426c8272 100644 --- a/include/linux/platform_data/x86/asus-wmi.h +++ b/include/linux/platform_data/x86/asus-wmi.h @@ -61,7 +61,6 @@ /* Misc */ #define ASUS_WMI_DEVID_CAMERA 0x00060013 -#define ASUS_WMI_CHARGE_THRESHOLD 0x00120057 /* Storage */ #define ASUS_WMI_DEVID_CARDREADER 0x00080013 @@ -82,6 +81,9 @@ /* Deep S3 / Resume on LID open */ #define ASUS_WMI_DEVID_LID_RESUME 0x00120031 +/* Maximum charging percentage */ +#define ASUS_WMI_CHARGE_THRESHOLD 0x00120057 + /* DSTS masks */ #define ASUS_WMI_DSTS_STATUS_BIT 0x00000001 #define ASUS_WMI_DSTS_UNKNOWN_BIT 0x00000002 -- cgit v1.2.3-71-gd317 From 0c37f44845557b5e5b91ab320f256a4fd5059648 Mon Sep 17 00:00:00 2001 From: Kristian Klausen Date: Mon, 9 Sep 2019 19:31:27 +0200 Subject: platform/x86: asus-wmi: Rename CHARGE_THRESHOLD to RSOC The device is officially called "Relative state of charge" (RSOC). At the same time add the missing DEVID from the name. Signed-off-by: Kristian Klausen Signed-off-by: Andy Shevchenko --- drivers/platform/x86/asus-wmi.c | 6 +++--- include/linux/platform_data/x86/asus-wmi.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include/linux/platform_data') diff --git a/drivers/platform/x86/asus-wmi.c b/drivers/platform/x86/asus-wmi.c index 848b23764fc3..92c149dc2e6e 100644 --- a/drivers/platform/x86/asus-wmi.c +++ b/drivers/platform/x86/asus-wmi.c @@ -2067,7 +2067,7 @@ static ssize_t charge_threshold_store(struct device *dev, if (value < 0 || value > 100) return -EINVAL; - ret = asus_wmi_set_devstate(ASUS_WMI_CHARGE_THRESHOLD, value, &rv); + ret = asus_wmi_set_devstate(ASUS_WMI_DEVID_RSOC, value, &rv); if (ret) return ret; @@ -2124,7 +2124,7 @@ static umode_t asus_sysfs_is_visible(struct kobject *kobj, else if (attr == &dev_attr_fan_boost_mode.attr) ok = asus->fan_boost_mode_available; else if (attr == &dev_attr_charge_threshold.attr) - devid = ASUS_WMI_CHARGE_THRESHOLD; + devid = ASUS_WMI_DEVID_RSOC; if (devid != -1) ok = !(asus_wmi_get_devstate_simple(asus, devid) < 0); @@ -2455,7 +2455,7 @@ static int asus_wmi_add(struct platform_device *pdev) * and we can't get the current threshold so let set it to 100% on * module load. */ - asus_wmi_set_devstate(ASUS_WMI_CHARGE_THRESHOLD, 100, NULL); + asus_wmi_set_devstate(ASUS_WMI_DEVID_RSOC, 100, NULL); asus->charge_threshold = 100; return 0; diff --git a/include/linux/platform_data/x86/asus-wmi.h b/include/linux/platform_data/x86/asus-wmi.h index 21f0426c8272..60249e22e844 100644 --- a/include/linux/platform_data/x86/asus-wmi.h +++ b/include/linux/platform_data/x86/asus-wmi.h @@ -82,7 +82,7 @@ #define ASUS_WMI_DEVID_LID_RESUME 0x00120031 /* Maximum charging percentage */ -#define ASUS_WMI_CHARGE_THRESHOLD 0x00120057 +#define ASUS_WMI_DEVID_RSOC 0x00120057 /* DSTS masks */ #define ASUS_WMI_DSTS_STATUS_BIT 0x00000001 -- cgit v1.2.3-71-gd317 From c34a024e4ee087b6d9e534160990082c3d9e7103 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 10 Sep 2019 16:15:29 +0200 Subject: gpio: htc-egpio: Remove unused exported htc_egpio_get_wakeup_irq() This function was never used upstream, and is a relic of the original handhelds.org code the htc-egpio driver was based on. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20190910141529.21030-1-geert+renesas@glider.be Signed-off-by: Linus Walleij --- drivers/gpio/gpio-htc-egpio.c | 14 -------------- include/linux/platform_data/gpio-htc-egpio.h | 3 --- 2 files changed, 17 deletions(-) (limited to 'include/linux/platform_data') diff --git a/drivers/gpio/gpio-htc-egpio.c b/drivers/gpio/gpio-htc-egpio.c index 9d3ac51a765c..6eb56f7ab9c9 100644 --- a/drivers/gpio/gpio-htc-egpio.c +++ b/drivers/gpio/gpio-htc-egpio.c @@ -118,20 +118,6 @@ static void egpio_handler(struct irq_desc *desc) } } -int htc_egpio_get_wakeup_irq(struct device *dev) -{ - struct egpio_info *ei = dev_get_drvdata(dev); - - /* Read current pins. */ - u16 readval = egpio_readw(ei, ei->ack_register); - /* Ack/unmask interrupts. */ - ack_irqs(ei); - /* Return first set pin. */ - readval &= ei->irqs_enabled; - return ei->irq_start + ffs(readval) - 1; -} -EXPORT_SYMBOL(htc_egpio_get_wakeup_irq); - static inline int egpio_pos(struct egpio_info *ei, int bit) { return bit >> ei->reg_shift; diff --git a/include/linux/platform_data/gpio-htc-egpio.h b/include/linux/platform_data/gpio-htc-egpio.h index 9a3e78082883..eaefba0b6465 100644 --- a/include/linux/platform_data/gpio-htc-egpio.h +++ b/include/linux/platform_data/gpio-htc-egpio.h @@ -50,7 +50,4 @@ struct htc_egpio_platform_data { int num_chips; }; -/* Determine the wakeup irq, to be called during early resume */ -extern int htc_egpio_get_wakeup_irq(struct device *dev); - #endif -- cgit v1.2.3-71-gd317 From 96a0a80738461d6d2421ae64ee9990b702efd2a6 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Mon, 2 Sep 2019 18:08:48 +0200 Subject: platform/chrome: cros_ec_chardev: Add a poll handler to receive MKBP events Allow to poll on the cros_ec device to receive the MKBP events. The /dev/cros_[ec|fp|..] file operations now implements the poll operation. The userspace can now receive specific MKBP events by doing the following: - Open the /dev/cros_XX file. - Call the CROS_EC_DEV_IOCEVENTMASK ioctl with the bitmap of the MKBP events it wishes to receive as argument. - Poll on the file descriptor. - When it gets POLLIN, do a read on the file descriptor, the first queued event will be returned (using the struct ec_response_get_next_event format: one byte of event type, then the payload). The read() operation returns at most one event even if there are several queued, and it might be truncated if the buffer is smaller than the event (but the caller should know the maximum size of the events it is reading). read() used to return the EC version string, it still does it when no event mask or an empty event is set for backward compatibility (despite nobody really using this feature). This will be used, for example, by the userspace daemon to receive and treat the EC_MKBP_EVENT_FINGERPRINT sent by the FP MCU. Signed-off-by: Vincent Palatin Signed-off-by: Enric Balletbo i Serra Acked-by: Andy Shevchenko Reviewed-by: Gwendal Grignou --- drivers/platform/chrome/cros_ec_chardev.c | 177 +++++++++++++++++++++++++- include/linux/platform_data/cros_ec_chardev.h | 1 + 2 files changed, 173 insertions(+), 5 deletions(-) (limited to 'include/linux/platform_data') diff --git a/drivers/platform/chrome/cros_ec_chardev.c b/drivers/platform/chrome/cros_ec_chardev.c index 08abd7e5c7bf..74ded441bb50 100644 --- a/drivers/platform/chrome/cros_ec_chardev.c +++ b/drivers/platform/chrome/cros_ec_chardev.c @@ -16,21 +16,42 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include #define DRV_NAME "cros-ec-chardev" +/* Arbitrary bounded size for the event queue */ +#define CROS_MAX_EVENT_LEN PAGE_SIZE + struct chardev_data { struct cros_ec_dev *ec_dev; struct miscdevice misc; }; +struct chardev_priv { + struct cros_ec_dev *ec_dev; + struct notifier_block notifier; + wait_queue_head_t wait_event; + unsigned long event_mask; + struct list_head events; + size_t event_len; +}; + +struct ec_event { + struct list_head node; + size_t size; + u8 event_type; + u8 data[0]; +}; + static int ec_get_version(struct cros_ec_dev *ec, char *str, int maxlen) { static const char * const current_image_name[] = { @@ -69,6 +90,71 @@ exit: return ret; } +static int cros_ec_chardev_mkbp_event(struct notifier_block *nb, + unsigned long queued_during_suspend, + void *_notify) +{ + struct chardev_priv *priv = container_of(nb, struct chardev_priv, + notifier); + struct cros_ec_device *ec_dev = priv->ec_dev->ec_dev; + struct ec_event *event; + unsigned long event_bit = 1 << ec_dev->event_data.event_type; + int total_size = sizeof(*event) + ec_dev->event_size; + + if (!(event_bit & priv->event_mask) || + (priv->event_len + total_size) > CROS_MAX_EVENT_LEN) + return NOTIFY_DONE; + + event = kzalloc(total_size, GFP_KERNEL); + if (!event) + return NOTIFY_DONE; + + event->size = ec_dev->event_size; + event->event_type = ec_dev->event_data.event_type; + memcpy(event->data, &ec_dev->event_data.data, ec_dev->event_size); + + spin_lock(&priv->wait_event.lock); + list_add_tail(&event->node, &priv->events); + priv->event_len += total_size; + wake_up_locked(&priv->wait_event); + spin_unlock(&priv->wait_event.lock); + + return NOTIFY_OK; +} + +static struct ec_event *cros_ec_chardev_fetch_event(struct chardev_priv *priv, + bool fetch, bool block) +{ + struct ec_event *event; + int err; + + spin_lock(&priv->wait_event.lock); + if (!block && list_empty(&priv->events)) { + event = ERR_PTR(-EWOULDBLOCK); + goto out; + } + + if (!fetch) { + event = NULL; + goto out; + } + + err = wait_event_interruptible_locked(priv->wait_event, + !list_empty(&priv->events)); + if (err) { + event = ERR_PTR(err); + goto out; + } + + event = list_first_entry(&priv->events, struct ec_event, node); + list_del(&event->node); + priv->event_len -= sizeof(*event) + event->size; + +out: + spin_unlock(&priv->wait_event.lock); + return event; +} + /* * Device file ops */ @@ -76,11 +162,40 @@ static int cros_ec_chardev_open(struct inode *inode, struct file *filp) { struct miscdevice *mdev = filp->private_data; struct cros_ec_dev *ec_dev = dev_get_drvdata(mdev->parent); + struct chardev_priv *priv; + int ret; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; - filp->private_data = ec_dev; + priv->ec_dev = ec_dev; + filp->private_data = priv; + INIT_LIST_HEAD(&priv->events); + init_waitqueue_head(&priv->wait_event); nonseekable_open(inode, filp); - return 0; + priv->notifier.notifier_call = cros_ec_chardev_mkbp_event; + ret = blocking_notifier_chain_register(&ec_dev->ec_dev->event_notifier, + &priv->notifier); + if (ret) { + dev_err(ec_dev->dev, "failed to register event notifier\n"); + kfree(priv); + } + + return ret; +} + +static __poll_t cros_ec_chardev_poll(struct file *filp, poll_table *wait) +{ + struct chardev_priv *priv = filp->private_data; + + poll_wait(filp, &priv->wait_event, wait); + + if (list_empty(&priv->events)) + return 0; + + return EPOLLIN | EPOLLRDNORM; } static ssize_t cros_ec_chardev_read(struct file *filp, char __user *buffer, @@ -88,14 +203,42 @@ static ssize_t cros_ec_chardev_read(struct file *filp, char __user *buffer, { char msg[sizeof(struct ec_response_get_version) + sizeof(CROS_EC_DEV_VERSION)]; - struct cros_ec_dev *ec = filp->private_data; + struct chardev_priv *priv = filp->private_data; + struct cros_ec_dev *ec_dev = priv->ec_dev; size_t count; int ret; + if (priv->event_mask) { /* queued MKBP event */ + struct ec_event *event; + + event = cros_ec_chardev_fetch_event(priv, length != 0, + !(filp->f_flags & O_NONBLOCK)); + if (IS_ERR(event)) + return PTR_ERR(event); + /* + * length == 0 is special - no IO is done but we check + * for error conditions. + */ + if (length == 0) + return 0; + + /* The event is 1 byte of type plus the payload */ + count = min(length, event->size + 1); + ret = copy_to_user(buffer, &event->event_type, count); + kfree(event); + if (ret) /* the copy failed */ + return -EFAULT; + *offset = count; + return count; + } + + /* + * Legacy behavior if no event mask is defined + */ if (*offset != 0) return 0; - ret = ec_get_version(ec, msg, sizeof(msg)); + ret = ec_get_version(ec_dev, msg, sizeof(msg)); if (ret) return ret; @@ -108,6 +251,24 @@ static ssize_t cros_ec_chardev_read(struct file *filp, char __user *buffer, return count; } +static int cros_ec_chardev_release(struct inode *inode, struct file *filp) +{ + struct chardev_priv *priv = filp->private_data; + struct cros_ec_dev *ec_dev = priv->ec_dev; + struct ec_event *event, *e; + + blocking_notifier_chain_unregister(&ec_dev->ec_dev->event_notifier, + &priv->notifier); + + list_for_each_entry_safe(event, e, &priv->events, node) { + list_del(&event->node); + kfree(event); + } + kfree(priv); + + return 0; +} + /* * Ioctls */ @@ -181,7 +342,8 @@ static long cros_ec_chardev_ioctl_readmem(struct cros_ec_dev *ec, static long cros_ec_chardev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { - struct cros_ec_dev *ec = filp->private_data; + struct chardev_priv *priv = filp->private_data; + struct cros_ec_dev *ec = priv->ec_dev; if (_IOC_TYPE(cmd) != CROS_EC_DEV_IOC) return -ENOTTY; @@ -191,6 +353,9 @@ static long cros_ec_chardev_ioctl(struct file *filp, unsigned int cmd, return cros_ec_chardev_ioctl_xcmd(ec, (void __user *)arg); case CROS_EC_DEV_IOCRDMEM: return cros_ec_chardev_ioctl_readmem(ec, (void __user *)arg); + case CROS_EC_DEV_IOCEVENTMASK: + priv->event_mask = arg; + return 0; } return -ENOTTY; @@ -198,7 +363,9 @@ static long cros_ec_chardev_ioctl(struct file *filp, unsigned int cmd, static const struct file_operations chardev_fops = { .open = cros_ec_chardev_open, + .poll = cros_ec_chardev_poll, .read = cros_ec_chardev_read, + .release = cros_ec_chardev_release, .unlocked_ioctl = cros_ec_chardev_ioctl, #ifdef CONFIG_COMPAT .compat_ioctl = cros_ec_chardev_ioctl, diff --git a/include/linux/platform_data/cros_ec_chardev.h b/include/linux/platform_data/cros_ec_chardev.h index 973b2615aa02..7de8faaf77df 100644 --- a/include/linux/platform_data/cros_ec_chardev.h +++ b/include/linux/platform_data/cros_ec_chardev.h @@ -33,5 +33,6 @@ struct cros_ec_readmem { #define CROS_EC_DEV_IOC 0xEC #define CROS_EC_DEV_IOCXCMD _IOWR(CROS_EC_DEV_IOC, 0, struct cros_ec_command) #define CROS_EC_DEV_IOCRDMEM _IOWR(CROS_EC_DEV_IOC, 1, struct cros_ec_readmem) +#define CROS_EC_DEV_IOCEVENTMASK _IO(CROS_EC_DEV_IOC, 2) #endif /* _CROS_EC_DEV_H_ */ -- cgit v1.2.3-71-gd317 From b0e1ee435aba68c4080e3cb67adf6573aa5bcc6d Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 18 Sep 2019 22:21:24 +0200 Subject: net: remove netx ethernet driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ARM netx platform got removed in 5.3, so this driver is now useless. Reported-by: Uwe Kleine-König Cc: Sascha Hauer Signed-off-by: Arnd Bergmann Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/Kconfig | 11 - drivers/net/ethernet/Makefile | 1 - drivers/net/ethernet/netx-eth.c | 497 --------------------------------- include/linux/platform_data/eth-netx.h | 13 - 4 files changed, 522 deletions(-) delete mode 100644 drivers/net/ethernet/netx-eth.c delete mode 100644 include/linux/platform_data/eth-netx.h (limited to 'include/linux/platform_data') diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig index 1e2de9d062bf..e8e9c166185d 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig @@ -140,17 +140,6 @@ source "drivers/net/ethernet/neterion/Kconfig" source "drivers/net/ethernet/netronome/Kconfig" source "drivers/net/ethernet/ni/Kconfig" source "drivers/net/ethernet/8390/Kconfig" - -config NET_NETX - tristate "NetX Ethernet support" - select MII - depends on ARCH_NETX - ---help--- - This is support for the Hilscher netX builtin Ethernet ports - - To compile this driver as a module, choose M here. The module - will be called netx-eth. - source "drivers/net/ethernet/nvidia/Kconfig" source "drivers/net/ethernet/nxp/Kconfig" source "drivers/net/ethernet/oki-semi/Kconfig" diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile index 77f9838a76c9..05abebc17804 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile @@ -64,7 +64,6 @@ obj-$(CONFIG_NET_VENDOR_NATSEMI) += natsemi/ obj-$(CONFIG_NET_VENDOR_NETERION) += neterion/ obj-$(CONFIG_NET_VENDOR_NETRONOME) += netronome/ obj-$(CONFIG_NET_VENDOR_NI) += ni/ -obj-$(CONFIG_NET_NETX) += netx-eth.o obj-$(CONFIG_NET_VENDOR_NVIDIA) += nvidia/ obj-$(CONFIG_LPC_ENET) += nxp/ obj-$(CONFIG_NET_VENDOR_OKI) += oki-semi/ diff --git a/drivers/net/ethernet/netx-eth.c b/drivers/net/ethernet/netx-eth.c deleted file mode 100644 index cf6e7eb1b1e1..000000000000 --- a/drivers/net/ethernet/netx-eth.c +++ /dev/null @@ -1,497 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * drivers/net/ethernet/netx-eth.c - * - * Copyright (c) 2005 Sascha Hauer , Pengutronix - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -/* XC Fifo Offsets */ -#define EMPTY_PTR_FIFO(xcno) (0 + ((xcno) << 3)) /* Index of the empty pointer FIFO */ -#define IND_FIFO_PORT_HI(xcno) (1 + ((xcno) << 3)) /* Index of the FIFO where received */ - /* Data packages are indicated by XC */ -#define IND_FIFO_PORT_LO(xcno) (2 + ((xcno) << 3)) /* Index of the FIFO where received */ - /* Data packages are indicated by XC */ -#define REQ_FIFO_PORT_HI(xcno) (3 + ((xcno) << 3)) /* Index of the FIFO where Data packages */ - /* have to be indicated by ARM which */ - /* shall be sent */ -#define REQ_FIFO_PORT_LO(xcno) (4 + ((xcno) << 3)) /* Index of the FIFO where Data packages */ - /* have to be indicated by ARM which shall */ - /* be sent */ -#define CON_FIFO_PORT_HI(xcno) (5 + ((xcno) << 3)) /* Index of the FIFO where sent Data packages */ - /* are confirmed */ -#define CON_FIFO_PORT_LO(xcno) (6 + ((xcno) << 3)) /* Index of the FIFO where sent Data */ - /* packages are confirmed */ -#define PFIFO_MASK(xcno) (0x7f << (xcno*8)) - -#define FIFO_PTR_FRAMELEN_SHIFT 0 -#define FIFO_PTR_FRAMELEN_MASK (0x7ff << 0) -#define FIFO_PTR_FRAMELEN(len) (((len) << 0) & FIFO_PTR_FRAMELEN_MASK) -#define FIFO_PTR_TIMETRIG (1<<11) -#define FIFO_PTR_MULTI_REQ -#define FIFO_PTR_ORIGIN (1<<14) -#define FIFO_PTR_VLAN (1<<15) -#define FIFO_PTR_FRAMENO_SHIFT 16 -#define FIFO_PTR_FRAMENO_MASK (0x3f << 16) -#define FIFO_PTR_FRAMENO(no) (((no) << 16) & FIFO_PTR_FRAMENO_MASK) -#define FIFO_PTR_SEGMENT_SHIFT 22 -#define FIFO_PTR_SEGMENT_MASK (0xf << 22) -#define FIFO_PTR_SEGMENT(seg) (((seg) & 0xf) << 22) -#define FIFO_PTR_ERROR_SHIFT 28 -#define FIFO_PTR_ERROR_MASK (0xf << 28) - -#define ISR_LINK_STATUS_CHANGE (1<<4) -#define ISR_IND_LO (1<<3) -#define ISR_CON_LO (1<<2) -#define ISR_IND_HI (1<<1) -#define ISR_CON_HI (1<<0) - -#define ETH_MAC_LOCAL_CONFIG 0x1560 -#define ETH_MAC_4321 0x1564 -#define ETH_MAC_65 0x1568 - -#define MAC_TRAFFIC_CLASS_ARRANGEMENT_SHIFT 16 -#define MAC_TRAFFIC_CLASS_ARRANGEMENT_MASK (0xf<data; - unsigned int len = skb->len; - - spin_lock_irq(&priv->lock); - memcpy_toio(priv->sram_base + 1560, (void *)buf, len); - if (len < 60) { - memset_io(priv->sram_base + 1560 + len, 0, 60 - len); - len = 60; - } - - pfifo_push(REQ_FIFO_PORT_LO(priv->id), - FIFO_PTR_SEGMENT(priv->id) | - FIFO_PTR_FRAMENO(1) | - FIFO_PTR_FRAMELEN(len)); - - ndev->stats.tx_packets++; - ndev->stats.tx_bytes += skb->len; - - netif_stop_queue(ndev); - spin_unlock_irq(&priv->lock); - dev_kfree_skb(skb); - - return NETDEV_TX_OK; -} - -static void netx_eth_receive(struct net_device *ndev) -{ - struct netx_eth_priv *priv = netdev_priv(ndev); - unsigned int val, frameno, seg, len; - unsigned char *data; - struct sk_buff *skb; - - val = pfifo_pop(IND_FIFO_PORT_LO(priv->id)); - - frameno = (val & FIFO_PTR_FRAMENO_MASK) >> FIFO_PTR_FRAMENO_SHIFT; - seg = (val & FIFO_PTR_SEGMENT_MASK) >> FIFO_PTR_SEGMENT_SHIFT; - len = (val & FIFO_PTR_FRAMELEN_MASK) >> FIFO_PTR_FRAMELEN_SHIFT; - - skb = netdev_alloc_skb(ndev, len); - if (unlikely(skb == NULL)) { - ndev->stats.rx_dropped++; - return; - } - - data = skb_put(skb, len); - - memcpy_fromio(data, priv->sram_base + frameno * 1560, len); - - pfifo_push(EMPTY_PTR_FIFO(priv->id), - FIFO_PTR_SEGMENT(seg) | FIFO_PTR_FRAMENO(frameno)); - - skb->protocol = eth_type_trans(skb, ndev); - netif_rx(skb); - ndev->stats.rx_packets++; - ndev->stats.rx_bytes += len; -} - -static irqreturn_t -netx_eth_interrupt(int irq, void *dev_id) -{ - struct net_device *ndev = dev_id; - struct netx_eth_priv *priv = netdev_priv(ndev); - int status; - unsigned long flags; - - spin_lock_irqsave(&priv->lock, flags); - - status = readl(NETX_PFIFO_XPEC_ISR(priv->id)); - while (status) { - int fill_level; - writel(status, NETX_PFIFO_XPEC_ISR(priv->id)); - - if ((status & ISR_CON_HI) || (status & ISR_IND_HI)) - printk("%s: unexpected status: 0x%08x\n", - __func__, status); - - fill_level = - readl(NETX_PFIFO_FILL_LEVEL(IND_FIFO_PORT_LO(priv->id))); - while (fill_level--) - netx_eth_receive(ndev); - - if (status & ISR_CON_LO) - netif_wake_queue(ndev); - - if (status & ISR_LINK_STATUS_CHANGE) - mii_check_media(&priv->mii, netif_msg_link(priv), 1); - - status = readl(NETX_PFIFO_XPEC_ISR(priv->id)); - } - spin_unlock_irqrestore(&priv->lock, flags); - return IRQ_HANDLED; -} - -static int netx_eth_open(struct net_device *ndev) -{ - struct netx_eth_priv *priv = netdev_priv(ndev); - - if (request_irq - (ndev->irq, netx_eth_interrupt, IRQF_SHARED, ndev->name, ndev)) - return -EAGAIN; - - writel(ndev->dev_addr[0] | - ndev->dev_addr[1]<<8 | - ndev->dev_addr[2]<<16 | - ndev->dev_addr[3]<<24, - priv->xpec_base + NETX_XPEC_RAM_START_OFS + ETH_MAC_4321); - writel(ndev->dev_addr[4] | - ndev->dev_addr[5]<<8, - priv->xpec_base + NETX_XPEC_RAM_START_OFS + ETH_MAC_65); - - writel(LOCAL_CONFIG_LINK_STATUS_IRQ_EN | - LOCAL_CONFIG_CON_LO_IRQ_EN | - LOCAL_CONFIG_CON_HI_IRQ_EN | - LOCAL_CONFIG_IND_LO_IRQ_EN | - LOCAL_CONFIG_IND_HI_IRQ_EN, - priv->xpec_base + NETX_XPEC_RAM_START_OFS + - ETH_MAC_LOCAL_CONFIG); - - mii_check_media(&priv->mii, netif_msg_link(priv), 1); - netif_start_queue(ndev); - - return 0; -} - -static int netx_eth_close(struct net_device *ndev) -{ - struct netx_eth_priv *priv = netdev_priv(ndev); - - netif_stop_queue(ndev); - - writel(0, - priv->xpec_base + NETX_XPEC_RAM_START_OFS + ETH_MAC_LOCAL_CONFIG); - - free_irq(ndev->irq, ndev); - - return 0; -} - -static void netx_eth_timeout(struct net_device *ndev) -{ - struct netx_eth_priv *priv = netdev_priv(ndev); - int i; - - printk(KERN_ERR "%s: transmit timed out, resetting\n", ndev->name); - - spin_lock_irq(&priv->lock); - - xc_reset(priv->xc); - xc_start(priv->xc); - - for (i=2; i<=18; i++) - pfifo_push(EMPTY_PTR_FIFO(priv->id), - FIFO_PTR_FRAMENO(i) | FIFO_PTR_SEGMENT(priv->id)); - - spin_unlock_irq(&priv->lock); - - netif_wake_queue(ndev); -} - -static int -netx_eth_phy_read(struct net_device *ndev, int phy_id, int reg) -{ - unsigned int val; - - val = MIIMU_SNRDY | MIIMU_PREAMBLE | MIIMU_PHYADDR(phy_id) | - MIIMU_REGADDR(reg) | MIIMU_PHY_NRES; - - writel(val, NETX_MIIMU); - while (readl(NETX_MIIMU) & MIIMU_SNRDY); - - return readl(NETX_MIIMU) >> 16; - -} - -static void -netx_eth_phy_write(struct net_device *ndev, int phy_id, int reg, int value) -{ - unsigned int val; - - val = MIIMU_SNRDY | MIIMU_PREAMBLE | MIIMU_PHYADDR(phy_id) | - MIIMU_REGADDR(reg) | MIIMU_PHY_NRES | MIIMU_OPMODE_WRITE | - MIIMU_DATA(value); - - writel(val, NETX_MIIMU); - while (readl(NETX_MIIMU) & MIIMU_SNRDY); -} - -static const struct net_device_ops netx_eth_netdev_ops = { - .ndo_open = netx_eth_open, - .ndo_stop = netx_eth_close, - .ndo_start_xmit = netx_eth_hard_start_xmit, - .ndo_tx_timeout = netx_eth_timeout, - .ndo_set_rx_mode = netx_eth_set_multicast_list, - .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, -}; - -static int netx_eth_enable(struct net_device *ndev) -{ - struct netx_eth_priv *priv = netdev_priv(ndev); - unsigned int mac4321, mac65; - int running, i, ret; - bool inv_mac_addr = false; - - ndev->netdev_ops = &netx_eth_netdev_ops; - ndev->watchdog_timeo = msecs_to_jiffies(5000); - - priv->msg_enable = NETIF_MSG_LINK; - priv->mii.phy_id_mask = 0x1f; - priv->mii.reg_num_mask = 0x1f; - priv->mii.force_media = 0; - priv->mii.full_duplex = 0; - priv->mii.dev = ndev; - priv->mii.mdio_read = netx_eth_phy_read; - priv->mii.mdio_write = netx_eth_phy_write; - priv->mii.phy_id = INTERNAL_PHY_ADR + priv->id; - - running = xc_running(priv->xc); - xc_stop(priv->xc); - - /* if the xc engine is already running, assume the bootloader has - * loaded the firmware for us - */ - if (running) { - /* get Node Address from hardware */ - mac4321 = readl(priv->xpec_base + - NETX_XPEC_RAM_START_OFS + ETH_MAC_4321); - mac65 = readl(priv->xpec_base + - NETX_XPEC_RAM_START_OFS + ETH_MAC_65); - - ndev->dev_addr[0] = mac4321 & 0xff; - ndev->dev_addr[1] = (mac4321 >> 8) & 0xff; - ndev->dev_addr[2] = (mac4321 >> 16) & 0xff; - ndev->dev_addr[3] = (mac4321 >> 24) & 0xff; - ndev->dev_addr[4] = mac65 & 0xff; - ndev->dev_addr[5] = (mac65 >> 8) & 0xff; - } else { - if (xc_request_firmware(priv->xc)) { - printk(CARDNAME ": requesting firmware failed\n"); - return -ENODEV; - } - } - - xc_reset(priv->xc); - xc_start(priv->xc); - - if (!is_valid_ether_addr(ndev->dev_addr)) - inv_mac_addr = true; - - for (i=2; i<=18; i++) - pfifo_push(EMPTY_PTR_FIFO(priv->id), - FIFO_PTR_FRAMENO(i) | FIFO_PTR_SEGMENT(priv->id)); - - ret = register_netdev(ndev); - if (inv_mac_addr) - printk("%s: Invalid ethernet MAC address. Please set using ip\n", - ndev->name); - - return ret; -} - -static int netx_eth_drv_probe(struct platform_device *pdev) -{ - struct netx_eth_priv *priv; - struct net_device *ndev; - struct netxeth_platform_data *pdata; - int ret; - - ndev = alloc_etherdev(sizeof (struct netx_eth_priv)); - if (!ndev) { - ret = -ENOMEM; - goto exit; - } - SET_NETDEV_DEV(ndev, &pdev->dev); - - platform_set_drvdata(pdev, ndev); - - priv = netdev_priv(ndev); - - pdata = dev_get_platdata(&pdev->dev); - priv->xc = request_xc(pdata->xcno, &pdev->dev); - if (!priv->xc) { - dev_err(&pdev->dev, "unable to request xc engine\n"); - ret = -ENODEV; - goto exit_free_netdev; - } - - ndev->irq = priv->xc->irq; - priv->id = pdev->id; - priv->xpec_base = priv->xc->xpec_base; - priv->xmac_base = priv->xc->xmac_base; - priv->sram_base = priv->xc->sram_base; - - spin_lock_init(&priv->lock); - - ret = pfifo_request(PFIFO_MASK(priv->id)); - if (ret) { - printk("unable to request PFIFO\n"); - goto exit_free_xc; - } - - ret = netx_eth_enable(ndev); - if (ret) - goto exit_free_pfifo; - - return 0; -exit_free_pfifo: - pfifo_free(PFIFO_MASK(priv->id)); -exit_free_xc: - free_xc(priv->xc); -exit_free_netdev: - free_netdev(ndev); -exit: - return ret; -} - -static int netx_eth_drv_remove(struct platform_device *pdev) -{ - struct net_device *ndev = platform_get_drvdata(pdev); - struct netx_eth_priv *priv = netdev_priv(ndev); - - unregister_netdev(ndev); - xc_stop(priv->xc); - free_xc(priv->xc); - free_netdev(ndev); - pfifo_free(PFIFO_MASK(priv->id)); - - return 0; -} - -static int netx_eth_drv_suspend(struct platform_device *pdev, pm_message_t state) -{ - dev_err(&pdev->dev, "suspend not implemented\n"); - return 0; -} - -static int netx_eth_drv_resume(struct platform_device *pdev) -{ - dev_err(&pdev->dev, "resume not implemented\n"); - return 0; -} - -static struct platform_driver netx_eth_driver = { - .probe = netx_eth_drv_probe, - .remove = netx_eth_drv_remove, - .suspend = netx_eth_drv_suspend, - .resume = netx_eth_drv_resume, - .driver = { - .name = CARDNAME, - }, -}; - -static int __init netx_eth_init(void) -{ - unsigned int phy_control, val; - - printk("NetX Ethernet driver\n"); - - phy_control = PHY_CONTROL_PHY_ADDRESS(INTERNAL_PHY_ADR>>1) | - PHY_CONTROL_PHY1_MODE(PHY_MODE_ALL) | - PHY_CONTROL_PHY1_AUTOMDIX | - PHY_CONTROL_PHY1_EN | - PHY_CONTROL_PHY0_MODE(PHY_MODE_ALL) | - PHY_CONTROL_PHY0_AUTOMDIX | - PHY_CONTROL_PHY0_EN | - PHY_CONTROL_CLK_XLATIN; - - val = readl(NETX_SYSTEM_IOC_ACCESS_KEY); - writel(val, NETX_SYSTEM_IOC_ACCESS_KEY); - - writel(phy_control | PHY_CONTROL_RESET, NETX_SYSTEM_PHY_CONTROL); - udelay(100); - - val = readl(NETX_SYSTEM_IOC_ACCESS_KEY); - writel(val, NETX_SYSTEM_IOC_ACCESS_KEY); - - writel(phy_control, NETX_SYSTEM_PHY_CONTROL); - - return platform_driver_register(&netx_eth_driver); -} - -static void __exit netx_eth_cleanup(void) -{ - platform_driver_unregister(&netx_eth_driver); -} - -module_init(netx_eth_init); -module_exit(netx_eth_cleanup); - -MODULE_AUTHOR("Sascha Hauer, Pengutronix"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:" CARDNAME); -MODULE_FIRMWARE("xc0.bin"); -MODULE_FIRMWARE("xc1.bin"); -MODULE_FIRMWARE("xc2.bin"); diff --git a/include/linux/platform_data/eth-netx.h b/include/linux/platform_data/eth-netx.h deleted file mode 100644 index a3a6322668d8..000000000000 --- a/include/linux/platform_data/eth-netx.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2005 Sascha Hauer , Pengutronix - */ - -#ifndef __ETH_NETX_H -#define __ETH_NETX_H - -struct netxeth_platform_data { - unsigned int xcno; /* number of xmac/xpec engine this eth uses */ -}; - -#endif -- cgit v1.2.3-71-gd317 From cb063a83ca321fbf0cb2b4044186f241d89f3dc1 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 28 Aug 2019 15:03:18 +0200 Subject: thermal: db8500: Finalize device tree conversion At some point there was an attempt to convert the DB8500 thermal sensor to device tree: a probe path was added and the device tree was augmented for the Snowball board. The switchover was never completed: instead the thermal devices came from from the PRCMU MFD device and the probe on the Snowball was confused as another set of configuration appeared from the device tree. Move over to a device-tree only approach, as we fixed up the device trees. Cc: Vincent Guittot Acked-by: Lee Jones Reviewed-by: Daniel Lezcano Signed-off-by: Linus Walleij Signed-off-by: Eduardo Valentin --- drivers/mfd/db8500-prcmu.c | 53 +--------------------------- drivers/thermal/Kconfig | 2 +- drivers/thermal/db8500_thermal.c | 30 ++++++++-------- include/linux/platform_data/db8500_thermal.h | 29 --------------- 4 files changed, 17 insertions(+), 97 deletions(-) delete mode 100644 include/linux/platform_data/db8500_thermal.h (limited to 'include/linux/platform_data') diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 90e0f21bc49c..518439c79826 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -36,7 +36,6 @@ #include #include #include -#include #include "dbx500-prcmu-regs.h" /* Index of different voltages to be used when accessing AVSData */ @@ -2984,53 +2983,6 @@ static struct ux500_wdt_data db8500_wdt_pdata = { .timeout = 600, /* 10 minutes */ .has_28_bits_resolution = true, }; -/* - * Thermal Sensor - */ - -static struct resource db8500_thsens_resources[] = { - { - .name = "IRQ_HOTMON_LOW", - .start = IRQ_PRCMU_HOTMON_LOW, - .end = IRQ_PRCMU_HOTMON_LOW, - .flags = IORESOURCE_IRQ, - }, - { - .name = "IRQ_HOTMON_HIGH", - .start = IRQ_PRCMU_HOTMON_HIGH, - .end = IRQ_PRCMU_HOTMON_HIGH, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct db8500_thsens_platform_data db8500_thsens_data = { - .trip_points[0] = { - .temp = 70000, - .type = THERMAL_TRIP_ACTIVE, - .cdev_name = { - [0] = "thermal-cpufreq-0", - }, - }, - .trip_points[1] = { - .temp = 75000, - .type = THERMAL_TRIP_ACTIVE, - .cdev_name = { - [0] = "thermal-cpufreq-0", - }, - }, - .trip_points[2] = { - .temp = 80000, - .type = THERMAL_TRIP_ACTIVE, - .cdev_name = { - [0] = "thermal-cpufreq-0", - }, - }, - .trip_points[3] = { - .temp = 85000, - .type = THERMAL_TRIP_CRITICAL, - }, - .num_trips = 4, -}; static const struct mfd_cell common_prcmu_devs[] = { { @@ -3054,10 +3006,7 @@ static const struct mfd_cell db8500_prcmu_devs[] = { }, { .name = "db8500-thermal", - .num_resources = ARRAY_SIZE(db8500_thsens_resources), - .resources = db8500_thsens_resources, - .platform_data = &db8500_thsens_data, - .pdata_size = sizeof(db8500_thsens_data), + .of_compatible = "stericsson,db8500-thermal", }, }; diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 9966364a6deb..001a21abcc28 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -310,7 +310,7 @@ config DOVE_THERMAL config DB8500_THERMAL tristate "DB8500 thermal management" - depends on MFD_DB8500_PRCMU + depends on MFD_DB8500_PRCMU && OF default y help Adds DB8500 thermal management implementation according to the thermal diff --git a/drivers/thermal/db8500_thermal.c b/drivers/thermal/db8500_thermal.c index b71a999d17d6..d650ae5fdf2a 100644 --- a/drivers/thermal/db8500_thermal.c +++ b/drivers/thermal/db8500_thermal.c @@ -13,13 +13,24 @@ #include #include #include -#include #include #include #include #define PRCMU_DEFAULT_MEASURE_TIME 0xFFF #define PRCMU_DEFAULT_LOW_TEMP 0 +#define COOLING_DEV_MAX 8 + +struct db8500_trip_point { + unsigned long temp; + enum thermal_trip_type type; + char cdev_name[COOLING_DEV_MAX][THERMAL_NAME_LENGTH]; +}; + +struct db8500_thsens_platform_data { + struct db8500_trip_point trip_points[THERMAL_MAX_TRIPS]; + int num_trips; +}; struct db8500_thermal_zone { struct thermal_zone_device *therm_dev; @@ -301,7 +312,6 @@ static void db8500_thermal_work(struct work_struct *work) dev_dbg(&pzone->therm_dev->device, "thermal work finished.\n"); } -#ifdef CONFIG_OF static struct db8500_thsens_platform_data* db8500_thermal_parse_dt(struct platform_device *pdev) { @@ -370,13 +380,6 @@ err_parse_dt: dev_err(&pdev->dev, "Parsing device tree data error.\n"); return NULL; } -#else -static inline struct db8500_thsens_platform_data* - db8500_thermal_parse_dt(struct platform_device *pdev) -{ - return NULL; -} -#endif static int db8500_thermal_probe(struct platform_device *pdev) { @@ -386,11 +389,10 @@ static int db8500_thermal_probe(struct platform_device *pdev) int low_irq, high_irq, ret = 0; unsigned long dft_low, dft_high; - if (np) - ptrips = db8500_thermal_parse_dt(pdev); - else - ptrips = dev_get_platdata(&pdev->dev); + if (!np) + return -EINVAL; + ptrips = db8500_thermal_parse_dt(pdev); if (!ptrips) return -EINVAL; @@ -498,13 +500,11 @@ static int db8500_thermal_resume(struct platform_device *pdev) return 0; } -#ifdef CONFIG_OF static const struct of_device_id db8500_thermal_match[] = { { .compatible = "stericsson,db8500-thermal" }, {}, }; MODULE_DEVICE_TABLE(of, db8500_thermal_match); -#endif static struct platform_driver db8500_thermal_driver = { .driver = { diff --git a/include/linux/platform_data/db8500_thermal.h b/include/linux/platform_data/db8500_thermal.h deleted file mode 100644 index 55e55750a165..000000000000 --- a/include/linux/platform_data/db8500_thermal.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * db8500_thermal.h - DB8500 Thermal Management Implementation - * - * Copyright (C) 2012 ST-Ericsson - * Copyright (C) 2012 Linaro Ltd. - * - * Author: Hongbo Zhang - */ - -#ifndef _DB8500_THERMAL_H_ -#define _DB8500_THERMAL_H_ - -#include - -#define COOLING_DEV_MAX 8 - -struct db8500_trip_point { - unsigned long temp; - enum thermal_trip_type type; - char cdev_name[COOLING_DEV_MAX][THERMAL_NAME_LENGTH]; -}; - -struct db8500_thsens_platform_data { - struct db8500_trip_point trip_points[THERMAL_MAX_TRIPS]; - int num_trips; -}; - -#endif /* _DB8500_THERMAL_H_ */ -- cgit v1.2.3-71-gd317