From b1b3ced389795d2671e88dd3e9e07a48dc9632fc Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Wed, 10 Mar 2021 10:06:05 +0200 Subject: mfd: Support ROHM BD9576MUF and BD9573MUF Add core support for ROHM BD9576MUF and BD9573MUF PMICs which are mainly used to power the R-Car series processors. Signed-off-by: Matti Vaittinen Signed-off-by: Lee Jones --- include/linux/mfd/rohm-bd957x.h | 59 ++++++++++++++++++++++++++++++++++++++++ include/linux/mfd/rohm-generic.h | 2 ++ 2 files changed, 61 insertions(+) create mode 100644 include/linux/mfd/rohm-bd957x.h (limited to 'include/linux') diff --git a/include/linux/mfd/rohm-bd957x.h b/include/linux/mfd/rohm-bd957x.h new file mode 100644 index 000000000000..a631abb2c101 --- /dev/null +++ b/include/linux/mfd/rohm-bd957x.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (C) 2021 ROHM Semiconductors */ + +#ifndef __LINUX_MFD_BD957X_H__ +#define __LINUX_MFD_BD957X_H__ + +enum { + BD957X_VD50, + BD957X_VD18, + BD957X_VDDDR, + BD957X_VD10, + BD957X_VOUTL1, + BD957X_VOUTS1, +}; + +#define BD957X_REG_SMRB_ASSERT 0x15 +#define BD957X_REG_PMIC_INTERNAL_STAT 0x20 +#define BD957X_REG_INT_THERM_STAT 0x23 +#define BD957X_REG_INT_THERM_MASK 0x24 +#define BD957X_REG_INT_OVP_STAT 0x25 +#define BD957X_REG_INT_SCP_STAT 0x26 +#define BD957X_REG_INT_OCP_STAT 0x27 +#define BD957X_REG_INT_OVD_STAT 0x28 +#define BD957X_REG_INT_UVD_STAT 0x29 +#define BD957X_REG_INT_UVP_STAT 0x2a +#define BD957X_REG_INT_SYS_STAT 0x2b +#define BD957X_REG_INT_SYS_MASK 0x2c +#define BD957X_REG_INT_MAIN_STAT 0x30 +#define BD957X_REG_INT_MAIN_MASK 0x31 + +#define BD957X_REG_WDT_CONF 0x16 + +#define BD957X_REG_POW_TRIGGER1 0x41 +#define BD957X_REG_POW_TRIGGER2 0x42 +#define BD957X_REG_POW_TRIGGER3 0x43 +#define BD957X_REG_POW_TRIGGER4 0x44 +#define BD957X_REG_POW_TRIGGERL1 0x45 +#define BD957X_REG_POW_TRIGGERS1 0x46 + +#define BD957X_REGULATOR_EN_MASK 0xff +#define BD957X_REGULATOR_DIS_VAL 0xff + +#define BD957X_VSEL_REG_MASK 0xff + +#define BD957X_MASK_VOUT1_TUNE 0x87 +#define BD957X_MASK_VOUT2_TUNE 0x87 +#define BD957X_MASK_VOUT3_TUNE 0x1f +#define BD957X_MASK_VOUT4_TUNE 0x1f +#define BD957X_MASK_VOUTL1_TUNE 0x87 + +#define BD957X_REG_VOUT1_TUNE 0x50 +#define BD957X_REG_VOUT2_TUNE 0x53 +#define BD957X_REG_VOUT3_TUNE 0x56 +#define BD957X_REG_VOUT4_TUNE 0x59 +#define BD957X_REG_VOUTL1_TUNE 0x5c + +#define BD957X_MAX_REGISTER 0x61 + +#endif diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h index 66f673c35303..ac6787464004 100644 --- a/include/linux/mfd/rohm-generic.h +++ b/include/linux/mfd/rohm-generic.h @@ -14,6 +14,8 @@ enum rohm_chip_type { ROHM_CHIP_TYPE_BD71828, ROHM_CHIP_TYPE_BD9571, ROHM_CHIP_TYPE_BD9574, + ROHM_CHIP_TYPE_BD9576, + ROHM_CHIP_TYPE_BD9573, ROHM_CHIP_TYPE_AMOUNT }; -- cgit v1.2.3-71-gd317 From 0e9692607f94ecc59aedc0ecfd2348124c743412 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Wed, 10 Mar 2021 10:08:02 +0200 Subject: mfd: bd9576: Add IRQ support BD9573 and BD9576 support set of "protection" interrupts for "fatal" issues. Those lead to SOC reset as PMIC shuts the power outputs. Thus there is no relevant IRQ handling for them. Few "detection" interrupts were added to the BD9576 with the idea that SOC could take some recovery-action before error gets unrecoverable. Unfortunately the BD9576 interrupt logic was not re-evaluated. IRQs are not designed to be properly acknowleged - and IRQ line is kept active for whole duration of error condition (in comparison to informing only about state change). For above reason, do not consider missing IRQ as error. Signed-off-by: Matti Vaittinen Signed-off-by: Lee Jones --- drivers/mfd/rohm-bd9576.c | 90 ++++++++++++++++++++++++++++++++++++++--- include/linux/mfd/rohm-bd957x.h | 62 ++++++++++++++++++++++++++++ 2 files changed, 147 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/drivers/mfd/rohm-bd9576.c b/drivers/mfd/rohm-bd9576.c index 2dbda1f401e2..6661a27d69a8 100644 --- a/drivers/mfd/rohm-bd9576.c +++ b/drivers/mfd/rohm-bd9576.c @@ -17,14 +17,30 @@ #include #include +enum { + BD957X_REGULATOR_CELL, + BD957X_WDT_CELL, +}; + +/* + * Due to the BD9576MUF nasty IRQ behaiour we don't always populate IRQs. + * These will be added to regulator resources only if IRQ information for the + * PMIC is populated in device-tree. + */ +static const struct resource bd9576_regulator_irqs[] = { + DEFINE_RES_IRQ_NAMED(BD9576_INT_THERM, "bd9576-temp"), + DEFINE_RES_IRQ_NAMED(BD9576_INT_OVD, "bd9576-ovd"), + DEFINE_RES_IRQ_NAMED(BD9576_INT_UVD, "bd9576-uvd"), +}; + static struct mfd_cell bd9573_mfd_cells[] = { - { .name = "bd9573-regulator", }, - { .name = "bd9576-wdt", }, + [BD957X_REGULATOR_CELL] = { .name = "bd9573-regulator", }, + [BD957X_WDT_CELL] = { .name = "bd9576-wdt", }, }; static struct mfd_cell bd9576_mfd_cells[] = { - { .name = "bd9576-regulator", }, - { .name = "bd9576-wdt", }, + [BD957X_REGULATOR_CELL] = { .name = "bd9576-regulator", }, + [BD957X_WDT_CELL] = { .name = "bd9576-wdt", }, }; static const struct regmap_range volatile_ranges[] = { @@ -49,6 +65,29 @@ static struct regmap_config bd957x_regmap = { .cache_type = REGCACHE_RBTREE, }; +static struct regmap_irq bd9576_irqs[] = { + REGMAP_IRQ_REG(BD9576_INT_THERM, 0, BD957X_MASK_INT_MAIN_THERM), + REGMAP_IRQ_REG(BD9576_INT_OVP, 0, BD957X_MASK_INT_MAIN_OVP), + REGMAP_IRQ_REG(BD9576_INT_SCP, 0, BD957X_MASK_INT_MAIN_SCP), + REGMAP_IRQ_REG(BD9576_INT_OCP, 0, BD957X_MASK_INT_MAIN_OCP), + REGMAP_IRQ_REG(BD9576_INT_OVD, 0, BD957X_MASK_INT_MAIN_OVD), + REGMAP_IRQ_REG(BD9576_INT_UVD, 0, BD957X_MASK_INT_MAIN_UVD), + REGMAP_IRQ_REG(BD9576_INT_UVP, 0, BD957X_MASK_INT_MAIN_UVP), + REGMAP_IRQ_REG(BD9576_INT_SYS, 0, BD957X_MASK_INT_MAIN_SYS), +}; + +static struct regmap_irq_chip bd9576_irq_chip = { + .name = "bd9576_irq", + .irqs = &bd9576_irqs[0], + .num_irqs = ARRAY_SIZE(bd9576_irqs), + .status_base = BD957X_REG_INT_MAIN_STAT, + .mask_base = BD957X_REG_INT_MAIN_MASK, + .ack_base = BD957X_REG_INT_MAIN_STAT, + .init_ack_masked = true, + .num_regs = 1, + .irq_reg_stride = 1, +}; + static int bd957x_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { @@ -57,6 +96,8 @@ static int bd957x_i2c_probe(struct i2c_client *i2c, struct mfd_cell *cells; int num_cells; unsigned long chip_type; + struct irq_domain *domain; + bool usable_irqs; chip_type = (unsigned long)of_device_get_match_data(&i2c->dev); @@ -64,10 +105,16 @@ static int bd957x_i2c_probe(struct i2c_client *i2c, case ROHM_CHIP_TYPE_BD9576: cells = bd9576_mfd_cells; num_cells = ARRAY_SIZE(bd9576_mfd_cells); + usable_irqs = !!i2c->irq; break; case ROHM_CHIP_TYPE_BD9573: cells = bd9573_mfd_cells; num_cells = ARRAY_SIZE(bd9573_mfd_cells); + /* + * BD9573 only supports fatal IRQs which we can not handle + * because SoC is going to lose the power. + */ + usable_irqs = false; break; default: dev_err(&i2c->dev, "Unknown device type"); @@ -80,8 +127,41 @@ static int bd957x_i2c_probe(struct i2c_client *i2c, return PTR_ERR(regmap); } + /* + * BD9576 behaves badly. It kepts IRQ line asserted for the whole + * duration of detected HW condition (like over temperature). So we + * don't require IRQ to be populated. + * If IRQ information is not given, then we mask all IRQs and do not + * provide IRQ resources to regulator driver - which then just omits + * the notifiers. + */ + if (usable_irqs) { + struct regmap_irq_chip_data *irq_data; + struct mfd_cell *regulators; + + regulators = &bd9576_mfd_cells[BD957X_REGULATOR_CELL]; + regulators->resources = bd9576_regulator_irqs; + regulators->num_resources = ARRAY_SIZE(bd9576_regulator_irqs); + + ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq, + IRQF_ONESHOT, 0, + &bd9576_irq_chip, &irq_data); + if (ret) { + dev_err(&i2c->dev, "Failed to add IRQ chip\n"); + return ret; + } + domain = regmap_irq_get_domain(irq_data); + } else { + ret = regmap_update_bits(regmap, BD957X_REG_INT_MAIN_MASK, + BD957X_MASK_INT_ALL, + BD957X_MASK_INT_ALL); + if (ret) + return ret; + domain = NULL; + } + ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, cells, - num_cells, NULL, 0, NULL); + num_cells, NULL, 0, domain); if (ret) dev_err(&i2c->dev, "Failed to create subdevices\n"); diff --git a/include/linux/mfd/rohm-bd957x.h b/include/linux/mfd/rohm-bd957x.h index a631abb2c101..ddb396ff2da5 100644 --- a/include/linux/mfd/rohm-bd957x.h +++ b/include/linux/mfd/rohm-bd957x.h @@ -13,6 +13,55 @@ enum { BD957X_VOUTS1, }; +/* + * The BD9576 has own IRQ 'blocks' for: + * - I2C/thermal, + * - Over voltage protection + * - Short-circuit protection + * - Over current protection + * - Over voltage detection + * - Under voltage detection + * - Under voltage protection + * - 'system interrupt'. + * + * Each of the blocks have a status register giving more accurate IRQ source + * information - for example which of the regulators have over-voltage. + * + * On top of this, there is "main IRQ" status register where each bit indicates + * which of sub-blocks have active IRQs. Fine. That would fit regmap-irq main + * status handling. Except that: + * - Only some sub-IRQs can be masked. + * - The IRQ informs us about fault-condition, not when fault state changes. + * The IRQ line it is kept asserted until the detected condition is acked + * AND cleared in HW. This is annoying for IRQs like the one informing high + * temperature because if IRQ is not disabled it keeps the CPU in IRQ + * handling loop. + * + * For now we do just use the main-IRQ register as source for our IRQ + * information and bind the regmap-irq to this. We leave fine-grained sub-IRQ + * register handling to handlers in sub-devices. The regulator driver shall + * read which regulators are source for problem - or if the detected error is + * regulator temperature error. The sub-drivers do also handle masking of "sub- + * IRQs" if this is supported/needed. + * + * To overcome the problem with HW keeping IRQ asserted we do call + * disable_irq_nosync() from sub-device handler and add a delayed work to + * re-enable IRQ roughly 1 second later. This should keep our CPU out of + * busy-loop. + */ +#define IRQS_SILENT_MS 1000 + +enum { + BD9576_INT_THERM, + BD9576_INT_OVP, + BD9576_INT_SCP, + BD9576_INT_OCP, + BD9576_INT_OVD, + BD9576_INT_UVD, + BD9576_INT_UVP, + BD9576_INT_SYS, +}; + #define BD957X_REG_SMRB_ASSERT 0x15 #define BD957X_REG_PMIC_INTERNAL_STAT 0x20 #define BD957X_REG_INT_THERM_STAT 0x23 @@ -28,6 +77,19 @@ enum { #define BD957X_REG_INT_MAIN_STAT 0x30 #define BD957X_REG_INT_MAIN_MASK 0x31 +#define UVD_IRQ_VALID_MASK 0x6F +#define OVD_IRQ_VALID_MASK 0x2F + +#define BD957X_MASK_INT_MAIN_THERM BIT(0) +#define BD957X_MASK_INT_MAIN_OVP BIT(1) +#define BD957X_MASK_INT_MAIN_SCP BIT(2) +#define BD957X_MASK_INT_MAIN_OCP BIT(3) +#define BD957X_MASK_INT_MAIN_OVD BIT(4) +#define BD957X_MASK_INT_MAIN_UVD BIT(5) +#define BD957X_MASK_INT_MAIN_UVP BIT(6) +#define BD957X_MASK_INT_MAIN_SYS BIT(7) +#define BD957X_MASK_INT_ALL 0xff + #define BD957X_REG_WDT_CONF 0x16 #define BD957X_REG_POW_TRIGGER1 0x41 -- cgit v1.2.3-71-gd317 From 42fc191d60e6d5fd8c52e7afa8bccdc912947ce4 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Wed, 10 Mar 2021 10:11:44 +0200 Subject: mfd: bd9576: Add safety limit/monitoring registers ROHM BD9576 contains safety features like over/under voltage detection, over curren detection and over temperature detection. Add the configuration register information. Signed-off-by: Matti Vaittinen Signed-off-by: Lee Jones --- include/linux/mfd/rohm-bd957x.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'include/linux') diff --git a/include/linux/mfd/rohm-bd957x.h b/include/linux/mfd/rohm-bd957x.h index ddb396ff2da5..acc920b64f75 100644 --- a/include/linux/mfd/rohm-bd957x.h +++ b/include/linux/mfd/rohm-bd957x.h @@ -116,6 +116,25 @@ enum { #define BD957X_REG_VOUT4_TUNE 0x59 #define BD957X_REG_VOUTL1_TUNE 0x5c +#define BD9576_REG_VOUT1_OVD 0x51 +#define BD9576_REG_VOUT1_UVD 0x52 +#define BD9576_REG_VOUT2_OVD 0x54 +#define BD9576_REG_VOUT2_UVD 0x55 +#define BD9576_REG_VOUT3_OVD 0x57 +#define BD9576_REG_VOUT3_UVD 0x58 +#define BD9576_REG_VOUT4_OVD 0x5a +#define BD9576_REG_VOUT4_UVD 0x5b +#define BD9576_REG_VOUTL1_OVD 0x5d +#define BD9576_REG_VOUTL1_UVD 0x5e + +#define BD9576_MASK_XVD 0x7f + +#define BD9576_REG_VOUT1S_OCW 0x5f +#define BD9576_REG_VOUT1S_OCP 0x60 + +#define BD9576_MASK_VOUT1S_OCW 0x3f +#define BD9576_MASK_VOUT1S_OCP 0x3f + #define BD957X_MAX_REGISTER 0x61 #endif -- cgit v1.2.3-71-gd317 From eceae583930666a69ab805eee8e81f9699bf6930 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sun, 24 Jan 2021 22:41:23 +0100 Subject: mfd: Add base driver for Netronix embedded controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Netronix embedded controller is a microcontroller found in some e-book readers designed by the original design manufacturer Netronix, Inc. It contains RTC, battery monitoring, system power management, and PWM functionality. This driver implements register access and version detection. Third-party hardware documentation is available at: https://github.com/neuschaefer/linux/wiki/Netronix-MSP430-embedded-controller The EC supports interrupts, but the driver doesn't make use of them so far. Signed-off-by: Jonathan Neuschäfer Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 11 +++ drivers/mfd/Makefile | 1 + drivers/mfd/ntxec.c | 221 ++++++++++++++++++++++++++++++++++++++++++++++ include/linux/mfd/ntxec.h | 37 ++++++++ 4 files changed, 270 insertions(+) create mode 100644 drivers/mfd/ntxec.c create mode 100644 include/linux/mfd/ntxec.h (limited to 'include/linux') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index b74efa469e90..a03de3f7a8ed 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -967,6 +967,17 @@ config MFD_VIPERBOARD You need to select the mfd cell drivers separately. The drivers do not support all features the board exposes. +config MFD_NTXEC + tristate "Netronix embedded controller (EC)" + depends on OF || COMPILE_TEST + depends on I2C + select REGMAP_I2C + select MFD_CORE + help + Say yes here if you want to support the embedded controller found in + certain e-book readers designed by the original design manufacturer + Netronix. + config MFD_RETU tristate "Nokia Retu and Tahvo multi-function device" select MFD_CORE diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 834f5463af28..bb5e8f2a8e3a 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -218,6 +218,7 @@ obj-$(CONFIG_MFD_INTEL_PMC_BXT) += intel_pmc_bxt.o obj-$(CONFIG_MFD_INTEL_PMT) += intel_pmt.o obj-$(CONFIG_MFD_PALMAS) += palmas.o obj-$(CONFIG_MFD_VIPERBOARD) += viperboard.o +obj-$(CONFIG_MFD_NTXEC) += ntxec.o obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o obj-$(CONFIG_MFD_RK808) += rk808.o obj-$(CONFIG_MFD_RN5T618) += rn5t618.o diff --git a/drivers/mfd/ntxec.c b/drivers/mfd/ntxec.c new file mode 100644 index 000000000000..957de2b03529 --- /dev/null +++ b/drivers/mfd/ntxec.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * The Netronix embedded controller is a microcontroller found in some + * e-book readers designed by the original design manufacturer Netronix, Inc. + * It contains RTC, battery monitoring, system power management, and PWM + * functionality. + * + * This driver implements register access, version detection, and system + * power-off/reset. + * + * Copyright 2020 Jonathan Neuschäfer + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NTXEC_REG_VERSION 0x00 +#define NTXEC_REG_POWEROFF 0x50 +#define NTXEC_REG_POWERKEEP 0x70 +#define NTXEC_REG_RESET 0x90 + +#define NTXEC_POWEROFF_VALUE 0x0100 +#define NTXEC_POWERKEEP_VALUE 0x0800 +#define NTXEC_RESET_VALUE 0xff00 + +static struct i2c_client *poweroff_restart_client; + +static void ntxec_poweroff(void) +{ + int res; + u8 buf[3] = { NTXEC_REG_POWEROFF }; + struct i2c_msg msgs[] = { + { + .addr = poweroff_restart_client->addr, + .flags = 0, + .len = sizeof(buf), + .buf = buf, + }, + }; + + put_unaligned_be16(NTXEC_POWEROFF_VALUE, buf + 1); + + res = i2c_transfer(poweroff_restart_client->adapter, msgs, ARRAY_SIZE(msgs)); + if (res < 0) + dev_warn(&poweroff_restart_client->dev, + "Failed to power off (err = %d)\n", res); + + /* + * The time from the register write until the host CPU is powered off + * has been observed to be about 2.5 to 3 seconds. Sleep long enough to + * safely avoid returning from the poweroff handler. + */ + msleep(5000); +} + +static int ntxec_restart(struct notifier_block *nb, + unsigned long action, void *data) +{ + int res; + u8 buf[3] = { NTXEC_REG_RESET }; + /* + * NOTE: The lower half of the reset value is not sent, because sending + * it causes an I2C error. (The reset handler in the downstream driver + * does send the full two-byte value, but doesn't check the result). + */ + struct i2c_msg msgs[] = { + { + .addr = poweroff_restart_client->addr, + .flags = 0, + .len = sizeof(buf) - 1, + .buf = buf, + }, + }; + + put_unaligned_be16(NTXEC_RESET_VALUE, buf + 1); + + res = i2c_transfer(poweroff_restart_client->adapter, msgs, ARRAY_SIZE(msgs)); + if (res < 0) + dev_warn(&poweroff_restart_client->dev, + "Failed to restart (err = %d)\n", res); + + return NOTIFY_DONE; +} + +static struct notifier_block ntxec_restart_handler = { + .notifier_call = ntxec_restart, + .priority = 128, +}; + +static const struct regmap_config regmap_config = { + .name = "ntxec", + .reg_bits = 8, + .val_bits = 16, + .cache_type = REGCACHE_NONE, + .val_format_endian = REGMAP_ENDIAN_BIG, +}; + +static const struct mfd_cell ntxec_subdevices[] = { + { .name = "ntxec-rtc" }, + { .name = "ntxec-pwm" }, +}; + +static int ntxec_probe(struct i2c_client *client) +{ + struct ntxec *ec; + unsigned int version; + int res; + + ec = devm_kmalloc(&client->dev, sizeof(*ec), GFP_KERNEL); + if (!ec) + return -ENOMEM; + + ec->dev = &client->dev; + + ec->regmap = devm_regmap_init_i2c(client, ®map_config); + if (IS_ERR(ec->regmap)) { + dev_err(ec->dev, "Failed to set up regmap for device\n"); + return PTR_ERR(ec->regmap); + } + + /* Determine the firmware version */ + res = regmap_read(ec->regmap, NTXEC_REG_VERSION, &version); + if (res < 0) { + dev_err(ec->dev, "Failed to read firmware version number\n"); + return res; + } + + /* Bail out if we encounter an unknown firmware version */ + switch (version) { + case NTXEC_VERSION_KOBO_AURA: + break; + default: + dev_err(ec->dev, + "Netronix embedded controller version %04x is not supported.\n", + version); + return -ENODEV; + } + + dev_info(ec->dev, + "Netronix embedded controller version %04x detected.\n", version); + + if (of_device_is_system_power_controller(ec->dev->of_node)) { + /* + * Set the 'powerkeep' bit. This is necessary on some boards + * in order to keep the system running. + */ + res = regmap_write(ec->regmap, NTXEC_REG_POWERKEEP, + NTXEC_POWERKEEP_VALUE); + if (res < 0) + return res; + + if (poweroff_restart_client) + /* + * Another instance of the driver already took + * poweroff/restart duties. + */ + dev_err(ec->dev, "poweroff_restart_client already assigned\n"); + else + poweroff_restart_client = client; + + if (pm_power_off) + /* Another driver already registered a poweroff handler. */ + dev_err(ec->dev, "pm_power_off already assigned\n"); + else + pm_power_off = ntxec_poweroff; + + res = register_restart_handler(&ntxec_restart_handler); + if (res) + dev_err(ec->dev, + "Failed to register restart handler: %d\n", res); + } + + i2c_set_clientdata(client, ec); + + res = devm_mfd_add_devices(ec->dev, PLATFORM_DEVID_NONE, ntxec_subdevices, + ARRAY_SIZE(ntxec_subdevices), NULL, 0, NULL); + if (res) + dev_err(ec->dev, "Failed to add subdevices: %d\n", res); + + return res; +} + +static int ntxec_remove(struct i2c_client *client) +{ + if (client == poweroff_restart_client) { + poweroff_restart_client = NULL; + pm_power_off = NULL; + unregister_restart_handler(&ntxec_restart_handler); + } + + return 0; +} + +static const struct of_device_id of_ntxec_match_table[] = { + { .compatible = "netronix,ntxec", }, + {} +}; +MODULE_DEVICE_TABLE(of, of_ntxec_match_table); + +static struct i2c_driver ntxec_driver = { + .driver = { + .name = "ntxec", + .of_match_table = of_ntxec_match_table, + }, + .probe_new = ntxec_probe, + .remove = ntxec_remove, +}; +module_i2c_driver(ntxec_driver); + +MODULE_AUTHOR("Jonathan Neuschäfer "); +MODULE_DESCRIPTION("Core driver for Netronix EC"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/ntxec.h b/include/linux/mfd/ntxec.h new file mode 100644 index 000000000000..361204d125f1 --- /dev/null +++ b/include/linux/mfd/ntxec.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 Jonathan Neuschäfer + * + * Register access and version information for the Netronix embedded + * controller. + */ + +#ifndef NTXEC_H +#define NTXEC_H + +#include + +struct device; +struct regmap; + +struct ntxec { + struct device *dev; + struct regmap *regmap; +}; + +/* + * Some registers, such as the battery status register (0x41), are in + * big-endian, but others only have eight significant bits, which are in the + * first byte transmitted over I2C (the MSB of the big-endian value). + * This convenience function converts an 8-bit value to 16-bit for use in the + * second kind of register. + */ +static inline __be16 ntxec_reg8(u8 value) +{ + return value << 8; +} + +/* Known firmware versions */ +#define NTXEC_VERSION_KOBO_AURA 0xd726 /* found in Kobo Aura */ + +#endif -- cgit v1.2.3-71-gd317 From f7cb7fe34db9f32e8b1c13ecc823112480b875f8 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 26 Jan 2021 11:55:59 +0200 Subject: mfd: Add MFD driver for ATC260x PMICs Add initial support for the Actions Semi ATC260x PMICs which integrates Audio Codec, Power management, Clock generation and GPIO controller blocks. For the moment this driver only supports Regulator, Poweroff and Onkey functionalities for the ATC2603C and ATC2609A chip variants. Since the PMICs can be accessed using both I2C and SPI buses, the following driver structure has been adopted: -----> atc260x-core.c (Implements core functionalities) / ATC260x --------> atc260x-i2c.c (Implements I2C interface) \ -----> atc260x-spi.c (Implements SPI interface - TODO) Co-developed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam Signed-off-by: Cristian Ciocaltea Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 18 ++ drivers/mfd/Makefile | 3 + drivers/mfd/atc260x-core.c | 310 +++++++++++++++++++++++++++++++++++ drivers/mfd/atc260x-i2c.c | 64 ++++++++ include/linux/mfd/atc260x/atc2603c.h | 281 +++++++++++++++++++++++++++++++ include/linux/mfd/atc260x/atc2609a.h | 308 ++++++++++++++++++++++++++++++++++ include/linux/mfd/atc260x/core.h | 58 +++++++ 7 files changed, 1042 insertions(+) create mode 100644 drivers/mfd/atc260x-core.c create mode 100644 drivers/mfd/atc260x-i2c.c create mode 100644 include/linux/mfd/atc260x/atc2603c.h create mode 100644 include/linux/mfd/atc260x/atc2609a.h create mode 100644 include/linux/mfd/atc260x/core.h (limited to 'include/linux') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index b74efa469e90..f9b43f15790b 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2055,6 +2055,24 @@ config MFD_WCD934X This driver provides common support WCD934x audio codec and its associated Pin Controller, Soundwire Controller and Audio codec. +config MFD_ATC260X + tristate + select MFD_CORE + select REGMAP + select REGMAP_IRQ + +config MFD_ATC260X_I2C + tristate "Actions Semi ATC260x PMICs with I2C" + select MFD_ATC260X + select REGMAP_I2C + depends on I2C + help + Support for the Actions Semi ATC260x PMICs controlled via I2C. + + This driver provides common support for accessing the ATC2603C + and ATC2609A chip variants, additional drivers must be enabled + in order to use the functionality of the device. + config MFD_KHADAS_MCU tristate "Support for Khadas System control Microcontroller" depends on I2C diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 834f5463af28..f7872d0bd570 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -268,3 +268,6 @@ obj-$(CONFIG_MFD_ACER_A500_EC) += acer-ec-a500.o obj-$(CONFIG_SGI_MFD_IOC3) += ioc3.o obj-$(CONFIG_MFD_SIMPLE_MFD_I2C) += simple-mfd-i2c.o obj-$(CONFIG_MFD_INTEL_M10_BMC) += intel-m10-bmc.o + +obj-$(CONFIG_MFD_ATC260X) += atc260x-core.o +obj-$(CONFIG_MFD_ATC260X_I2C) += atc260x-i2c.o diff --git a/drivers/mfd/atc260x-core.c b/drivers/mfd/atc260x-core.c new file mode 100644 index 000000000000..7148ff5b05b1 --- /dev/null +++ b/drivers/mfd/atc260x-core.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Core support for ATC260x PMICs + * + * Copyright (C) 2019 Manivannan Sadhasivam + * Copyright (C) 2020 Cristian Ciocaltea + */ + +#include +#include +#include +#include +#include +#include +#include + +#define ATC260X_CHIP_REV_MAX 31 + +struct atc260x_init_regs { + unsigned int cmu_devrst; + unsigned int cmu_devrst_ints; + unsigned int ints_msk; + unsigned int pad_en; + unsigned int pad_en_extirq; +}; + +static void regmap_lock_mutex(void *__mutex) +{ + struct mutex *mutex = __mutex; + + /* + * Using regmap within an atomic context (e.g. accessing a PMIC when + * powering system down) is normally allowed only if the regmap type + * is MMIO and the regcache type is either REGCACHE_NONE or + * REGCACHE_FLAT. For slow buses like I2C and SPI, the regmap is + * internally protected by a mutex which is acquired non-atomically. + * + * Let's improve this by using a customized locking scheme inspired + * from I2C atomic transfer. See i2c_in_atomic_xfer_mode() for a + * starting point. + */ + if (system_state > SYSTEM_RUNNING && irqs_disabled()) + mutex_trylock(mutex); + else + mutex_lock(mutex); +} + +static void regmap_unlock_mutex(void *__mutex) +{ + struct mutex *mutex = __mutex; + + mutex_unlock(mutex); +} + +static const struct regmap_config atc2603c_regmap_config = { + .reg_bits = 8, + .val_bits = 16, + .max_register = ATC2603C_SADDR, + .cache_type = REGCACHE_NONE, +}; + +static const struct regmap_config atc2609a_regmap_config = { + .reg_bits = 8, + .val_bits = 16, + .max_register = ATC2609A_SADDR, + .cache_type = REGCACHE_NONE, +}; + +static const struct regmap_irq atc2603c_regmap_irqs[] = { + REGMAP_IRQ_REG(ATC2603C_IRQ_AUDIO, 0, ATC2603C_INTS_MSK_AUDIO), + REGMAP_IRQ_REG(ATC2603C_IRQ_OV, 0, ATC2603C_INTS_MSK_OV), + REGMAP_IRQ_REG(ATC2603C_IRQ_OC, 0, ATC2603C_INTS_MSK_OC), + REGMAP_IRQ_REG(ATC2603C_IRQ_OT, 0, ATC2603C_INTS_MSK_OT), + REGMAP_IRQ_REG(ATC2603C_IRQ_UV, 0, ATC2603C_INTS_MSK_UV), + REGMAP_IRQ_REG(ATC2603C_IRQ_ALARM, 0, ATC2603C_INTS_MSK_ALARM), + REGMAP_IRQ_REG(ATC2603C_IRQ_ONOFF, 0, ATC2603C_INTS_MSK_ONOFF), + REGMAP_IRQ_REG(ATC2603C_IRQ_SGPIO, 0, ATC2603C_INTS_MSK_SGPIO), + REGMAP_IRQ_REG(ATC2603C_IRQ_IR, 0, ATC2603C_INTS_MSK_IR), + REGMAP_IRQ_REG(ATC2603C_IRQ_REMCON, 0, ATC2603C_INTS_MSK_REMCON), + REGMAP_IRQ_REG(ATC2603C_IRQ_POWER_IN, 0, ATC2603C_INTS_MSK_POWERIN), +}; + +static const struct regmap_irq atc2609a_regmap_irqs[] = { + REGMAP_IRQ_REG(ATC2609A_IRQ_AUDIO, 0, ATC2609A_INTS_MSK_AUDIO), + REGMAP_IRQ_REG(ATC2609A_IRQ_OV, 0, ATC2609A_INTS_MSK_OV), + REGMAP_IRQ_REG(ATC2609A_IRQ_OC, 0, ATC2609A_INTS_MSK_OC), + REGMAP_IRQ_REG(ATC2609A_IRQ_OT, 0, ATC2609A_INTS_MSK_OT), + REGMAP_IRQ_REG(ATC2609A_IRQ_UV, 0, ATC2609A_INTS_MSK_UV), + REGMAP_IRQ_REG(ATC2609A_IRQ_ALARM, 0, ATC2609A_INTS_MSK_ALARM), + REGMAP_IRQ_REG(ATC2609A_IRQ_ONOFF, 0, ATC2609A_INTS_MSK_ONOFF), + REGMAP_IRQ_REG(ATC2609A_IRQ_WKUP, 0, ATC2609A_INTS_MSK_WKUP), + REGMAP_IRQ_REG(ATC2609A_IRQ_IR, 0, ATC2609A_INTS_MSK_IR), + REGMAP_IRQ_REG(ATC2609A_IRQ_REMCON, 0, ATC2609A_INTS_MSK_REMCON), + REGMAP_IRQ_REG(ATC2609A_IRQ_POWER_IN, 0, ATC2609A_INTS_MSK_POWERIN), +}; + +static const struct regmap_irq_chip atc2603c_regmap_irq_chip = { + .name = "atc2603c", + .irqs = atc2603c_regmap_irqs, + .num_irqs = ARRAY_SIZE(atc2603c_regmap_irqs), + .num_regs = 1, + .status_base = ATC2603C_INTS_PD, + .mask_base = ATC2603C_INTS_MSK, + .mask_invert = true, +}; + +static const struct regmap_irq_chip atc2609a_regmap_irq_chip = { + .name = "atc2609a", + .irqs = atc2609a_regmap_irqs, + .num_irqs = ARRAY_SIZE(atc2609a_regmap_irqs), + .num_regs = 1, + .status_base = ATC2609A_INTS_PD, + .mask_base = ATC2609A_INTS_MSK, + .mask_invert = true, +}; + +static const struct resource atc2603c_onkey_resources[] = { + DEFINE_RES_IRQ(ATC2603C_IRQ_ONOFF), +}; + +static const struct resource atc2609a_onkey_resources[] = { + DEFINE_RES_IRQ(ATC2609A_IRQ_ONOFF), +}; + +static const struct mfd_cell atc2603c_mfd_cells[] = { + { .name = "atc260x-regulator" }, + { .name = "atc260x-pwrc" }, + { + .name = "atc260x-onkey", + .num_resources = ARRAY_SIZE(atc2603c_onkey_resources), + .resources = atc2603c_onkey_resources, + }, +}; + +static const struct mfd_cell atc2609a_mfd_cells[] = { + { .name = "atc260x-regulator" }, + { .name = "atc260x-pwrc" }, + { + .name = "atc260x-onkey", + .num_resources = ARRAY_SIZE(atc2609a_onkey_resources), + .resources = atc2609a_onkey_resources, + }, +}; + +static const struct atc260x_init_regs atc2603c_init_regs = { + .cmu_devrst = ATC2603C_CMU_DEVRST, + .cmu_devrst_ints = ATC2603C_CMU_DEVRST_INTS, + .ints_msk = ATC2603C_INTS_MSK, + .pad_en = ATC2603C_PAD_EN, + .pad_en_extirq = ATC2603C_PAD_EN_EXTIRQ, +}; + +static const struct atc260x_init_regs atc2609a_init_regs = { + .cmu_devrst = ATC2609A_CMU_DEVRST, + .cmu_devrst_ints = ATC2609A_CMU_DEVRST_INTS, + .ints_msk = ATC2609A_INTS_MSK, + .pad_en = ATC2609A_PAD_EN, + .pad_en_extirq = ATC2609A_PAD_EN_EXTIRQ, +}; + +static void atc260x_cmu_reset(struct atc260x *atc260x) +{ + const struct atc260x_init_regs *regs = atc260x->init_regs; + + /* Assert reset */ + regmap_update_bits(atc260x->regmap, regs->cmu_devrst, + regs->cmu_devrst_ints, ~regs->cmu_devrst_ints); + + /* De-assert reset */ + regmap_update_bits(atc260x->regmap, regs->cmu_devrst, + regs->cmu_devrst_ints, regs->cmu_devrst_ints); +} + +static void atc260x_dev_init(struct atc260x *atc260x) +{ + const struct atc260x_init_regs *regs = atc260x->init_regs; + + /* Initialize interrupt block */ + atc260x_cmu_reset(atc260x); + + /* Disable all interrupt sources */ + regmap_write(atc260x->regmap, regs->ints_msk, 0); + + /* Enable EXTIRQ pad */ + regmap_update_bits(atc260x->regmap, regs->pad_en, + regs->pad_en_extirq, regs->pad_en_extirq); +} + +/** + * atc260x_match_device(): Setup ATC260x variant related fields + * + * @atc260x: ATC260x device to setup (.dev field must be set) + * @regmap_cfg: regmap config associated with this ATC260x device + * + * This lets the ATC260x core configure the MFD cells and register maps + * for later use. + */ +int atc260x_match_device(struct atc260x *atc260x, struct regmap_config *regmap_cfg) +{ + struct device *dev = atc260x->dev; + const void *of_data; + + of_data = of_device_get_match_data(dev); + if (!of_data) + return -ENODEV; + + atc260x->ic_type = (unsigned long)of_data; + + switch (atc260x->ic_type) { + case ATC2603C: + *regmap_cfg = atc2603c_regmap_config; + atc260x->regmap_irq_chip = &atc2603c_regmap_irq_chip; + atc260x->cells = atc2603c_mfd_cells; + atc260x->nr_cells = ARRAY_SIZE(atc2603c_mfd_cells); + atc260x->type_name = "atc2603c"; + atc260x->rev_reg = ATC2603C_CHIP_VER; + atc260x->init_regs = &atc2603c_init_regs; + break; + case ATC2609A: + *regmap_cfg = atc2609a_regmap_config; + atc260x->regmap_irq_chip = &atc2609a_regmap_irq_chip; + atc260x->cells = atc2609a_mfd_cells; + atc260x->nr_cells = ARRAY_SIZE(atc2609a_mfd_cells); + atc260x->type_name = "atc2609a"; + atc260x->rev_reg = ATC2609A_CHIP_VER; + atc260x->init_regs = &atc2609a_init_regs; + break; + default: + dev_err(dev, "Unsupported ATC260x device type: %u\n", + atc260x->ic_type); + return -EINVAL; + } + + atc260x->regmap_mutex = devm_kzalloc(dev, sizeof(*atc260x->regmap_mutex), + GFP_KERNEL); + if (!atc260x->regmap_mutex) + return -ENOMEM; + + mutex_init(atc260x->regmap_mutex); + + regmap_cfg->lock = regmap_lock_mutex, + regmap_cfg->unlock = regmap_unlock_mutex, + regmap_cfg->lock_arg = atc260x->regmap_mutex; + + return 0; +} +EXPORT_SYMBOL_GPL(atc260x_match_device); + +/** + * atc260x_device_probe(): Probe a configured ATC260x device + * + * @atc260x: ATC260x device to probe (must be configured) + * + * This function lets the ATC260x core register the ATC260x MFD devices + * and IRQCHIP. The ATC260x device passed in must be fully configured + * with atc260x_match_device, its IRQ set, and regmap created. + */ +int atc260x_device_probe(struct atc260x *atc260x) +{ + struct device *dev = atc260x->dev; + unsigned int chip_rev; + int ret; + + if (!atc260x->irq) { + dev_err(dev, "No interrupt support\n"); + return -EINVAL; + } + + /* Initialize the hardware */ + atc260x_dev_init(atc260x); + + ret = regmap_read(atc260x->regmap, atc260x->rev_reg, &chip_rev); + if (ret) { + dev_err(dev, "Failed to get chip revision\n"); + return ret; + } + + if (chip_rev > ATC260X_CHIP_REV_MAX) { + dev_err(dev, "Unknown chip revision: %u\n", chip_rev); + return -EINVAL; + } + + atc260x->ic_ver = __ffs(chip_rev + 1U); + + dev_info(dev, "Detected chip type %s rev.%c\n", + atc260x->type_name, 'A' + atc260x->ic_ver); + + ret = devm_regmap_add_irq_chip(dev, atc260x->regmap, atc260x->irq, IRQF_ONESHOT, + -1, atc260x->regmap_irq_chip, &atc260x->irq_data); + if (ret) { + dev_err(dev, "Failed to add IRQ chip: %d\n", ret); + return ret; + } + + ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, + atc260x->cells, atc260x->nr_cells, NULL, 0, + regmap_irq_get_domain(atc260x->irq_data)); + if (ret) { + dev_err(dev, "Failed to add child devices: %d\n", ret); + regmap_del_irq_chip(atc260x->irq, atc260x->irq_data); + } + + return ret; +} +EXPORT_SYMBOL_GPL(atc260x_device_probe); + +MODULE_DESCRIPTION("ATC260x PMICs Core support"); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_AUTHOR("Cristian Ciocaltea "); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/atc260x-i2c.c b/drivers/mfd/atc260x-i2c.c new file mode 100644 index 000000000000..362005703367 --- /dev/null +++ b/drivers/mfd/atc260x-i2c.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * I2C bus interface for ATC260x PMICs + * + * Copyright (C) 2019 Manivannan Sadhasivam + * Copyright (C) 2020 Cristian Ciocaltea + */ + +#include +#include +#include +#include +#include + +static int atc260x_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct atc260x *atc260x; + struct regmap_config regmap_cfg; + int ret; + + atc260x = devm_kzalloc(&client->dev, sizeof(*atc260x), GFP_KERNEL); + if (!atc260x) + return -ENOMEM; + + atc260x->dev = &client->dev; + atc260x->irq = client->irq; + + ret = atc260x_match_device(atc260x, ®map_cfg); + if (ret) + return ret; + + i2c_set_clientdata(client, atc260x); + + atc260x->regmap = devm_regmap_init_i2c(client, ®map_cfg); + if (IS_ERR(atc260x->regmap)) { + ret = PTR_ERR(atc260x->regmap); + dev_err(&client->dev, "failed to init regmap: %d\n", ret); + return ret; + } + + return atc260x_device_probe(atc260x); +} + +const struct of_device_id atc260x_i2c_of_match[] = { + { .compatible = "actions,atc2603c", .data = (void *)ATC2603C }, + { .compatible = "actions,atc2609a", .data = (void *)ATC2609A }, + { } +}; +MODULE_DEVICE_TABLE(of, atc260x_i2c_of_match); + +static struct i2c_driver atc260x_i2c_driver = { + .driver = { + .name = "atc260x", + .of_match_table = of_match_ptr(atc260x_i2c_of_match), + }, + .probe = atc260x_i2c_probe, +}; +module_i2c_driver(atc260x_i2c_driver); + +MODULE_DESCRIPTION("ATC260x PMICs I2C bus interface"); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_AUTHOR("Cristian Ciocaltea "); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/atc260x/atc2603c.h b/include/linux/mfd/atc260x/atc2603c.h new file mode 100644 index 000000000000..07ac640ef3e1 --- /dev/null +++ b/include/linux/mfd/atc260x/atc2603c.h @@ -0,0 +1,281 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * ATC2603C PMIC register definitions + * + * Copyright (C) 2020 Cristian Ciocaltea + */ + +#ifndef __LINUX_MFD_ATC260X_ATC2603C_H +#define __LINUX_MFD_ATC260X_ATC2603C_H + +enum atc2603c_irq_def { + ATC2603C_IRQ_AUDIO = 0, + ATC2603C_IRQ_OV, + ATC2603C_IRQ_OC, + ATC2603C_IRQ_OT, + ATC2603C_IRQ_UV, + ATC2603C_IRQ_ALARM, + ATC2603C_IRQ_ONOFF, + ATC2603C_IRQ_SGPIO, + ATC2603C_IRQ_IR, + ATC2603C_IRQ_REMCON, + ATC2603C_IRQ_POWER_IN, +}; + +/* PMU Registers */ +#define ATC2603C_PMU_SYS_CTL0 0x00 +#define ATC2603C_PMU_SYS_CTL1 0x01 +#define ATC2603C_PMU_SYS_CTL2 0x02 +#define ATC2603C_PMU_SYS_CTL3 0x03 +#define ATC2603C_PMU_SYS_CTL4 0x04 +#define ATC2603C_PMU_SYS_CTL5 0x05 +#define ATC2603C_PMU_SYS_CTL6 0x06 +#define ATC2603C_PMU_SYS_CTL7 0x07 +#define ATC2603C_PMU_SYS_CTL8 0x08 +#define ATC2603C_PMU_SYS_CTL9 0x09 +#define ATC2603C_PMU_BAT_CTL0 0x0A +#define ATC2603C_PMU_BAT_CTL1 0x0B +#define ATC2603C_PMU_VBUS_CTL0 0x0C +#define ATC2603C_PMU_VBUS_CTL1 0x0D +#define ATC2603C_PMU_WALL_CTL0 0x0E +#define ATC2603C_PMU_WALL_CTL1 0x0F +#define ATC2603C_PMU_SYS_PENDING 0x10 +#define ATC2603C_PMU_DC1_CTL0 0x11 +#define ATC2603C_PMU_DC1_CTL1 0x12 // Undocumented +#define ATC2603C_PMU_DC1_CTL2 0x13 // Undocumented +#define ATC2603C_PMU_DC2_CTL0 0x14 +#define ATC2603C_PMU_DC2_CTL1 0x15 // Undocumented +#define ATC2603C_PMU_DC2_CTL2 0x16 // Undocumented +#define ATC2603C_PMU_DC3_CTL0 0x17 +#define ATC2603C_PMU_DC3_CTL1 0x18 // Undocumented +#define ATC2603C_PMU_DC3_CTL2 0x19 // Undocumented +#define ATC2603C_PMU_DC4_CTL0 0x1A // Undocumented +#define ATC2603C_PMU_DC4_CTL1 0x1B // Undocumented +#define ATC2603C_PMU_DC5_CTL0 0x1C // Undocumented +#define ATC2603C_PMU_DC5_CTL1 0x1D // Undocumented +#define ATC2603C_PMU_LDO1_CTL 0x1E +#define ATC2603C_PMU_LDO2_CTL 0x1F +#define ATC2603C_PMU_LDO3_CTL 0x20 +#define ATC2603C_PMU_LDO4_CTL 0x21 // Undocumented +#define ATC2603C_PMU_LDO5_CTL 0x22 +#define ATC2603C_PMU_LDO6_CTL 0x23 +#define ATC2603C_PMU_LDO7_CTL 0x24 +#define ATC2603C_PMU_LDO8_CTL 0x25 // Undocumented +#define ATC2603C_PMU_LDO9_CTL 0x26 // Undocumented +#define ATC2603C_PMU_LDO10_CTL 0x27 // Undocumented +#define ATC2603C_PMU_LDO11_CTL 0x28 +#define ATC2603C_PMU_SWITCH_CTL 0x29 +#define ATC2603C_PMU_OV_CTL0 0x2A +#define ATC2603C_PMU_OV_CTL1 0x2B +#define ATC2603C_PMU_OV_STATUS 0x2C +#define ATC2603C_PMU_OV_EN 0x2D +#define ATC2603C_PMU_OV_INT_EN 0x2E +#define ATC2603C_PMU_OC_CTL 0x2F +#define ATC2603C_PMU_OC_STATUS 0x30 +#define ATC2603C_PMU_OC_EN 0x31 +#define ATC2603C_PMU_OC_INT_EN 0x32 +#define ATC2603C_PMU_UV_CTL0 0x33 +#define ATC2603C_PMU_UV_CTL1 0x34 +#define ATC2603C_PMU_UV_STATUS 0x35 +#define ATC2603C_PMU_UV_EN 0x36 +#define ATC2603C_PMU_UV_INT_EN 0x37 +#define ATC2603C_PMU_OT_CTL 0x38 +#define ATC2603C_PMU_CHARGER_CTL0 0x39 +#define ATC2603C_PMU_CHARGER_CTL1 0x3A +#define ATC2603C_PMU_CHARGER_CTL2 0x3B +#define ATC2603C_PMU_BAKCHARGER_CTL 0x3C // Undocumented +#define ATC2603C_PMU_APDS_CTL 0x3D +#define ATC2603C_PMU_AUXADC_CTL0 0x3E +#define ATC2603C_PMU_AUXADC_CTL1 0x3F +#define ATC2603C_PMU_BATVADC 0x40 +#define ATC2603C_PMU_BATIADC 0x41 +#define ATC2603C_PMU_WALLVADC 0x42 +#define ATC2603C_PMU_WALLIADC 0x43 +#define ATC2603C_PMU_VBUSVADC 0x44 +#define ATC2603C_PMU_VBUSIADC 0x45 +#define ATC2603C_PMU_SYSPWRADC 0x46 +#define ATC2603C_PMU_REMCONADC 0x47 +#define ATC2603C_PMU_SVCCADC 0x48 +#define ATC2603C_PMU_CHGIADC 0x49 +#define ATC2603C_PMU_IREFADC 0x4A +#define ATC2603C_PMU_BAKBATADC 0x4B +#define ATC2603C_PMU_ICTEMPADC 0x4C +#define ATC2603C_PMU_AUXADC0 0x4D +#define ATC2603C_PMU_AUXADC1 0x4E +#define ATC2603C_PMU_AUXADC2 0x4F +#define ATC2603C_PMU_ICMADC 0x50 +#define ATC2603C_PMU_BDG_CTL 0x51 // Undocumented +#define ATC2603C_RTC_CTL 0x52 +#define ATC2603C_RTC_MSALM 0x53 +#define ATC2603C_RTC_HALM 0x54 +#define ATC2603C_RTC_YMDALM 0x55 +#define ATC2603C_RTC_MS 0x56 +#define ATC2603C_RTC_H 0x57 +#define ATC2603C_RTC_DC 0x58 +#define ATC2603C_RTC_YMD 0x59 +#define ATC2603C_EFUSE_DAT 0x5A // Undocumented +#define ATC2603C_EFUSECRTL1 0x5B // Undocumented +#define ATC2603C_EFUSECRTL2 0x5C // Undocumented +#define ATC2603C_PMU_FW_USE0 0x5D // Undocumented +#define ATC2603C_PMU_FW_USE1 0x5E // Undocumented +#define ATC2603C_PMU_FW_USE2 0x5F // Undocumented +#define ATC2603C_PMU_FW_USE3 0x60 // Undocumented +#define ATC2603C_PMU_FW_USE4 0x61 // Undocumented +#define ATC2603C_PMU_ABNORMAL_STATUS 0x62 +#define ATC2603C_PMU_WALL_APDS_CTL 0x63 +#define ATC2603C_PMU_REMCON_CTL0 0x64 +#define ATC2603C_PMU_REMCON_CTL1 0x65 +#define ATC2603C_PMU_MUX_CTL0 0x66 +#define ATC2603C_PMU_SGPIO_CTL0 0x67 +#define ATC2603C_PMU_SGPIO_CTL1 0x68 +#define ATC2603C_PMU_SGPIO_CTL2 0x69 +#define ATC2603C_PMU_SGPIO_CTL3 0x6A +#define ATC2603C_PMU_SGPIO_CTL4 0x6B +#define ATC2603C_PWMCLK_CTL 0x6C +#define ATC2603C_PWM0_CTL 0x6D +#define ATC2603C_PWM1_CTL 0x6E +#define ATC2603C_PMU_ADC_DBG0 0x70 +#define ATC2603C_PMU_ADC_DBG1 0x71 +#define ATC2603C_PMU_ADC_DBG2 0x72 +#define ATC2603C_PMU_ADC_DBG3 0x73 +#define ATC2603C_PMU_ADC_DBG4 0x74 +#define ATC2603C_IRC_CTL 0x80 +#define ATC2603C_IRC_STAT 0x81 +#define ATC2603C_IRC_CC 0x82 +#define ATC2603C_IRC_KDC 0x83 +#define ATC2603C_IRC_WK 0x84 +#define ATC2603C_IRC_RCC 0x85 +#define ATC2603C_IRC_FILTER 0x86 + +/* AUDIO_OUT Registers */ +#define ATC2603C_AUDIOINOUT_CTL 0xA0 +#define ATC2603C_AUDIO_DEBUGOUTCTL 0xA1 +#define ATC2603C_DAC_DIGITALCTL 0xA2 +#define ATC2603C_DAC_VOLUMECTL0 0xA3 +#define ATC2603C_DAC_ANALOG0 0xA4 +#define ATC2603C_DAC_ANALOG1 0xA5 +#define ATC2603C_DAC_ANALOG2 0xA6 +#define ATC2603C_DAC_ANALOG3 0xA7 + +/* AUDIO_IN Registers */ +#define ATC2603C_ADC_DIGITALCTL 0xA8 +#define ATC2603C_ADC_HPFCTL 0xA9 +#define ATC2603C_ADC_CTL 0xAA +#define ATC2603C_AGC_CTL0 0xAB +#define ATC2603C_AGC_CTL1 0xAC // Undocumented +#define ATC2603C_AGC_CTL2 0xAD +#define ATC2603C_ADC_ANALOG0 0xAE +#define ATC2603C_ADC_ANALOG1 0xAF + +/* PCM_IF Registers */ +#define ATC2603C_PCM0_CTL 0xB0 // Undocumented +#define ATC2603C_PCM1_CTL 0xB1 // Undocumented +#define ATC2603C_PCM2_CTL 0xB2 // Undocumented +#define ATC2603C_PCMIF_CTL 0xB3 // Undocumented + +/* CMU_CONTROL Registers */ +#define ATC2603C_CMU_DEVRST 0xC1 // Undocumented + +/* INTS Registers */ +#define ATC2603C_INTS_PD 0xC8 +#define ATC2603C_INTS_MSK 0xC9 + +/* MFP Registers */ +#define ATC2603C_MFP_CTL 0xD0 +#define ATC2603C_PAD_VSEL 0xD1 // Undocumented +#define ATC2603C_GPIO_OUTEN 0xD2 +#define ATC2603C_GPIO_INEN 0xD3 +#define ATC2603C_GPIO_DAT 0xD4 +#define ATC2603C_PAD_DRV 0xD5 +#define ATC2603C_PAD_EN 0xD6 +#define ATC2603C_DEBUG_SEL 0xD7 // Undocumented +#define ATC2603C_DEBUG_IE 0xD8 // Undocumented +#define ATC2603C_DEBUG_OE 0xD9 // Undocumented +#define ATC2603C_BIST_START 0x0A // Undocumented +#define ATC2603C_BIST_RESULT 0x0B // Undocumented +#define ATC2603C_CHIP_VER 0xDC + +/* TWSI Registers */ +#define ATC2603C_SADDR 0xFF + +/* PMU_SYS_CTL0 Register Mask Bits */ +#define ATC2603C_PMU_SYS_CTL0_IR_WK_EN BIT(5) +#define ATC2603C_PMU_SYS_CTL0_RESET_WK_EN BIT(6) +#define ATC2603C_PMU_SYS_CTL0_HDSW_WK_EN BIT(7) +#define ATC2603C_PMU_SYS_CTL0_ALARM_WK_EN BIT(8) +#define ATC2603C_PMU_SYS_CTL0_REM_CON_WK_EN BIT(9) +#define ATC2603C_PMU_SYS_CTL0_RESTART_EN BIT(10) +#define ATC2603C_PMU_SYS_CTL0_SGPIOIRQ_WK_EN BIT(11) +#define ATC2603C_PMU_SYS_CTL0_ONOFF_SHORT_WK_EN BIT(12) +#define ATC2603C_PMU_SYS_CTL0_ONOFF_LONG_WK_EN BIT(13) +#define ATC2603C_PMU_SYS_CTL0_WALL_WK_EN BIT(14) +#define ATC2603C_PMU_SYS_CTL0_USB_WK_EN BIT(15) +#define ATC2603C_PMU_SYS_CTL0_WK_ALL (GENMASK(15, 5) & (~BIT(10))) + +/* PMU_SYS_CTL1 Register Mask Bits */ +#define ATC2603C_PMU_SYS_CTL1_EN_S1 BIT(0) +#define ATC2603C_PMU_SYS_CTL1_LB_S4_EN BIT(2) +#define ATC2603C_PMU_SYS_CTL1_LB_S4 GENMASK(4, 3) +#define ATC2603C_PMU_SYS_CTL1_LB_S4_3_1V BIT(4) +#define ATC2603C_PMU_SYS_CTL1_IR_WK_FLAG BIT(5) +#define ATC2603C_PMU_SYS_CTL1_RESET_WK_FLAG BIT(6) +#define ATC2603C_PMU_SYS_CTL1_HDSW_WK_FLAG BIT(7) +#define ATC2603C_PMU_SYS_CTL1_ALARM_WK_FLAG BIT(8) +#define ATC2603C_PMU_SYS_CTL1_REM_CON_WK_FLAG BIT(9) +#define ATC2603C_PMU_SYS_CTL1_ONOFF_PRESS_RESET_IRQ_PD BIT(10) +#define ATC2603C_PMU_SYS_CTL1_SGPIOIRQ_WK_FLAG BIT(11) +#define ATC2603C_PMU_SYS_CTL1_ONOFF_SHORT_WK_FLAG BIT(12) +#define ATC2603C_PMU_SYS_CTL1_ONOFF_LONG_WK_FLAG BIT(13) +#define ATC2603C_PMU_SYS_CTL1_WALL_WK_FLAG BIT(14) +#define ATC2603C_PMU_SYS_CTL1_USB_WK_FLAG BIT(15) + +/* PMU_SYS_CTL2 Register Mask Bits */ +#define ATC2603C_PMU_SYS_CTL2_PMU_A_EN BIT(0) +#define ATC2603C_PMU_SYS_CTL2_ONOFF_PRESS_INT_EN BIT(1) +#define ATC2603C_PMU_SYS_CTL2_ONOFF_PRESS_PD BIT(2) +#define ATC2603C_PMU_SYS_CTL2_S2TIMER GENMASK(5, 3) +#define ATC2603C_PMU_SYS_CTL2_S2_TIMER_EN BIT(6) +#define ATC2603C_PMU_SYS_CTL2_ONOFF_RESET_TIME_SEL GENMASK(8, 7) +#define ATC2603C_PMU_SYS_CTL2_ONOFF_PRESS_RESET_EN BIT(9) +#define ATC2603C_PMU_SYS_CTL2_ONOFF_PRESS_TIME GENMASK(11, 10) +#define ATC2603C_PMU_SYS_CTL2_ONOFF_INT_EN BIT(12) +#define ATC2603C_PMU_SYS_CTL2_ONOFF_LONG_PRESS BIT(13) +#define ATC2603C_PMU_SYS_CTL2_ONOFF_SHORT_PRESS BIT(14) +#define ATC2603C_PMU_SYS_CTL2_ONOFF_PRESS BIT(15) + +/* PMU_SYS_CTL3 Register Mask Bits */ +#define ATC2603C_PMU_SYS_CTL3_S2S3TOS1_TIMER GENMASK(8, 7) +#define ATC2603C_PMU_SYS_CTL3_S2S3TOS1_TIMER_EN BIT(9) +#define ATC2603C_PMU_SYS_CTL3_S3_TIMER GENMASK(12, 10) +#define ATC2603C_PMU_SYS_CTL3_S3_TIMER_EN BIT(13) +#define ATC2603C_PMU_SYS_CTL3_EN_S3 BIT(14) +#define ATC2603C_PMU_SYS_CTL3_EN_S2 BIT(15) + +/* PMU_SYS_CTL5 Register Mask Bits */ +#define ATC2603C_PMU_SYS_CTL5_WALLWKDTEN BIT(7) +#define ATC2603C_PMU_SYS_CTL5_VBUSWKDTEN BIT(8) +#define ATC2603C_PMU_SYS_CTL5_REMCON_DECT_EN BIT(9) +#define ATC2603C_PMU_SYS_CTL5_ONOFF_8S_SEL BIT(10) + +/* INTS_MSK Register Mask Bits */ +#define ATC2603C_INTS_MSK_AUDIO BIT(0) +#define ATC2603C_INTS_MSK_OV BIT(1) +#define ATC2603C_INTS_MSK_OC BIT(2) +#define ATC2603C_INTS_MSK_OT BIT(3) +#define ATC2603C_INTS_MSK_UV BIT(4) +#define ATC2603C_INTS_MSK_ALARM BIT(5) +#define ATC2603C_INTS_MSK_ONOFF BIT(6) +#define ATC2603C_INTS_MSK_SGPIO BIT(7) +#define ATC2603C_INTS_MSK_IR BIT(8) +#define ATC2603C_INTS_MSK_REMCON BIT(9) +#define ATC2603C_INTS_MSK_POWERIN BIT(10) + +/* CMU_DEVRST Register Mask Bits */ +#define ATC2603C_CMU_DEVRST_MFP BIT(1) +#define ATC2603C_CMU_DEVRST_INTS BIT(2) +#define ATC2603C_CMU_DEVRST_AUDIO BIT(4) + +/* PAD_EN Register Mask Bits */ +#define ATC2603C_PAD_EN_EXTIRQ BIT(0) + +#endif /* __LINUX_MFD_ATC260X_ATC2603C_H */ diff --git a/include/linux/mfd/atc260x/atc2609a.h b/include/linux/mfd/atc260x/atc2609a.h new file mode 100644 index 000000000000..b957d7bd73e9 --- /dev/null +++ b/include/linux/mfd/atc260x/atc2609a.h @@ -0,0 +1,308 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * ATC2609A PMIC register definitions + * + * Copyright (C) 2019 Manivannan Sadhasivam + */ + +#ifndef __LINUX_MFD_ATC260X_ATC2609A_H +#define __LINUX_MFD_ATC260X_ATC2609A_H + +enum atc2609a_irq_def { + ATC2609A_IRQ_AUDIO = 0, + ATC2609A_IRQ_OV, + ATC2609A_IRQ_OC, + ATC2609A_IRQ_OT, + ATC2609A_IRQ_UV, + ATC2609A_IRQ_ALARM, + ATC2609A_IRQ_ONOFF, + ATC2609A_IRQ_WKUP, + ATC2609A_IRQ_IR, + ATC2609A_IRQ_REMCON, + ATC2609A_IRQ_POWER_IN, +}; + +/* PMU Registers */ +#define ATC2609A_PMU_SYS_CTL0 0x00 +#define ATC2609A_PMU_SYS_CTL1 0x01 +#define ATC2609A_PMU_SYS_CTL2 0x02 +#define ATC2609A_PMU_SYS_CTL3 0x03 +#define ATC2609A_PMU_SYS_CTL4 0x04 +#define ATC2609A_PMU_SYS_CTL5 0x05 +#define ATC2609A_PMU_SYS_CTL6 0x06 +#define ATC2609A_PMU_SYS_CTL7 0x07 +#define ATC2609A_PMU_SYS_CTL8 0x08 +#define ATC2609A_PMU_SYS_CTL9 0x09 +#define ATC2609A_PMU_BAT_CTL0 0x0A +#define ATC2609A_PMU_BAT_CTL1 0x0B +#define ATC2609A_PMU_VBUS_CTL0 0x0C +#define ATC2609A_PMU_VBUS_CTL1 0x0D +#define ATC2609A_PMU_WALL_CTL0 0x0E +#define ATC2609A_PMU_WALL_CTL1 0x0F +#define ATC2609A_PMU_SYS_PENDING 0x10 +#define ATC2609A_PMU_APDS_CTL0 0x11 +#define ATC2609A_PMU_APDS_CTL1 0x12 +#define ATC2609A_PMU_APDS_CTL2 0x13 +#define ATC2609A_PMU_CHARGER_CTL 0x14 +#define ATC2609A_PMU_BAKCHARGER_CTL 0x15 +#define ATC2609A_PMU_SWCHG_CTL0 0x16 +#define ATC2609A_PMU_SWCHG_CTL1 0x17 +#define ATC2609A_PMU_SWCHG_CTL2 0x18 +#define ATC2609A_PMU_SWCHG_CTL3 0x19 +#define ATC2609A_PMU_SWCHG_CTL4 0x1A +#define ATC2609A_PMU_DC_OSC 0x1B +#define ATC2609A_PMU_DC0_CTL0 0x1C +#define ATC2609A_PMU_DC0_CTL1 0x1D +#define ATC2609A_PMU_DC0_CTL2 0x1E +#define ATC2609A_PMU_DC0_CTL3 0x1F +#define ATC2609A_PMU_DC0_CTL4 0x20 +#define ATC2609A_PMU_DC0_CTL5 0x21 +#define ATC2609A_PMU_DC0_CTL6 0x22 +#define ATC2609A_PMU_DC1_CTL0 0x23 +#define ATC2609A_PMU_DC1_CTL1 0x24 +#define ATC2609A_PMU_DC1_CTL2 0x25 +#define ATC2609A_PMU_DC1_CTL3 0x26 +#define ATC2609A_PMU_DC1_CTL4 0x27 +#define ATC2609A_PMU_DC1_CTL5 0x28 +#define ATC2609A_PMU_DC1_CTL6 0x29 +#define ATC2609A_PMU_DC2_CTL0 0x2A +#define ATC2609A_PMU_DC2_CTL1 0x2B +#define ATC2609A_PMU_DC2_CTL2 0x2C +#define ATC2609A_PMU_DC2_CTL3 0x2D +#define ATC2609A_PMU_DC2_CTL4 0x2E +#define ATC2609A_PMU_DC2_CTL5 0x2F +#define ATC2609A_PMU_DC2_CTL6 0x30 +#define ATC2609A_PMU_DC3_CTL0 0x31 +#define ATC2609A_PMU_DC3_CTL1 0x32 +#define ATC2609A_PMU_DC3_CTL2 0x33 +#define ATC2609A_PMU_DC3_CTL3 0x34 +#define ATC2609A_PMU_DC3_CTL4 0x35 +#define ATC2609A_PMU_DC3_CTL5 0x36 +#define ATC2609A_PMU_DC3_CTL6 0x37 +#define ATC2609A_PMU_DC_ZR 0x38 +#define ATC2609A_PMU_LDO0_CTL0 0x39 +#define ATC2609A_PMU_LDO0_CTL1 0x3A +#define ATC2609A_PMU_LDO1_CTL0 0x3B +#define ATC2609A_PMU_LDO1_CTL1 0x3C +#define ATC2609A_PMU_LDO2_CTL0 0x3D +#define ATC2609A_PMU_LDO2_CTL1 0x3E +#define ATC2609A_PMU_LDO3_CTL0 0x3F +#define ATC2609A_PMU_LDO3_CTL1 0x40 +#define ATC2609A_PMU_LDO4_CTL0 0x41 +#define ATC2609A_PMU_LDO4_CTL1 0x42 +#define ATC2609A_PMU_LDO5_CTL0 0x43 +#define ATC2609A_PMU_LDO5_CTL1 0x44 +#define ATC2609A_PMU_LDO6_CTL0 0x45 +#define ATC2609A_PMU_LDO6_CTL1 0x46 +#define ATC2609A_PMU_LDO7_CTL0 0x47 +#define ATC2609A_PMU_LDO7_CTL1 0x48 +#define ATC2609A_PMU_LDO8_CTL0 0x49 +#define ATC2609A_PMU_LDO8_CTL1 0x4A +#define ATC2609A_PMU_LDO9_CTL 0x4B +#define ATC2609A_PMU_OV_INT_EN 0x4C +#define ATC2609A_PMU_OV_STATUS 0x4D +#define ATC2609A_PMU_UV_INT_EN 0x4E +#define ATC2609A_PMU_UV_STATUS 0x4F +#define ATC2609A_PMU_OC_INT_EN 0x50 +#define ATC2609A_PMU_OC_STATUS 0x51 +#define ATC2609A_PMU_OT_CTL 0x52 +#define ATC2609A_PMU_CM_CTL0 0x53 +#define ATC2609A_PMU_FW_USE0 0x54 +#define ATC2609A_PMU_FW_USE1 0x55 +#define ATC2609A_PMU_ADC12B_I 0x56 +#define ATC2609A_PMU_ADC12B_V 0x57 +#define ATC2609A_PMU_ADC12B_DUMMY 0x58 +#define ATC2609A_PMU_AUXADC_CTL0 0x59 +#define ATC2609A_PMU_AUXADC_CTL1 0x5A +#define ATC2609A_PMU_BATVADC 0x5B +#define ATC2609A_PMU_BATIADC 0x5C +#define ATC2609A_PMU_WALLVADC 0x5D +#define ATC2609A_PMU_WALLIADC 0x5E +#define ATC2609A_PMU_VBUSVADC 0x5F +#define ATC2609A_PMU_VBUSIADC 0x60 +#define ATC2609A_PMU_SYSPWRADC 0x61 +#define ATC2609A_PMU_REMCONADC 0x62 +#define ATC2609A_PMU_SVCCADC 0x63 +#define ATC2609A_PMU_CHGIADC 0x64 +#define ATC2609A_PMU_IREFADC 0x65 +#define ATC2609A_PMU_BAKBATADC 0x66 +#define ATC2609A_PMU_ICTEMPADC 0x67 +#define ATC2609A_PMU_AUXADC0 0x68 +#define ATC2609A_PMU_AUXADC1 0x69 +#define ATC2609A_PMU_AUXADC2 0x6A +#define ATC2609A_PMU_AUXADC3 0x6B +#define ATC2609A_PMU_ICTEMPADC_ADJ 0x6C +#define ATC2609A_PMU_BDG_CTL 0x6D +#define ATC2609A_RTC_CTL 0x6E +#define ATC2609A_RTC_MSALM 0x6F +#define ATC2609A_RTC_HALM 0x70 +#define ATC2609A_RTC_YMDALM 0x71 +#define ATC2609A_RTC_MS 0x72 +#define ATC2609A_RTC_H 0x73 +#define ATC2609A_RTC_DC 0x74 +#define ATC2609A_RTC_YMD 0x75 +#define ATC2609A_EFUSE_DAT 0x76 +#define ATC2609A_EFUSECRTL1 0x77 +#define ATC2609A_EFUSECRTL2 0x78 +#define ATC2609A_PMU_DC4_CTL0 0x79 +#define ATC2609A_PMU_DC4_CTL1 0x7A +#define ATC2609A_PMU_DC4_CTL2 0x7B +#define ATC2609A_PMU_DC4_CTL3 0x7C +#define ATC2609A_PMU_DC4_CTL4 0x7D +#define ATC2609A_PMU_DC4_CTL5 0x7E +#define ATC2609A_PMU_DC4_CTL6 0x7F +#define ATC2609A_PMU_PWR_STATUS 0x80 +#define ATC2609A_PMU_S2_PWR 0x81 +#define ATC2609A_CLMT_CTL0 0x82 +#define ATC2609A_CLMT_DATA0 0x83 +#define ATC2609A_CLMT_DATA1 0x84 +#define ATC2609A_CLMT_DATA2 0x85 +#define ATC2609A_CLMT_DATA3 0x86 +#define ATC2609A_CLMT_ADD0 0x87 +#define ATC2609A_CLMT_ADD1 0x88 +#define ATC2609A_CLMT_OCV_TABLE 0x89 +#define ATC2609A_CLMT_R_TABLE 0x8A +#define ATC2609A_PMU_PWRON_CTL0 0x8D +#define ATC2609A_PMU_PWRON_CTL1 0x8E +#define ATC2609A_PMU_PWRON_CTL2 0x8F +#define ATC2609A_IRC_CTL 0x90 +#define ATC2609A_IRC_STAT 0x91 +#define ATC2609A_IRC_CC 0x92 +#define ATC2609A_IRC_KDC 0x93 +#define ATC2609A_IRC_WK 0x94 +#define ATC2609A_IRC_RCC 0x95 + +/* AUDIO_OUT Registers */ +#define ATC2609A_AUDIOINOUT_CTL 0xA0 +#define ATC2609A_AUDIO_DEBUGOUTCTL 0xA1 +#define ATC2609A_DAC_DIGITALCTL 0xA2 +#define ATC2609A_DAC_VOLUMECTL0 0xA3 +#define ATC2609A_DAC_ANALOG0 0xA4 +#define ATC2609A_DAC_ANALOG1 0xA5 +#define ATC2609A_DAC_ANALOG2 0xA6 +#define ATC2609A_DAC_ANALOG3 0xA7 + +/* AUDIO_IN Registers */ +#define ATC2609A_ADC_DIGITALCTL 0xA8 +#define ATC2609A_ADC_HPFCTL 0xA9 +#define ATC2609A_ADC_CTL 0xAA +#define ATC2609A_AGC_CTL0 0xAB +#define ATC2609A_AGC_CTL1 0xAC +#define ATC2609A_AGC_CTL2 0xAD +#define ATC2609A_ADC_ANALOG0 0xAE +#define ATC2609A_ADC_ANALOG1 0xAF + +/* PCM_IF Registers */ +#define ATC2609A_PCM0_CTL 0xB0 +#define ATC2609A_PCM1_CTL 0xB1 +#define ATC2609A_PCM2_CTL 0xB2 +#define ATC2609A_PCMIF_CTL 0xB3 + +/* CMU_CONTROL Registers */ +#define ATC2609A_CMU_DEVRST 0xC1 + +/* INTS Registers */ +#define ATC2609A_INTS_PD 0xC8 +#define ATC2609A_INTS_MSK 0xC9 + +/* MFP Registers */ +#define ATC2609A_MFP_CTL 0xD0 +#define ATC2609A_PAD_VSEL 0xD1 +#define ATC2609A_GPIO_OUTEN 0xD2 +#define ATC2609A_GPIO_INEN 0xD3 +#define ATC2609A_GPIO_DAT 0xD4 +#define ATC2609A_PAD_DRV 0xD5 +#define ATC2609A_PAD_EN 0xD6 +#define ATC2609A_DEBUG_SEL 0xD7 +#define ATC2609A_DEBUG_IE 0xD8 +#define ATC2609A_DEBUG_OE 0xD9 +#define ATC2609A_CHIP_VER 0xDC + +/* PWSI Registers */ +#define ATC2609A_PWSI_CTL 0xF0 +#define ATC2609A_PWSI_STATUS 0xF1 + +/* TWSI Registers */ +#define ATC2609A_SADDR 0xFF + +/* PMU_SYS_CTL0 Register Mask Bits */ +#define ATC2609A_PMU_SYS_CTL0_IR_WK_EN BIT(5) +#define ATC2609A_PMU_SYS_CTL0_RESET_WK_EN BIT(6) +#define ATC2609A_PMU_SYS_CTL0_HDSW_WK_EN BIT(7) +#define ATC2609A_PMU_SYS_CTL0_ALARM_WK_EN BIT(8) +#define ATC2609A_PMU_SYS_CTL0_REM_CON_WK_EN BIT(9) +#define ATC2609A_PMU_SYS_CTL0_RESTART_EN BIT(10) +#define ATC2609A_PMU_SYS_CTL0_WKIRQ_WK_EN BIT(11) +#define ATC2609A_PMU_SYS_CTL0_ONOFF_SHORT_WK_EN BIT(12) +#define ATC2609A_PMU_SYS_CTL0_ONOFF_LONG_WK_EN BIT(13) +#define ATC2609A_PMU_SYS_CTL0_WALL_WK_EN BIT(14) +#define ATC2609A_PMU_SYS_CTL0_USB_WK_EN BIT(15) +#define ATC2609A_PMU_SYS_CTL0_WK_ALL (GENMASK(15, 5) & (~BIT(10))) + +/* PMU_SYS_CTL1 Register Mask Bits */ +#define ATC2609A_PMU_SYS_CTL1_EN_S1 BIT(0) +#define ATC2609A_PMU_SYS_CTL1_LB_S4_EN BIT(2) +#define ATC2609A_PMU_SYS_CTL1_LB_S4 GENMASK(4, 3) +#define ATC2609A_PMU_SYS_CTL1_LB_S4_3_1V BIT(4) +#define ATC2609A_PMU_SYS_CTL1_IR_WK_FLAG BIT(5) +#define ATC2609A_PMU_SYS_CTL1_RESET_WK_FLAG BIT(6) +#define ATC2609A_PMU_SYS_CTL1_HDSW_WK_FLAG BIT(7) +#define ATC2609A_PMU_SYS_CTL1_ALARM_WK_FLAG BIT(8) +#define ATC2609A_PMU_SYS_CTL1_REM_CON_WK_FLAG BIT(9) +#define ATC2609A_PMU_SYS_CTL1_RESTART_WK_FLAG BIT(10) +#define ATC2609A_PMU_SYS_CTL1_WKIRQ_WK_FLAG BIT(11) +#define ATC2609A_PMU_SYS_CTL1_ONOFF_SHORT_WK_FLAG BIT(12) +#define ATC2609A_PMU_SYS_CTL1_ONOFF_LONG_WK_FLAG BIT(13) +#define ATC2609A_PMU_SYS_CTL1_WALL_WK_FLAG BIT(14) +#define ATC2609A_PMU_SYS_CTL1_USB_WK_FLAG BIT(15) + +/* PMU_SYS_CTL2 Register Mask Bits */ +#define ATC2609A_PMU_SYS_CTL2_PMU_A_EN BIT(0) +#define ATC2609A_PMU_SYS_CTL2_ONOFF_PRESS_INT_EN BIT(1) +#define ATC2609A_PMU_SYS_CTL2_ONOFF_PRESS_PD BIT(2) +#define ATC2609A_PMU_SYS_CTL2_S2TIMER GENMASK(5, 3) +#define ATC2609A_PMU_SYS_CTL2_S2_TIMER_EN BIT(6) +#define ATC2609A_PMU_SYS_CTL2_ONOFF_RESET_TIME_SEL GENMASK(8, 7) +#define ATC2609A_PMU_SYS_CTL2_ONOFF_RESET_EN BIT(9) +#define ATC2609A_PMU_SYS_CTL2_ONOFF_PRESS_TIME GENMASK(11, 10) +#define ATC2609A_PMU_SYS_CTL2_ONOFF_LSP_INT_EN BIT(12) +#define ATC2609A_PMU_SYS_CTL2_ONOFF_LONG_PRESS BIT(13) +#define ATC2609A_PMU_SYS_CTL2_ONOFF_SHORT_PRESS BIT(14) +#define ATC2609A_PMU_SYS_CTL2_ONOFF_PRESS BIT(15) + +/* PMU_SYS_CTL3 Register Mask Bits */ +#define ATC2609A_PMU_SYS_CTL3_S2S3TOS1_TIMER GENMASK(8, 7) +#define ATC2609A_PMU_SYS_CTL3_S2S3TOS1_TIMER_EN BIT(9) +#define ATC2609A_PMU_SYS_CTL3_S3_TIMER GENMASK(12, 10) +#define ATC2609A_PMU_SYS_CTL3_S3_TIMER_EN BIT(13) +#define ATC2609A_PMU_SYS_CTL3_EN_S3 BIT(14) +#define ATC2609A_PMU_SYS_CTL3_EN_S2 BIT(15) + +/* PMU_SYS_CTL5 Register Mask Bits */ +#define ATC2609A_PMU_SYS_CTL5_WALLWKDTEN BIT(7) +#define ATC2609A_PMU_SYS_CTL5_VBUSWKDTEN BIT(8) +#define ATC2609A_PMU_SYS_CTL5_REMCON_DECT_EN BIT(9) +#define ATC2609A_PMU_SYS_CTL5_ONOFF_8S_SEL BIT(10) + +/* INTS_MSK Register Mask Bits */ +#define ATC2609A_INTS_MSK_AUDIO BIT(0) +#define ATC2609A_INTS_MSK_OV BIT(1) +#define ATC2609A_INTS_MSK_OC BIT(2) +#define ATC2609A_INTS_MSK_OT BIT(3) +#define ATC2609A_INTS_MSK_UV BIT(4) +#define ATC2609A_INTS_MSK_ALARM BIT(5) +#define ATC2609A_INTS_MSK_ONOFF BIT(6) +#define ATC2609A_INTS_MSK_WKUP BIT(7) +#define ATC2609A_INTS_MSK_IR BIT(8) +#define ATC2609A_INTS_MSK_REMCON BIT(9) +#define ATC2609A_INTS_MSK_POWERIN BIT(10) + +/* CMU_DEVRST Register Mask Bits */ +#define ATC2609A_CMU_DEVRST_AUDIO BIT(0) +#define ATC2609A_CMU_DEVRST_MFP BIT(1) +#define ATC2609A_CMU_DEVRST_INTS BIT(2) + +/* PAD_EN Register Mask Bits */ +#define ATC2609A_PAD_EN_EXTIRQ BIT(0) + +#endif /* __LINUX_MFD_ATC260X_ATC2609A_H */ diff --git a/include/linux/mfd/atc260x/core.h b/include/linux/mfd/atc260x/core.h new file mode 100644 index 000000000000..777b6c345d44 --- /dev/null +++ b/include/linux/mfd/atc260x/core.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Core MFD defines for ATC260x PMICs + * + * Copyright (C) 2019 Manivannan Sadhasivam + * Copyright (C) 2020 Cristian Ciocaltea + */ + +#ifndef __LINUX_MFD_ATC260X_CORE_H +#define __LINUX_MFD_ATC260X_CORE_H + +#include +#include + +enum atc260x_type { + ATC2603A = 0, + ATC2603C, + ATC2609A, +}; + +enum atc260x_ver { + ATC260X_A = 0, + ATC260X_B, + ATC260X_C, + ATC260X_D, + ATC260X_E, + ATC260X_F, + ATC260X_G, + ATC260X_H, +}; + +struct atc260x { + struct device *dev; + + struct regmap *regmap; + const struct regmap_irq_chip *regmap_irq_chip; + struct regmap_irq_chip_data *irq_data; + + struct mutex *regmap_mutex; /* mutex for custom regmap locking */ + + const struct mfd_cell *cells; + int nr_cells; + int irq; + + enum atc260x_type ic_type; + enum atc260x_ver ic_ver; + const char *type_name; + unsigned int rev_reg; + + const struct atc260x_init_regs *init_regs; /* regs for device init */ +}; + +struct regmap_config; + +int atc260x_match_device(struct atc260x *atc260x, struct regmap_config *regmap_cfg); +int atc260x_device_probe(struct atc260x *atc260x); + +#endif /* __LINUX_MFD_ATC260X_CORE_H */ -- cgit v1.2.3-71-gd317 From 316d0d92fbc9b926bda8ce7ccc109de0dccb4d92 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Mon, 5 Apr 2021 14:40:44 +0300 Subject: mfd: bd718x7: simplify by cleaning unnecessary device data Most ROHM PMIC sub-devices only use the regmap pointer from parent device. They can obtain this by dev_get_regamap so in most cases the MFD device does not need to allocate and populate the driver data. Simplify drivers by removing this. The BD70528 still needs the access to watchdog mutex so keep rohm_regmap_dev in use on BD70528 RTC and WDG drivers for now. Signed-off-by: Matti Vaittinen Signed-off-by: Lee Jones --- drivers/mfd/rohm-bd718x7.c | 43 +++++++++++++++------------------------- include/linux/mfd/rohm-bd718x7.h | 13 ------------ 2 files changed, 16 insertions(+), 40 deletions(-) (limited to 'include/linux') diff --git a/drivers/mfd/rohm-bd718x7.c b/drivers/mfd/rohm-bd718x7.c index c32c1b6c98fa..bfd81f78beae 100644 --- a/drivers/mfd/rohm-bd718x7.c +++ b/drivers/mfd/rohm-bd718x7.c @@ -91,9 +91,9 @@ static const struct regmap_config bd718xx_regmap_config = { .cache_type = REGCACHE_RBTREE, }; -static int bd718xx_init_press_duration(struct bd718xx *bd718xx) +static int bd718xx_init_press_duration(struct regmap *regmap, + struct device *dev) { - struct device* dev = bd718xx->chip.dev; u32 short_press_ms, long_press_ms; u32 short_press_value, long_press_value; int ret; @@ -102,8 +102,7 @@ static int bd718xx_init_press_duration(struct bd718xx *bd718xx) &short_press_ms); if (!ret) { short_press_value = min(15u, (short_press_ms + 250) / 500); - ret = regmap_update_bits(bd718xx->chip.regmap, - BD718XX_REG_PWRONCONFIG0, + ret = regmap_update_bits(regmap, BD718XX_REG_PWRONCONFIG0, BD718XX_PWRBTN_PRESS_DURATION_MASK, short_press_value); if (ret) { @@ -116,8 +115,7 @@ static int bd718xx_init_press_duration(struct bd718xx *bd718xx) &long_press_ms); if (!ret) { long_press_value = min(15u, (long_press_ms + 500) / 1000); - ret = regmap_update_bits(bd718xx->chip.regmap, - BD718XX_REG_PWRONCONFIG1, + ret = regmap_update_bits(regmap, BD718XX_REG_PWRONCONFIG1, BD718XX_PWRBTN_PRESS_DURATION_MASK, long_press_value); if (ret) { @@ -132,7 +130,8 @@ static int bd718xx_init_press_duration(struct bd718xx *bd718xx) static int bd718xx_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { - struct bd718xx *bd718xx; + struct regmap *regmap; + struct regmap_irq_chip_data *irq_data; int ret; unsigned int chip_type; struct mfd_cell *mfd; @@ -142,13 +141,6 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c, dev_err(&i2c->dev, "No IRQ configured\n"); return -EINVAL; } - - bd718xx = devm_kzalloc(&i2c->dev, sizeof(struct bd718xx), GFP_KERNEL); - - if (!bd718xx) - return -ENOMEM; - - bd718xx->chip_irq = i2c->irq; chip_type = (unsigned int)(uintptr_t) of_device_get_match_data(&i2c->dev); switch (chip_type) { @@ -164,29 +156,26 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c, dev_err(&i2c->dev, "Unknown device type"); return -EINVAL; } - bd718xx->chip.dev = &i2c->dev; - dev_set_drvdata(&i2c->dev, bd718xx); - bd718xx->chip.regmap = devm_regmap_init_i2c(i2c, - &bd718xx_regmap_config); - if (IS_ERR(bd718xx->chip.regmap)) { + regmap = devm_regmap_init_i2c(i2c, &bd718xx_regmap_config); + if (IS_ERR(regmap)) { dev_err(&i2c->dev, "regmap initialization failed\n"); - return PTR_ERR(bd718xx->chip.regmap); + return PTR_ERR(regmap); } - ret = devm_regmap_add_irq_chip(&i2c->dev, bd718xx->chip.regmap, - bd718xx->chip_irq, IRQF_ONESHOT, 0, - &bd718xx_irq_chip, &bd718xx->irq_data); + ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq, + IRQF_ONESHOT, 0, &bd718xx_irq_chip, + &irq_data); if (ret) { dev_err(&i2c->dev, "Failed to add irq_chip\n"); return ret; } - ret = bd718xx_init_press_duration(bd718xx); + ret = bd718xx_init_press_duration(regmap, &i2c->dev); if (ret) return ret; - ret = regmap_irq_get_virq(bd718xx->irq_data, BD718XX_INT_PWRBTN_S); + ret = regmap_irq_get_virq(irq_data, BD718XX_INT_PWRBTN_S); if (ret < 0) { dev_err(&i2c->dev, "Failed to get the IRQ\n"); @@ -195,9 +184,9 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c, button.irq = ret; - ret = devm_mfd_add_devices(bd718xx->chip.dev, PLATFORM_DEVID_AUTO, + ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, mfd, cells, NULL, 0, - regmap_irq_get_domain(bd718xx->irq_data)); + regmap_irq_get_domain(irq_data)); if (ret) dev_err(&i2c->dev, "Failed to create subdevices\n"); diff --git a/include/linux/mfd/rohm-bd718x7.h b/include/linux/mfd/rohm-bd718x7.h index bee2474a8f9f..df2918198d37 100644 --- a/include/linux/mfd/rohm-bd718x7.h +++ b/include/linux/mfd/rohm-bd718x7.h @@ -310,17 +310,4 @@ enum { BD718XX_PWRBTN_LONG_PRESS_15S }; -struct bd718xx { - /* - * Please keep this as the first member here as some - * drivers (clk) supporting more than one chip may only know this - * generic struct 'struct rohm_regmap_dev' and assume it is - * the first chunk of parent device's private data. - */ - struct rohm_regmap_dev chip; - - int chip_irq; - struct regmap_irq_chip_data *irq_data; -}; - #endif /* __LINUX_MFD_BD718XX_H__ */ -- cgit v1.2.3-71-gd317 From 488b205e57181a56f3503cb97240d32798d3d3bd Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Mon, 5 Apr 2021 14:42:13 +0300 Subject: mfd: Add ROHM BD71815 ID Add chip ID for ROHM BD71815 and PMIC so that drivers can identify this IC. Signed-off-by: Matti Vaittinen Signed-off-by: Lee Jones --- include/linux/mfd/rohm-generic.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux') diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h index 66f673c35303..e107b4769101 100644 --- a/include/linux/mfd/rohm-generic.h +++ b/include/linux/mfd/rohm-generic.h @@ -11,6 +11,7 @@ enum rohm_chip_type { ROHM_CHIP_TYPE_BD71837 = 0, ROHM_CHIP_TYPE_BD71847, ROHM_CHIP_TYPE_BD70528, + ROHM_CHIP_TYPE_BD71815, ROHM_CHIP_TYPE_BD71828, ROHM_CHIP_TYPE_BD9571, ROHM_CHIP_TYPE_BD9574, -- cgit v1.2.3-71-gd317 From 06b2f5f5ecf3e3a3b74b42057b654a5dba7e63bb Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Mon, 5 Apr 2021 14:42:34 +0300 Subject: mfd: Sort ROHM chip ID list for better readability Sort the ID list so it is easier to see which ICs are present. Signed-off-by: Matti Vaittinen Suggested-by: Lee Jones Signed-off-by: Lee Jones --- include/linux/mfd/rohm-generic.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h index e107b4769101..9e2880e06950 100644 --- a/include/linux/mfd/rohm-generic.h +++ b/include/linux/mfd/rohm-generic.h @@ -8,13 +8,13 @@ #include enum rohm_chip_type { - ROHM_CHIP_TYPE_BD71837 = 0, - ROHM_CHIP_TYPE_BD71847, + ROHM_CHIP_TYPE_BD9571, + ROHM_CHIP_TYPE_BD9574, ROHM_CHIP_TYPE_BD70528, ROHM_CHIP_TYPE_BD71815, ROHM_CHIP_TYPE_BD71828, - ROHM_CHIP_TYPE_BD9571, - ROHM_CHIP_TYPE_BD9574, + ROHM_CHIP_TYPE_BD71837, + ROHM_CHIP_TYPE_BD71847, ROHM_CHIP_TYPE_AMOUNT }; -- cgit v1.2.3-71-gd317 From 4dcdcfd5abb34d3139669fcd830b756d45678c47 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Mon, 5 Apr 2021 14:42:51 +0300 Subject: mfd: Support for ROHM BD71815 PMIC core Add core support for ROHM BD71815 Power Management IC. The IC integrates regulators, a battery charger with a coulomb counter, a real-time clock (RTC), clock gate and general-purpose outputs (GPO). Signed-off-by: Matti Vaittinen Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 15 +- drivers/mfd/rohm-bd71828.c | 486 ++++++++++++++++++++++++--------- include/linux/mfd/rohm-bd71815.h | 562 +++++++++++++++++++++++++++++++++++++++ include/linux/mfd/rohm-bd71828.h | 3 + 4 files changed, 933 insertions(+), 133 deletions(-) create mode 100644 include/linux/mfd/rohm-bd71815.h (limited to 'include/linux') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index b74efa469e90..60d9ae559f0a 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1975,19 +1975,20 @@ config MFD_ROHM_BD70528 charger. config MFD_ROHM_BD71828 - tristate "ROHM BD71828 Power Management IC" + tristate "ROHM BD71828 and BD71815 Power Management IC" depends on I2C=y depends on OF select REGMAP_I2C select REGMAP_IRQ select MFD_CORE help - Select this option to get support for the ROHM BD71828 Power - Management IC. BD71828GW is a single-chip power management IC for - battery-powered portable devices. The IC integrates 7 buck - converters, 7 LDOs, and a 1500 mA single-cell linear charger. - Also included is a Coulomb counter, a real-time clock (RTC), and - a 32.768 kHz clock gate. + Select this option to get support for the ROHM BD71828 and BD71815 + Power Management ICs. BD71828GW and BD71815AGW are single-chip power + management ICs mainly for battery-powered portable devices. + The BD71828 integrates 7 buck converters and 7 LDOs. The BD71815 + has 5 bucks, 7 LDOs, and a boost for driving LEDs. Both ICs provide + also a single-cell linear charger, a Coulomb counter, a real-time + clock (RTC), GPIOs and a 32.768 kHz clock gate. config MFD_STM32_LPTIMER tristate "Support for STM32 Low-Power Timer" diff --git a/drivers/mfd/rohm-bd71828.c b/drivers/mfd/rohm-bd71828.c index 210261d026f2..714d9fcbf07b 100644 --- a/drivers/mfd/rohm-bd71828.c +++ b/drivers/mfd/rohm-bd71828.c @@ -2,7 +2,7 @@ // // Copyright (C) 2019 ROHM Semiconductors // -// ROHM BD71828 PMIC driver +// ROHM BD71828/BD71815 PMIC driver #include #include @@ -11,7 +11,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -29,12 +31,84 @@ static struct gpio_keys_platform_data bd71828_powerkey_data = { .name = "bd71828-pwrkey", }; -static const struct resource rtc_irqs[] = { +static const struct resource bd71815_rtc_irqs[] = { + DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd71815-rtc-alm-0"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd71815-rtc-alm-1"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd71815-rtc-alm-2"), +}; + +static const struct resource bd71828_rtc_irqs[] = { DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd71828-rtc-alm-0"), DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd71828-rtc-alm-1"), DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd71828-rtc-alm-2"), }; +static struct resource bd71815_power_irqs[] = { + DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-clps-out"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-clps-in"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_RES, "bd71815-dcin-ovp-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_DET, "bd71815-dcin-ovp-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_RES, "bd71815-dcin-mon-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_DET, "bd71815-dcin-mon-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_RES, "bd71815-vsys-uv-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_DET, "bd71815-vsys-uv-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_RES, "bd71815-vsys-low-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_DET, "bd71815-vsys-low-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TEMP, "bd71815-chg-wdg-temp"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TIME, "bd71815-chg-wdg"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_RES, "bd71815-rechg-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_DET, "bd71815-rechg-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, "bd71815-ranged-temp-transit"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_STATE_TRANSITION, "bd71815-chg-state-change"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_NORMAL, "bd71815-bat-temp-normal"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_ERANGE, "bd71815-bat-temp-erange"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_REMOVED, "bd71815-bat-rmv"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DETECTED, "bd71815-bat-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_REMOVED, "bd71815-therm-rmv"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_DETECTED, "bd71815-therm-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DEAD, "bd71815-bat-dead"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_RES, "bd71815-bat-short-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_DET, "bd71815-bat-short-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_RES, "bd71815-bat-low-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_DET, "bd71815-bat-low-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_RES, "bd71815-bat-over-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_DET, "bd71815-bat-over-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_RES, "bd71815-bat-mon-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_DET, "bd71815-bat-mon-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON1, "bd71815-bat-cc-mon1"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON2, "bd71815-bat-cc-mon2"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON3, "bd71815-bat-cc-mon3"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_RES, "bd71815-bat-oc1-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_DET, "bd71815-bat-oc1-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_RES, "bd71815-bat-oc2-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_DET, "bd71815-bat-oc2-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_RES, "bd71815-bat-oc3-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_DET, "bd71815-bat-oc3-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-bat-low-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-bat-low-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-bat-hi-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-bat-hi-det"), +}; + +static struct mfd_cell bd71815_mfd_cells[] = { + { .name = "bd71815-pmic", }, + { .name = "bd71815-clk", }, + { .name = "bd71815-gpo", }, + { + .name = "bd71815-power", + .num_resources = ARRAY_SIZE(bd71815_power_irqs), + .resources = &bd71815_power_irqs[0], + }, + { + .name = "bd71815-rtc", + .num_resources = ARRAY_SIZE(bd71815_rtc_irqs), + .resources = &bd71815_rtc_irqs[0], + }, +}; + static struct mfd_cell bd71828_mfd_cells[] = { { .name = "bd71828-pmic", }, { .name = "bd71828-gpio", }, @@ -47,8 +121,8 @@ static struct mfd_cell bd71828_mfd_cells[] = { { .name = "bd71827-power", }, { .name = "bd71828-rtc", - .resources = rtc_irqs, - .num_resources = ARRAY_SIZE(rtc_irqs), + .resources = bd71828_rtc_irqs, + .num_resources = ARRAY_SIZE(bd71828_rtc_irqs), }, { .name = "gpio-keys", .platform_data = &bd71828_powerkey_data, @@ -56,7 +130,35 @@ static struct mfd_cell bd71828_mfd_cells[] = { }, }; -static const struct regmap_range volatile_ranges[] = { +static const struct regmap_range bd71815_volatile_ranges[] = { + { + .range_min = BD71815_REG_SEC, + .range_max = BD71815_REG_YEAR, + }, { + .range_min = BD71815_REG_CONF, + .range_max = BD71815_REG_BAT_TEMP, + }, { + .range_min = BD71815_REG_VM_IBAT_U, + .range_max = BD71815_REG_CC_CTRL, + }, { + .range_min = BD71815_REG_CC_STAT, + .range_max = BD71815_REG_CC_CURCD_L, + }, { + .range_min = BD71815_REG_VM_BTMP_MON, + .range_max = BD71815_REG_VM_BTMP_MON, + }, { + .range_min = BD71815_REG_INT_STAT, + .range_max = BD71815_REG_INT_UPDATE, + }, { + .range_min = BD71815_REG_VM_VSYS_U, + .range_max = BD71815_REG_REX_CTRL_1, + }, { + .range_min = BD71815_REG_FULL_CCNTD_3, + .range_max = BD71815_REG_CCNTD_CHG_2, + }, +}; + +static const struct regmap_range bd71828_volatile_ranges[] = { { .range_min = BD71828_REG_PS_CTRL_1, .range_max = BD71828_REG_PS_CTRL_1, @@ -80,15 +182,28 @@ static const struct regmap_range volatile_ranges[] = { }, }; -static const struct regmap_access_table volatile_regs = { - .yes_ranges = &volatile_ranges[0], - .n_yes_ranges = ARRAY_SIZE(volatile_ranges), +static const struct regmap_access_table bd71815_volatile_regs = { + .yes_ranges = &bd71815_volatile_ranges[0], + .n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ranges), +}; + +static const struct regmap_access_table bd71828_volatile_regs = { + .yes_ranges = &bd71828_volatile_ranges[0], + .n_yes_ranges = ARRAY_SIZE(bd71828_volatile_ranges), +}; + +static const struct regmap_config bd71815_regmap = { + .reg_bits = 8, + .val_bits = 8, + .volatile_table = &bd71815_volatile_regs, + .max_register = BD71815_MAX_REGISTER - 1, + .cache_type = REGCACHE_RBTREE, }; -static struct regmap_config bd71828_regmap = { +static const struct regmap_config bd71828_regmap = { .reg_bits = 8, .val_bits = 8, - .volatile_table = &volatile_regs, + .volatile_table = &bd71828_volatile_regs, .max_register = BD71828_MAX_REGISTER, .cache_type = REGCACHE_RBTREE, }; @@ -96,7 +211,7 @@ static struct regmap_config bd71828_regmap = { /* * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can * access corect sub-IRQ registers based on bits that are set in main IRQ - * register. + * register. BD71815 and BD71828 have same sub-register-block offests. */ static unsigned int bit0_offsets[] = {11}; /* RTC IRQ */ @@ -108,7 +223,7 @@ static unsigned int bit5_offsets[] = {3}; /* VSYS IRQ */ static unsigned int bit6_offsets[] = {1, 2}; /* DCIN IRQ */ static unsigned int bit7_offsets[] = {0}; /* BUCK IRQ */ -static struct regmap_irq_sub_irq_map bd71828_sub_irq_offsets[] = { +static struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = { REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), @@ -119,6 +234,88 @@ static struct regmap_irq_sub_irq_map bd71828_sub_irq_offsets[] = { REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), }; +static const struct regmap_irq bd71815_irqs[] = { + REGMAP_IRQ_REG(BD71815_INT_BUCK1_OCP, 0, BD71815_INT_BUCK1_OCP_MASK), + REGMAP_IRQ_REG(BD71815_INT_BUCK2_OCP, 0, BD71815_INT_BUCK2_OCP_MASK), + REGMAP_IRQ_REG(BD71815_INT_BUCK3_OCP, 0, BD71815_INT_BUCK3_OCP_MASK), + REGMAP_IRQ_REG(BD71815_INT_BUCK4_OCP, 0, BD71815_INT_BUCK4_OCP_MASK), + REGMAP_IRQ_REG(BD71815_INT_BUCK5_OCP, 0, BD71815_INT_BUCK5_OCP_MASK), + REGMAP_IRQ_REG(BD71815_INT_LED_OVP, 0, BD71815_INT_LED_OVP_MASK), + REGMAP_IRQ_REG(BD71815_INT_LED_OCP, 0, BD71815_INT_LED_OCP_MASK), + REGMAP_IRQ_REG(BD71815_INT_LED_SCP, 0, BD71815_INT_LED_SCP_MASK), + /* DCIN1 interrupts */ + REGMAP_IRQ_REG(BD71815_INT_DCIN_RMV, 1, BD71815_INT_DCIN_RMV_MASK), + REGMAP_IRQ_REG(BD71815_INT_CLPS_OUT, 1, BD71815_INT_CLPS_OUT_MASK), + REGMAP_IRQ_REG(BD71815_INT_CLPS_IN, 1, BD71815_INT_CLPS_IN_MASK), + REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_RES, 1, BD71815_INT_DCIN_OVP_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_DET, 1, BD71815_INT_DCIN_OVP_DET_MASK), + /* DCIN2 interrupts */ + REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_RES, 2, BD71815_INT_DCIN_MON_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_DET, 2, BD71815_INT_DCIN_MON_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_WDOG, 2, BD71815_INT_WDOG_MASK), + /* Vsys */ + REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_RES, 3, BD71815_INT_VSYS_UV_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_DET, 3, BD71815_INT_VSYS_UV_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_RES, 3, BD71815_INT_VSYS_LOW_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_DET, 3, BD71815_INT_VSYS_LOW_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_RES, 3, BD71815_INT_VSYS_MON_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_DET, 3, BD71815_INT_VSYS_MON_DET_MASK), + /* Charger */ + REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TEMP, 4, BD71815_INT_CHG_WDG_TEMP_MASK), + REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TIME, 4, BD71815_INT_CHG_WDG_TIME_MASK), + REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_RES, 4, BD71815_INT_CHG_RECHARGE_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_DET, 4, BD71815_INT_CHG_RECHARGE_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, 4, + BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK), + REGMAP_IRQ_REG(BD71815_INT_CHG_STATE_TRANSITION, 4, BD71815_INT_CHG_STATE_TRANSITION_MASK), + /* Battery */ + REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_NORMAL, 5, BD71815_INT_BAT_TEMP_NORMAL_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_ERANGE, 5, BD71815_INT_BAT_TEMP_ERANGE_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_REMOVED, 5, BD71815_INT_BAT_REMOVED_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_DETECTED, 5, BD71815_INT_BAT_DETECTED_MASK), + REGMAP_IRQ_REG(BD71815_INT_THERM_REMOVED, 5, BD71815_INT_THERM_REMOVED_MASK), + REGMAP_IRQ_REG(BD71815_INT_THERM_DETECTED, 5, BD71815_INT_THERM_DETECTED_MASK), + /* Battery Mon 1 */ + REGMAP_IRQ_REG(BD71815_INT_BAT_DEAD, 6, BD71815_INT_BAT_DEAD_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_RES, 6, BD71815_INT_BAT_SHORTC_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_DET, 6, BD71815_INT_BAT_SHORTC_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_RES, 6, BD71815_INT_BAT_LOW_VOLT_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_DET, 6, BD71815_INT_BAT_LOW_VOLT_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_RES, 6, BD71815_INT_BAT_OVER_VOLT_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_DET, 6, BD71815_INT_BAT_OVER_VOLT_DET_MASK), + /* Battery Mon 2 */ + REGMAP_IRQ_REG(BD71815_INT_BAT_MON_RES, 7, BD71815_INT_BAT_MON_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_MON_DET, 7, BD71815_INT_BAT_MON_DET_MASK), + /* Battery Mon 3 (Coulomb counter) */ + REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON1, 8, BD71815_INT_BAT_CC_MON1_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON2, 8, BD71815_INT_BAT_CC_MON2_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON3, 8, BD71815_INT_BAT_CC_MON3_MASK), + /* Battery Mon 4 */ + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_RES, 9, BD71815_INT_BAT_OVER_CURR_1_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_DET, 9, BD71815_INT_BAT_OVER_CURR_1_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_RES, 9, BD71815_INT_BAT_OVER_CURR_2_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_DET, 9, BD71815_INT_BAT_OVER_CURR_2_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_RES, 9, BD71815_INT_BAT_OVER_CURR_3_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_DET, 9, BD71815_INT_BAT_OVER_CURR_3_DET_MASK), + /* Temperature */ + REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_RES, 10, BD71815_INT_TEMP_BAT_LOW_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_DET, 10, BD71815_INT_TEMP_BAT_LOW_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_RES, 10, BD71815_INT_TEMP_BAT_HI_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_DET, 10, BD71815_INT_TEMP_BAT_HI_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_RES, 10, + BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_DET, 10, + BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_RES, 10, + BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_DET, 10, + BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK), + /* RTC Alarm */ + REGMAP_IRQ_REG(BD71815_INT_RTC0, 11, BD71815_INT_RTC0_MASK), + REGMAP_IRQ_REG(BD71815_INT_RTC1, 11, BD71815_INT_RTC1_MASK), + REGMAP_IRQ_REG(BD71815_INT_RTC2, 11, BD71815_INT_RTC2_MASK), +}; + static struct regmap_irq bd71828_irqs[] = { REGMAP_IRQ_REG(BD71828_INT_BUCK1_OCP, 0, BD71828_INT_BUCK1_OCP_MASK), REGMAP_IRQ_REG(BD71828_INT_BUCK2_OCP, 0, BD71828_INT_BUCK2_OCP_MASK), @@ -134,10 +331,8 @@ static struct regmap_irq bd71828_irqs[] = { REGMAP_IRQ_REG(BD71828_INT_CLPS_OUT, 1, BD71828_INT_CLPS_OUT_MASK), REGMAP_IRQ_REG(BD71828_INT_CLPS_IN, 1, BD71828_INT_CLPS_IN_MASK), /* DCIN2 interrupts */ - REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_RES, 2, - BD71828_INT_DCIN_MON_RES_MASK), - REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_DET, 2, - BD71828_INT_DCIN_MON_DET_MASK), + REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_RES, 2, BD71828_INT_DCIN_MON_RES_MASK), + REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_DET, 2, BD71828_INT_DCIN_MON_DET_MASK), REGMAP_IRQ_REG(BD71828_INT_LONGPUSH, 2, BD71828_INT_LONGPUSH_MASK), REGMAP_IRQ_REG(BD71828_INT_MIDPUSH, 2, BD71828_INT_MIDPUSH_MASK), REGMAP_IRQ_REG(BD71828_INT_SHORTPUSH, 2, BD71828_INT_SHORTPUSH_MASK), @@ -145,102 +340,59 @@ static struct regmap_irq bd71828_irqs[] = { REGMAP_IRQ_REG(BD71828_INT_WDOG, 2, BD71828_INT_WDOG_MASK), REGMAP_IRQ_REG(BD71828_INT_SWRESET, 2, BD71828_INT_SWRESET_MASK), /* Vsys */ - REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_RES, 3, - BD71828_INT_VSYS_UV_RES_MASK), - REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_DET, 3, - BD71828_INT_VSYS_UV_DET_MASK), - REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_RES, 3, - BD71828_INT_VSYS_LOW_RES_MASK), - REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_DET, 3, - BD71828_INT_VSYS_LOW_DET_MASK), - REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_IN, 3, - BD71828_INT_VSYS_HALL_IN_MASK), - REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_TOGGLE, 3, - BD71828_INT_VSYS_HALL_TOGGLE_MASK), - REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_RES, 3, - BD71828_INT_VSYS_MON_RES_MASK), - REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_DET, 3, - BD71828_INT_VSYS_MON_DET_MASK), + REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_RES, 3, BD71828_INT_VSYS_UV_RES_MASK), + REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_DET, 3, BD71828_INT_VSYS_UV_DET_MASK), + REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_RES, 3, BD71828_INT_VSYS_LOW_RES_MASK), + REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_DET, 3, BD71828_INT_VSYS_LOW_DET_MASK), + REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_IN, 3, BD71828_INT_VSYS_HALL_IN_MASK), + REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_TOGGLE, 3, BD71828_INT_VSYS_HALL_TOGGLE_MASK), + REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_RES, 3, BD71828_INT_VSYS_MON_RES_MASK), + REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_DET, 3, BD71828_INT_VSYS_MON_DET_MASK), /* Charger */ - REGMAP_IRQ_REG(BD71828_INT_CHG_DCIN_ILIM, 4, - BD71828_INT_CHG_DCIN_ILIM_MASK), - REGMAP_IRQ_REG(BD71828_INT_CHG_TOPOFF_TO_DONE, 4, - BD71828_INT_CHG_TOPOFF_TO_DONE_MASK), - REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TEMP, 4, - BD71828_INT_CHG_WDG_TEMP_MASK), - REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TIME, 4, - BD71828_INT_CHG_WDG_TIME_MASK), - REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_RES, 4, - BD71828_INT_CHG_RECHARGE_RES_MASK), - REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_DET, 4, - BD71828_INT_CHG_RECHARGE_DET_MASK), + REGMAP_IRQ_REG(BD71828_INT_CHG_DCIN_ILIM, 4, BD71828_INT_CHG_DCIN_ILIM_MASK), + REGMAP_IRQ_REG(BD71828_INT_CHG_TOPOFF_TO_DONE, 4, BD71828_INT_CHG_TOPOFF_TO_DONE_MASK), + REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TEMP, 4, BD71828_INT_CHG_WDG_TEMP_MASK), + REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TIME, 4, BD71828_INT_CHG_WDG_TIME_MASK), + REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_RES, 4, BD71828_INT_CHG_RECHARGE_RES_MASK), + REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_DET, 4, BD71828_INT_CHG_RECHARGE_DET_MASK), REGMAP_IRQ_REG(BD71828_INT_CHG_RANGED_TEMP_TRANSITION, 4, BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK), - REGMAP_IRQ_REG(BD71828_INT_CHG_STATE_TRANSITION, 4, - BD71828_INT_CHG_STATE_TRANSITION_MASK), + REGMAP_IRQ_REG(BD71828_INT_CHG_STATE_TRANSITION, 4, BD71828_INT_CHG_STATE_TRANSITION_MASK), /* Battery */ - REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_NORMAL, 5, - BD71828_INT_BAT_TEMP_NORMAL_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_ERANGE, 5, - BD71828_INT_BAT_TEMP_ERANGE_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_WARN, 5, - BD71828_INT_BAT_TEMP_WARN_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_REMOVED, 5, - BD71828_INT_BAT_REMOVED_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_DETECTED, 5, - BD71828_INT_BAT_DETECTED_MASK), - REGMAP_IRQ_REG(BD71828_INT_THERM_REMOVED, 5, - BD71828_INT_THERM_REMOVED_MASK), - REGMAP_IRQ_REG(BD71828_INT_THERM_DETECTED, 5, - BD71828_INT_THERM_DETECTED_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_NORMAL, 5, BD71828_INT_BAT_TEMP_NORMAL_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_ERANGE, 5, BD71828_INT_BAT_TEMP_ERANGE_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_WARN, 5, BD71828_INT_BAT_TEMP_WARN_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_REMOVED, 5, BD71828_INT_BAT_REMOVED_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_DETECTED, 5, BD71828_INT_BAT_DETECTED_MASK), + REGMAP_IRQ_REG(BD71828_INT_THERM_REMOVED, 5, BD71828_INT_THERM_REMOVED_MASK), + REGMAP_IRQ_REG(BD71828_INT_THERM_DETECTED, 5, BD71828_INT_THERM_DETECTED_MASK), /* Battery Mon 1 */ REGMAP_IRQ_REG(BD71828_INT_BAT_DEAD, 6, BD71828_INT_BAT_DEAD_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_RES, 6, - BD71828_INT_BAT_SHORTC_RES_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_DET, 6, - BD71828_INT_BAT_SHORTC_DET_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_RES, 6, - BD71828_INT_BAT_LOW_VOLT_RES_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_DET, 6, - BD71828_INT_BAT_LOW_VOLT_DET_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_RES, 6, - BD71828_INT_BAT_OVER_VOLT_RES_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_DET, 6, - BD71828_INT_BAT_OVER_VOLT_DET_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_RES, 6, BD71828_INT_BAT_SHORTC_RES_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_DET, 6, BD71828_INT_BAT_SHORTC_DET_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_RES, 6, BD71828_INT_BAT_LOW_VOLT_RES_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_DET, 6, BD71828_INT_BAT_LOW_VOLT_DET_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_RES, 6, BD71828_INT_BAT_OVER_VOLT_RES_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_DET, 6, BD71828_INT_BAT_OVER_VOLT_DET_MASK), /* Battery Mon 2 */ - REGMAP_IRQ_REG(BD71828_INT_BAT_MON_RES, 7, - BD71828_INT_BAT_MON_RES_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_MON_DET, 7, - BD71828_INT_BAT_MON_DET_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_MON_RES, 7, BD71828_INT_BAT_MON_RES_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_MON_DET, 7, BD71828_INT_BAT_MON_DET_MASK), /* Battery Mon 3 (Coulomb counter) */ - REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON1, 8, - BD71828_INT_BAT_CC_MON1_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON2, 8, - BD71828_INT_BAT_CC_MON2_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON3, 8, - BD71828_INT_BAT_CC_MON3_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON1, 8, BD71828_INT_BAT_CC_MON1_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON2, 8, BD71828_INT_BAT_CC_MON2_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON3, 8, BD71828_INT_BAT_CC_MON3_MASK), /* Battery Mon 4 */ - REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_RES, 9, - BD71828_INT_BAT_OVER_CURR_1_RES_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_DET, 9, - BD71828_INT_BAT_OVER_CURR_1_DET_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_RES, 9, - BD71828_INT_BAT_OVER_CURR_2_RES_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_DET, 9, - BD71828_INT_BAT_OVER_CURR_2_DET_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_RES, 9, - BD71828_INT_BAT_OVER_CURR_3_RES_MASK), - REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_DET, 9, - BD71828_INT_BAT_OVER_CURR_3_DET_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_RES, 9, BD71828_INT_BAT_OVER_CURR_1_RES_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_DET, 9, BD71828_INT_BAT_OVER_CURR_1_DET_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_RES, 9, BD71828_INT_BAT_OVER_CURR_2_RES_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_DET, 9, BD71828_INT_BAT_OVER_CURR_2_DET_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_RES, 9, BD71828_INT_BAT_OVER_CURR_3_RES_MASK), + REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_DET, 9, BD71828_INT_BAT_OVER_CURR_3_DET_MASK), /* Temperature */ - REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_RES, 10, - BD71828_INT_TEMP_BAT_LOW_RES_MASK), - REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_DET, 10, - BD71828_INT_TEMP_BAT_LOW_DET_MASK), - REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_RES, 10, - BD71828_INT_TEMP_BAT_HI_RES_MASK), - REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_DET, 10, - BD71828_INT_TEMP_BAT_HI_DET_MASK), + REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_RES, 10, BD71828_INT_TEMP_BAT_LOW_RES_MASK), + REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_DET, 10, BD71828_INT_TEMP_BAT_LOW_DET_MASK), + REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_RES, 10, BD71828_INT_TEMP_BAT_HI_RES_MASK), + REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_DET, 10, BD71828_INT_TEMP_BAT_HI_DET_MASK), REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_RES, 10, BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK), REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_DET, 10, @@ -267,57 +419,133 @@ static struct regmap_irq_chip bd71828_irq_chip = { .init_ack_masked = true, .num_regs = 12, .num_main_regs = 1, - .sub_reg_offsets = &bd71828_sub_irq_offsets[0], + .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], + .num_main_status_bits = 8, + .irq_reg_stride = 1, +}; + +static struct regmap_irq_chip bd71815_irq_chip = { + .name = "bd71815_irq", + .main_status = BD71815_REG_INT_STAT, + .irqs = &bd71815_irqs[0], + .num_irqs = ARRAY_SIZE(bd71815_irqs), + .status_base = BD71815_REG_INT_STAT_01, + .mask_base = BD71815_REG_INT_EN_01, + .ack_base = BD71815_REG_INT_STAT_01, + .mask_invert = true, + .init_ack_masked = true, + .num_regs = 12, + .num_main_regs = 1, + .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], .num_main_status_bits = 8, .irq_reg_stride = 1, }; +static int set_clk_mode(struct device *dev, struct regmap *regmap, + int clkmode_reg) +{ + int ret; + unsigned int open_drain; + + ret = of_property_read_u32(dev->of_node, "rohm,clkout-open-drain", &open_drain); + if (ret) { + if (ret == -EINVAL) + return 0; + return ret; + } + if (open_drain > 1) { + dev_err(dev, "bad clk32kout mode configuration"); + return -EINVAL; + } + + if (open_drain) + return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE, + OUT32K_MODE_OPEN_DRAIN); + + return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE, + OUT32K_MODE_CMOS); +} + static int bd71828_i2c_probe(struct i2c_client *i2c) { - struct rohm_regmap_dev *chip; struct regmap_irq_chip_data *irq_data; int ret; + struct regmap *regmap; + const struct regmap_config *regmap_config; + struct regmap_irq_chip *irqchip; + unsigned int chip_type; + struct mfd_cell *mfd; + int cells; + int button_irq; + int clkmode_reg; if (!i2c->irq) { dev_err(&i2c->dev, "No IRQ configured\n"); return -EINVAL; } - chip = devm_kzalloc(&i2c->dev, sizeof(*chip), GFP_KERNEL); - if (!chip) - return -ENOMEM; - - dev_set_drvdata(&i2c->dev, chip); + chip_type = (unsigned int)(uintptr_t) + of_device_get_match_data(&i2c->dev); + switch (chip_type) { + case ROHM_CHIP_TYPE_BD71828: + mfd = bd71828_mfd_cells; + cells = ARRAY_SIZE(bd71828_mfd_cells); + regmap_config = &bd71828_regmap; + irqchip = &bd71828_irq_chip; + clkmode_reg = BD71828_REG_OUT32K; + button_irq = BD71828_INT_SHORTPUSH; + break; + case ROHM_CHIP_TYPE_BD71815: + mfd = bd71815_mfd_cells; + cells = ARRAY_SIZE(bd71815_mfd_cells); + regmap_config = &bd71815_regmap; + irqchip = &bd71815_irq_chip; + clkmode_reg = BD71815_REG_OUT32K; + /* + * If BD71817 support is needed we should be able to handle it + * with proper DT configs + BD71815 drivers + power-button. + * BD71815 data-sheet does not list the power-button IRQ so we + * don't use it. + */ + button_irq = 0; + break; + default: + dev_err(&i2c->dev, "Unknown device type"); + return -EINVAL; + } - chip->regmap = devm_regmap_init_i2c(i2c, &bd71828_regmap); - if (IS_ERR(chip->regmap)) { + regmap = devm_regmap_init_i2c(i2c, regmap_config); + if (IS_ERR(regmap)) { dev_err(&i2c->dev, "Failed to initialize Regmap\n"); - return PTR_ERR(chip->regmap); + return PTR_ERR(regmap); } - ret = devm_regmap_add_irq_chip(&i2c->dev, chip->regmap, - i2c->irq, IRQF_ONESHOT, 0, - &bd71828_irq_chip, &irq_data); + ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq, + IRQF_ONESHOT, 0, irqchip, &irq_data); if (ret) { dev_err(&i2c->dev, "Failed to add IRQ chip\n"); return ret; } dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n", - bd71828_irq_chip.num_irqs); + irqchip->num_irqs); - ret = regmap_irq_get_virq(irq_data, BD71828_INT_SHORTPUSH); - if (ret < 0) { - dev_err(&i2c->dev, "Failed to get the power-key IRQ\n"); - return ret; + if (button_irq) { + ret = regmap_irq_get_virq(irq_data, button_irq); + if (ret < 0) { + dev_err(&i2c->dev, "Failed to get the power-key IRQ\n"); + return ret; + } + + button.irq = ret; } - button.irq = ret; + ret = set_clk_mode(&i2c->dev, regmap, clkmode_reg); + if (ret) + return ret; - ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, - bd71828_mfd_cells, - ARRAY_SIZE(bd71828_mfd_cells), NULL, 0, - regmap_irq_get_domain(irq_data)); + ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, mfd, cells, + NULL, 0, regmap_irq_get_domain(irq_data)); if (ret) dev_err(&i2c->dev, "Failed to create subdevices\n"); @@ -325,7 +553,13 @@ static int bd71828_i2c_probe(struct i2c_client *i2c) } static const struct of_device_id bd71828_of_match[] = { - { .compatible = "rohm,bd71828", }, + { + .compatible = "rohm,bd71828", + .data = (void *)ROHM_CHIP_TYPE_BD71828, + }, { + .compatible = "rohm,bd71815", + .data = (void *)ROHM_CHIP_TYPE_BD71815, + }, { }, }; MODULE_DEVICE_TABLE(of, bd71828_of_match); diff --git a/include/linux/mfd/rohm-bd71815.h b/include/linux/mfd/rohm-bd71815.h new file mode 100644 index 000000000000..ec6d9612bebe --- /dev/null +++ b/include/linux/mfd/rohm-bd71815.h @@ -0,0 +1,562 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2021 ROHM Semiconductors. + * + * Author: Matti Vaittinen + * + * Copyright 2014 Embest Technology Co. Ltd. Inc. + * + * Author: yanglsh@embest-tech.com + */ + +#ifndef _MFD_BD71815_H +#define _MFD_BD71815_H + +#include + +enum { + BD71815_BUCK1 = 0, + BD71815_BUCK2, + BD71815_BUCK3, + BD71815_BUCK4, + BD71815_BUCK5, + /* General Purpose */ + BD71815_LDO1, + BD71815_LDO2, + BD71815_LDO3, + /* LDOs for SD Card and SD Card Interface */ + BD71815_LDO4, + BD71815_LDO5, + /* LDO for DDR Reference Voltage */ + BD71815_LDODVREF, + /* LDO for Low-Power State Retention */ + BD71815_LDOLPSR, + BD71815_WLED, + BD71815_REGULATOR_CNT, +}; + +#define BD71815_SUPPLY_STATE_ENABLED 0x1 + +enum { + BD71815_REG_DEVICE = 0, + BD71815_REG_PWRCTRL, + BD71815_REG_BUCK1_MODE, + BD71815_REG_BUCK2_MODE, + BD71815_REG_BUCK3_MODE, + BD71815_REG_BUCK4_MODE, + BD71815_REG_BUCK5_MODE, + BD71815_REG_BUCK1_VOLT_H, + BD71815_REG_BUCK1_VOLT_L, + BD71815_REG_BUCK2_VOLT_H, + BD71815_REG_BUCK2_VOLT_L, + BD71815_REG_BUCK3_VOLT, + BD71815_REG_BUCK4_VOLT, + BD71815_REG_BUCK5_VOLT, + BD71815_REG_LED_CTRL, + BD71815_REG_LED_DIMM, + BD71815_REG_LDO_MODE1, + BD71815_REG_LDO_MODE2, + BD71815_REG_LDO_MODE3, + BD71815_REG_LDO_MODE4, + BD71815_REG_LDO1_VOLT, + BD71815_REG_LDO2_VOLT, + BD71815_REG_LDO3_VOLT, + BD71815_REG_LDO4_VOLT, + BD71815_REG_LDO5_VOLT_H, + BD71815_REG_LDO5_VOLT_L, + BD71815_REG_BUCK_PD_DIS, + BD71815_REG_LDO_PD_DIS, + BD71815_REG_GPO, + BD71815_REG_OUT32K, + BD71815_REG_SEC, + BD71815_REG_MIN, + BD71815_REG_HOUR, + BD71815_REG_WEEK, + BD71815_REG_DAY, + BD71815_REG_MONTH, + BD71815_REG_YEAR, + BD71815_REG_ALM0_SEC, + + BD71815_REG_ALM1_SEC = 0x2C, + + BD71815_REG_ALM0_MASK = 0x33, + BD71815_REG_ALM1_MASK, + BD71815_REG_ALM2, + BD71815_REG_TRIM, + BD71815_REG_CONF, + BD71815_REG_SYS_INIT, + BD71815_REG_CHG_STATE, + BD71815_REG_CHG_LAST_STATE, + BD71815_REG_BAT_STAT, + BD71815_REG_DCIN_STAT, + BD71815_REG_VSYS_STAT, + BD71815_REG_CHG_STAT, + BD71815_REG_CHG_WDT_STAT, + BD71815_REG_BAT_TEMP, + BD71815_REG_IGNORE_0, + BD71815_REG_INHIBIT_0, + BD71815_REG_DCIN_CLPS, + BD71815_REG_VSYS_REG, + BD71815_REG_VSYS_MAX, + BD71815_REG_VSYS_MIN, + BD71815_REG_CHG_SET1, + BD71815_REG_CHG_SET2, + BD71815_REG_CHG_WDT_PRE, + BD71815_REG_CHG_WDT_FST, + BD71815_REG_CHG_IPRE, + BD71815_REG_CHG_IFST, + BD71815_REG_CHG_IFST_TERM, + BD71815_REG_CHG_VPRE, + BD71815_REG_CHG_VBAT_1, + BD71815_REG_CHG_VBAT_2, + BD71815_REG_CHG_VBAT_3, + BD71815_REG_CHG_LED_1, + BD71815_REG_VF_TH, + BD71815_REG_BAT_SET_1, + BD71815_REG_BAT_SET_2, + BD71815_REG_BAT_SET_3, + BD71815_REG_ALM_VBAT_TH_U, + BD71815_REG_ALM_VBAT_TH_L, + BD71815_REG_ALM_DCIN_TH, + BD71815_REG_ALM_VSYS_TH, + BD71815_REG_VM_IBAT_U, + BD71815_REG_VM_IBAT_L, + BD71815_REG_VM_VBAT_U, + BD71815_REG_VM_VBAT_L, + BD71815_REG_VM_BTMP, + BD71815_REG_VM_VTH, + BD71815_REG_VM_DCIN_U, + BD71815_REG_VM_DCIN_L, + BD71815_REG_VM_VSYS, + BD71815_REG_VM_VF, + BD71815_REG_VM_OCI_PRE_U, + BD71815_REG_VM_OCI_PRE_L, + BD71815_REG_VM_OCV_PRE_U, + BD71815_REG_VM_OCV_PRE_L, + BD71815_REG_VM_OCI_PST_U, + BD71815_REG_VM_OCI_PST_L, + BD71815_REG_VM_OCV_PST_U, + BD71815_REG_VM_OCV_PST_L, + BD71815_REG_VM_SA_VBAT_U, + BD71815_REG_VM_SA_VBAT_L, + BD71815_REG_VM_SA_IBAT_U, + BD71815_REG_VM_SA_IBAT_L, + BD71815_REG_CC_CTRL, + BD71815_REG_CC_BATCAP1_TH_U, + BD71815_REG_CC_BATCAP1_TH_L, + BD71815_REG_CC_BATCAP2_TH_U, + BD71815_REG_CC_BATCAP2_TH_L, + BD71815_REG_CC_BATCAP3_TH_U, + BD71815_REG_CC_BATCAP3_TH_L, + BD71815_REG_CC_STAT, + BD71815_REG_CC_CCNTD_3, + BD71815_REG_CC_CCNTD_2, + BD71815_REG_CC_CCNTD_1, + BD71815_REG_CC_CCNTD_0, + BD71815_REG_CC_CURCD_U, + BD71815_REG_CC_CURCD_L, + BD71815_REG_VM_OCUR_THR_1, + BD71815_REG_VM_OCUR_DUR_1, + BD71815_REG_VM_OCUR_THR_2, + BD71815_REG_VM_OCUR_DUR_2, + BD71815_REG_VM_OCUR_THR_3, + BD71815_REG_VM_OCUR_DUR_3, + BD71815_REG_VM_OCUR_MON, + BD71815_REG_VM_BTMP_OV_THR, + BD71815_REG_VM_BTMP_OV_DUR, + BD71815_REG_VM_BTMP_LO_THR, + BD71815_REG_VM_BTMP_LO_DUR, + BD71815_REG_VM_BTMP_MON, + BD71815_REG_INT_EN_01, + + BD71815_REG_INT_EN_11 = 0x95, + BD71815_REG_INT_EN_12, + BD71815_REG_INT_STAT, + BD71815_REG_INT_STAT_01, + BD71815_REG_INT_STAT_02, + BD71815_REG_INT_STAT_03, + BD71815_REG_INT_STAT_04, + BD71815_REG_INT_STAT_05, + BD71815_REG_INT_STAT_06, + BD71815_REG_INT_STAT_07, + BD71815_REG_INT_STAT_08, + BD71815_REG_INT_STAT_09, + BD71815_REG_INT_STAT_10, + BD71815_REG_INT_STAT_11, + BD71815_REG_INT_STAT_12, + BD71815_REG_INT_UPDATE, + + BD71815_REG_VM_VSYS_U = 0xC0, + BD71815_REG_VM_VSYS_L, + BD71815_REG_VM_SA_VSYS_U, + BD71815_REG_VM_SA_VSYS_L, + + BD71815_REG_VM_SA_IBAT_MIN_U = 0xD0, + BD71815_REG_VM_SA_IBAT_MIN_L, + BD71815_REG_VM_SA_IBAT_MAX_U, + BD71815_REG_VM_SA_IBAT_MAX_L, + BD71815_REG_VM_SA_VBAT_MIN_U, + BD71815_REG_VM_SA_VBAT_MIN_L, + BD71815_REG_VM_SA_VBAT_MAX_U, + BD71815_REG_VM_SA_VBAT_MAX_L, + BD71815_REG_VM_SA_VSYS_MIN_U, + BD71815_REG_VM_SA_VSYS_MIN_L, + BD71815_REG_VM_SA_VSYS_MAX_U, + BD71815_REG_VM_SA_VSYS_MAX_L, + BD71815_REG_VM_SA_MINMAX_CLR, + + BD71815_REG_REX_CCNTD_3 = 0xE0, + BD71815_REG_REX_CCNTD_2, + BD71815_REG_REX_CCNTD_1, + BD71815_REG_REX_CCNTD_0, + BD71815_REG_REX_SA_VBAT_U, + BD71815_REG_REX_SA_VBAT_L, + BD71815_REG_REX_CTRL_1, + BD71815_REG_REX_CTRL_2, + BD71815_REG_FULL_CCNTD_3, + BD71815_REG_FULL_CCNTD_2, + BD71815_REG_FULL_CCNTD_1, + BD71815_REG_FULL_CCNTD_0, + BD71815_REG_FULL_CTRL, + + BD71815_REG_CCNTD_CHG_3 = 0xF0, + BD71815_REG_CCNTD_CHG_2, + + BD71815_REG_TEST_MODE = 0xFE, + BD71815_MAX_REGISTER, +}; + +/* BD71815_REG_BUCK1_MODE bits */ +#define BD71815_BUCK_RAMPRATE_MASK 0xC0 +#define BD71815_BUCK_RAMPRATE_10P00MV 0x0 +#define BD71815_BUCK_RAMPRATE_5P00MV 0x01 +#define BD71815_BUCK_RAMPRATE_2P50MV 0x02 +#define BD71815_BUCK_RAMPRATE_1P25MV 0x03 + +#define BD71815_BUCK_PWM_FIXED BIT(4) +#define BD71815_BUCK_SNVS_ON BIT(3) +#define BD71815_BUCK_RUN_ON BIT(2) +#define BD71815_BUCK_LPSR_ON BIT(1) +#define BD71815_BUCK_SUSP_ON BIT(0) + +/* BD71815_REG_BUCK1_VOLT_H bits */ +#define BD71815_BUCK_DVSSEL BIT(7) +#define BD71815_BUCK_STBY_DVS BIT(6) +#define BD71815_VOLT_MASK 0x3F +#define BD71815_BUCK1_H_DEFAULT 0x14 +#define BD71815_BUCK1_L_DEFAULT 0x14 + +/* BD71815_REG_BUCK2_VOLT_H bits */ +#define BD71815_BUCK2_H_DEFAULT 0x14 +#define BD71815_BUCK2_L_DEFAULT 0x14 + +/* WLED output */ +/* current register mask */ +#define LED_DIMM_MASK 0x3f +/* LED enable bits at LED_CTRL reg */ +#define LED_CHGDONE_EN BIT(4) +#define LED_RUN_ON BIT(2) +#define LED_LPSR_ON BIT(1) +#define LED_SUSP_ON BIT(0) + +/* BD71815_REG_LDO1_CTRL bits */ +#define LDO1_EN BIT(0) +#define LDO2_EN BIT(1) +#define LDO3_EN BIT(2) +#define DVREF_EN BIT(3) +#define VOSNVS_SW_EN BIT(4) + +/* LDO_MODE1_register */ +#define LDO1_SNVS_ON BIT(7) +#define LDO1_RUN_ON BIT(6) +#define LDO1_LPSR_ON BIT(5) +#define LDO1_SUSP_ON BIT(4) +/* set => register control, unset => GPIO control */ +#define LDO4_MODE_MASK BIT(3) +#define LDO4_MODE_I2C BIT(3) +#define LDO4_MODE_GPIO 0 +/* set => register control, unset => start when DCIN connected */ +#define LDO3_MODE_MASK BIT(2) +#define LDO3_MODE_I2C BIT(2) +#define LDO3_MODE_DCIN 0 + +/* LDO_MODE2 register */ +#define LDO3_SNVS_ON BIT(7) +#define LDO3_RUN_ON BIT(6) +#define LDO3_LPSR_ON BIT(5) +#define LDO3_SUSP_ON BIT(4) +#define LDO2_SNVS_ON BIT(3) +#define LDO2_RUN_ON BIT(2) +#define LDO2_LPSR_ON BIT(1) +#define LDO2_SUSP_ON BIT(0) + + +/* LDO_MODE3 register */ +#define LDO5_SNVS_ON BIT(7) +#define LDO5_RUN_ON BIT(6) +#define LDO5_LPSR_ON BIT(5) +#define LDO5_SUSP_ON BIT(4) +#define LDO4_SNVS_ON BIT(3) +#define LDO4_RUN_ON BIT(2) +#define LDO4_LPSR_ON BIT(1) +#define LDO4_SUSP_ON BIT(0) + +/* LDO_MODE4 register */ +#define DVREF_SNVS_ON BIT(7) +#define DVREF_RUN_ON BIT(6) +#define DVREF_LPSR_ON BIT(5) +#define DVREF_SUSP_ON BIT(4) +#define LDO_LPSR_SNVS_ON BIT(3) +#define LDO_LPSR_RUN_ON BIT(2) +#define LDO_LPSR_LPSR_ON BIT(1) +#define LDO_LPSR_SUSP_ON BIT(0) + +/* BD71815_REG_OUT32K bits */ +#define OUT32K_EN BIT(0) +#define OUT32K_MODE BIT(1) +#define OUT32K_MODE_CMOS BIT(1) +#define OUT32K_MODE_OPEN_DRAIN 0 + +/* BD71815_REG_BAT_STAT bits */ +#define BAT_DET BIT(5) +#define BAT_DET_OFFSET 5 +#define BAT_DET_DONE BIT(4) +#define VBAT_OV BIT(3) +#define DBAT_DET BIT(0) + +/* BD71815_REG_VBUS_STAT bits */ +#define VBUS_DET BIT(0) + +#define BD71815_REG_RTC_START BD71815_REG_SEC +#define BD71815_REG_RTC_ALM_START BD71815_REG_ALM0_SEC + +/* BD71815_REG_ALM0_MASK bits */ +#define A0_ONESEC BIT(7) + +/* BD71815_REG_INT_EN_00 bits */ +#define ALMALE BIT(0) + +/* BD71815_REG_INT_STAT_03 bits */ +#define DCIN_MON_DET BIT(1) +#define DCIN_MON_RES BIT(0) +#define POWERON_LONG BIT(2) +#define POWERON_MID BIT(3) +#define POWERON_SHORT BIT(4) +#define POWERON_PRESS BIT(5) + +/* BD71805_REG_INT_STAT_08 bits */ +#define VBAT_MON_DET BIT(1) +#define VBAT_MON_RES BIT(0) + +/* BD71805_REG_INT_STAT_11 bits */ +#define INT_STAT_11_VF_DET BIT(7) +#define INT_STAT_11_VF_RES BIT(6) +#define INT_STAT_11_VF125_DET BIT(5) +#define INT_STAT_11_VF125_RES BIT(4) +#define INT_STAT_11_OVTMP_DET BIT(3) +#define INT_STAT_11_OVTMP_RES BIT(2) +#define INT_STAT_11_LOTMP_DET BIT(1) +#define INT_STAT_11_LOTMP_RES BIT(0) + +#define VBAT_MON_DET BIT(1) +#define VBAT_MON_RES BIT(0) + +/* BD71815_REG_PWRCTRL bits */ +#define RESTARTEN BIT(0) + +/* BD71815_REG_GPO bits */ +#define READY_FORCE_LOW BIT(2) +#define BD71815_GPIO_DRIVE_MASK BIT(4) +#define BD71815_GPIO_OPEN_DRAIN 0 +#define BD71815_GPIO_CMOS BIT(4) + +/* BD71815 interrupt masks */ +enum { + BD71815_INT_EN_01_BUCKAST_MASK = 0x0F, + BD71815_INT_EN_02_DCINAST_MASK = 0x3E, + BD71815_INT_EN_03_DCINAST_MASK = 0x3F, + BD71815_INT_EN_04_VSYSAST_MASK = 0xCF, + BD71815_INT_EN_05_CHGAST_MASK = 0xFC, + BD71815_INT_EN_06_BATAST_MASK = 0xF3, + BD71815_INT_EN_07_BMONAST_MASK = 0xFE, + BD71815_INT_EN_08_BMONAST_MASK = 0x03, + BD71815_INT_EN_09_BMONAST_MASK = 0x07, + BD71815_INT_EN_10_BMONAST_MASK = 0x3F, + BD71815_INT_EN_11_TMPAST_MASK = 0xFF, + BD71815_INT_EN_12_ALMAST_MASK = 0x07, +}; +/* BD71815 interrupt irqs */ +enum { + /* BUCK reg interrupts */ + BD71815_INT_BUCK1_OCP, + BD71815_INT_BUCK2_OCP, + BD71815_INT_BUCK3_OCP, + BD71815_INT_BUCK4_OCP, + BD71815_INT_BUCK5_OCP, + BD71815_INT_LED_OVP, + BD71815_INT_LED_OCP, + BD71815_INT_LED_SCP, + /* DCIN1 interrupts */ + BD71815_INT_DCIN_RMV, + BD71815_INT_CLPS_OUT, + BD71815_INT_CLPS_IN, + BD71815_INT_DCIN_OVP_RES, + BD71815_INT_DCIN_OVP_DET, + /* DCIN2 interrupts */ + BD71815_INT_DCIN_MON_RES, + BD71815_INT_DCIN_MON_DET, + BD71815_INT_WDOG, + /* Vsys INT_STAT_04 */ + BD71815_INT_VSYS_UV_RES, + BD71815_INT_VSYS_UV_DET, + BD71815_INT_VSYS_LOW_RES, + BD71815_INT_VSYS_LOW_DET, + BD71815_INT_VSYS_MON_RES, + BD71815_INT_VSYS_MON_DET, + /* Charger INT_STAT_05 */ + BD71815_INT_CHG_WDG_TEMP, + BD71815_INT_CHG_WDG_TIME, + BD71815_INT_CHG_RECHARGE_RES, + BD71815_INT_CHG_RECHARGE_DET, + BD71815_INT_CHG_RANGED_TEMP_TRANSITION, + BD71815_INT_CHG_STATE_TRANSITION, + /* Battery INT_STAT_06 */ + BD71815_INT_BAT_TEMP_NORMAL, + BD71815_INT_BAT_TEMP_ERANGE, + BD71815_INT_BAT_REMOVED, + BD71815_INT_BAT_DETECTED, + BD71815_INT_THERM_REMOVED, + BD71815_INT_THERM_DETECTED, + /* Battery Mon 1 INT_STAT_07 */ + BD71815_INT_BAT_DEAD, + BD71815_INT_BAT_SHORTC_RES, + BD71815_INT_BAT_SHORTC_DET, + BD71815_INT_BAT_LOW_VOLT_RES, + BD71815_INT_BAT_LOW_VOLT_DET, + BD71815_INT_BAT_OVER_VOLT_RES, + BD71815_INT_BAT_OVER_VOLT_DET, + /* Battery Mon 2 INT_STAT_08 */ + BD71815_INT_BAT_MON_RES, + BD71815_INT_BAT_MON_DET, + /* Battery Mon 3 (Coulomb counter) INT_STAT_09 */ + BD71815_INT_BAT_CC_MON1, + BD71815_INT_BAT_CC_MON2, + BD71815_INT_BAT_CC_MON3, + /* Battery Mon 4 INT_STAT_10 */ + BD71815_INT_BAT_OVER_CURR_1_RES, + BD71815_INT_BAT_OVER_CURR_1_DET, + BD71815_INT_BAT_OVER_CURR_2_RES, + BD71815_INT_BAT_OVER_CURR_2_DET, + BD71815_INT_BAT_OVER_CURR_3_RES, + BD71815_INT_BAT_OVER_CURR_3_DET, + /* Temperature INT_STAT_11 */ + BD71815_INT_TEMP_BAT_LOW_RES, + BD71815_INT_TEMP_BAT_LOW_DET, + BD71815_INT_TEMP_BAT_HI_RES, + BD71815_INT_TEMP_BAT_HI_DET, + BD71815_INT_TEMP_CHIP_OVER_125_RES, + BD71815_INT_TEMP_CHIP_OVER_125_DET, + BD71815_INT_TEMP_CHIP_OVER_VF_RES, + BD71815_INT_TEMP_CHIP_OVER_VF_DET, + /* RTC Alarm INT_STAT_12 */ + BD71815_INT_RTC0, + BD71815_INT_RTC1, + BD71815_INT_RTC2, +}; + +#define BD71815_INT_BUCK1_OCP_MASK BIT(0) +#define BD71815_INT_BUCK2_OCP_MASK BIT(1) +#define BD71815_INT_BUCK3_OCP_MASK BIT(2) +#define BD71815_INT_BUCK4_OCP_MASK BIT(3) +#define BD71815_INT_BUCK5_OCP_MASK BIT(4) +#define BD71815_INT_LED_OVP_MASK BIT(5) +#define BD71815_INT_LED_OCP_MASK BIT(6) +#define BD71815_INT_LED_SCP_MASK BIT(7) + +#define BD71815_INT_DCIN_RMV_MASK BIT(1) +#define BD71815_INT_CLPS_OUT_MASK BIT(2) +#define BD71815_INT_CLPS_IN_MASK BIT(3) +#define BD71815_INT_DCIN_OVP_RES_MASK BIT(4) +#define BD71815_INT_DCIN_OVP_DET_MASK BIT(5) + +#define BD71815_INT_DCIN_MON_RES_MASK BIT(0) +#define BD71815_INT_DCIN_MON_DET_MASK BIT(1) +#define BD71815_INT_WDOG_MASK BIT(6) + +#define BD71815_INT_VSYS_UV_RES_MASK BIT(0) +#define BD71815_INT_VSYS_UV_DET_MASK BIT(1) +#define BD71815_INT_VSYS_LOW_RES_MASK BIT(2) +#define BD71815_INT_VSYS_LOW_DET_MASK BIT(3) +#define BD71815_INT_VSYS_MON_RES_MASK BIT(6) +#define BD71815_INT_VSYS_MON_DET_MASK BIT(7) + +#define BD71815_INT_CHG_WDG_TEMP_MASK BIT(2) +#define BD71815_INT_CHG_WDG_TIME_MASK BIT(3) +#define BD71815_INT_CHG_RECHARGE_RES_MASK BIT(4) +#define BD71815_INT_CHG_RECHARGE_DET_MASK BIT(5) +#define BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK BIT(6) +#define BD71815_INT_CHG_STATE_TRANSITION_MASK BIT(7) + +#define BD71815_INT_BAT_TEMP_NORMAL_MASK BIT(0) +#define BD71815_INT_BAT_TEMP_ERANGE_MASK BIT(1) +#define BD71815_INT_BAT_REMOVED_MASK BIT(4) +#define BD71815_INT_BAT_DETECTED_MASK BIT(5) +#define BD71815_INT_THERM_REMOVED_MASK BIT(6) +#define BD71815_INT_THERM_DETECTED_MASK BIT(7) + +#define BD71815_INT_BAT_DEAD_MASK BIT(1) +#define BD71815_INT_BAT_SHORTC_RES_MASK BIT(2) +#define BD71815_INT_BAT_SHORTC_DET_MASK BIT(3) +#define BD71815_INT_BAT_LOW_VOLT_RES_MASK BIT(4) +#define BD71815_INT_BAT_LOW_VOLT_DET_MASK BIT(5) +#define BD71815_INT_BAT_OVER_VOLT_RES_MASK BIT(6) +#define BD71815_INT_BAT_OVER_VOLT_DET_MASK BIT(7) + +#define BD71815_INT_BAT_MON_RES_MASK BIT(0) +#define BD71815_INT_BAT_MON_DET_MASK BIT(1) + +#define BD71815_INT_BAT_CC_MON1_MASK BIT(0) +#define BD71815_INT_BAT_CC_MON2_MASK BIT(1) +#define BD71815_INT_BAT_CC_MON3_MASK BIT(2) + +#define BD71815_INT_BAT_OVER_CURR_1_RES_MASK BIT(0) +#define BD71815_INT_BAT_OVER_CURR_1_DET_MASK BIT(1) +#define BD71815_INT_BAT_OVER_CURR_2_RES_MASK BIT(2) +#define BD71815_INT_BAT_OVER_CURR_2_DET_MASK BIT(3) +#define BD71815_INT_BAT_OVER_CURR_3_RES_MASK BIT(4) +#define BD71815_INT_BAT_OVER_CURR_3_DET_MASK BIT(5) + +#define BD71815_INT_TEMP_BAT_LOW_RES_MASK BIT(0) +#define BD71815_INT_TEMP_BAT_LOW_DET_MASK BIT(1) +#define BD71815_INT_TEMP_BAT_HI_RES_MASK BIT(2) +#define BD71815_INT_TEMP_BAT_HI_DET_MASK BIT(3) +#define BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK BIT(4) +#define BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK BIT(5) +#define BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK BIT(6) +#define BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK BIT(7) + +#define BD71815_INT_RTC0_MASK BIT(0) +#define BD71815_INT_RTC1_MASK BIT(1) +#define BD71815_INT_RTC2_MASK BIT(2) + +/* BD71815_REG_CC_CTRL bits */ +#define CCNTRST 0x80 +#define CCNTENB 0x40 +#define CCCALIB 0x20 + +/* BD71815_REG_CC_CURCD */ +#define CURDIR_Discharging 0x8000 + +/* BD71815_REG_VM_SA_IBAT */ +#define IBAT_SA_DIR_Discharging 0x8000 + +/* BD71815_REG_REX_CTRL_1 bits */ +#define REX_CLR BIT(4) + +/* BD71815_REG_REX_CTRL_1 bits */ +#define REX_PMU_STATE_MASK BIT(2) + +/* BD71815_REG_LED_CTRL bits */ +#define CHGDONE_LED_EN BIT(4) + +#endif /* __LINUX_MFD_BD71815_H */ diff --git a/include/linux/mfd/rohm-bd71828.h b/include/linux/mfd/rohm-bd71828.h index 017a4c01cb31..c7ab69c87ee8 100644 --- a/include/linux/mfd/rohm-bd71828.h +++ b/include/linux/mfd/rohm-bd71828.h @@ -151,6 +151,9 @@ enum { #define BD71828_REG_GPIO_CTRL3 0x49 #define BD71828_REG_IO_STAT 0xed +/* clk */ +#define BD71828_REG_OUT32K 0x4b + /* RTC */ #define BD71828_REG_RTC_SEC 0x4c #define BD71828_REG_RTC_MINUTE 0x4d -- cgit v1.2.3-71-gd317 From 80a71170646df80914a7290a197aca1e6116a49d Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Mon, 5 Apr 2021 14:43:44 +0300 Subject: regulator: rohm-regulator: Support SNVS HW state. The ROHM BD71815 supports setting voltage levels/regulator status for HW-states "RUN", "SUSPEND", "LPSR" and "SNVS". Add DT parsing helper also for SNVS state. Signed-off-by: Matti Vaittinen Acked-by: Mark Brown Signed-off-by: Lee Jones --- drivers/regulator/rohm-regulator.c | 6 ++++++ include/linux/mfd/rohm-generic.h | 6 +++++- 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/drivers/regulator/rohm-regulator.c b/drivers/regulator/rohm-regulator.c index 63aabb8c7786..6e0d9c08ec1c 100644 --- a/drivers/regulator/rohm-regulator.c +++ b/drivers/regulator/rohm-regulator.c @@ -95,6 +95,12 @@ int rohm_regulator_set_dvs_levels(const struct rohm_dvs_config *dvs, mask = dvs->lpsr_mask; omask = dvs->lpsr_on_mask; break; + case ROHM_DVS_LEVEL_SNVS: + prop = "rohm,dvs-snvs-voltage"; + reg = dvs->snvs_reg; + mask = dvs->snvs_mask; + omask = dvs->snvs_on_mask; + break; default: return -EINVAL; } diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h index 9e2880e06950..a9144284cf6d 100644 --- a/include/linux/mfd/rohm-generic.h +++ b/include/linux/mfd/rohm-generic.h @@ -27,7 +27,8 @@ struct rohm_regmap_dev { #define ROHM_DVS_LEVEL_IDLE BIT(1) #define ROHM_DVS_LEVEL_SUSPEND BIT(2) #define ROHM_DVS_LEVEL_LPSR BIT(3) -#define ROHM_DVS_LEVEL_VALID_AMOUNT 4 +#define ROHM_DVS_LEVEL_SNVS BIT(4) +#define ROHM_DVS_LEVEL_VALID_AMOUNT 5 #define ROHM_DVS_LEVEL_UNKNOWN 0 /** @@ -66,6 +67,9 @@ struct rohm_dvs_config { unsigned int lpsr_reg; unsigned int lpsr_mask; unsigned int lpsr_on_mask; + unsigned int snvs_reg; + unsigned int snvs_mask; + unsigned int snvs_on_mask; }; #if IS_ENABLED(CONFIG_REGULATOR_ROHM) -- cgit v1.2.3-71-gd317 From 1c7c1488898e1b3fd15d38f373a8c947a2d9b1e3 Mon Sep 17 00:00:00 2001 From: Jiapeng Chong Date: Wed, 10 Feb 2021 15:07:36 +0800 Subject: mfd: dbx500-prcmu: Use true and false for bool variable Fix the following coccicheck warning: ./include/linux/mfd/db8500-prcmu.h:723:8-9: WARNING: return of 0/1 in function 'db8500_prcmu_is_ac_wake_requested' with return type bool. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong Signed-off-by: Lee Jones --- include/linux/mfd/db8500-prcmu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h index 4b63d3ecdcff..a62de3d155ed 100644 --- a/include/linux/mfd/db8500-prcmu.h +++ b/include/linux/mfd/db8500-prcmu.h @@ -720,7 +720,7 @@ static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val) static inline bool db8500_prcmu_is_ac_wake_requested(void) { - return 0; + return false; } static inline int db8500_prcmu_set_arm_opp(u8 opp) -- cgit v1.2.3-71-gd317 From 911490a5ca2a3289ac734ca7c127c7dbc72466cc Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Fri, 19 Feb 2021 23:39:09 +0100 Subject: mfd: lp87565: Remove unused define 'LP87565_NUM_BUCK' This define appears incorrect, but it is completely unused so it can be removed. Signed-off-by: Luca Ceresoli Signed-off-by: Lee Jones --- include/linux/mfd/lp87565.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mfd/lp87565.h b/include/linux/mfd/lp87565.h index d44ddfb6bb63..5640e6088fe6 100644 --- a/include/linux/mfd/lp87565.h +++ b/include/linux/mfd/lp87565.h @@ -237,9 +237,6 @@ enum lp87565_device_type { #define LP87565_GOIO2_OUT BIT(1) #define LP87565_GOIO1_OUT BIT(0) -/* Number of step-down converters available */ -#define LP87565_NUM_BUCK 6 - enum LP87565_regulator_id { /* BUCK's */ LP87565_BUCK_0, -- cgit v1.2.3-71-gd317 From 16f961544bfd7170f75d805d7585e09023671dbc Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 7 Mar 2021 21:23:25 +0100 Subject: mfd: Remove support for AB3100 The ST-Ericsson U300 platform has been removed, so this driver is no longer needed. Signed-off-by: Arnd Bergmann Reviewed-by: Linus Walleij Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 26 +- drivers/mfd/Makefile | 2 - drivers/mfd/ab3100-core.c | 929 --------------------------------------------- drivers/mfd/ab3100-otp.c | 240 ------------ include/linux/mfd/ab3100.h | 128 ------- 5 files changed, 1 insertion(+), 1324 deletions(-) delete mode 100644 drivers/mfd/ab3100-core.c delete mode 100644 drivers/mfd/ab3100-otp.c delete mode 100644 include/linux/mfd/ab3100.h (limited to 'include/linux') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 6e31210915c7..2152126c5b0b 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1235,7 +1235,7 @@ config MFD_SC27XX_PMIC config ABX500_CORE bool "ST-Ericsson ABX500 Mixed Signal Circuit register functions" - default y if ARCH_U300 || ARCH_U8500 || COMPILE_TEST + default y if ARCH_U8500 || COMPILE_TEST help Say yes here if you have the ABX500 Mixed Signal IC family chips. This core driver expose register access functions. @@ -1243,30 +1243,6 @@ config ABX500_CORE remain unchanged when IC changes. Binding of the functions to actual register access is done by the IC core driver. -config AB3100_CORE - bool "ST-Ericsson AB3100 Mixed Signal Circuit core functions" - depends on I2C=y && ABX500_CORE - select MFD_CORE - default y if ARCH_U300 - help - Select this to enable the AB3100 Mixed Signal IC core - functionality. This connects to a AB3100 on the I2C bus - and expose a number of symbols needed for dependent devices - to read and write registers and subscribe to events from - this multi-functional IC. This is needed to use other features - of the AB3100 such as battery-backed RTC, charging control, - LEDs, vibrator, system power and temperature, power management - and ALSA sound. - -config AB3100_OTP - tristate "ST-Ericsson AB3100 OTP functions" - depends on AB3100_CORE - default y if AB3100_CORE - help - Select this to enable the AB3100 Mixed Signal IC OTP (one-time - programmable memory) support. This exposes a sysfs file to read - out OTP values. - config AB8500_CORE bool "ST-Ericsson AB8500 Mixed Signal Power Management chip" depends on ABX500_CORE && MFD_DB8500_PRCMU diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 279b80822147..4f6d2b8a5f76 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -178,8 +178,6 @@ obj-$(CONFIG_MFD_PCF50633) += pcf50633.o obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o obj-$(CONFIG_ABX500_CORE) += abx500-core.o -obj-$(CONFIG_AB3100_CORE) += ab3100-core.o -obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o obj-$(CONFIG_AB8500_DEBUG) += ab8500-debugfs.o obj-$(CONFIG_MFD_DB8500_PRCMU) += db8500-prcmu.o # ab8500-core need to come after db8500-prcmu (which provides the channel) diff --git a/drivers/mfd/ab3100-core.c b/drivers/mfd/ab3100-core.c deleted file mode 100644 index ee71ae04b5e6..000000000000 --- a/drivers/mfd/ab3100-core.c +++ /dev/null @@ -1,929 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2007-2010 ST-Ericsson - * Low-level core for exclusive access to the AB3100 IC on the I2C bus - * and some basic chip-configuration. - * Author: Linus Walleij - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* These are the only registers inside AB3100 used in this main file */ - -/* Interrupt event registers */ -#define AB3100_EVENTA1 0x21 -#define AB3100_EVENTA2 0x22 -#define AB3100_EVENTA3 0x23 - -/* AB3100 DAC converter registers */ -#define AB3100_DIS 0x00 -#define AB3100_D0C 0x01 -#define AB3100_D1C 0x02 -#define AB3100_D2C 0x03 -#define AB3100_D3C 0x04 - -/* Chip ID register */ -#define AB3100_CID 0x20 - -/* AB3100 interrupt registers */ -#define AB3100_IMRA1 0x24 -#define AB3100_IMRA2 0x25 -#define AB3100_IMRA3 0x26 -#define AB3100_IMRB1 0x2B -#define AB3100_IMRB2 0x2C -#define AB3100_IMRB3 0x2D - -/* System Power Monitoring and control registers */ -#define AB3100_MCA 0x2E -#define AB3100_MCB 0x2F - -/* SIM power up */ -#define AB3100_SUP 0x50 - -/* - * I2C communication - * - * The AB3100 is usually assigned address 0x48 (7-bit) - * The chip is defined in the platform i2c_board_data section. - */ -static int ab3100_get_chip_id(struct device *dev) -{ - struct ab3100 *ab3100 = dev_get_drvdata(dev->parent); - - return (int)ab3100->chip_id; -} - -static int ab3100_set_register_interruptible(struct ab3100 *ab3100, - u8 reg, u8 regval) -{ - u8 regandval[2] = {reg, regval}; - int err; - - err = mutex_lock_interruptible(&ab3100->access_mutex); - if (err) - return err; - - /* - * A two-byte write message with the first byte containing the register - * number and the second byte containing the value to be written - * effectively sets a register in the AB3100. - */ - err = i2c_master_send(ab3100->i2c_client, regandval, 2); - if (err < 0) { - dev_err(ab3100->dev, - "write error (write register): %d\n", - err); - } else if (err != 2) { - dev_err(ab3100->dev, - "write error (write register)\n" - " %d bytes transferred (expected 2)\n", - err); - err = -EIO; - } else { - /* All is well */ - err = 0; - } - mutex_unlock(&ab3100->access_mutex); - return err; -} - -static int set_register_interruptible(struct device *dev, - u8 bank, u8 reg, u8 value) -{ - struct ab3100 *ab3100 = dev_get_drvdata(dev->parent); - - return ab3100_set_register_interruptible(ab3100, reg, value); -} - -/* - * The test registers exist at an I2C bus address up one - * from the ordinary base. They are not supposed to be used - * in production code, but sometimes you have to do that - * anyway. It's currently only used from this file so declare - * it static and do not export. - */ -static int ab3100_set_test_register_interruptible(struct ab3100 *ab3100, - u8 reg, u8 regval) -{ - u8 regandval[2] = {reg, regval}; - int err; - - err = mutex_lock_interruptible(&ab3100->access_mutex); - if (err) - return err; - - err = i2c_master_send(ab3100->testreg_client, regandval, 2); - if (err < 0) { - dev_err(ab3100->dev, - "write error (write test register): %d\n", - err); - } else if (err != 2) { - dev_err(ab3100->dev, - "write error (write test register)\n" - " %d bytes transferred (expected 2)\n", - err); - err = -EIO; - } else { - /* All is well */ - err = 0; - } - mutex_unlock(&ab3100->access_mutex); - - return err; -} - -static int ab3100_get_register_interruptible(struct ab3100 *ab3100, - u8 reg, u8 *regval) -{ - int err; - - err = mutex_lock_interruptible(&ab3100->access_mutex); - if (err) - return err; - - /* - * AB3100 require an I2C "stop" command between each message, else - * it will not work. The only way of achieveing this with the - * message transport layer is to send the read and write messages - * separately. - */ - err = i2c_master_send(ab3100->i2c_client, ®, 1); - if (err < 0) { - dev_err(ab3100->dev, - "write error (send register address): %d\n", - err); - goto get_reg_out_unlock; - } else if (err != 1) { - dev_err(ab3100->dev, - "write error (send register address)\n" - " %d bytes transferred (expected 1)\n", - err); - err = -EIO; - goto get_reg_out_unlock; - } else { - /* All is well */ - err = 0; - } - - err = i2c_master_recv(ab3100->i2c_client, regval, 1); - if (err < 0) { - dev_err(ab3100->dev, - "write error (read register): %d\n", - err); - goto get_reg_out_unlock; - } else if (err != 1) { - dev_err(ab3100->dev, - "write error (read register)\n" - " %d bytes transferred (expected 1)\n", - err); - err = -EIO; - goto get_reg_out_unlock; - } else { - /* All is well */ - err = 0; - } - - get_reg_out_unlock: - mutex_unlock(&ab3100->access_mutex); - return err; -} - -static int get_register_interruptible(struct device *dev, u8 bank, u8 reg, - u8 *value) -{ - struct ab3100 *ab3100 = dev_get_drvdata(dev->parent); - - return ab3100_get_register_interruptible(ab3100, reg, value); -} - -static int ab3100_get_register_page_interruptible(struct ab3100 *ab3100, - u8 first_reg, u8 *regvals, u8 numregs) -{ - int err; - - if (ab3100->chip_id == 0xa0 || - ab3100->chip_id == 0xa1) - /* These don't support paged reads */ - return -EIO; - - err = mutex_lock_interruptible(&ab3100->access_mutex); - if (err) - return err; - - /* - * Paged read also require an I2C "stop" command. - */ - err = i2c_master_send(ab3100->i2c_client, &first_reg, 1); - if (err < 0) { - dev_err(ab3100->dev, - "write error (send first register address): %d\n", - err); - goto get_reg_page_out_unlock; - } else if (err != 1) { - dev_err(ab3100->dev, - "write error (send first register address)\n" - " %d bytes transferred (expected 1)\n", - err); - err = -EIO; - goto get_reg_page_out_unlock; - } - - err = i2c_master_recv(ab3100->i2c_client, regvals, numregs); - if (err < 0) { - dev_err(ab3100->dev, - "write error (read register page): %d\n", - err); - goto get_reg_page_out_unlock; - } else if (err != numregs) { - dev_err(ab3100->dev, - "write error (read register page)\n" - " %d bytes transferred (expected %d)\n", - err, numregs); - err = -EIO; - goto get_reg_page_out_unlock; - } - - /* All is well */ - err = 0; - - get_reg_page_out_unlock: - mutex_unlock(&ab3100->access_mutex); - return err; -} - -static int get_register_page_interruptible(struct device *dev, u8 bank, - u8 first_reg, u8 *regvals, u8 numregs) -{ - struct ab3100 *ab3100 = dev_get_drvdata(dev->parent); - - return ab3100_get_register_page_interruptible(ab3100, - first_reg, regvals, numregs); -} - -static int ab3100_mask_and_set_register_interruptible(struct ab3100 *ab3100, - u8 reg, u8 andmask, u8 ormask) -{ - u8 regandval[2] = {reg, 0}; - int err; - - err = mutex_lock_interruptible(&ab3100->access_mutex); - if (err) - return err; - - /* First read out the target register */ - err = i2c_master_send(ab3100->i2c_client, ®, 1); - if (err < 0) { - dev_err(ab3100->dev, - "write error (maskset send address): %d\n", - err); - goto get_maskset_unlock; - } else if (err != 1) { - dev_err(ab3100->dev, - "write error (maskset send address)\n" - " %d bytes transferred (expected 1)\n", - err); - err = -EIO; - goto get_maskset_unlock; - } - - err = i2c_master_recv(ab3100->i2c_client, ®andval[1], 1); - if (err < 0) { - dev_err(ab3100->dev, - "write error (maskset read register): %d\n", - err); - goto get_maskset_unlock; - } else if (err != 1) { - dev_err(ab3100->dev, - "write error (maskset read register)\n" - " %d bytes transferred (expected 1)\n", - err); - err = -EIO; - goto get_maskset_unlock; - } - - /* Modify the register */ - regandval[1] &= andmask; - regandval[1] |= ormask; - - /* Write the register */ - err = i2c_master_send(ab3100->i2c_client, regandval, 2); - if (err < 0) { - dev_err(ab3100->dev, - "write error (write register): %d\n", - err); - goto get_maskset_unlock; - } else if (err != 2) { - dev_err(ab3100->dev, - "write error (write register)\n" - " %d bytes transferred (expected 2)\n", - err); - err = -EIO; - goto get_maskset_unlock; - } - - /* All is well */ - err = 0; - - get_maskset_unlock: - mutex_unlock(&ab3100->access_mutex); - return err; -} - -static int mask_and_set_register_interruptible(struct device *dev, u8 bank, - u8 reg, u8 bitmask, u8 bitvalues) -{ - struct ab3100 *ab3100 = dev_get_drvdata(dev->parent); - - return ab3100_mask_and_set_register_interruptible(ab3100, - reg, bitmask, (bitmask & bitvalues)); -} - -/* - * Register a simple callback for handling any AB3100 events. - */ -int ab3100_event_register(struct ab3100 *ab3100, - struct notifier_block *nb) -{ - return blocking_notifier_chain_register(&ab3100->event_subscribers, - nb); -} -EXPORT_SYMBOL(ab3100_event_register); - -/* - * Remove a previously registered callback. - */ -int ab3100_event_unregister(struct ab3100 *ab3100, - struct notifier_block *nb) -{ - return blocking_notifier_chain_unregister(&ab3100->event_subscribers, - nb); -} -EXPORT_SYMBOL(ab3100_event_unregister); - - -static int ab3100_event_registers_startup_state_get(struct device *dev, - u8 *event) -{ - struct ab3100 *ab3100 = dev_get_drvdata(dev->parent); - - if (!ab3100->startup_events_read) - return -EAGAIN; /* Try again later */ - memcpy(event, ab3100->startup_events, 3); - - return 0; -} - -static struct abx500_ops ab3100_ops = { - .get_chip_id = ab3100_get_chip_id, - .set_register = set_register_interruptible, - .get_register = get_register_interruptible, - .get_register_page = get_register_page_interruptible, - .set_register_page = NULL, - .mask_and_set_register = mask_and_set_register_interruptible, - .event_registers_startup_state_get = - ab3100_event_registers_startup_state_get, - .startup_irq_enabled = NULL, -}; - -/* - * This is a threaded interrupt handler so we can make some - * I2C calls etc. - */ -static irqreturn_t ab3100_irq_handler(int irq, void *data) -{ - struct ab3100 *ab3100 = data; - u8 event_regs[3]; - u32 fatevent; - int err; - - err = ab3100_get_register_page_interruptible(ab3100, AB3100_EVENTA1, - event_regs, 3); - if (err) - goto err_event; - - fatevent = (event_regs[0] << 16) | - (event_regs[1] << 8) | - event_regs[2]; - - if (!ab3100->startup_events_read) { - ab3100->startup_events[0] = event_regs[0]; - ab3100->startup_events[1] = event_regs[1]; - ab3100->startup_events[2] = event_regs[2]; - ab3100->startup_events_read = true; - } - /* - * The notified parties will have to mask out the events - * they're interested in and react to them. They will be - * notified on all events, then they use the fatevent value - * to determine if they're interested. - */ - blocking_notifier_call_chain(&ab3100->event_subscribers, - fatevent, NULL); - - dev_dbg(ab3100->dev, - "IRQ Event: 0x%08x\n", fatevent); - - return IRQ_HANDLED; - - err_event: - dev_dbg(ab3100->dev, - "error reading event status\n"); - return IRQ_HANDLED; -} - -#ifdef CONFIG_DEBUG_FS -/* - * Some debugfs entries only exposed if we're using debug - */ -static int ab3100_registers_print(struct seq_file *s, void *p) -{ - struct ab3100 *ab3100 = s->private; - u8 value; - u8 reg; - - seq_puts(s, "AB3100 registers:\n"); - - for (reg = 0; reg < 0xff; reg++) { - ab3100_get_register_interruptible(ab3100, reg, &value); - seq_printf(s, "[0x%x]: 0x%x\n", reg, value); - } - return 0; -} - -static int ab3100_registers_open(struct inode *inode, struct file *file) -{ - return single_open(file, ab3100_registers_print, inode->i_private); -} - -static const struct file_operations ab3100_registers_fops = { - .open = ab3100_registers_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, - .owner = THIS_MODULE, -}; - -struct ab3100_get_set_reg_priv { - struct ab3100 *ab3100; - bool mode; -}; - -static ssize_t ab3100_get_set_reg(struct file *file, - const char __user *user_buf, - size_t count, loff_t *ppos) -{ - struct ab3100_get_set_reg_priv *priv = file->private_data; - struct ab3100 *ab3100 = priv->ab3100; - char buf[32]; - ssize_t buf_size; - int regp; - u8 user_reg; - int err; - int i = 0; - - /* Get userspace string and assure termination */ - buf_size = min((ssize_t)count, (ssize_t)(sizeof(buf)-1)); - if (copy_from_user(buf, user_buf, buf_size)) - return -EFAULT; - buf[buf_size] = 0; - - /* - * The idea is here to parse a string which is either - * "0xnn" for reading a register, or "0xaa 0xbb" for - * writing 0xbb to the register 0xaa. First move past - * whitespace and then begin to parse the register. - */ - while ((i < buf_size) && (buf[i] == ' ')) - i++; - regp = i; - - /* - * Advance pointer to end of string then terminate - * the register string. This is needed to satisfy - * the kstrtou8() function. - */ - while ((i < buf_size) && (buf[i] != ' ')) - i++; - buf[i] = '\0'; - - err = kstrtou8(&buf[regp], 16, &user_reg); - if (err) - return err; - - /* Either we read or we write a register here */ - if (!priv->mode) { - /* Reading */ - u8 regvalue; - - ab3100_get_register_interruptible(ab3100, user_reg, ®value); - - dev_info(ab3100->dev, - "debug read AB3100 reg[0x%02x]: 0x%02x\n", - user_reg, regvalue); - } else { - int valp; - u8 user_value; - u8 regvalue; - - /* - * Writing, we need some value to write to - * the register so keep parsing the string - * from userspace. - */ - i++; - while ((i < buf_size) && (buf[i] == ' ')) - i++; - valp = i; - while ((i < buf_size) && (buf[i] != ' ')) - i++; - buf[i] = '\0'; - - err = kstrtou8(&buf[valp], 16, &user_value); - if (err) - return err; - - ab3100_set_register_interruptible(ab3100, user_reg, user_value); - ab3100_get_register_interruptible(ab3100, user_reg, ®value); - - dev_info(ab3100->dev, - "debug write reg[0x%02x]\n" - " with 0x%02x, after readback: 0x%02x\n", - user_reg, user_value, regvalue); - } - return buf_size; -} - -static const struct file_operations ab3100_get_set_reg_fops = { - .open = simple_open, - .write = ab3100_get_set_reg, - .llseek = noop_llseek, -}; - -static struct ab3100_get_set_reg_priv ab3100_get_priv; -static struct ab3100_get_set_reg_priv ab3100_set_priv; - -static void ab3100_setup_debugfs(struct ab3100 *ab3100) -{ - struct dentry *ab3100_dir; - - ab3100_dir = debugfs_create_dir("ab3100", NULL); - - debugfs_create_file("registers", S_IRUGO, ab3100_dir, ab3100, - &ab3100_registers_fops); - - ab3100_get_priv.ab3100 = ab3100; - ab3100_get_priv.mode = false; - debugfs_create_file("get_reg", S_IWUSR, ab3100_dir, &ab3100_get_priv, - &ab3100_get_set_reg_fops); - - ab3100_set_priv.ab3100 = ab3100; - ab3100_set_priv.mode = true; - debugfs_create_file("set_reg", S_IWUSR, ab3100_dir, &ab3100_set_priv, - &ab3100_get_set_reg_fops); -} -#else -static inline void ab3100_setup_debugfs(struct ab3100 *ab3100) -{ -} -#endif - -/* - * Basic set-up, datastructure creation/destruction and I2C interface. - * This sets up a default config in the AB3100 chip so that it - * will work as expected. - */ - -struct ab3100_init_setting { - u8 abreg; - u8 setting; -}; - -static const struct ab3100_init_setting ab3100_init_settings[] = { - { - .abreg = AB3100_MCA, - .setting = 0x01 - }, { - .abreg = AB3100_MCB, - .setting = 0x30 - }, { - .abreg = AB3100_IMRA1, - .setting = 0x00 - }, { - .abreg = AB3100_IMRA2, - .setting = 0xFF - }, { - .abreg = AB3100_IMRA3, - .setting = 0x01 - }, { - .abreg = AB3100_IMRB1, - .setting = 0xBF - }, { - .abreg = AB3100_IMRB2, - .setting = 0xFF - }, { - .abreg = AB3100_IMRB3, - .setting = 0xFF - }, { - .abreg = AB3100_SUP, - .setting = 0x00 - }, { - .abreg = AB3100_DIS, - .setting = 0xF0 - }, { - .abreg = AB3100_D0C, - .setting = 0x00 - }, { - .abreg = AB3100_D1C, - .setting = 0x00 - }, { - .abreg = AB3100_D2C, - .setting = 0x00 - }, { - .abreg = AB3100_D3C, - .setting = 0x00 - }, -}; - -static int ab3100_setup(struct ab3100 *ab3100) -{ - int err = 0; - int i; - - for (i = 0; i < ARRAY_SIZE(ab3100_init_settings); i++) { - err = ab3100_set_register_interruptible(ab3100, - ab3100_init_settings[i].abreg, - ab3100_init_settings[i].setting); - if (err) - goto exit_no_setup; - } - - /* - * Special trick to make the AB3100 use the 32kHz clock (RTC) - * bit 3 in test register 0x02 is a special, undocumented test - * register bit that only exist in AB3100 P1E - */ - if (ab3100->chip_id == 0xc4) { - dev_warn(ab3100->dev, - "AB3100 P1E variant detected forcing chip to 32KHz\n"); - err = ab3100_set_test_register_interruptible(ab3100, - 0x02, 0x08); - } - - exit_no_setup: - return err; -} - -/* The subdevices of the AB3100 */ -static struct mfd_cell ab3100_devs[] = { - { - .name = "ab3100-dac", - .id = -1, - }, - { - .name = "ab3100-leds", - .id = -1, - }, - { - .name = "ab3100-power", - .id = -1, - }, - { - .name = "ab3100-regulators", - .of_compatible = "stericsson,ab3100-regulators", - .id = -1, - }, - { - .name = "ab3100-sim", - .id = -1, - }, - { - .name = "ab3100-uart", - .id = -1, - }, - { - .name = "ab3100-rtc", - .id = -1, - }, - { - .name = "ab3100-charger", - .id = -1, - }, - { - .name = "ab3100-boost", - .id = -1, - }, - { - .name = "ab3100-adc", - .id = -1, - }, - { - .name = "ab3100-fuelgauge", - .id = -1, - }, - { - .name = "ab3100-vibrator", - .id = -1, - }, - { - .name = "ab3100-otp", - .id = -1, - }, - { - .name = "ab3100-codec", - .id = -1, - }, -}; - -struct ab_family_id { - u8 id; - char *name; -}; - -static const struct ab_family_id ids[] = { - /* AB3100 */ - { - .id = 0xc0, - .name = "P1A" - }, { - .id = 0xc1, - .name = "P1B" - }, { - .id = 0xc2, - .name = "P1C" - }, { - .id = 0xc3, - .name = "P1D" - }, { - .id = 0xc4, - .name = "P1E" - }, { - .id = 0xc5, - .name = "P1F/R1A" - }, { - .id = 0xc6, - .name = "P1G/R1A" - }, { - .id = 0xc7, - .name = "P2A/R2A" - }, { - .id = 0xc8, - .name = "P2B/R2B" - }, - /* AB3000 variants, not supported */ - { - .id = 0xa0 - }, { - .id = 0xa1 - }, { - .id = 0xa2 - }, { - .id = 0xa3 - }, { - .id = 0xa4 - }, { - .id = 0xa5 - }, { - .id = 0xa6 - }, { - .id = 0xa7 - }, - /* Terminator */ - { - .id = 0x00, - }, -}; - -static int ab3100_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct ab3100 *ab3100; - struct ab3100_platform_data *ab3100_plf_data = - dev_get_platdata(&client->dev); - int err; - int i; - - ab3100 = devm_kzalloc(&client->dev, sizeof(struct ab3100), GFP_KERNEL); - if (!ab3100) - return -ENOMEM; - - /* Initialize data structure */ - mutex_init(&ab3100->access_mutex); - BLOCKING_INIT_NOTIFIER_HEAD(&ab3100->event_subscribers); - - ab3100->i2c_client = client; - ab3100->dev = &ab3100->i2c_client->dev; - - i2c_set_clientdata(client, ab3100); - - /* Read chip ID register */ - err = ab3100_get_register_interruptible(ab3100, AB3100_CID, - &ab3100->chip_id); - if (err) { - dev_err(&client->dev, - "failed to communicate with AB3100 chip\n"); - goto exit_no_detect; - } - - for (i = 0; ids[i].id != 0x0; i++) { - if (ids[i].id == ab3100->chip_id) { - if (ids[i].name) - break; - - dev_err(&client->dev, "AB3000 is not supported\n"); - goto exit_no_detect; - } - } - - snprintf(&ab3100->chip_name[0], - sizeof(ab3100->chip_name) - 1, "AB3100 %s", ids[i].name); - - if (ids[i].id == 0x0) { - dev_err(&client->dev, "unknown analog baseband chip id: 0x%x\n", - ab3100->chip_id); - dev_err(&client->dev, - "accepting it anyway. Please update the driver.\n"); - goto exit_no_detect; - } - - dev_info(&client->dev, "Detected chip: %s\n", - &ab3100->chip_name[0]); - - /* Attach a second dummy i2c_client to the test register address */ - ab3100->testreg_client = i2c_new_dummy_device(client->adapter, - client->addr + 1); - if (IS_ERR(ab3100->testreg_client)) { - err = PTR_ERR(ab3100->testreg_client); - goto exit_no_testreg_client; - } - - err = ab3100_setup(ab3100); - if (err) - goto exit_no_setup; - - err = devm_request_threaded_irq(&client->dev, - client->irq, NULL, ab3100_irq_handler, - IRQF_ONESHOT, "ab3100-core", ab3100); - if (err) - goto exit_no_irq; - - err = abx500_register_ops(&client->dev, &ab3100_ops); - if (err) - goto exit_no_ops; - - /* Set up and register the platform devices. */ - for (i = 0; i < ARRAY_SIZE(ab3100_devs); i++) { - ab3100_devs[i].platform_data = ab3100_plf_data; - ab3100_devs[i].pdata_size = sizeof(struct ab3100_platform_data); - } - - err = mfd_add_devices(&client->dev, 0, ab3100_devs, - ARRAY_SIZE(ab3100_devs), NULL, 0, NULL); - - ab3100_setup_debugfs(ab3100); - - return 0; - - exit_no_ops: - exit_no_irq: - exit_no_setup: - i2c_unregister_device(ab3100->testreg_client); - exit_no_testreg_client: - exit_no_detect: - return err; -} - -static const struct i2c_device_id ab3100_id[] = { - { "ab3100", 0 }, - { } -}; - -static struct i2c_driver ab3100_driver = { - .driver = { - .name = "ab3100", - .suppress_bind_attrs = true, - }, - .id_table = ab3100_id, - .probe = ab3100_probe, -}; - -static int __init ab3100_i2c_init(void) -{ - return i2c_add_driver(&ab3100_driver); -} -subsys_initcall(ab3100_i2c_init); diff --git a/drivers/mfd/ab3100-otp.c b/drivers/mfd/ab3100-otp.c deleted file mode 100644 index c393102e3a39..000000000000 --- a/drivers/mfd/ab3100-otp.c +++ /dev/null @@ -1,240 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * drivers/mfd/ab3100_otp.c - * - * Copyright (C) 2007-2009 ST-Ericsson AB - * Driver to read out OTP from the AB3100 Mixed-signal circuit - * Author: Linus Walleij - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* The OTP registers */ -#define AB3100_OTP0 0xb0 -#define AB3100_OTP1 0xb1 -#define AB3100_OTP2 0xb2 -#define AB3100_OTP3 0xb3 -#define AB3100_OTP4 0xb4 -#define AB3100_OTP5 0xb5 -#define AB3100_OTP6 0xb6 -#define AB3100_OTP7 0xb7 -#define AB3100_OTPP 0xbf - -/** - * struct ab3100_otp - * @dev: containing device - * @locked: whether the OTP is locked, after locking, no more bits - * can be changed but before locking it is still possible - * to change bits from 1->0. - * @freq: clocking frequency for the OTP, this frequency is either - * 32768Hz or 1MHz/30 - * @paf: product activation flag, indicates whether this is a real - * product (paf true) or a lab board etc (paf false) - * @imeich: if this is set it is possible to override the - * IMEI number found in the tac, fac and svn fields with - * (secured) software - * @cid: customer ID - * @tac: type allocation code of the IMEI - * @fac: final assembly code of the IMEI - * @svn: software version number of the IMEI - * @debugfs: a debugfs file used when dumping to file - */ -struct ab3100_otp { - struct device *dev; - bool locked; - u32 freq; - bool paf; - bool imeich; - u16 cid:14; - u32 tac:20; - u8 fac; - u32 svn:20; - struct dentry *debugfs; -}; - -static int __init ab3100_otp_read(struct ab3100_otp *otp) -{ - u8 otpval[8]; - u8 otpp; - int err; - - err = abx500_get_register_interruptible(otp->dev, 0, - AB3100_OTPP, &otpp); - if (err) { - dev_err(otp->dev, "unable to read OTPP register\n"); - return err; - } - - err = abx500_get_register_page_interruptible(otp->dev, 0, - AB3100_OTP0, otpval, 8); - if (err) { - dev_err(otp->dev, "unable to read OTP register page\n"); - return err; - } - - /* Cache OTP properties, they never change by nature */ - otp->locked = (otpp & 0x80); - otp->freq = (otpp & 0x40) ? 32768 : 34100; - otp->paf = (otpval[1] & 0x80); - otp->imeich = (otpval[1] & 0x40); - otp->cid = ((otpval[1] << 8) | otpval[0]) & 0x3fff; - otp->tac = ((otpval[4] & 0x0f) << 16) | (otpval[3] << 8) | otpval[2]; - otp->fac = ((otpval[5] & 0x0f) << 4) | (otpval[4] >> 4); - otp->svn = (otpval[7] << 12) | (otpval[6] << 4) | (otpval[5] >> 4); - return 0; -} - -/* - * This is a simple debugfs human-readable file that dumps out - * the contents of the OTP. - */ -#ifdef CONFIG_DEBUG_FS -static int ab3100_show_otp(struct seq_file *s, void *v) -{ - struct ab3100_otp *otp = s->private; - - seq_printf(s, "OTP is %s\n", otp->locked ? "LOCKED" : "UNLOCKED"); - seq_printf(s, "OTP clock switch startup is %uHz\n", otp->freq); - seq_printf(s, "PAF is %s\n", otp->paf ? "SET" : "NOT SET"); - seq_printf(s, "IMEI is %s\n", otp->imeich ? - "CHANGEABLE" : "NOT CHANGEABLE"); - seq_printf(s, "CID: 0x%04x (decimal: %d)\n", otp->cid, otp->cid); - seq_printf(s, "IMEI: %u-%u-%u\n", otp->tac, otp->fac, otp->svn); - return 0; -} - -static int ab3100_otp_open(struct inode *inode, struct file *file) -{ - return single_open(file, ab3100_show_otp, inode->i_private); -} - -static const struct file_operations ab3100_otp_operations = { - .open = ab3100_otp_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static void __init ab3100_otp_init_debugfs(struct device *dev, - struct ab3100_otp *otp) -{ - otp->debugfs = debugfs_create_file("ab3100_otp", S_IFREG | S_IRUGO, - NULL, otp, &ab3100_otp_operations); -} - -static void __exit ab3100_otp_exit_debugfs(struct ab3100_otp *otp) -{ - debugfs_remove(otp->debugfs); -} -#else -/* Compile this out if debugfs not selected */ -static inline void __init ab3100_otp_init_debugfs(struct device *dev, - struct ab3100_otp *otp) -{ -} - -static inline void __exit ab3100_otp_exit_debugfs(struct ab3100_otp *otp) -{ -} -#endif - -#define SHOW_AB3100_ATTR(name) \ -static ssize_t ab3100_otp_##name##_show(struct device *dev, \ - struct device_attribute *attr, \ - char *buf) \ -{\ - struct ab3100_otp *otp = dev_get_drvdata(dev); \ - return sprintf(buf, "%u\n", otp->name); \ -} - -SHOW_AB3100_ATTR(locked) -SHOW_AB3100_ATTR(freq) -SHOW_AB3100_ATTR(paf) -SHOW_AB3100_ATTR(imeich) -SHOW_AB3100_ATTR(cid) -SHOW_AB3100_ATTR(fac) -SHOW_AB3100_ATTR(tac) -SHOW_AB3100_ATTR(svn) - -static struct device_attribute ab3100_otp_attrs[] = { - __ATTR(locked, S_IRUGO, ab3100_otp_locked_show, NULL), - __ATTR(freq, S_IRUGO, ab3100_otp_freq_show, NULL), - __ATTR(paf, S_IRUGO, ab3100_otp_paf_show, NULL), - __ATTR(imeich, S_IRUGO, ab3100_otp_imeich_show, NULL), - __ATTR(cid, S_IRUGO, ab3100_otp_cid_show, NULL), - __ATTR(fac, S_IRUGO, ab3100_otp_fac_show, NULL), - __ATTR(tac, S_IRUGO, ab3100_otp_tac_show, NULL), - __ATTR(svn, S_IRUGO, ab3100_otp_svn_show, NULL), -}; - -static int __init ab3100_otp_probe(struct platform_device *pdev) -{ - struct ab3100_otp *otp; - int err = 0; - int i; - - otp = devm_kzalloc(&pdev->dev, sizeof(struct ab3100_otp), GFP_KERNEL); - if (!otp) - return -ENOMEM; - - otp->dev = &pdev->dev; - - /* Replace platform data coming in with a local struct */ - platform_set_drvdata(pdev, otp); - - err = ab3100_otp_read(otp); - if (err) - return err; - - dev_info(&pdev->dev, "AB3100 OTP readout registered\n"); - - /* sysfs entries */ - for (i = 0; i < ARRAY_SIZE(ab3100_otp_attrs); i++) { - err = device_create_file(&pdev->dev, - &ab3100_otp_attrs[i]); - if (err) - goto err; - } - - /* debugfs entries */ - ab3100_otp_init_debugfs(&pdev->dev, otp); - - return 0; - -err: - while (--i >= 0) - device_remove_file(&pdev->dev, &ab3100_otp_attrs[i]); - return err; -} - -static int __exit ab3100_otp_remove(struct platform_device *pdev) -{ - struct ab3100_otp *otp = platform_get_drvdata(pdev); - int i; - - for (i = 0; i < ARRAY_SIZE(ab3100_otp_attrs); i++) - device_remove_file(&pdev->dev, - &ab3100_otp_attrs[i]); - ab3100_otp_exit_debugfs(otp); - return 0; -} - -static struct platform_driver ab3100_otp_driver = { - .driver = { - .name = "ab3100-otp", - }, - .remove = __exit_p(ab3100_otp_remove), -}; - -module_platform_driver_probe(ab3100_otp_driver, ab3100_otp_probe); - -MODULE_AUTHOR("Linus Walleij "); -MODULE_DESCRIPTION("AB3100 OTP Readout Driver"); -MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/ab3100.h b/include/linux/mfd/ab3100.h deleted file mode 100644 index a881d8495186..000000000000 --- a/include/linux/mfd/ab3100.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2007-2009 ST-Ericsson AB - * AB3100 core access functions - * Author: Linus Walleij - */ - -#include - -struct device; - -#ifndef MFD_AB3100_H -#define MFD_AB3100_H - - -#define AB3100_P1A 0xc0 -#define AB3100_P1B 0xc1 -#define AB3100_P1C 0xc2 -#define AB3100_P1D 0xc3 -#define AB3100_P1E 0xc4 -#define AB3100_P1F 0xc5 -#define AB3100_P1G 0xc6 -#define AB3100_R2A 0xc7 -#define AB3100_R2B 0xc8 - -/* - * AB3100, EVENTA1, A2 and A3 event register flags - * these are catenated into a single 32-bit flag in the code - * for event notification broadcasts. - */ -#define AB3100_EVENTA1_ONSWA (0x01<<16) -#define AB3100_EVENTA1_ONSWB (0x02<<16) -#define AB3100_EVENTA1_ONSWC (0x04<<16) -#define AB3100_EVENTA1_DCIO (0x08<<16) -#define AB3100_EVENTA1_OVER_TEMP (0x10<<16) -#define AB3100_EVENTA1_SIM_OFF (0x20<<16) -#define AB3100_EVENTA1_VBUS (0x40<<16) -#define AB3100_EVENTA1_VSET_USB (0x80<<16) - -#define AB3100_EVENTA2_READY_TX (0x01<<8) -#define AB3100_EVENTA2_READY_RX (0x02<<8) -#define AB3100_EVENTA2_OVERRUN_ERROR (0x04<<8) -#define AB3100_EVENTA2_FRAMING_ERROR (0x08<<8) -#define AB3100_EVENTA2_CHARG_OVERCURRENT (0x10<<8) -#define AB3100_EVENTA2_MIDR (0x20<<8) -#define AB3100_EVENTA2_BATTERY_REM (0x40<<8) -#define AB3100_EVENTA2_ALARM (0x80<<8) - -#define AB3100_EVENTA3_ADC_TRIG5 (0x01) -#define AB3100_EVENTA3_ADC_TRIG4 (0x02) -#define AB3100_EVENTA3_ADC_TRIG3 (0x04) -#define AB3100_EVENTA3_ADC_TRIG2 (0x08) -#define AB3100_EVENTA3_ADC_TRIGVBAT (0x10) -#define AB3100_EVENTA3_ADC_TRIGVTX (0x20) -#define AB3100_EVENTA3_ADC_TRIG1 (0x40) -#define AB3100_EVENTA3_ADC_TRIG0 (0x80) - -/* AB3100, STR register flags */ -#define AB3100_STR_ONSWA (0x01) -#define AB3100_STR_ONSWB (0x02) -#define AB3100_STR_ONSWC (0x04) -#define AB3100_STR_DCIO (0x08) -#define AB3100_STR_BOOT_MODE (0x10) -#define AB3100_STR_SIM_OFF (0x20) -#define AB3100_STR_BATT_REMOVAL (0x40) -#define AB3100_STR_VBUS (0x80) - -/* - * AB3100 contains 8 regulators, one external regulator controller - * and a buck converter, further the LDO E and buck converter can - * have separate settings if they are in sleep mode, this is - * modeled as a separate regulator. - */ -#define AB3100_NUM_REGULATORS 10 - -/** - * struct ab3100 - * @access_mutex: lock out concurrent accesses to the AB3100 registers - * @dev: pointer to the containing device - * @i2c_client: I2C client for this chip - * @testreg_client: secondary client for test registers - * @chip_name: name of this chip variant - * @chip_id: 8 bit chip ID for this chip variant - * @event_subscribers: event subscribers are listed here - * @startup_events: a copy of the first reading of the event registers - * @startup_events_read: whether the first events have been read - * - * This struct is PRIVATE and devices using it should NOT - * access ANY fields. It is used as a token for calling the - * AB3100 functions. - */ -struct ab3100 { - struct mutex access_mutex; - struct device *dev; - struct i2c_client *i2c_client; - struct i2c_client *testreg_client; - char chip_name[32]; - u8 chip_id; - struct blocking_notifier_head event_subscribers; - u8 startup_events[3]; - bool startup_events_read; -}; - -/** - * struct ab3100_platform_data - * Data supplied to initialize board connections to the AB3100 - * @reg_constraints: regulator constraints for target board - * the order of these constraints are: LDO A, C, D, E, - * F, G, H, K, EXT and BUCK. - * @reg_initvals: initial values for the regulator registers - * plus two sleep settings for LDO E and the BUCK converter. - * exactly AB3100_NUM_REGULATORS+2 values must be sent in. - * Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK, - * BUCK sleep, LDO D. (LDO D need to be initialized last.) - * @external_voltage: voltage level of the external regulator. - */ -struct ab3100_platform_data { - struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS]; - u8 reg_initvals[AB3100_NUM_REGULATORS+2]; - int external_voltage; -}; - -int ab3100_event_register(struct ab3100 *ab3100, - struct notifier_block *nb); -int ab3100_event_unregister(struct ab3100 *ab3100, - struct notifier_block *nb); - -#endif /* MFD_AB3100_H */ -- cgit v1.2.3-71-gd317 From d9b326b2c3673f939941806146aee38e5c635fd0 Mon Sep 17 00:00:00 2001 From: Xu Yilun Date: Wed, 10 Mar 2021 23:55:45 +0800 Subject: mfd: intel-m10-bmc: Fix the register access range This patch fixes the max register address of MAX 10 BMC. The range 0x20000000 ~ 0x200000fc are for control registers of the QSPI flash controller, which are not accessible to host. Signed-off-by: Xu Yilun Reviewed-by: Tom Rix Signed-off-by: Lee Jones --- include/linux/mfd/intel-m10-bmc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h index 74d4e193966a..9b54ca13eac3 100644 --- a/include/linux/mfd/intel-m10-bmc.h +++ b/include/linux/mfd/intel-m10-bmc.h @@ -11,7 +11,7 @@ #define M10BMC_LEGACY_SYS_BASE 0x300400 #define M10BMC_SYS_BASE 0x300800 -#define M10BMC_MEM_END 0x200000fc +#define M10BMC_MEM_END 0x1fffffff /* Register offset of system registers */ #define NIOS2_FW_VERSION 0x0 -- cgit v1.2.3-71-gd317 From 5893f4d1f43036664010e3ae1d3f7a98b2165a5d Mon Sep 17 00:00:00 2001 From: Xu Yilun Date: Wed, 10 Mar 2021 23:55:46 +0800 Subject: mfd: intel-m10-bmc: Simplify the legacy version reg definition The version register is the only one in the legacy I/O space to be accessed, so it is not necessary to define the legacy base & version register offset. A direct definition of the legacy version register address would be fine. Signed-off-by: Xu Yilun Reviewed-by: Tom Rix Signed-off-by: Lee Jones --- drivers/mfd/intel-m10-bmc.c | 17 +++++++---------- include/linux/mfd/intel-m10-bmc.h | 2 +- 2 files changed, 8 insertions(+), 11 deletions(-) (limited to 'include/linux') diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c index 06c977519479..90d0448a5500 100644 --- a/drivers/mfd/intel-m10-bmc.c +++ b/drivers/mfd/intel-m10-bmc.c @@ -116,17 +116,14 @@ static int check_m10bmc_version(struct intel_m10bmc *ddata) int ret; /* - * This check is to filter out the very old legacy BMC versions, - * M10BMC_LEGACY_SYS_BASE is the offset to this old block of mmio - * registers. In the old BMC chips, the BMC version info is stored - * in this old version register (M10BMC_LEGACY_SYS_BASE + - * M10BMC_BUILD_VER), so its read out value would have not been - * LEGACY_INVALID (0xffffffff). But in new BMC chips that the - * driver supports, the value of this register should be - * LEGACY_INVALID. + * This check is to filter out the very old legacy BMC versions. In the + * old BMC chips, the BMC version info is stored in the old version + * register (M10BMC_LEGACY_BUILD_VER), so its read out value would have + * not been M10BMC_VER_LEGACY_INVALID (0xffffffff). But in new BMC + * chips that the driver supports, the value of this register should be + * M10BMC_VER_LEGACY_INVALID. */ - ret = m10bmc_raw_read(ddata, - M10BMC_LEGACY_SYS_BASE + M10BMC_BUILD_VER, &v); + ret = m10bmc_raw_read(ddata, M10BMC_LEGACY_BUILD_VER, &v); if (ret) return -ENODEV; diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h index 9b54ca13eac3..4f1071febb9e 100644 --- a/include/linux/mfd/intel-m10-bmc.h +++ b/include/linux/mfd/intel-m10-bmc.h @@ -9,7 +9,7 @@ #include -#define M10BMC_LEGACY_SYS_BASE 0x300400 +#define M10BMC_LEGACY_BUILD_VER 0x300468 #define M10BMC_SYS_BASE 0x300800 #define M10BMC_MEM_END 0x1fffffff -- cgit v1.2.3-71-gd317 From 8169f74ca6f318f4187536050d2f5408fce9c264 Mon Sep 17 00:00:00 2001 From: Matthew Gerlach Date: Wed, 10 Mar 2021 23:55:47 +0800 Subject: mfd: intel-m10-bmc: Add access table configuration to the regmap This patch adds access tables to the MAX 10 BMC regmap. This prevents the host from accessing the unwanted I/O space. It also filters out the invalid outputs when reading the regmap debugfs interface. Signed-off-by: Matthew Gerlach Signed-off-by: Xu Yilun Reviewed-by: Tom Rix Signed-off-by: Lee Jones --- drivers/mfd/intel-m10-bmc.c | 13 +++++++++++++ include/linux/mfd/intel-m10-bmc.h | 5 ++++- 2 files changed, 17 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c index 90d0448a5500..1161933cbd4a 100644 --- a/drivers/mfd/intel-m10-bmc.c +++ b/drivers/mfd/intel-m10-bmc.c @@ -23,10 +23,23 @@ static struct mfd_cell m10bmc_pacn3000_subdevs[] = { { .name = "n3000bmc-secure" }, }; +static const struct regmap_range m10bmc_regmap_range[] = { + regmap_reg_range(M10BMC_LEGACY_BUILD_VER, M10BMC_LEGACY_BUILD_VER), + regmap_reg_range(M10BMC_SYS_BASE, M10BMC_SYS_END), + regmap_reg_range(M10BMC_FLASH_BASE, M10BMC_FLASH_END), +}; + +static const struct regmap_access_table m10bmc_access_table = { + .yes_ranges = m10bmc_regmap_range, + .n_yes_ranges = ARRAY_SIZE(m10bmc_regmap_range), +}; + static struct regmap_config intel_m10bmc_regmap_config = { .reg_bits = 32, .val_bits = 32, .reg_stride = 4, + .wr_table = &m10bmc_access_table, + .rd_table = &m10bmc_access_table, .max_register = M10BMC_MEM_END, }; diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h index 4f1071febb9e..c4eb38c13eda 100644 --- a/include/linux/mfd/intel-m10-bmc.h +++ b/include/linux/mfd/intel-m10-bmc.h @@ -11,7 +11,10 @@ #define M10BMC_LEGACY_BUILD_VER 0x300468 #define M10BMC_SYS_BASE 0x300800 -#define M10BMC_MEM_END 0x1fffffff +#define M10BMC_SYS_END 0x300fff +#define M10BMC_FLASH_BASE 0x10000000 +#define M10BMC_FLASH_END 0x1fffffff +#define M10BMC_MEM_END M10BMC_FLASH_END /* Register offset of system registers */ #define NIOS2_FW_VERSION 0x0 -- cgit v1.2.3-71-gd317 From 586478bfc9f7e16504d6f64cf18bcbdf6fd0cbc9 Mon Sep 17 00:00:00 2001 From: Hubert Streidl Date: Tue, 16 Mar 2021 17:22:37 +0100 Subject: mfd: da9063: Support SMBus and I2C mode By default the PMIC DA9063 2-wire interface is SMBus compliant. This means the PMIC will automatically reset the interface when the clock signal ceases for more than the SMBus timeout of 35 ms. If the I2C driver / device is not capable of creating atomic I2C transactions, a context change can cause a ceasing of the clock signal. This can happen if for example a real-time thread is scheduled. Then the DA9063 in SMBus mode will reset the 2-wire interface. Subsequently a write message could end up in the wrong register. This could cause unpredictable system behavior. The DA9063 PMIC also supports an I2C compliant mode for the 2-wire interface. This mode does not reset the interface when the clock signal ceases. Thus the problem depicted above does not occur. This patch tests for the bus functionality "I2C_FUNC_I2C". It can reasonably be assumed that the bus cannot obey SMBus timings if this functionality is set. SMBus commands most probably are emulated in this case which is prone to the latency issue described above. This patch enables the I2C bus mode if I2C_FUNC_I2C is set or otherwise keeps the default SMBus mode. Signed-off-by: Hubert Streidl Signed-off-by: Mark Jonas Reviewed-by: Wolfram Sang Signed-off-by: Lee Jones --- drivers/mfd/da9063-i2c.c | 10 ++++++++++ include/linux/mfd/da9063/registers.h | 3 +++ 2 files changed, 13 insertions(+) (limited to 'include/linux') diff --git a/drivers/mfd/da9063-i2c.c b/drivers/mfd/da9063-i2c.c index 3781d0bb7786..783a14af18e2 100644 --- a/drivers/mfd/da9063-i2c.c +++ b/drivers/mfd/da9063-i2c.c @@ -442,6 +442,16 @@ static int da9063_i2c_probe(struct i2c_client *i2c, return ret; } + /* If SMBus is not available and only I2C is possible, enter I2C mode */ + if (i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) { + ret = regmap_clear_bits(da9063->regmap, DA9063_REG_CONFIG_J, + DA9063_TWOWIRE_TO); + if (ret < 0) { + dev_err(da9063->dev, "Failed to set Two-Wire Bus Mode.\n"); + return -EIO; + } + } + return da9063_device_init(da9063, i2c->irq); } diff --git a/include/linux/mfd/da9063/registers.h b/include/linux/mfd/da9063/registers.h index 1dbabf1b3cb8..6e0f66a2e727 100644 --- a/include/linux/mfd/da9063/registers.h +++ b/include/linux/mfd/da9063/registers.h @@ -1037,6 +1037,9 @@ #define DA9063_NONKEY_PIN_AUTODOWN 0x02 #define DA9063_NONKEY_PIN_AUTOFLPRT 0x03 +/* DA9063_REG_CONFIG_J (addr=0x10F) */ +#define DA9063_TWOWIRE_TO 0x40 + /* DA9063_REG_MON_REG_5 (addr=0x116) */ #define DA9063_MON_A8_IDX_MASK 0x07 #define DA9063_MON_A8_IDX_NONE 0x00 -- cgit v1.2.3-71-gd317 From 42e59982917a25ad254b74e6e8decee5e684763d Mon Sep 17 00:00:00 2001 From: Heikki Krogerus Date: Mon, 1 Mar 2021 16:42:19 +0200 Subject: mfd: core: Add support for software nodes The old device property API is going to be removed and replaced with the newer software node API. This prepares MFD subsystem for the transition. Signed-off-by: Heikki Krogerus Signed-off-by: Andy Shevchenko Signed-off-by: Lee Jones --- drivers/mfd/mfd-core.c | 9 +++++++++ include/linux/mfd/core.h | 4 ++++ 2 files changed, 13 insertions(+) (limited to 'include/linux') diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c index fc00aaccb5f7..e24008b94aac 100644 --- a/drivers/mfd/mfd-core.c +++ b/drivers/mfd/mfd-core.c @@ -244,6 +244,12 @@ static int mfd_add_device(struct device *parent, int id, goto fail_of_entry; } + if (cell->swnode) { + ret = device_add_software_node(&pdev->dev, cell->swnode); + if (ret) + goto fail_of_entry; + } + for (r = 0; r < cell->num_resources; r++) { res[r].name = cell->resources[r].name; res[r].flags = cell->resources[r].flags; @@ -304,6 +310,7 @@ fail_of_entry: list_del(&of_entry->list); kfree(of_entry); } + device_remove_software_node(&pdev->dev); fail_alias: regulator_bulk_unregister_supply_alias(&pdev->dev, cell->parent_supplies, @@ -372,6 +379,8 @@ static int mfd_remove_devices_fn(struct device *dev, void *data) regulator_bulk_unregister_supply_alias(dev, cell->parent_supplies, cell->num_parent_supplies); + device_remove_software_node(&pdev->dev); + platform_device_unregister(pdev); return 0; } diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h index 2009c4b936d9..9ec599167fe6 100644 --- a/include/linux/mfd/core.h +++ b/include/linux/mfd/core.h @@ -50,6 +50,7 @@ #define MFD_DEP_LEVEL_HIGH 1 struct irq_domain; +struct software_node; struct property_entry; /* Matches ACPI PNP id, either _HID or _CID, or ACPI _ADR */ @@ -78,6 +79,9 @@ struct mfd_cell { void *platform_data; size_t pdata_size; + /* Software node for the device. */ + const struct software_node *swnode; + /* device properties passed to the sub devices drivers */ const struct property_entry *properties; -- cgit v1.2.3-71-gd317 From b4a66acc0997cff7cb9a4c3992e97808700aa1ff Mon Sep 17 00:00:00 2001 From: Heikki Krogerus Date: Mon, 1 Mar 2021 16:42:22 +0200 Subject: mfd: core: Remove support for dangling device properties From now on only accepting complete software nodes. Signed-off-by: Heikki Krogerus Signed-off-by: Andy Shevchenko Signed-off-by: Lee Jones --- drivers/mfd/mfd-core.c | 6 ------ include/linux/mfd/core.h | 4 ---- 2 files changed, 10 deletions(-) (limited to 'include/linux') diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c index e24008b94aac..6dcff4b8e15e 100644 --- a/drivers/mfd/mfd-core.c +++ b/drivers/mfd/mfd-core.c @@ -238,12 +238,6 @@ static int mfd_add_device(struct device *parent, int id, goto fail_of_entry; } - if (cell->properties) { - ret = platform_device_add_properties(pdev, cell->properties); - if (ret) - goto fail_of_entry; - } - if (cell->swnode) { ret = device_add_software_node(&pdev->dev, cell->swnode); if (ret) diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h index 9ec599167fe6..0bc7cba798a3 100644 --- a/include/linux/mfd/core.h +++ b/include/linux/mfd/core.h @@ -51,7 +51,6 @@ struct irq_domain; struct software_node; -struct property_entry; /* Matches ACPI PNP id, either _HID or _CID, or ACPI _ADR */ struct mfd_cell_acpi_match { @@ -82,9 +81,6 @@ struct mfd_cell { /* Software node for the device. */ const struct software_node *swnode; - /* device properties passed to the sub devices drivers */ - const struct property_entry *properties; - /* * Device Tree compatible string * See: Documentation/devicetree/usage-model.rst Chapter 2.2 for details -- cgit v1.2.3-71-gd317 From 4502647e60cb4afd74f74d648bc2990954c1b73a Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Sun, 14 Mar 2021 12:02:36 +0100 Subject: mfd: rn5t618: Do not cache various USB related registers These register get reset to their OTP defaults after USB plugging. And while at it, also add a missing register for detecting the charger type. Signed-off-by: Andreas Kemnade Signed-off-by: Lee Jones --- drivers/mfd/rn5t618.c | 3 +++ include/linux/mfd/rn5t618.h | 1 + 2 files changed, 4 insertions(+) (limited to 'include/linux') diff --git a/drivers/mfd/rn5t618.c b/drivers/mfd/rn5t618.c index dc452df1f1bf..6ed04e6dbc78 100644 --- a/drivers/mfd/rn5t618.c +++ b/drivers/mfd/rn5t618.c @@ -45,8 +45,11 @@ static bool rn5t618_volatile_reg(struct device *dev, unsigned int reg) case RN5T618_INTMON: case RN5T618_RTC_CTRL1 ... RN5T618_RTC_CTRL2: case RN5T618_RTC_SECONDS ... RN5T618_RTC_YEAR: + case RN5T618_CHGCTL1: + case RN5T618_REGISET1 ... RN5T618_REGISET2: case RN5T618_CHGSTATE: case RN5T618_CHGCTRL_IRR ... RN5T618_CHGERR_MONI: + case RN5T618_GCHGDET: case RN5T618_CONTROL ... RN5T618_CC_AVEREG0: return true; default: diff --git a/include/linux/mfd/rn5t618.h b/include/linux/mfd/rn5t618.h index fba0df13d9a8..8aa0bda1af4f 100644 --- a/include/linux/mfd/rn5t618.h +++ b/include/linux/mfd/rn5t618.h @@ -188,6 +188,7 @@ #define RN5T618_CHGOSCSCORESET3 0xd7 #define RN5T618_CHGOSCFREQSET1 0xd8 #define RN5T618_CHGOSCFREQSET2 0xd9 +#define RN5T618_GCHGDET 0xda #define RN5T618_CONTROL 0xe0 #define RN5T618_SOC 0xe1 #define RN5T618_RE_CAP_H 0xe2 -- cgit v1.2.3-71-gd317 From d1157530d476ffce4485182eea5b492065362a09 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Mon, 15 Mar 2021 20:18:32 +0100 Subject: mfd: ntxec: Support for EC in Tolino Shine 2 HD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the version of the EC in the Tolino Shine 2 HD to the supported versions. It seems not to have an RTC and does not ack data written to it. The vendor kernel happily ignores write errors, using I2C via userspace i2c-set also shows the error. So add a quirk to ignore that error. PWM can be successfully configured despite of that error. Signed-off-by: Andreas Kemnade Reviewed-by: Jonathan Neuschäfer Signed-off-by: Lee Jones --- drivers/mfd/ntxec.c | 56 ++++++++++++++++++++++++++++++++++++++++++++--- include/linux/mfd/ntxec.h | 1 + 2 files changed, 54 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/drivers/mfd/ntxec.c b/drivers/mfd/ntxec.c index 957de2b03529..b711e73eedcb 100644 --- a/drivers/mfd/ntxec.c +++ b/drivers/mfd/ntxec.c @@ -96,6 +96,38 @@ static struct notifier_block ntxec_restart_handler = { .priority = 128, }; +static int regmap_ignore_write(void *context, + unsigned int reg, unsigned int val) + +{ + struct regmap *regmap = context; + + regmap_write(regmap, reg, val); + + return 0; +} + +static int regmap_wrap_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct regmap *regmap = context; + + return regmap_read(regmap, reg, val); +} + +/* + * Some firmware versions do not ack written data, add a wrapper. It + * is used to stack another regmap on top. + */ +static const struct regmap_config regmap_config_noack = { + .name = "ntxec_noack", + .reg_bits = 8, + .val_bits = 16, + .cache_type = REGCACHE_NONE, + .reg_write = regmap_ignore_write, + .reg_read = regmap_wrap_read +}; + static const struct regmap_config regmap_config = { .name = "ntxec", .reg_bits = 8, @@ -104,16 +136,22 @@ static const struct regmap_config regmap_config = { .val_format_endian = REGMAP_ENDIAN_BIG, }; -static const struct mfd_cell ntxec_subdevices[] = { +static const struct mfd_cell ntxec_subdev[] = { { .name = "ntxec-rtc" }, { .name = "ntxec-pwm" }, }; +static const struct mfd_cell ntxec_subdev_pwm[] = { + { .name = "ntxec-pwm" }, +}; + static int ntxec_probe(struct i2c_client *client) { struct ntxec *ec; unsigned int version; int res; + const struct mfd_cell *subdevs; + size_t n_subdevs; ec = devm_kmalloc(&client->dev, sizeof(*ec), GFP_KERNEL); if (!ec) @@ -137,6 +175,18 @@ static int ntxec_probe(struct i2c_client *client) /* Bail out if we encounter an unknown firmware version */ switch (version) { case NTXEC_VERSION_KOBO_AURA: + subdevs = ntxec_subdev; + n_subdevs = ARRAY_SIZE(ntxec_subdev); + break; + case NTXEC_VERSION_TOLINO_SHINE2: + subdevs = ntxec_subdev_pwm; + n_subdevs = ARRAY_SIZE(ntxec_subdev_pwm); + /* Another regmap stacked on top of the other */ + ec->regmap = devm_regmap_init(ec->dev, NULL, + ec->regmap, + ®map_config_noack); + if (IS_ERR(ec->regmap)) + return PTR_ERR(ec->regmap); break; default: dev_err(ec->dev, @@ -181,8 +231,8 @@ static int ntxec_probe(struct i2c_client *client) i2c_set_clientdata(client, ec); - res = devm_mfd_add_devices(ec->dev, PLATFORM_DEVID_NONE, ntxec_subdevices, - ARRAY_SIZE(ntxec_subdevices), NULL, 0, NULL); + res = devm_mfd_add_devices(ec->dev, PLATFORM_DEVID_NONE, + subdevs, n_subdevs, NULL, 0, NULL); if (res) dev_err(ec->dev, "Failed to add subdevices: %d\n", res); diff --git a/include/linux/mfd/ntxec.h b/include/linux/mfd/ntxec.h index 361204d125f1..26ab3b8eb612 100644 --- a/include/linux/mfd/ntxec.h +++ b/include/linux/mfd/ntxec.h @@ -33,5 +33,6 @@ static inline __be16 ntxec_reg8(u8 value) /* Known firmware versions */ #define NTXEC_VERSION_KOBO_AURA 0xd726 /* found in Kobo Aura */ +#define NTXEC_VERSION_TOLINO_SHINE2 0xf110 /* found in Tolino Shine 2 HD */ #endif -- cgit v1.2.3-71-gd317 From 0b79c53e8a1c5c26c5a364c8f041ca6890a29f08 Mon Sep 17 00:00:00 2001 From: Timon Baetz Date: Wed, 27 Jan 2021 07:32:42 +0000 Subject: mfd: max8997: Replace 8998 with 8997 The max8997 header is using "max8998" in some identifiers. Fix it by replacing 8998 with 8997 in enum and macro. Signed-off-by: Timon Baetz Signed-off-by: Lee Jones --- include/linux/mfd/max8997.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h index e955e2f0a2cc..6c98edcf4b0b 100644 --- a/include/linux/mfd/max8997.h +++ b/include/linux/mfd/max8997.h @@ -14,13 +14,13 @@ * others and b) it can be enabled simply by using MAX17042 driver. */ -#ifndef __LINUX_MFD_MAX8998_H -#define __LINUX_MFD_MAX8998_H +#ifndef __LINUX_MFD_MAX8997_H +#define __LINUX_MFD_MAX8997_H #include /* MAX8997/8966 regulator IDs */ -enum max8998_regulators { +enum max8997_regulators { MAX8997_LDO1 = 0, MAX8997_LDO2, MAX8997_LDO3, @@ -207,4 +207,4 @@ struct max8997_platform_data { struct max8997_led_platform_data *led_pdata; }; -#endif /* __LINUX_MFD_MAX8998_H */ +#endif /* __LINUX_MFD_MAX8997_H */ -- cgit v1.2.3-71-gd317 From 5a517b5bf687028149d55ba50b393c288a054601 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 31 Mar 2021 18:48:51 +0300 Subject: i2c: designware: Get rid of legacy platform data Platform data is a legacy interface to supply device properties to the driver. In this case we don't have anymore in-kernel users for it. Just remove it for good. Signed-off-by: Andy Shevchenko Acked-by: Wolfram Sang Acked-by: Jarkko Nikula Signed-off-by: Lee Jones --- drivers/i2c/busses/i2c-designware-platdrv.c | 7 +------ include/linux/platform_data/i2c-designware.h | 13 ------------- 2 files changed, 1 insertion(+), 19 deletions(-) delete mode 100644 include/linux/platform_data/i2c-designware.h (limited to 'include/linux') diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c index 0dfeb2d11603..4b37f28ec0c6 100644 --- a/drivers/i2c/busses/i2c-designware-platdrv.c +++ b/drivers/i2c/busses/i2c-designware-platdrv.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -206,7 +205,6 @@ static const struct dmi_system_id dw_i2c_hwmon_class_dmi[] = { static int dw_i2c_plat_probe(struct platform_device *pdev) { - struct dw_i2c_platform_data *pdata = dev_get_platdata(&pdev->dev); struct i2c_adapter *adap; struct dw_i2c_dev *dev; struct i2c_timings *t; @@ -236,10 +234,7 @@ static int dw_i2c_plat_probe(struct platform_device *pdev) reset_control_deassert(dev->rst); t = &dev->timings; - if (pdata) - t->bus_freq_hz = pdata->i2c_scl_freq; - else - i2c_parse_fw_timings(&pdev->dev, t, false); + i2c_parse_fw_timings(&pdev->dev, t, false); i2c_dw_adjust_bus_speed(dev); diff --git a/include/linux/platform_data/i2c-designware.h b/include/linux/platform_data/i2c-designware.h deleted file mode 100644 index 014c4a5a7e13..000000000000 --- a/include/linux/platform_data/i2c-designware.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright(c) 2014 Intel Corporation. - */ - -#ifndef I2C_DESIGNWARE_H -#define I2C_DESIGNWARE_H - -struct dw_i2c_platform_data { - unsigned int i2c_scl_freq; -}; - -#endif -- cgit v1.2.3-71-gd317 From ed25b4f00b61e109b29dc443dd1333b9b0da9bb4 Mon Sep 17 00:00:00 2001 From: YueHaibing Date: Thu, 1 Apr 2021 22:18:40 +0800 Subject: mfd: twl: Remove unused inline function twl4030charger_usb_en() There is no caller in tree, so can remove it. Signed-off-by: YueHaibing Signed-off-by: Lee Jones --- include/linux/mfd/twl.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mfd/twl.h b/include/linux/mfd/twl.h index 089e8942223a..8871cc5188a0 100644 --- a/include/linux/mfd/twl.h +++ b/include/linux/mfd/twl.h @@ -781,8 +781,6 @@ int twl4030_sih_setup(struct device *dev, int module, int irq_base); #define TWL4030_VAUX3_DEV_GRP 0x1F #define TWL4030_VAUX3_DEDICATED 0x22 -static inline int twl4030charger_usb_en(int enable) { return 0; } - /*----------------------------------------------------------------------*/ /* Linux-specific regulator identifiers ... for now, we only support -- cgit v1.2.3-71-gd317 From f9386c91574fe6da9f4fca9a47734816b0db0019 Mon Sep 17 00:00:00 2001 From: Russ Weight Date: Mon, 12 Apr 2021 12:53:28 -0700 Subject: mfd: intel-m10-bmc: Add support for MAX10 BMC Secure Updates Add macros and definitions required by the MAX10 BMC Secure Update driver. Signed-off-by: Russ Weight Signed-off-by: Lee Jones --- include/linux/mfd/intel-m10-bmc.h | 85 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) (limited to 'include/linux') diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h index c4eb38c13eda..f0044b14136e 100644 --- a/include/linux/mfd/intel-m10-bmc.h +++ b/include/linux/mfd/intel-m10-bmc.h @@ -16,6 +16,9 @@ #define M10BMC_FLASH_END 0x1fffffff #define M10BMC_MEM_END M10BMC_FLASH_END +#define M10BMC_STAGING_BASE 0x18000000 +#define M10BMC_STAGING_SIZE 0x3800000 + /* Register offset of system registers */ #define NIOS2_FW_VERSION 0x0 #define M10BMC_MAC_LOW 0x10 @@ -33,6 +36,88 @@ #define M10BMC_VER_PCB_INFO_MSK GENMASK(31, 24) #define M10BMC_VER_LEGACY_INVALID 0xffffffff +/* Secure update doorbell register, in system register region */ +#define M10BMC_DOORBELL 0x400 + +/* Authorization Result register, in system register region */ +#define M10BMC_AUTH_RESULT 0x404 + +/* Doorbell register fields */ +#define DRBL_RSU_REQUEST BIT(0) +#define DRBL_RSU_PROGRESS GENMASK(7, 4) +#define DRBL_HOST_STATUS GENMASK(11, 8) +#define DRBL_RSU_STATUS GENMASK(23, 16) +#define DRBL_PKVL_EEPROM_LOAD_SEC BIT(24) +#define DRBL_PKVL1_POLL_EN BIT(25) +#define DRBL_PKVL2_POLL_EN BIT(26) +#define DRBL_CONFIG_SEL BIT(28) +#define DRBL_REBOOT_REQ BIT(29) +#define DRBL_REBOOT_DISABLED BIT(30) + +/* Progress states */ +#define RSU_PROG_IDLE 0x0 +#define RSU_PROG_PREPARE 0x1 +#define RSU_PROG_READY 0x3 +#define RSU_PROG_AUTHENTICATING 0x4 +#define RSU_PROG_COPYING 0x5 +#define RSU_PROG_UPDATE_CANCEL 0x6 +#define RSU_PROG_PROGRAM_KEY_HASH 0x7 +#define RSU_PROG_RSU_DONE 0x8 +#define RSU_PROG_PKVL_PROM_DONE 0x9 + +/* Device and error states */ +#define RSU_STAT_NORMAL 0x0 +#define RSU_STAT_TIMEOUT 0x1 +#define RSU_STAT_AUTH_FAIL 0x2 +#define RSU_STAT_COPY_FAIL 0x3 +#define RSU_STAT_FATAL 0x4 +#define RSU_STAT_PKVL_REJECT 0x5 +#define RSU_STAT_NON_INC 0x6 +#define RSU_STAT_ERASE_FAIL 0x7 +#define RSU_STAT_WEAROUT 0x8 +#define RSU_STAT_NIOS_OK 0x80 +#define RSU_STAT_USER_OK 0x81 +#define RSU_STAT_FACTORY_OK 0x82 +#define RSU_STAT_USER_FAIL 0x83 +#define RSU_STAT_FACTORY_FAIL 0x84 +#define RSU_STAT_NIOS_FLASH_ERR 0x85 +#define RSU_STAT_FPGA_FLASH_ERR 0x86 + +#define HOST_STATUS_IDLE 0x0 +#define HOST_STATUS_WRITE_DONE 0x1 +#define HOST_STATUS_ABORT_RSU 0x2 + +#define rsu_prog(doorbell) FIELD_GET(DRBL_RSU_PROGRESS, doorbell) +#define rsu_stat(doorbell) FIELD_GET(DRBL_RSU_STATUS, doorbell) + +/* interval 100ms and timeout 5s */ +#define NIOS_HANDSHAKE_INTERVAL_US (100 * 1000) +#define NIOS_HANDSHAKE_TIMEOUT_US (5 * 1000 * 1000) + +/* RSU PREP Timeout (2 minutes) to erase flash staging area */ +#define RSU_PREP_INTERVAL_MS 100 +#define RSU_PREP_TIMEOUT_MS (2 * 60 * 1000) + +/* RSU Complete Timeout (40 minutes) for full flash update */ +#define RSU_COMPLETE_INTERVAL_MS 1000 +#define RSU_COMPLETE_TIMEOUT_MS (40 * 60 * 1000) + +/* Addresses for security related data in FLASH */ +#define BMC_REH_ADDR 0x17ffc004 +#define BMC_PROG_ADDR 0x17ffc000 +#define BMC_PROG_MAGIC 0x5746 + +#define SR_REH_ADDR 0x17ffd004 +#define SR_PROG_ADDR 0x17ffd000 +#define SR_PROG_MAGIC 0x5253 + +#define PR_REH_ADDR 0x17ffe004 +#define PR_PROG_ADDR 0x17ffe000 +#define PR_PROG_MAGIC 0x5250 + +/* Address of 4KB inverted bit vector containing staging area FLASH count */ +#define STAGING_FLASH_COUNT 0x17ffb000 + /** * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure * @dev: this device -- cgit v1.2.3-71-gd317