From 1ac710e08a86e4723286873db73edb2a6e99f591 Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Wed, 7 Oct 2015 14:54:08 +0100 Subject: mfd: da9150: Add support for Fuel-Gauge Signed-off-by: Adam Thomson Signed-off-by: Lee Jones --- include/linux/mfd/da9150/core.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/mfd/da9150/core.h b/include/linux/mfd/da9150/core.h index 76e668933a77..1bf50caeb9fa 100644 --- a/include/linux/mfd/da9150/core.h +++ b/include/linux/mfd/da9150/core.h @@ -15,6 +15,7 @@ #define __DA9150_CORE_H #include +#include #include #include @@ -46,23 +47,39 @@ #define DA9150_IRQ_GPADC 19 #define DA9150_IRQ_WKUP 20 +/* I2C sub-device address */ +#define DA9150_QIF_I2C_ADDR_LSB 0x5 + +struct da9150_fg_pdata { + u32 update_interval; /* msecs */ + u8 warn_soc_lvl; /* % value */ + u8 crit_soc_lvl; /* % value */ +}; + struct da9150_pdata { int irq_base; + struct da9150_fg_pdata *fg_pdata; }; struct da9150 { struct device *dev; struct regmap *regmap; + struct i2c_client *core_qif; + struct regmap_irq_chip_data *regmap_irq_data; int irq; int irq_base; }; -/* Device I/O */ +/* Device I/O - Query Interface for FG and standard register access */ +void da9150_read_qif(struct da9150 *da9150, u8 addr, int count, u8 *buf); +void da9150_write_qif(struct da9150 *da9150, u8 addr, int count, const u8 *buf); + u8 da9150_reg_read(struct da9150 *da9150, u16 reg); void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val); void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val); void da9150_bulk_read(struct da9150 *da9150, u16 reg, int count, u8 *buf); void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf); + #endif /* __DA9150_CORE_H */ -- cgit v1.2.3-71-gd317 From 98a3be44ffa67b812de7aa7aed9f2331edcfb1a5 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 23 Oct 2015 12:16:41 +0300 Subject: mfd: core: redo ACPI matching of the children devices There is at least one board on the market, i.e. Intel Galileo Gen2, that uses _ADR to distinguish the devices under one actual device. Due to this we have to improve the quirk in the MFD core to handle that board. Acked-by: Rafael J. Wysocki Acked-by: Lee Jones Signed-off-by: Andy Shevchenko Signed-off-by: Wolfram Sang --- Documentation/acpi/enumeration.txt | 11 +++++--- drivers/mfd/mfd-core.c | 52 ++++++++++++++++++++++++++------------ include/linux/mfd/core.h | 10 ++++++-- 3 files changed, 52 insertions(+), 21 deletions(-) (limited to 'include/linux') diff --git a/Documentation/acpi/enumeration.txt b/Documentation/acpi/enumeration.txt index b731b292e812..a91ec5af52df 100644 --- a/Documentation/acpi/enumeration.txt +++ b/Documentation/acpi/enumeration.txt @@ -347,13 +347,18 @@ For the first case, the MFD drivers do not need to do anything. The resulting child platform device will have its ACPI_COMPANION() set to point to the parent device. -If the ACPI namespace has a device that we can match using an ACPI id, -the id should be set like: +If the ACPI namespace has a device that we can match using an ACPI id or ACPI +adr, the cell should be set like: + + static struct mfd_cell_acpi_match my_subdevice_cell_acpi_match = { + .pnpid = "XYZ0001", + .adr = 0, + }; static struct mfd_cell my_subdevice_cell = { .name = "my_subdevice", /* set the resources relative to the parent */ - .acpi_pnpid = "XYZ0001", + .acpi_match = &my_subdevice_cell_acpi_match, }; The ACPI id "XYZ0001" is then used to lookup an ACPI device directly under diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c index c17635d3e504..60b60dc63ddd 100644 --- a/drivers/mfd/mfd-core.c +++ b/drivers/mfd/mfd-core.c @@ -82,29 +82,49 @@ static int mfd_platform_add_cell(struct platform_device *pdev, static void mfd_acpi_add_device(const struct mfd_cell *cell, struct platform_device *pdev) { - struct acpi_device *parent_adev; + const struct mfd_cell_acpi_match *match = cell->acpi_match; + struct acpi_device *parent, *child; struct acpi_device *adev; - parent_adev = ACPI_COMPANION(pdev->dev.parent); - if (!parent_adev) + parent = ACPI_COMPANION(pdev->dev.parent); + if (!parent) return; /* - * MFD child device gets its ACPI handle either from the ACPI - * device directly under the parent that matches the acpi_pnpid or - * it will use the parent handle if is no acpi_pnpid is given. + * MFD child device gets its ACPI handle either from the ACPI device + * directly under the parent that matches the either _HID or _CID, or + * _ADR or it will use the parent handle if is no ID is given. + * + * Note that use of _ADR is a grey area in the ACPI specification, + * though Intel Galileo Gen2 is using it to distinguish the children + * devices. */ - adev = parent_adev; - if (cell->acpi_pnpid) { - struct acpi_device_id ids[2] = {}; - struct acpi_device *child_adev; - - strlcpy(ids[0].id, cell->acpi_pnpid, sizeof(ids[0].id)); - list_for_each_entry(child_adev, &parent_adev->children, node) - if (acpi_match_device_ids(child_adev, ids)) { - adev = child_adev; - break; + adev = parent; + if (match) { + if (match->pnpid) { + struct acpi_device_id ids[2] = {}; + + strlcpy(ids[0].id, match->pnpid, sizeof(ids[0].id)); + list_for_each_entry(child, &parent->children, node) { + if (acpi_match_device_ids(child, ids)) { + adev = child; + break; + } + } + } else { + unsigned long long adr; + acpi_status status; + + list_for_each_entry(child, &parent->children, node) { + status = acpi_evaluate_integer(child->handle, + "_ADR", NULL, + &adr); + if (ACPI_SUCCESS(status) && match->adr == adr) { + adev = child; + break; + } } + } } ACPI_COMPANION_SET(&pdev->dev, adev); diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h index a76bc100bf97..27dac3ff18b9 100644 --- a/include/linux/mfd/core.h +++ b/include/linux/mfd/core.h @@ -18,6 +18,12 @@ struct irq_domain; +/* Matches ACPI PNP id, either _HID or _CID, or ACPI _ADR */ +struct mfd_cell_acpi_match { + const char *pnpid; + const unsigned long long adr; +}; + /* * This struct describes the MFD part ("cell"). * After registration the copy of this structure will become the platform data @@ -44,8 +50,8 @@ struct mfd_cell { */ const char *of_compatible; - /* Matches ACPI PNP id, either _HID or _CID */ - const char *acpi_pnpid; + /* Matches ACPI */ + const struct mfd_cell_acpi_match *acpi_match; /* * These resources can be specified relative to the parent device. -- cgit v1.2.3-71-gd317 From 62a2e633474107a9ae93dfedf16341ec6414a907 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Tue, 25 Aug 2015 14:34:28 +0530 Subject: mfd: 88pm80x: Add 88pm860 chip type support Add chip identification support for 88PM860 device to the pm80x_chip_mapping table. Signed-off-by: Vaibhav Hiremath Reviewed-by: Krzysztof Kozlowski Signed-off-by: Lee Jones --- drivers/mfd/88pm80x.c | 2 ++ include/linux/mfd/88pm80x.h | 1 + 2 files changed, 3 insertions(+) (limited to 'include/linux') diff --git a/drivers/mfd/88pm80x.c b/drivers/mfd/88pm80x.c index 5e72f65ef94c..63445ea6b0bf 100644 --- a/drivers/mfd/88pm80x.c +++ b/drivers/mfd/88pm80x.c @@ -33,6 +33,8 @@ static struct pm80x_chip_mapping chip_mapping[] = { {0x3, CHIP_PM800}, /* 88PM805 chip id number */ {0x0, CHIP_PM805}, + /* 88PM860 chip id number */ + {0x4, CHIP_PM860}, }; /* diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h index 8fcad63fab55..d409ceb2231e 100644 --- a/include/linux/mfd/88pm80x.h +++ b/include/linux/mfd/88pm80x.h @@ -21,6 +21,7 @@ enum { CHIP_INVALID = 0, CHIP_PM800, CHIP_PM805, + CHIP_PM860, CHIP_MAX, }; -- cgit v1.2.3-71-gd317 From d785334a0d5deff30a487c74324b842d2179553d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 14 Sep 2015 21:12:45 +0900 Subject: mfd: s2mps11: Add manual shutdown method for Odroid XU3 On Odroid XU3 board (with S2MPS11 PMIC) the PWRHOLD bit in CTRL1 register must be manually set to 0 before initiating power off sequence. One of usual power down methods for Exynos based devices looks like: 1. PWRHOLD pin of PMIC is connected to PSHOLD of Exynos SoC. 2. Exynos holds up this pin during system operation. 3. ACOKB pin of PMIC is pulled up to VBATT and optionally to pin in other device. 4. When PWRHOLD/PSHOLD goes low, the PMIC will turn off the power if ACOKB goes high. On Odroid XU3 family the difference is in (3) - the ACOKB is grounded. This means that PMIC must manually set PWRHOLD field to low and then wait for signal from Application Processor (the usual change in PWRHOLD/PSHOLD pin will actually cut off the power). The patch adds respective binding allowing Odroid XU3 device to be powered off. Signed-off-by: Krzysztof Kozlowski Reported-by: Anand Moon Tested-by: Anand Moon Reviewed-by: Javier Martinez Canillas Signed-off-by: Lee Jones --- drivers/mfd/sec-core.c | 30 ++++++++++++++++++++++++++++++ include/linux/mfd/samsung/core.h | 2 ++ include/linux/mfd/samsung/s2mps11.h | 1 + 3 files changed, 33 insertions(+) (limited to 'include/linux') diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c index d206a3e8fe87..2d1137a7a0ee 100644 --- a/drivers/mfd/sec-core.c +++ b/drivers/mfd/sec-core.c @@ -278,6 +278,8 @@ static struct sec_platform_data *sec_pmic_i2c_parse_dt_pdata( * not parsed here. */ + pd->manual_poweroff = of_property_read_bool(dev->of_node, + "samsung,s2mps11-acokb-ground"); return pd; } #else @@ -440,6 +442,33 @@ static int sec_pmic_remove(struct i2c_client *i2c) return 0; } +static void sec_pmic_shutdown(struct i2c_client *i2c) +{ + struct sec_pmic_dev *sec_pmic = i2c_get_clientdata(i2c); + unsigned int reg, mask; + + if (!sec_pmic->pdata->manual_poweroff) + return; + + switch (sec_pmic->device_type) { + case S2MPS11X: + reg = S2MPS11_REG_CTRL1; + mask = S2MPS11_CTRL1_PWRHOLD_MASK; + break; + default: + /* + * Currently only one board with S2MPS11 needs this, so just + * ignore the rest. + */ + dev_warn(sec_pmic->dev, + "Unsupported device %lu for manual power off\n", + sec_pmic->device_type); + return; + } + + regmap_update_bits(sec_pmic->regmap_pmic, reg, mask, 0); +} + #ifdef CONFIG_PM_SLEEP static int sec_pmic_suspend(struct device *dev) { @@ -491,6 +520,7 @@ static struct i2c_driver sec_pmic_driver = { }, .probe = sec_pmic_probe, .remove = sec_pmic_remove, + .shutdown = sec_pmic_shutdown, .id_table = sec_pmic_id, }; diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h index 75115384f3fc..aa78957e092f 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -132,6 +132,8 @@ struct sec_platform_data { int buck2_init; int buck3_init; int buck4_init; + /* Whether or not manually set PWRHOLD to low during shutdown. */ + bool manual_poweroff; }; /** diff --git a/include/linux/mfd/samsung/s2mps11.h b/include/linux/mfd/samsung/s2mps11.h index 7981a9d77d3f..b288965e8101 100644 --- a/include/linux/mfd/samsung/s2mps11.h +++ b/include/linux/mfd/samsung/s2mps11.h @@ -179,6 +179,7 @@ enum s2mps11_regulators { #define S2MPS11_BUCK_N_VOLTAGES (S2MPS11_BUCK_VSEL_MASK + 1) #define S2MPS11_RAMP_DELAY 25000 /* uV/us */ +#define S2MPS11_CTRL1_PWRHOLD_MASK BIT(4) #define S2MPS11_BUCK2_RAMP_SHIFT 6 #define S2MPS11_BUCK34_RAMP_SHIFT 4 -- cgit v1.2.3-71-gd317 From 9111fa5c4032589e9b7ccc01e330810ba05726bf Mon Sep 17 00:00:00 2001 From: Charles Keepax Date: Wed, 9 Sep 2015 09:49:22 +0100 Subject: mfd: arizona: Add register bits to support the ANC block Some Arizona devices have a hardware ANC block present. This patch adds the registers necessary to configure this hardware block. Signed-off-by: Charles Keepax Signed-off-by: Lee Jones --- drivers/mfd/wm5110-tables.c | 186 ++++++++++++++++++++++++++++++++++ include/linux/mfd/arizona/registers.h | 70 +++++++++++++ 2 files changed, 256 insertions(+) (limited to 'include/linux') diff --git a/drivers/mfd/wm5110-tables.c b/drivers/mfd/wm5110-tables.c index 46cad3280114..2bb2d0467a92 100644 --- a/drivers/mfd/wm5110-tables.c +++ b/drivers/mfd/wm5110-tables.c @@ -1633,6 +1633,185 @@ static const struct reg_default wm5110_reg_default[] = { { 0x00000EF8, 0x0000 }, /* R3832 - ISRC 3 CTRL 3 */ { 0x00000F00, 0x0000 }, /* R3840 - Clock Control */ { 0x00000F01, 0x0000 }, /* R3841 - ANC_SRC */ + { 0x00000F08, 0x001c }, /* R3848 - ANC Coefficient */ + { 0x00000F09, 0x0000 }, /* R3849 - ANC Coefficient */ + { 0x00000F0A, 0x0000 }, /* R3850 - ANC Coefficient */ + { 0x00000F0B, 0x0000 }, /* R3851 - ANC Coefficient */ + { 0x00000F0C, 0x0000 }, /* R3852 - ANC Coefficient */ + { 0x00000F0D, 0x0000 }, /* R3853 - ANC Coefficient */ + { 0x00000F0E, 0x0000 }, /* R3854 - ANC Coefficient */ + { 0x00000F0F, 0x0000 }, /* R3855 - ANC Coefficient */ + { 0x00000F10, 0x0000 }, /* R3856 - ANC Coefficient */ + { 0x00000F11, 0x0000 }, /* R3857 - ANC Coefficient */ + { 0x00000F12, 0x0000 }, /* R3858 - ANC Coefficient */ + { 0x00000F15, 0x0000 }, /* R3861 - FCL Filter Control */ + { 0x00000F17, 0x0004 }, /* R3863 - FCL ADC Reformatter Control */ + { 0x00000F18, 0x0004 }, /* R3864 - ANC Coefficient */ + { 0x00000F19, 0x0002 }, /* R3865 - ANC Coefficient */ + { 0x00000F1A, 0x0000 }, /* R3866 - ANC Coefficient */ + { 0x00000F1B, 0x0010 }, /* R3867 - ANC Coefficient */ + { 0x00000F1C, 0x0000 }, /* R3868 - ANC Coefficient */ + { 0x00000F1D, 0x0000 }, /* R3869 - ANC Coefficient */ + { 0x00000F1E, 0x0000 }, /* R3870 - ANC Coefficient */ + { 0x00000F1F, 0x0000 }, /* R3871 - ANC Coefficient */ + { 0x00000F20, 0x0000 }, /* R3872 - ANC Coefficient */ + { 0x00000F21, 0x0000 }, /* R3873 - ANC Coefficient */ + { 0x00000F22, 0x0000 }, /* R3874 - ANC Coefficient */ + { 0x00000F23, 0x0000 }, /* R3875 - ANC Coefficient */ + { 0x00000F24, 0x0000 }, /* R3876 - ANC Coefficient */ + { 0x00000F25, 0x0000 }, /* R3877 - ANC Coefficient */ + { 0x00000F26, 0x0000 }, /* R3878 - ANC Coefficient */ + { 0x00000F27, 0x0000 }, /* R3879 - ANC Coefficient */ + { 0x00000F28, 0x0000 }, /* R3880 - ANC Coefficient */ + { 0x00000F29, 0x0000 }, /* R3881 - ANC Coefficient */ + { 0x00000F2A, 0x0000 }, /* R3882 - ANC Coefficient */ + { 0x00000F2B, 0x0000 }, /* R3883 - ANC Coefficient */ + { 0x00000F2C, 0x0000 }, /* R3884 - ANC Coefficient */ + { 0x00000F2D, 0x0000 }, /* R3885 - ANC Coefficient */ + { 0x00000F2E, 0x0000 }, /* R3886 - ANC Coefficient */ + { 0x00000F2F, 0x0000 }, /* R3887 - ANC Coefficient */ + { 0x00000F30, 0x0000 }, /* R3888 - ANC Coefficient */ + { 0x00000F31, 0x0000 }, /* R3889 - ANC Coefficient */ + { 0x00000F32, 0x0000 }, /* R3890 - ANC Coefficient */ + { 0x00000F33, 0x0000 }, /* R3891 - ANC Coefficient */ + { 0x00000F34, 0x0000 }, /* R3892 - ANC Coefficient */ + { 0x00000F35, 0x0000 }, /* R3893 - ANC Coefficient */ + { 0x00000F36, 0x0000 }, /* R3894 - ANC Coefficient */ + { 0x00000F37, 0x0000 }, /* R3895 - ANC Coefficient */ + { 0x00000F38, 0x0000 }, /* R3896 - ANC Coefficient */ + { 0x00000F39, 0x0000 }, /* R3897 - ANC Coefficient */ + { 0x00000F3A, 0x0000 }, /* R3898 - ANC Coefficient */ + { 0x00000F3B, 0x0000 }, /* R3899 - ANC Coefficient */ + { 0x00000F3C, 0x0000 }, /* R3900 - ANC Coefficient */ + { 0x00000F3D, 0x0000 }, /* R3901 - ANC Coefficient */ + { 0x00000F3E, 0x0000 }, /* R3902 - ANC Coefficient */ + { 0x00000F3F, 0x0000 }, /* R3903 - ANC Coefficient */ + { 0x00000F40, 0x0000 }, /* R3904 - ANC Coefficient */ + { 0x00000F41, 0x0000 }, /* R3905 - ANC Coefficient */ + { 0x00000F42, 0x0000 }, /* R3906 - ANC Coefficient */ + { 0x00000F43, 0x0000 }, /* R3907 - ANC Coefficient */ + { 0x00000F44, 0x0000 }, /* R3908 - ANC Coefficient */ + { 0x00000F45, 0x0000 }, /* R3909 - ANC Coefficient */ + { 0x00000F46, 0x0000 }, /* R3910 - ANC Coefficient */ + { 0x00000F47, 0x0000 }, /* R3911 - ANC Coefficient */ + { 0x00000F48, 0x0000 }, /* R3912 - ANC Coefficient */ + { 0x00000F49, 0x0000 }, /* R3913 - ANC Coefficient */ + { 0x00000F4A, 0x0000 }, /* R3914 - ANC Coefficient */ + { 0x00000F4B, 0x0000 }, /* R3915 - ANC Coefficient */ + { 0x00000F4C, 0x0000 }, /* R3916 - ANC Coefficient */ + { 0x00000F4D, 0x0000 }, /* R3917 - ANC Coefficient */ + { 0x00000F4E, 0x0000 }, /* R3918 - ANC Coefficient */ + { 0x00000F4F, 0x0000 }, /* R3919 - ANC Coefficient */ + { 0x00000F50, 0x0000 }, /* R3920 - ANC Coefficient */ + { 0x00000F51, 0x0000 }, /* R3921 - ANC Coefficient */ + { 0x00000F52, 0x0000 }, /* R3922 - ANC Coefficient */ + { 0x00000F53, 0x0000 }, /* R3923 - ANC Coefficient */ + { 0x00000F54, 0x0000 }, /* R3924 - ANC Coefficient */ + { 0x00000F55, 0x0000 }, /* R3925 - ANC Coefficient */ + { 0x00000F56, 0x0000 }, /* R3926 - ANC Coefficient */ + { 0x00000F57, 0x0000 }, /* R3927 - ANC Coefficient */ + { 0x00000F58, 0x0000 }, /* R3928 - ANC Coefficient */ + { 0x00000F59, 0x0000 }, /* R3929 - ANC Coefficient */ + { 0x00000F5A, 0x0000 }, /* R3930 - ANC Coefficient */ + { 0x00000F5B, 0x0000 }, /* R3931 - ANC Coefficient */ + { 0x00000F5C, 0x0000 }, /* R3932 - ANC Coefficient */ + { 0x00000F5D, 0x0000 }, /* R3933 - ANC Coefficient */ + { 0x00000F5E, 0x0000 }, /* R3934 - ANC Coefficient */ + { 0x00000F5F, 0x0000 }, /* R3935 - ANC Coefficient */ + { 0x00000F60, 0x0000 }, /* R3936 - ANC Coefficient */ + { 0x00000F61, 0x0000 }, /* R3937 - ANC Coefficient */ + { 0x00000F62, 0x0000 }, /* R3938 - ANC Coefficient */ + { 0x00000F63, 0x0000 }, /* R3939 - ANC Coefficient */ + { 0x00000F64, 0x0000 }, /* R3940 - ANC Coefficient */ + { 0x00000F65, 0x0000 }, /* R3941 - ANC Coefficient */ + { 0x00000F66, 0x0000 }, /* R3942 - ANC Coefficient */ + { 0x00000F67, 0x0000 }, /* R3943 - ANC Coefficient */ + { 0x00000F68, 0x0000 }, /* R3944 - ANC Coefficient */ + { 0x00000F69, 0x0000 }, /* R3945 - ANC Coefficient */ + { 0x00000F70, 0x0000 }, /* R3952 - FCR Filter Control */ + { 0x00000F72, 0x0004 }, /* R3954 - FCR ADC Reformatter Control */ + { 0x00000F73, 0x0004 }, /* R3955 - ANC Coefficient */ + { 0x00000F74, 0x0002 }, /* R3956 - ANC Coefficient */ + { 0x00000F75, 0x0000 }, /* R3957 - ANC Coefficient */ + { 0x00000F76, 0x0010 }, /* R3958 - ANC Coefficient */ + { 0x00000F77, 0x0000 }, /* R3959 - ANC Coefficient */ + { 0x00000F78, 0x0000 }, /* R3960 - ANC Coefficient */ + { 0x00000F79, 0x0000 }, /* R3961 - ANC Coefficient */ + { 0x00000F7A, 0x0000 }, /* R3962 - ANC Coefficient */ + { 0x00000F7B, 0x0000 }, /* R3963 - ANC Coefficient */ + { 0x00000F7C, 0x0000 }, /* R3964 - ANC Coefficient */ + { 0x00000F7D, 0x0000 }, /* R3965 - ANC Coefficient */ + { 0x00000F7E, 0x0000 }, /* R3966 - ANC Coefficient */ + { 0x00000F7F, 0x0000 }, /* R3967 - ANC Coefficient */ + { 0x00000F80, 0x0000 }, /* R3968 - ANC Coefficient */ + { 0x00000F81, 0x0000 }, /* R3969 - ANC Coefficient */ + { 0x00000F82, 0x0000 }, /* R3970 - ANC Coefficient */ + { 0x00000F83, 0x0000 }, /* R3971 - ANC Coefficient */ + { 0x00000F84, 0x0000 }, /* R3972 - ANC Coefficient */ + { 0x00000F85, 0x0000 }, /* R3973 - ANC Coefficient */ + { 0x00000F86, 0x0000 }, /* R3974 - ANC Coefficient */ + { 0x00000F87, 0x0000 }, /* R3975 - ANC Coefficient */ + { 0x00000F88, 0x0000 }, /* R3976 - ANC Coefficient */ + { 0x00000F89, 0x0000 }, /* R3977 - ANC Coefficient */ + { 0x00000F8A, 0x0000 }, /* R3978 - ANC Coefficient */ + { 0x00000F8B, 0x0000 }, /* R3979 - ANC Coefficient */ + { 0x00000F8C, 0x0000 }, /* R3980 - ANC Coefficient */ + { 0x00000F8D, 0x0000 }, /* R3981 - ANC Coefficient */ + { 0x00000F8E, 0x0000 }, /* R3982 - ANC Coefficient */ + { 0x00000F8F, 0x0000 }, /* R3983 - ANC Coefficient */ + { 0x00000F90, 0x0000 }, /* R3984 - ANC Coefficient */ + { 0x00000F91, 0x0000 }, /* R3985 - ANC Coefficient */ + { 0x00000F92, 0x0000 }, /* R3986 - ANC Coefficient */ + { 0x00000F93, 0x0000 }, /* R3987 - ANC Coefficient */ + { 0x00000F94, 0x0000 }, /* R3988 - ANC Coefficient */ + { 0x00000F95, 0x0000 }, /* R3989 - ANC Coefficient */ + { 0x00000F96, 0x0000 }, /* R3990 - ANC Coefficient */ + { 0x00000F97, 0x0000 }, /* R3991 - ANC Coefficient */ + { 0x00000F98, 0x0000 }, /* R3992 - ANC Coefficient */ + { 0x00000F99, 0x0000 }, /* R3993 - ANC Coefficient */ + { 0x00000F9A, 0x0000 }, /* R3994 - ANC Coefficient */ + { 0x00000F9B, 0x0000 }, /* R3995 - ANC Coefficient */ + { 0x00000F9C, 0x0000 }, /* R3996 - ANC Coefficient */ + { 0x00000F9D, 0x0000 }, /* R3997 - ANC Coefficient */ + { 0x00000F9E, 0x0000 }, /* R3998 - ANC Coefficient */ + { 0x00000F9F, 0x0000 }, /* R3999 - ANC Coefficient */ + { 0x00000FA0, 0x0000 }, /* R4000 - ANC Coefficient */ + { 0x00000FA1, 0x0000 }, /* R4001 - ANC Coefficient */ + { 0x00000FA2, 0x0000 }, /* R4002 - ANC Coefficient */ + { 0x00000FA3, 0x0000 }, /* R4003 - ANC Coefficient */ + { 0x00000FA4, 0x0000 }, /* R4004 - ANC Coefficient */ + { 0x00000FA5, 0x0000 }, /* R4005 - ANC Coefficient */ + { 0x00000FA6, 0x0000 }, /* R4006 - ANC Coefficient */ + { 0x00000FA7, 0x0000 }, /* R4007 - ANC Coefficient */ + { 0x00000FA8, 0x0000 }, /* R4008 - ANC Coefficient */ + { 0x00000FA9, 0x0000 }, /* R4009 - ANC Coefficient */ + { 0x00000FAA, 0x0000 }, /* R4010 - ANC Coefficient */ + { 0x00000FAB, 0x0000 }, /* R4011 - ANC Coefficient */ + { 0x00000FAC, 0x0000 }, /* R4012 - ANC Coefficient */ + { 0x00000FAD, 0x0000 }, /* R4013 - ANC Coefficient */ + { 0x00000FAE, 0x0000 }, /* R4014 - ANC Coefficient */ + { 0x00000FAF, 0x0000 }, /* R4015 - ANC Coefficient */ + { 0x00000FB0, 0x0000 }, /* R4016 - ANC Coefficient */ + { 0x00000FB1, 0x0000 }, /* R4017 - ANC Coefficient */ + { 0x00000FB2, 0x0000 }, /* R4018 - ANC Coefficient */ + { 0x00000FB3, 0x0000 }, /* R4019 - ANC Coefficient */ + { 0x00000FB4, 0x0000 }, /* R4020 - ANC Coefficient */ + { 0x00000FB5, 0x0000 }, /* R4021 - ANC Coefficient */ + { 0x00000FB6, 0x0000 }, /* R4022 - ANC Coefficient */ + { 0x00000FB7, 0x0000 }, /* R4023 - ANC Coefficient */ + { 0x00000FB8, 0x0000 }, /* R4024 - ANC Coefficient */ + { 0x00000FB9, 0x0000 }, /* R4025 - ANC Coefficient */ + { 0x00000FBA, 0x0000 }, /* R4026 - ANC Coefficient */ + { 0x00000FBB, 0x0000 }, /* R4027 - ANC Coefficient */ + { 0x00000FBC, 0x0000 }, /* R4028 - ANC Coefficient */ + { 0x00000FBD, 0x0000 }, /* R4029 - ANC Coefficient */ + { 0x00000FBE, 0x0000 }, /* R4030 - ANC Coefficient */ + { 0x00000FBF, 0x0000 }, /* R4031 - ANC Coefficient */ + { 0x00000FC0, 0x0000 }, /* R4032 - ANC Coefficient */ + { 0x00000FC1, 0x0000 }, /* R4033 - ANC Coefficient */ + { 0x00000FC2, 0x0000 }, /* R4034 - ANC Coefficient */ + { 0x00000FC3, 0x0000 }, /* R4035 - ANC Coefficient */ + { 0x00000FC4, 0x0000 }, /* R4036 - ANC Coefficient */ { 0x00001100, 0x0010 }, /* R4352 - DSP1 Control 1 */ { 0x00001200, 0x0010 }, /* R4608 - DSP2 Control 1 */ { 0x00001300, 0x0010 }, /* R4864 - DSP3 Control 1 */ @@ -2710,6 +2889,13 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_CLOCK_CONTROL: case ARIZONA_ANC_SRC: case ARIZONA_DSP_STATUS: + case ARIZONA_ANC_COEFF_START ... ARIZONA_ANC_COEFF_END: + case ARIZONA_FCL_FILTER_CONTROL: + case ARIZONA_FCL_ADC_REFORMATTER_CONTROL: + case ARIZONA_FCL_COEFF_START ... ARIZONA_FCL_COEFF_END: + case ARIZONA_FCR_FILTER_CONTROL: + case ARIZONA_FCR_ADC_REFORMATTER_CONTROL: + case ARIZONA_FCR_COEFF_START ... ARIZONA_FCR_COEFF_END: case ARIZONA_DSP1_CONTROL_1: case ARIZONA_DSP1_CLOCKING_1: case ARIZONA_DSP1_STATUS_1: diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h index c7c11c900196..cd7e78eae006 100644 --- a/include/linux/mfd/arizona/registers.h +++ b/include/linux/mfd/arizona/registers.h @@ -1065,6 +1065,16 @@ #define ARIZONA_CLOCK_CONTROL 0xF00 #define ARIZONA_ANC_SRC 0xF01 #define ARIZONA_DSP_STATUS 0xF02 +#define ARIZONA_ANC_COEFF_START 0xF08 +#define ARIZONA_ANC_COEFF_END 0xF12 +#define ARIZONA_FCL_FILTER_CONTROL 0xF15 +#define ARIZONA_FCL_ADC_REFORMATTER_CONTROL 0xF17 +#define ARIZONA_FCL_COEFF_START 0xF18 +#define ARIZONA_FCL_COEFF_END 0xF69 +#define ARIZONA_FCR_FILTER_CONTROL 0xF70 +#define ARIZONA_FCR_ADC_REFORMATTER_CONTROL 0xF72 +#define ARIZONA_FCR_COEFF_START 0xF73 +#define ARIZONA_FCR_COEFF_END 0xFC4 #define ARIZONA_DSP1_CONTROL_1 0x1100 #define ARIZONA_DSP1_CLOCKING_1 0x1101 #define ARIZONA_DSP1_STATUS_1 0x1104 @@ -8050,6 +8060,66 @@ #define ARIZONA_ISRC3_NOTCH_ENA_SHIFT 0 /* ISRC3_NOTCH_ENA */ #define ARIZONA_ISRC3_NOTCH_ENA_WIDTH 1 /* ISRC3_NOTCH_ENA */ +/* + * R3840 (0xF00) - Clock Control + */ +#define ARIZONA_EXT_NG_SEL_CLR 0x0080 /* EXT_NG_SEL_CLR */ +#define ARIZONA_EXT_NG_SEL_CLR_MASK 0x0080 /* EXT_NG_SEL_CLR */ +#define ARIZONA_EXT_NG_SEL_CLR_SHIFT 7 /* EXT_NG_SEL_CLR */ +#define ARIZONA_EXT_NG_SEL_CLR_WIDTH 1 /* EXT_NG_SEL_CLR */ +#define ARIZONA_EXT_NG_SEL_SET 0x0040 /* EXT_NG_SEL_SET */ +#define ARIZONA_EXT_NG_SEL_SET_MASK 0x0040 /* EXT_NG_SEL_SET */ +#define ARIZONA_EXT_NG_SEL_SET_SHIFT 6 /* EXT_NG_SEL_SET */ +#define ARIZONA_EXT_NG_SEL_SET_WIDTH 1 /* EXT_NG_SEL_SET */ +#define ARIZONA_CLK_R_ENA_CLR 0x0020 /* CLK_R_ENA_CLR */ +#define ARIZONA_CLK_R_ENA_CLR_MASK 0x0020 /* CLK_R_ENA_CLR */ +#define ARIZONA_CLK_R_ENA_CLR_SHIFT 5 /* CLK_R_ENA_CLR */ +#define ARIZONA_CLK_R_ENA_CLR_WIDTH 1 /* CLK_R_ENA_CLR */ +#define ARIZONA_CLK_R_ENA_SET 0x0010 /* CLK_R_ENA_SET */ +#define ARIZONA_CLK_R_ENA_SET_MASK 0x0010 /* CLK_R_ENA_SET */ +#define ARIZONA_CLK_R_ENA_SET_SHIFT 4 /* CLK_R_ENA_SET */ +#define ARIZONA_CLK_R_ENA_SET_WIDTH 1 /* CLK_R_ENA_SET */ +#define ARIZONA_CLK_NG_ENA_CLR 0x0008 /* CLK_NG_ENA_CLR */ +#define ARIZONA_CLK_NG_ENA_CLR_MASK 0x0008 /* CLK_NG_ENA_CLR */ +#define ARIZONA_CLK_NG_ENA_CLR_SHIFT 3 /* CLK_NG_ENA_CLR */ +#define ARIZONA_CLK_NG_ENA_CLR_WIDTH 1 /* CLK_NG_ENA_CLR */ +#define ARIZONA_CLK_NG_ENA_SET 0x0004 /* CLK_NG_ENA_SET */ +#define ARIZONA_CLK_NG_ENA_SET_MASK 0x0004 /* CLK_NG_ENA_SET */ +#define ARIZONA_CLK_NG_ENA_SET_SHIFT 2 /* CLK_NG_ENA_SET */ +#define ARIZONA_CLK_NG_ENA_SET_WIDTH 1 /* CLK_NG_ENA_SET */ +#define ARIZONA_CLK_L_ENA_CLR 0x0002 /* CLK_L_ENA_CLR */ +#define ARIZONA_CLK_L_ENA_CLR_MASK 0x0002 /* CLK_L_ENA_CLR */ +#define ARIZONA_CLK_L_ENA_CLR_SHIFT 1 /* CLK_L_ENA_CLR */ +#define ARIZONA_CLK_L_ENA_CLR_WIDTH 1 /* CLK_L_ENA_CLR */ +#define ARIZONA_CLK_L_ENA_SET 0x0001 /* CLK_L_ENA_SET */ +#define ARIZONA_CLK_L_ENA_SET_MASK 0x0001 /* CLK_L_ENA_SET */ +#define ARIZONA_CLK_L_ENA_SET_SHIFT 0 /* CLK_L_ENA_SET */ +#define ARIZONA_CLK_L_ENA_SET_WIDTH 1 /* CLK_L_ENA_SET */ + +/* + * R3841 (0xF01) - ANC SRC + */ +#define ARIZONA_IN_RXANCR_SEL_MASK 0x0070 /* IN_RXANCR_SEL - [4:6] */ +#define ARIZONA_IN_RXANCR_SEL_SHIFT 4 /* IN_RXANCR_SEL - [4:6] */ +#define ARIZONA_IN_RXANCR_SEL_WIDTH 3 /* IN_RXANCR_SEL - [4:6] */ +#define ARIZONA_IN_RXANCL_SEL_MASK 0x0007 /* IN_RXANCL_SEL - [0:2] */ +#define ARIZONA_IN_RXANCL_SEL_SHIFT 0 /* IN_RXANCL_SEL - [0:2] */ +#define ARIZONA_IN_RXANCL_SEL_WIDTH 3 /* IN_RXANCL_SEL - [0:2] */ + +/* + * R3863 (0xF17) - FCL ADC Reformatter Control + */ +#define ARIZONA_FCL_MIC_MODE_SEL 0x000C /* FCL_MIC_MODE_SEL - [2:3] */ +#define ARIZONA_FCL_MIC_MODE_SEL_SHIFT 2 /* FCL_MIC_MODE_SEL - [2:3] */ +#define ARIZONA_FCL_MIC_MODE_SEL_WIDTH 2 /* FCL_MIC_MODE_SEL - [2:3] */ + +/* + * R3954 (0xF72) - FCR ADC Reformatter Control + */ +#define ARIZONA_FCR_MIC_MODE_SEL 0x000C /* FCR_MIC_MODE_SEL - [2:3] */ +#define ARIZONA_FCR_MIC_MODE_SEL_SHIFT 2 /* FCR_MIC_MODE_SEL - [2:3] */ +#define ARIZONA_FCR_MIC_MODE_SEL_WIDTH 2 /* FCR_MIC_MODE_SEL - [2:3] */ + /* * R4352 (0x1100) - DSP1 Control 1 */ -- cgit v1.2.3-71-gd317 From 6bb3b3acc3d096b938887c90f4bb19a639b99852 Mon Sep 17 00:00:00 2001 From: Qipeng Zha Date: Tue, 15 Sep 2015 00:39:18 +0800 Subject: mfd: intel_soc_pmic: Add support for Broxton WC PMIC IRQ control registers of Intel Broxton Whisky Cove PMIC are separated in two parts, so add secondary IRQ chip. And the new member of device will be used in PMC IPC regmap APIs. Signed-off-by: Qipeng Zha Signed-off-by: Lee Jones --- include/linux/mfd/intel_soc_pmic.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/linux') diff --git a/include/linux/mfd/intel_soc_pmic.h b/include/linux/mfd/intel_soc_pmic.h index abcbfcf32d10..cf619dbeace2 100644 --- a/include/linux/mfd/intel_soc_pmic.h +++ b/include/linux/mfd/intel_soc_pmic.h @@ -25,6 +25,8 @@ struct intel_soc_pmic { int irq; struct regmap *regmap; struct regmap_irq_chip_data *irq_chip_data; + struct regmap_irq_chip_data *irq_chip_data_level2; + struct device *dev; }; #endif /* __INTEL_SOC_PMIC_H__ */ -- cgit v1.2.3-71-gd317 From 39d047c0b1c812e9f0014e7100e372e61f2de3de Mon Sep 17 00:00:00 2001 From: Qipeng Zha Date: Tue, 15 Sep 2015 00:39:19 +0800 Subject: mfd: add Intel Broxton Whiskey Cove PMIC driver Add MFD core driver for Intel Broxton Whiskey Cove PMIC, which is specially accessed by hardware IPC, not a generic I2C device Signed-off-by: Qipeng Zha Signed-off-by: Lee Jones --- drivers/mfd/Makefile | 1 + drivers/mfd/intel_soc_pmic_bxtwc.c | 478 +++++++++++++++++++++++++++++++++++++ include/linux/mfd/intel_bxtwc.h | 69 ++++++ 3 files changed, 548 insertions(+) create mode 100644 drivers/mfd/intel_soc_pmic_bxtwc.c create mode 100644 include/linux/mfd/intel_bxtwc.h (limited to 'include/linux') diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index a59e3fcc8626..d6c21e3c409f 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -190,5 +190,6 @@ obj-$(CONFIG_MFD_RT5033) += rt5033.o obj-$(CONFIG_MFD_SKY81452) += sky81452.o intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o +intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC) += intel_soc_pmic_bxtwc.o obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o obj-$(CONFIG_MFD_MT6397) += mt6397-core.o diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c new file mode 100644 index 000000000000..40acaff2e1c3 --- /dev/null +++ b/drivers/mfd/intel_soc_pmic_bxtwc.c @@ -0,0 +1,478 @@ +/* + * MFD core driver for Intel Broxton Whiskey Cove PMIC + * + * Copyright (C) 2015 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PMIC device registers */ +#define REG_ADDR_MASK 0xFF00 +#define REG_ADDR_SHIFT 8 +#define REG_OFFSET_MASK 0xFF + +/* Interrupt Status Registers */ +#define BXTWC_IRQLVL1 0x4E02 +#define BXTWC_PWRBTNIRQ 0x4E03 + +#define BXTWC_THRM0IRQ 0x4E04 +#define BXTWC_THRM1IRQ 0x4E05 +#define BXTWC_THRM2IRQ 0x4E06 +#define BXTWC_BCUIRQ 0x4E07 +#define BXTWC_ADCIRQ 0x4E08 +#define BXTWC_CHGR0IRQ 0x4E09 +#define BXTWC_CHGR1IRQ 0x4E0A +#define BXTWC_GPIOIRQ0 0x4E0B +#define BXTWC_GPIOIRQ1 0x4E0C +#define BXTWC_CRITIRQ 0x4E0D + +/* Interrupt MASK Registers */ +#define BXTWC_MIRQLVL1 0x4E0E +#define BXTWC_MPWRTNIRQ 0x4E0F + +#define BXTWC_MTHRM0IRQ 0x4E12 +#define BXTWC_MTHRM1IRQ 0x4E13 +#define BXTWC_MTHRM2IRQ 0x4E14 +#define BXTWC_MBCUIRQ 0x4E15 +#define BXTWC_MADCIRQ 0x4E16 +#define BXTWC_MCHGR0IRQ 0x4E17 +#define BXTWC_MCHGR1IRQ 0x4E18 +#define BXTWC_MGPIO0IRQ 0x4E19 +#define BXTWC_MGPIO1IRQ 0x4E1A +#define BXTWC_MCRITIRQ 0x4E1B + +/* Whiskey Cove PMIC share same ACPI ID between different platforms */ +#define BROXTON_PMIC_WC_HRV 4 + +/* Manage in two IRQ chips since mask registers are not consecutive */ +enum bxtwc_irqs { + /* Level 1 */ + BXTWC_PWRBTN_LVL1_IRQ = 0, + BXTWC_TMU_LVL1_IRQ, + BXTWC_THRM_LVL1_IRQ, + BXTWC_BCU_LVL1_IRQ, + BXTWC_ADC_LVL1_IRQ, + BXTWC_CHGR_LVL1_IRQ, + BXTWC_GPIO_LVL1_IRQ, + BXTWC_CRIT_LVL1_IRQ, + + /* Level 2 */ + BXTWC_PWRBTN_IRQ, +}; + +enum bxtwc_irqs_level2 { + /* Level 2 */ + BXTWC_THRM0_IRQ = 0, + BXTWC_THRM1_IRQ, + BXTWC_THRM2_IRQ, + BXTWC_BCU_IRQ, + BXTWC_ADC_IRQ, + BXTWC_CHGR0_IRQ, + BXTWC_CHGR1_IRQ, + BXTWC_GPIO0_IRQ, + BXTWC_GPIO1_IRQ, + BXTWC_CRIT_IRQ, +}; + +static const struct regmap_irq bxtwc_regmap_irqs[] = { + REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)), + REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)), + REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)), + REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)), + REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)), + REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)), + REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)), + REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)), + REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03), +}; + +static const struct regmap_irq bxtwc_regmap_irqs_level2[] = { + REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff), + REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf), + REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff), + REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f), + REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff), + REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f), + REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f), + REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff), + REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f), + REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03), +}; + +static struct regmap_irq_chip bxtwc_regmap_irq_chip = { + .name = "bxtwc_irq_chip", + .status_base = BXTWC_IRQLVL1, + .mask_base = BXTWC_MIRQLVL1, + .irqs = bxtwc_regmap_irqs, + .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs), + .num_regs = 2, +}; + +static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = { + .name = "bxtwc_irq_chip_level2", + .status_base = BXTWC_THRM0IRQ, + .mask_base = BXTWC_MTHRM0IRQ, + .irqs = bxtwc_regmap_irqs_level2, + .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2), + .num_regs = 10, +}; + +static struct resource gpio_resources[] = { + DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"), + DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"), +}; + +static struct resource adc_resources[] = { + DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"), +}; + +static struct resource charger_resources[] = { + DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"), + DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"), +}; + +static struct resource thermal_resources[] = { + DEFINE_RES_IRQ(BXTWC_THRM0_IRQ), + DEFINE_RES_IRQ(BXTWC_THRM1_IRQ), + DEFINE_RES_IRQ(BXTWC_THRM2_IRQ), +}; + +static struct resource bcu_resources[] = { + DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"), +}; + +static struct mfd_cell bxt_wc_dev[] = { + { + .name = "bxt_wcove_gpadc", + .num_resources = ARRAY_SIZE(adc_resources), + .resources = adc_resources, + }, + { + .name = "bxt_wcove_thermal", + .num_resources = ARRAY_SIZE(thermal_resources), + .resources = thermal_resources, + }, + { + .name = "bxt_wcove_ext_charger", + .num_resources = ARRAY_SIZE(charger_resources), + .resources = charger_resources, + }, + { + .name = "bxt_wcove_bcu", + .num_resources = ARRAY_SIZE(bcu_resources), + .resources = bcu_resources, + }, + { + .name = "bxt_wcove_gpio", + .num_resources = ARRAY_SIZE(gpio_resources), + .resources = gpio_resources, + }, + { + .name = "bxt_wcove_region", + }, +}; + +static int regmap_ipc_byte_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + int ret; + int i2c_addr; + u8 ipc_in[2]; + u8 ipc_out[4]; + struct intel_soc_pmic *pmic = context; + + if (reg & REG_ADDR_MASK) + i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT; + else { + i2c_addr = BXTWC_DEVICE1_ADDR; + if (!i2c_addr) { + dev_err(pmic->dev, "I2C address not set\n"); + return -EINVAL; + } + } + reg &= REG_OFFSET_MASK; + + ipc_in[0] = reg; + ipc_in[1] = i2c_addr; + ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS, + PMC_IPC_PMIC_ACCESS_READ, + ipc_in, sizeof(ipc_in), (u32 *)ipc_out, 1); + if (ret) { + dev_err(pmic->dev, "Failed to read from PMIC\n"); + return ret; + } + *val = ipc_out[0]; + + return 0; +} + +static int regmap_ipc_byte_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + int ret; + int i2c_addr; + u8 ipc_in[3]; + struct intel_soc_pmic *pmic = context; + + if (reg & REG_ADDR_MASK) + i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT; + else { + i2c_addr = BXTWC_DEVICE1_ADDR; + if (!i2c_addr) { + dev_err(pmic->dev, "I2C address not set\n"); + return -EINVAL; + } + } + reg &= REG_OFFSET_MASK; + + ipc_in[0] = reg; + ipc_in[1] = i2c_addr; + ipc_in[2] = val; + ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS, + PMC_IPC_PMIC_ACCESS_WRITE, + ipc_in, sizeof(ipc_in), NULL, 0); + if (ret) { + dev_err(pmic->dev, "Failed to write to PMIC\n"); + return ret; + } + + return 0; +} + +/* sysfs interfaces to r/w PMIC registers, required by initial script */ +static unsigned long bxtwc_reg_addr; +static ssize_t bxtwc_reg_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "0x%lx\n", bxtwc_reg_addr); +} + +static ssize_t bxtwc_reg_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + if (kstrtoul(buf, 0, &bxtwc_reg_addr)) { + dev_err(dev, "Invalid register address\n"); + return -EINVAL; + } + return (ssize_t)count; +} + +static ssize_t bxtwc_val_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + unsigned int val; + struct intel_soc_pmic *pmic = dev_get_drvdata(dev); + + ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val); + if (ret < 0) { + dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr); + return -EIO; + } + + return sprintf(buf, "0x%02x\n", val); +} + +static ssize_t bxtwc_val_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int ret; + unsigned int val; + struct intel_soc_pmic *pmic = dev_get_drvdata(dev); + + if (kstrtoul(buf, 0, (unsigned long *)&val)) { + dev_err(dev, "Invalid register value\n"); + return -EINVAL; + } + + ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val); + if (ret) { + dev_err(dev, "Failed to write value 0x%02x to address 0x%lx", + val, bxtwc_reg_addr); + return -EIO; + } + return count; +} + +static DEVICE_ATTR(addr, S_IWUSR | S_IRUSR, bxtwc_reg_show, bxtwc_reg_store); +static DEVICE_ATTR(val, S_IWUSR | S_IRUSR, bxtwc_val_show, bxtwc_val_store); +static struct attribute *bxtwc_attrs[] = { + &dev_attr_addr.attr, + &dev_attr_val.attr, + NULL +}; + +static const struct attribute_group bxtwc_group = { + .attrs = bxtwc_attrs, +}; + +static const struct regmap_config bxtwc_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .reg_write = regmap_ipc_byte_reg_write, + .reg_read = regmap_ipc_byte_reg_read, +}; + +static int bxtwc_probe(struct platform_device *pdev) +{ + int ret; + acpi_handle handle; + acpi_status status; + unsigned long long hrv; + struct intel_soc_pmic *pmic; + + handle = ACPI_HANDLE(&pdev->dev); + status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv); + if (ACPI_FAILURE(status)) { + dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n"); + return -ENODEV; + } + if (hrv != BROXTON_PMIC_WC_HRV) { + dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n", + hrv); + return -ENODEV; + } + + pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); + if (!pmic) + return -ENOMEM; + + ret = platform_get_irq(pdev, 0); + if (ret < 0) { + dev_err(&pdev->dev, "Invalid IRQ\n"); + return ret; + } + pmic->irq = ret; + + dev_set_drvdata(&pdev->dev, pmic); + pmic->dev = &pdev->dev; + + pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic, + &bxtwc_regmap_config); + if (IS_ERR(pmic->regmap)) { + ret = PTR_ERR(pmic->regmap); + dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret); + return ret; + } + + ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, + IRQF_ONESHOT | IRQF_SHARED, + 0, &bxtwc_regmap_irq_chip, + &pmic->irq_chip_data); + if (ret) { + dev_err(&pdev->dev, "Failed to add IRQ chip\n"); + return ret; + } + + ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, + IRQF_ONESHOT | IRQF_SHARED, + 0, &bxtwc_regmap_irq_chip_level2, + &pmic->irq_chip_data_level2); + if (ret) { + dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n"); + goto err_irq_chip_level2; + } + + ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev, + ARRAY_SIZE(bxt_wc_dev), NULL, 0, + NULL); + if (ret) { + dev_err(&pdev->dev, "Failed to add devices\n"); + goto err_mfd; + } + + ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group); + if (ret) { + dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret); + goto err_sysfs; + } + + return 0; + +err_sysfs: + mfd_remove_devices(&pdev->dev); +err_mfd: + regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2); +err_irq_chip_level2: + regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data); + + return ret; +} + +static int bxtwc_remove(struct platform_device *pdev) +{ + struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev); + + sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group); + mfd_remove_devices(&pdev->dev); + regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data); + regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2); + + return 0; +} + +static void bxtwc_shutdown(struct platform_device *pdev) +{ + struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev); + + disable_irq(pmic->irq); +} + +#ifdef CONFIG_PM_SLEEP +static int bxtwc_suspend(struct device *dev) +{ + struct intel_soc_pmic *pmic = dev_get_drvdata(dev); + + disable_irq(pmic->irq); + + return 0; +} + +static int bxtwc_resume(struct device *dev) +{ + struct intel_soc_pmic *pmic = dev_get_drvdata(dev); + + enable_irq(pmic->irq); + return 0; +} +#endif +static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume); + +static const struct acpi_device_id bxtwc_acpi_ids[] = { + { "INT34D3", }, + { } +}; +MODULE_DEVICE_TABLE(acpi, pmic_acpi_ids); + +static struct platform_driver bxtwc_driver = { + .probe = bxtwc_probe, + .remove = bxtwc_remove, + .shutdown = bxtwc_shutdown, + .driver = { + .name = "BXTWC PMIC", + .pm = &bxtwc_pm_ops, + .acpi_match_table = ACPI_PTR(bxtwc_acpi_ids), + }, +}; + +module_platform_driver(bxtwc_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Qipeng Zha"); diff --git a/include/linux/mfd/intel_bxtwc.h b/include/linux/mfd/intel_bxtwc.h new file mode 100644 index 000000000000..1a0ee9d6efe9 --- /dev/null +++ b/include/linux/mfd/intel_bxtwc.h @@ -0,0 +1,69 @@ +/* + * intel_bxtwc.h - Header file for Intel Broxton Whiskey Cove PMIC + * + * Copyright (C) 2015 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#ifndef __INTEL_BXTWC_H__ +#define __INTEL_BXTWC_H__ + +/* BXT WC devices */ +#define BXTWC_DEVICE1_ADDR 0x4E +#define BXTWC_DEVICE2_ADDR 0x4F +#define BXTWC_DEVICE3_ADDR 0x5E + +/* device1 Registers */ +#define BXTWC_CHIPID 0x4E00 +#define BXTWC_CHIPVER 0x4E01 + +#define BXTWC_SCHGRIRQ0_ADDR 0x5E1A +#define BXTWC_CHGRCTRL0_ADDR 0x5E16 +#define BXTWC_CHGRCTRL1_ADDR 0x5E17 +#define BXTWC_CHGRCTRL2_ADDR 0x5E18 +#define BXTWC_CHGRSTATUS_ADDR 0x5E19 +#define BXTWC_THRMBATZONE_ADDR 0x4F22 + +#define BXTWC_USBPATH_ADDR 0x5E19 +#define BXTWC_USBPHYCTRL_ADDR 0x5E07 +#define BXTWC_USBIDCTRL_ADDR 0x5E05 +#define BXTWC_USBIDEN_MASK 0x01 +#define BXTWC_USBIDSTAT_ADDR 0x00FF +#define BXTWC_USBSRCDETSTATUS_ADDR 0x5E29 + +#define BXTWC_DBGUSBBC1_ADDR 0x5FE0 +#define BXTWC_DBGUSBBC2_ADDR 0x5FE1 +#define BXTWC_DBGUSBBCSTAT_ADDR 0x5FE2 + +#define BXTWC_WAKESRC_ADDR 0x4E22 +#define BXTWC_WAKESRC2_ADDR 0x4EE5 +#define BXTWC_CHRTTADDR_ADDR 0x5E22 +#define BXTWC_CHRTTDATA_ADDR 0x5E23 + +#define BXTWC_STHRMIRQ0_ADDR 0x4F19 +#define WC_MTHRMIRQ1_ADDR 0x4E12 +#define WC_STHRMIRQ1_ADDR 0x4F1A +#define WC_STHRMIRQ2_ADDR 0x4F1B + +#define BXTWC_THRMZN0H_ADDR 0x4F44 +#define BXTWC_THRMZN0L_ADDR 0x4F45 +#define BXTWC_THRMZN1H_ADDR 0x4F46 +#define BXTWC_THRMZN1L_ADDR 0x4F47 +#define BXTWC_THRMZN2H_ADDR 0x4F48 +#define BXTWC_THRMZN2L_ADDR 0x4F49 +#define BXTWC_THRMZN3H_ADDR 0x4F4A +#define BXTWC_THRMZN3L_ADDR 0x4F4B +#define BXTWC_THRMZN4H_ADDR 0x4F4C +#define BXTWC_THRMZN4L_ADDR 0x4F4D + +#endif -- cgit v1.2.3-71-gd317 From 0386af30d3d99d942dd68a8c64beb4f03958e74f Mon Sep 17 00:00:00 2001 From: Steve Twiss Date: Thu, 8 Oct 2015 16:17:51 +0100 Subject: mfd: da9053: Addition of extra registers for GPIOs 8-13 Definitions for GPIO registers 8, 9, 10, 11, 12 and 13 are added into the register header file. - DA9052_GPIO_8_9_REG 25 - DA9052_GPIO_10_11_REG 26 - DA9052_GPIO_12_13_REG 27 A modification is also made to the MFD core code to define these registers as readable and writable. The functions for da9052_reg_readable() and da9052_reg_writeable() have had their case statements altered to include these new registers. Signed-off-by: Steve Twiss Signed-off-by: Lee Jones --- drivers/mfd/da9052-core.c | 6 ++++++ include/linux/mfd/da9052/reg.h | 3 +++ 2 files changed, 9 insertions(+) (limited to 'include/linux') diff --git a/drivers/mfd/da9052-core.c b/drivers/mfd/da9052-core.c index 46e3840c7a37..c0bf68a3e614 100644 --- a/drivers/mfd/da9052-core.c +++ b/drivers/mfd/da9052-core.c @@ -51,6 +51,9 @@ static bool da9052_reg_readable(struct device *dev, unsigned int reg) case DA9052_GPIO_2_3_REG: case DA9052_GPIO_4_5_REG: case DA9052_GPIO_6_7_REG: + case DA9052_GPIO_8_9_REG: + case DA9052_GPIO_10_11_REG: + case DA9052_GPIO_12_13_REG: case DA9052_GPIO_14_15_REG: case DA9052_ID_0_1_REG: case DA9052_ID_2_3_REG: @@ -178,6 +181,9 @@ static bool da9052_reg_writeable(struct device *dev, unsigned int reg) case DA9052_GPIO_2_3_REG: case DA9052_GPIO_4_5_REG: case DA9052_GPIO_6_7_REG: + case DA9052_GPIO_8_9_REG: + case DA9052_GPIO_10_11_REG: + case DA9052_GPIO_12_13_REG: case DA9052_GPIO_14_15_REG: case DA9052_ID_0_1_REG: case DA9052_ID_2_3_REG: diff --git a/include/linux/mfd/da9052/reg.h b/include/linux/mfd/da9052/reg.h index c4dd3a8add21..5010f978725c 100644 --- a/include/linux/mfd/da9052/reg.h +++ b/include/linux/mfd/da9052/reg.h @@ -65,6 +65,9 @@ #define DA9052_GPIO_2_3_REG 22 #define DA9052_GPIO_4_5_REG 23 #define DA9052_GPIO_6_7_REG 24 +#define DA9052_GPIO_8_9_REG 25 +#define DA9052_GPIO_10_11_REG 26 +#define DA9052_GPIO_12_13_REG 27 #define DA9052_GPIO_14_15_REG 28 /* POWER SEQUENCER CONTROL REGISTERS */ -- cgit v1.2.3-71-gd317 From ce6a5acc93876f619f32f8f60c7c6e549e46d962 Mon Sep 17 00:00:00 2001 From: Micky Ching Date: Mon, 29 Jun 2015 09:19:39 +0800 Subject: mfd: rtsx: Add support for rts522A rts522a(rts5227s) is derived from rts5227, and mainly same with rts5227. Add it to file mfd/rts5227.c to support this chip. Signed-off-by: Micky Ching Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 7 ++-- drivers/mfd/rts5227.c | 77 ++++++++++++++++++++++++++++++++++++++++++-- drivers/mfd/rtsx_pcr.c | 5 +++ drivers/mfd/rtsx_pcr.h | 3 ++ include/linux/mfd/rtsx_pci.h | 6 ++++ 5 files changed, 93 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index d6514fb35f78..2db1337432cf 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -736,9 +736,10 @@ config MFD_RTSX_PCI select MFD_CORE help This supports for Realtek PCI-Express card reader including rts5209, - rts5229, rtl8411, etc. Realtek card reader supports access to many - types of memory cards, such as Memory Stick, Memory Stick Pro, - Secure Digital and MultiMediaCard. + rts5227, rts522A, rts5229, rts5249, rts524A, rts525A, rtl8411, etc. + Realtek card reader supports access to many types of memory cards, + such as Memory Stick, Memory Stick Pro, Secure Digital and + MultiMediaCard. config MFD_RT5033 tristate "Richtek RT5033 Power Management IC" diff --git a/drivers/mfd/rts5227.c b/drivers/mfd/rts5227.c index c5a65298c781..ff296a4bf3d2 100644 --- a/drivers/mfd/rts5227.c +++ b/drivers/mfd/rts5227.c @@ -26,6 +26,14 @@ #include "rtsx_pcr.h" +static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr) +{ + u8 val; + + rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); + return val & 0x0F; +} + static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage) { u8 driving_3v3[4][3] = { @@ -88,7 +96,7 @@ static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state) rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0); if (pm_state == HOST_ENTER_S3) - rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10); + rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x10); rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03); } @@ -121,7 +129,7 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0xB8); else rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0x88); - rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00); + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00); return rtsx_pci_send_cmd(pcr, 100); } @@ -294,8 +302,73 @@ void rts5227_init_params(struct rtsx_pcr *pcr) pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15); pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7); + pcr->ic_version = rts5227_get_ic_version(pcr); pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl; pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl; pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl; pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl; + + pcr->reg_pm_ctrl3 = PM_CTRL3; +} + +static int rts522a_optimize_phy(struct rtsx_pcr *pcr) +{ + int err; + + err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN, + 0x00); + if (err < 0) + return err; + + if (is_version(pcr, 0x522A, IC_VER_A)) { + err = rtsx_pci_write_phy_register(pcr, PHY_RCR2, + PHY_RCR2_INIT_27S); + if (err) + return err; + + rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S); + rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S); + rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S); + rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S); + } + + return 0; +} + +static int rts522a_extra_init_hw(struct rtsx_pcr *pcr) +{ + rts5227_extra_init_hw(pcr); + + rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG, + FUNC_FORCE_UPME_XMT_DBG); + rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04); + rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); + rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11); + + return 0; +} + +/* rts522a operations mainly derived from rts5227, except phy/hw init setting. + */ +static const struct pcr_ops rts522a_pcr_ops = { + .fetch_vendor_settings = rts5227_fetch_vendor_settings, + .extra_init_hw = rts522a_extra_init_hw, + .optimize_phy = rts522a_optimize_phy, + .turn_on_led = rts5227_turn_on_led, + .turn_off_led = rts5227_turn_off_led, + .enable_auto_blink = rts5227_enable_auto_blink, + .disable_auto_blink = rts5227_disable_auto_blink, + .card_power_on = rts5227_card_power_on, + .card_power_off = rts5227_card_power_off, + .switch_output_voltage = rts5227_switch_output_voltage, + .cd_deglitch = NULL, + .conv_clk_and_div_n = NULL, + .force_power_down = rts5227_force_power_down, +}; + +void rts522a_init_params(struct rtsx_pcr *pcr) +{ + rts5227_init_params(pcr); + + pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3; } diff --git a/drivers/mfd/rtsx_pcr.c b/drivers/mfd/rtsx_pcr.c index b98cf1de0a55..f3820d08c9a3 100644 --- a/drivers/mfd/rtsx_pcr.c +++ b/drivers/mfd/rtsx_pcr.c @@ -55,6 +55,7 @@ static const struct pci_device_id rtsx_pci_ids[] = { { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 }, { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 }, { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 }, + { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 }, { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 }, { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 }, { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 }, @@ -1098,6 +1099,10 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) rts5227_init_params(pcr); break; + case 0x522A: + rts522a_init_params(pcr); + break; + case 0x5249: rts5249_init_params(pcr); break; diff --git a/drivers/mfd/rtsx_pcr.h b/drivers/mfd/rtsx_pcr.h index ce48842570d7..931d1ae3ce32 100644 --- a/drivers/mfd/rtsx_pcr.h +++ b/drivers/mfd/rtsx_pcr.h @@ -27,6 +27,8 @@ #define MIN_DIV_N_PCR 80 #define MAX_DIV_N_PCR 208 +#define RTS522A_PM_CTRL3 0xFF7E + #define RTS524A_PME_FORCE_CTL 0xFF78 #define RTS524A_PM_CTRL3 0xFF7E @@ -38,6 +40,7 @@ void rts5229_init_params(struct rtsx_pcr *pcr); void rtl8411_init_params(struct rtsx_pcr *pcr); void rtl8402_init_params(struct rtsx_pcr *pcr); void rts5227_init_params(struct rtsx_pcr *pcr); +void rts522a_init_params(struct rtsx_pcr *pcr); void rts5249_init_params(struct rtsx_pcr *pcr); void rts524a_init_params(struct rtsx_pcr *pcr); void rts525a_init_params(struct rtsx_pcr *pcr); diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h index ff843e7ca23d..7eb7cbac0a9a 100644 --- a/include/linux/mfd/rtsx_pci.h +++ b/include/linux/mfd/rtsx_pci.h @@ -589,6 +589,7 @@ #define FORCE_ASPM_NO_ASPM 0x00 #define PM_CLK_FORCE_CTL 0xFE58 #define FUNC_FORCE_CTL 0xFE59 +#define FUNC_FORCE_UPME_XMT_DBG 0x02 #define PERST_GLITCH_WIDTH 0xFE5C #define CHANGE_LINK_STATE 0xFE5B #define RESET_LOAD_REG 0xFE5E @@ -712,6 +713,7 @@ #define PHY_RCR1 0x02 #define PHY_RCR1_ADP_TIME_4 0x0400 #define PHY_RCR1_VCO_COARSE 0x001F +#define PHY_RCR1_INIT_27S 0x0A1F #define PHY_SSCCR2 0x02 #define PHY_SSCCR2_PLL_NCODE 0x0A00 #define PHY_SSCCR2_TIME0 0x001C @@ -724,6 +726,7 @@ #define PHY_RCR2_FREQSEL_12 0x0040 #define PHY_RCR2_CDR_SC_12P 0x0010 #define PHY_RCR2_CALIB_LATE 0x0002 +#define PHY_RCR2_INIT_27S 0xC152 #define PHY_SSCCR3 0x03 #define PHY_SSCCR3_STEP_IN 0x2740 #define PHY_SSCCR3_CHECK_DELAY 0x0008 @@ -800,12 +803,14 @@ #define PHY_ANA1A_RXT_BIST 0x0500 #define PHY_ANA1A_TXR_BIST 0x0040 #define PHY_ANA1A_REV 0x0006 +#define PHY_FLD0_INIT_27S 0x2546 #define PHY_FLD1 0x1B #define PHY_FLD2 0x1C #define PHY_FLD3 0x1D #define PHY_FLD3_TIMER_4 0x0800 #define PHY_FLD3_TIMER_6 0x0020 #define PHY_FLD3_RXDELINK 0x0004 +#define PHY_FLD3_INIT_27S 0x0004 #define PHY_ANA1D 0x1D #define PHY_ANA1D_DEBUG_ADDR 0x0004 #define _PHY_FLD0 0x1D @@ -824,6 +829,7 @@ #define PHY_FLD4_BER_COUNT 0x00E0 #define PHY_FLD4_BER_TIMER 0x000A #define PHY_FLD4_BER_CHK_EN 0x0001 +#define PHY_FLD4_INIT_27S 0x5C7F #define PHY_DIG1E 0x1E #define PHY_DIG1E_REV 0x4000 #define PHY_DIG1E_D0_X_D1 0x1000 -- cgit v1.2.3-71-gd317 From 8a97d4287e2659f3460a8dec61ccc935154726c0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 7 Oct 2015 09:44:41 +0900 Subject: mfd: sec-core: Disable buck voltage reset on watchdog falling edge The WRSTBI bit (disabled by default but enabled by bootloader), when set, is responsible for resetting voltages to default values of certain bucks on falling edge of Warm Reset Input pin from AP. However on some boards (with S2MPS13) the pin is pulled down so any suspend will effectively trigger the reset of bucks supplying the power to the little and big cores. In the same time when resuming, these bucks must provide voltage greater or equal to voltage before suspend to match the frequency chosen by cpufreq. If voltage (default value of voltage after reset) is lower than one set by cpufreq before suspend, then system will hang during resuming. Signed-off-by: Krzysztof Kozlowski Reported-by: Bartlomiej Zolnierkiewicz Tested-by: Bartlomiej Zolnierkiewicz Signed-off-by: Lee Jones --- drivers/mfd/sec-core.c | 26 ++++++++++++++++++++++++++ include/linux/mfd/samsung/core.h | 2 ++ include/linux/mfd/samsung/s2mps13.h | 1 + 3 files changed, 29 insertions(+) (limited to 'include/linux') diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c index 589e5efc2d7f..2626fc0b5b8c 100644 --- a/drivers/mfd/sec-core.c +++ b/drivers/mfd/sec-core.c @@ -262,6 +262,29 @@ static void sec_pmic_dump_rev(struct sec_pmic_dev *sec_pmic) dev_dbg(sec_pmic->dev, "Revision: 0x%x\n", val); } +static void sec_pmic_configure(struct sec_pmic_dev *sec_pmic) +{ + int err; + + if (sec_pmic->device_type != S2MPS13X) + return; + + if (sec_pmic->pdata->disable_wrstbi) { + /* + * If WRSTBI pin is pulled down this feature must be disabled + * because each Suspend to RAM will trigger buck voltage reset + * to default values. + */ + err = regmap_update_bits(sec_pmic->regmap_pmic, + S2MPS13_REG_WRSTBI, + S2MPS13_REG_WRSTBI_MASK, 0x0); + if (err) + dev_warn(sec_pmic->dev, + "Cannot initialize WRSTBI config: %d\n", + err); + } +} + #ifdef CONFIG_OF /* * Only the common platform data elements for s5m8767 are parsed here from the @@ -289,6 +312,8 @@ static struct sec_platform_data *sec_pmic_i2c_parse_dt_pdata( pd->manual_poweroff = of_property_read_bool(dev->of_node, "samsung,s2mps11-acokb-ground"); + pd->disable_wrstbi = of_property_read_bool(dev->of_node, + "samsung,s2mps11-wrstbi-ground"); return pd; } #else @@ -434,6 +459,7 @@ static int sec_pmic_probe(struct i2c_client *i2c, goto err_mfd; device_init_wakeup(sec_pmic->dev, sec_pmic->wakeup); + sec_pmic_configure(sec_pmic); sec_pmic_dump_rev(sec_pmic); return ret; diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h index aa78957e092f..a06098639399 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -134,6 +134,8 @@ struct sec_platform_data { int buck4_init; /* Whether or not manually set PWRHOLD to low during shutdown. */ bool manual_poweroff; + /* Disable the WRSTBI (buck voltage warm reset) when probing? */ + bool disable_wrstbi; }; /** diff --git a/include/linux/mfd/samsung/s2mps13.h b/include/linux/mfd/samsung/s2mps13.h index b1fd675fa36f..239e977ba45d 100644 --- a/include/linux/mfd/samsung/s2mps13.h +++ b/include/linux/mfd/samsung/s2mps13.h @@ -184,5 +184,6 @@ enum s2mps13_regulators { * Let's assume that default value will be set. */ #define S2MPS13_BUCK_RAMP_DELAY 12500 +#define S2MPS13_REG_WRSTBI_MASK BIT(5) #endif /* __LINUX_MFD_S2MPS13_H */ -- cgit v1.2.3-71-gd317