From 06d8308c61e54346585b2691c13ee3f90cb6fb2f Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sat, 22 Mar 2008 09:20:24 +0100 Subject: NOHZ: reevaluate idle sleep length after add_timer_on() add_timer_on() can add a timer on a CPU which is currently in a long idle sleep, but the timer wheel is not reevaluated by the nohz code on that CPU. So a timer can be delayed for quite a long time. This triggered a false positive in the clocksource watchdog code. To avoid this we need to wake up the idle CPU and enforce the reevaluation of the timer wheel for the next timer event. Add a function, which checks a given CPU for idle state, marks the idle task with NEED_RESCHED and sends a reschedule IPI to notify the other CPU of the change in the timer wheel. Call this function from add_timer_on(). Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra Acked-by: Ingo Molnar Cc: stable@kernel.org -- include/linux/sched.h | 6 ++++++ kernel/sched.c | 43 +++++++++++++++++++++++++++++++++++++++++++ kernel/timer.c | 10 +++++++++- 3 files changed, 58 insertions(+), 1 deletion(-) --- include/linux/sched.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/linux') diff --git a/include/linux/sched.h b/include/linux/sched.h index fed07d03364e..6a1e7afb099b 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -1541,6 +1541,12 @@ static inline void idle_task_exit(void) {} extern void sched_idle_next(void); +#if defined(CONFIG_NO_HZ) && defined(CONFIG_SMP) +extern void wake_up_idle_cpu(int cpu); +#else +static inline void wake_up_idle_cpu(int cpu) { } +#endif + #ifdef CONFIG_SCHED_DEBUG extern unsigned int sysctl_sched_latency; extern unsigned int sysctl_sched_min_granularity; -- cgit v1.2.3-71-gd317 From abc848c182960118fbb7cdae397b5608c5bcef1b Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:39 -0400 Subject: introduce mbus DRAM target info abstraction Introduce struct mbus_dram_target_info, which will be used for passing information about the mbus target ID of the DDR unit, and mbus target attribute, base address and size for each of the DRAM chip selects from the platform code to peripheral drivers. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- include/linux/mbus.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 include/linux/mbus.h (limited to 'include/linux') diff --git a/include/linux/mbus.h b/include/linux/mbus.h new file mode 100644 index 000000000000..c11ff2932549 --- /dev/null +++ b/include/linux/mbus.h @@ -0,0 +1,36 @@ +/* + * Marvell MBUS common definitions. + * + * Copyright (C) 2008 Marvell Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __LINUX_MBUS_H +#define __LINUX_MBUS_H + +struct mbus_dram_target_info +{ + /* + * The 4-bit MBUS target ID of the DRAM controller. + */ + u8 mbus_dram_target_id; + + /* + * The base address, size, and MBUS attribute ID for each + * of the possible DRAM chip selects. Peripherals are + * required to support at least 4 decode windows. + */ + int num_cs; + struct mbus_dram_window { + u8 cs_index; + u8 mbus_attr; + u32 base; + u32 size; + } cs[4]; +}; + + +#endif -- cgit v1.2.3-71-gd317 From 15a32632d94011911497052a96cdbf3b905b325d Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:39 -0400 Subject: sata_mv: mbus decode window support Make it possible to pass mbus_dram_target_info to the sata_mv driver via the platform data, make the sata_mv driver program the window registers based on this data if it is passed in, and make the Orion platform setup code use this method instead of programming the SATA mbus window registers by hand. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 39 --------------------------------------- arch/arm/mach-orion/common.c | 4 ++-- arch/arm/mach-orion/common.h | 1 - drivers/ata/sata_mv.c | 31 +++++++++++++++++++++++++++++++ include/linux/ata_platform.h | 3 +++ 5 files changed, 36 insertions(+), 42 deletions(-) (limited to 'include/linux') diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index 40bcb986ab96..3de5de9ac656 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -103,13 +103,6 @@ #define ETH_MAX_WIN 6 #define ETH_MAX_REMAP_WIN 4 -/* - * SATA Address Decode Windows registers - */ -#define SATA_WIN_CTRL(win) ORION_SATA_REG(0x30 + ((win) * 0x10)) -#define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10)) -#define SATA_MAX_WIN 4 - struct mbus_dram_target_info orion_mbus_dram_info; @@ -288,35 +281,3 @@ void __init orion_setup_eth_wins(void) } } } - -void __init orion_setup_sata_wins(void) -{ - int i; - - /* - * First, disable and clear windows - */ - for (i = 0; i < SATA_MAX_WIN; i++) { - orion_write(SATA_WIN_BASE(i), 0); - orion_write(SATA_WIN_CTRL(i), 0); - } - - /* - * Setup windows for DDR banks. - */ - for (i = 0; i < DDR_MAX_CS; i++) { - u32 base, size; - size = orion_read(DDR_SIZE_CS(i)); - base = orion_read(DDR_BASE_CS(i)); - if (size & DDR_BANK_EN) { - base = DDR_REG_TO_BASE(base); - size = DDR_REG_TO_SIZE(size); - orion_write(SATA_WIN_CTRL(i), - ((size-1) & 0xffff0000) | - (ATTR_DDR_CS(i) << 8) | - (TARGET_DDR << 4) | WIN_EN); - orion_write(SATA_WIN_BASE(i), - base & 0xffff0000); - } - } -} diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index d33c01dfc3f2..a32fe8e108bc 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -289,6 +290,7 @@ static struct platform_device orion_sata = { void __init orion_sata_init(struct mv_sata_platform_data *sata_data) { + sata_data->dram = &orion_mbus_dram_info; orion_sata.dev.platform_data = sata_data; platform_device_register(&orion_sata); } @@ -342,8 +344,6 @@ void __init orion_init(void) */ orion_setup_cpu_wins(); orion_setup_eth_wins(); - if (dev == MV88F5182_DEV_ID) - orion_setup_sata_wins(); /* * REgister devices diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index c100355754f3..b676be0a4a86 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -33,7 +33,6 @@ extern struct mbus_dram_target_info orion_mbus_dram_info; void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap); void orion_setup_cpu_wins(void); void orion_setup_eth_wins(void); -void orion_setup_sata_wins(void); /* * Shared code used internally by other Orion core functions. diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 6ebebde8454a..83584b6e1ba5 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -74,6 +74,7 @@ #include #include #include +#include #include #include #include @@ -352,6 +353,9 @@ enum { #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) +#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) +#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) + enum { /* DMA boundary 0xffff is required by the s/g splitting * we need on /length/ in mv_fill-sg(). @@ -2897,6 +2901,27 @@ static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) return 0; } +static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, + struct mbus_dram_target_info *dram) +{ + int i; + + for (i = 0; i < 4; i++) { + writel(0, hpriv->base + WINDOW_CTRL(i)); + writel(0, hpriv->base + WINDOW_BASE(i)); + } + + for (i = 0; i < dram->num_cs; i++) { + struct mbus_dram_window *cs = dram->cs + i; + + writel(((cs->size - 1) & 0xffff0000) | + (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + hpriv->base + WINDOW_CTRL(i)); + writel(cs->base, hpriv->base + WINDOW_BASE(i)); + } +} + /** * mv_platform_probe - handle a positive probe of an soc Marvell * host @@ -2951,6 +2976,12 @@ static int mv_platform_probe(struct platform_device *pdev) res->end - res->start + 1); hpriv->base -= MV_SATAHC0_REG_BASE; + /* + * (Re-)program MBUS remapping windows if we are asked to. + */ + if (mv_platform_data->dram != NULL) + mv_conf_mbus_windows(hpriv, mv_platform_data->dram); + rc = mv_create_dma_pools(hpriv, &pdev->dev); if (rc) return rc; diff --git a/include/linux/ata_platform.h b/include/linux/ata_platform.h index b856a2a590d9..9a26c83a2c9e 100644 --- a/include/linux/ata_platform.h +++ b/include/linux/ata_platform.h @@ -27,7 +27,10 @@ extern int __devexit __pata_platform_remove(struct device *dev); /* * Marvell SATA private data */ +struct mbus_dram_target_info; + struct mv_sata_platform_data { + struct mbus_dram_target_info *dram; int n_ports; /* number of sata ports */ }; -- cgit v1.2.3-71-gd317 From a1635b8fe59de2c5223cda5ca8397b875c901904 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Wed, 9 Apr 2008 19:20:34 +0100 Subject: [ARM] 4947/1: htc-egpio, a driver for GPIO/IRQ expanders with fixed input/output pins implemented in CPLD chips on several HTC devices. The original driver was written by Kevin O'Connor, I have adapted it to use gpiolib and made the bus/register widths configurable. Signed-off-by: Philipp Zabel Signed-off-by: Russell King --- drivers/mfd/Kconfig | 8 + drivers/mfd/Makefile | 2 + drivers/mfd/htc-egpio.c | 440 ++++++++++++++++++++++++++++++++++++++++++ include/linux/mfd/htc-egpio.h | 57 ++++++ 4 files changed, 507 insertions(+) create mode 100644 drivers/mfd/htc-egpio.c create mode 100644 include/linux/mfd/htc-egpio.h (limited to 'include/linux') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 0c886c882385..284b2dc03444 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -22,6 +22,14 @@ config MFD_ASIC3 This driver supports the ASIC3 multifunction chip found on many PDAs (mainly iPAQ and HTC based ones) +config HTC_EGPIO + bool "HTC EGPIO support" + depends on GENERIC_HARDIRQS && HAVE_GPIO_LIB + help + This driver supports the CPLD egpio chip present on + several HTC phones. It provides basic support for input + pins, output pins, and irqs. + endmenu menu "Multimedia Capabilities Port drivers" diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 521cd5cb68af..f81f8d2e2c03 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -5,6 +5,8 @@ obj-$(CONFIG_MFD_SM501) += sm501.o obj-$(CONFIG_MFD_ASIC3) += asic3.o +obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o + obj-$(CONFIG_MCP) += mcp-core.o obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o diff --git a/drivers/mfd/htc-egpio.c b/drivers/mfd/htc-egpio.c new file mode 100644 index 000000000000..8872cc077519 --- /dev/null +++ b/drivers/mfd/htc-egpio.c @@ -0,0 +1,440 @@ +/* + * Support for the GPIO/IRQ expander chips present on several HTC phones. + * These are implemented in CPLD chips present on the board. + * + * Copyright (c) 2007 Kevin O'Connor + * Copyright (c) 2007 Philipp Zabel + * + * This file may be distributed under the terms of the GNU GPL license. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct egpio_chip { + int reg_start; + int cached_values; + unsigned long is_out; + struct device *dev; + struct gpio_chip chip; +}; + +struct egpio_info { + spinlock_t lock; + + /* iomem info */ + void __iomem *base_addr; + int bus_shift; /* byte shift */ + int reg_shift; /* bit shift */ + int reg_mask; + + /* irq info */ + int ack_register; + int ack_write; + u16 irqs_enabled; + uint irq_start; + int nirqs; + uint chained_irq; + + /* egpio info */ + struct egpio_chip *chip; + int nchips; +}; + +static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg) +{ + writew(value, ei->base_addr + (reg << ei->bus_shift)); +} + +static inline u16 egpio_readw(struct egpio_info *ei, int reg) +{ + return readw(ei->base_addr + (reg << ei->bus_shift)); +} + +/* + * IRQs + */ + +static inline void ack_irqs(struct egpio_info *ei) +{ + egpio_writew(ei->ack_write, ei, ei->ack_register); + pr_debug("EGPIO ack - write %x to base+%x\n", + ei->ack_write, ei->ack_register << ei->bus_shift); +} + +static void egpio_ack(unsigned int irq) +{ +} + +/* There does not appear to be a way to proactively mask interrupts + * on the egpio chip itself. So, we simply ignore interrupts that + * aren't desired. */ +static void egpio_mask(unsigned int irq) +{ + struct egpio_info *ei = get_irq_chip_data(irq); + ei->irqs_enabled &= ~(1 << (irq - ei->irq_start)); + pr_debug("EGPIO mask %d %04x\n", irq, ei->irqs_enabled); +} +static void egpio_unmask(unsigned int irq) +{ + struct egpio_info *ei = get_irq_chip_data(irq); + ei->irqs_enabled |= 1 << (irq - ei->irq_start); + pr_debug("EGPIO unmask %d %04x\n", irq, ei->irqs_enabled); +} + +static struct irq_chip egpio_muxed_chip = { + .name = "htc-egpio", + .ack = egpio_ack, + .mask = egpio_mask, + .unmask = egpio_unmask, +}; + +static void egpio_handler(unsigned int irq, struct irq_desc *desc) +{ + struct egpio_info *ei = get_irq_data(irq); + int irqpin; + + /* Read current pins. */ + unsigned long readval = egpio_readw(ei, ei->ack_register); + pr_debug("IRQ reg: %x\n", (unsigned int)readval); + /* Ack/unmask interrupts. */ + ack_irqs(ei); + /* Process all set pins. */ + readval &= ei->irqs_enabled; + for_each_bit(irqpin, &readval, ei->nirqs) { + /* Run irq handler */ + pr_debug("got IRQ %d\n", irqpin); + irq = ei->irq_start + irqpin; + desc = &irq_desc[irq]; + desc->handle_irq(irq, desc); + } +} + +int htc_egpio_get_wakeup_irq(struct device *dev) +{ + struct egpio_info *ei = dev_get_drvdata(dev); + + /* Read current pins. */ + u16 readval = egpio_readw(ei, ei->ack_register); + /* Ack/unmask interrupts. */ + ack_irqs(ei); + /* Return first set pin. */ + readval &= ei->irqs_enabled; + return ei->irq_start + ffs(readval) - 1; +} +EXPORT_SYMBOL(htc_egpio_get_wakeup_irq); + +static inline int egpio_pos(struct egpio_info *ei, int bit) +{ + return bit >> ei->reg_shift; +} + +static inline int egpio_bit(struct egpio_info *ei, int bit) +{ + return 1 << (bit & ((1 << ei->reg_shift)-1)); +} + +/* + * Input pins + */ + +static int egpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct egpio_chip *egpio; + struct egpio_info *ei; + unsigned bit; + int reg; + int value; + + pr_debug("egpio_get_value(%d)\n", chip->base + offset); + + egpio = container_of(chip, struct egpio_chip, chip); + ei = dev_get_drvdata(egpio->dev); + bit = egpio_bit(ei, offset); + reg = egpio->reg_start + egpio_pos(ei, offset); + + value = egpio_readw(ei, reg); + pr_debug("readw(%p + %x) = %x\n", + ei->base_addr, reg << ei->bus_shift, value); + return value & bit; +} + +static int egpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct egpio_chip *egpio; + + egpio = container_of(chip, struct egpio_chip, chip); + return test_bit(offset, &egpio->is_out) ? -EINVAL : 0; +} + + +/* + * Output pins + */ + +static void egpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + unsigned long flag; + struct egpio_chip *egpio; + struct egpio_info *ei; + unsigned bit; + int pos; + int reg; + int shift; + + pr_debug("egpio_set(%s, %d(%d), %d)\n", + chip->label, offset, offset+chip->base, value); + + egpio = container_of(chip, struct egpio_chip, chip); + ei = dev_get_drvdata(egpio->dev); + bit = egpio_bit(ei, offset); + pos = egpio_pos(ei, offset); + reg = egpio->reg_start + pos; + shift = pos << ei->reg_shift; + + pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear", + reg, (egpio->cached_values >> shift) & ei->reg_mask); + + spin_lock_irqsave(&ei->lock, flag); + if (value) + egpio->cached_values |= (1 << offset); + else + egpio->cached_values &= ~(1 << offset); + egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg); + spin_unlock_irqrestore(&ei->lock, flag); +} + +static int egpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct egpio_chip *egpio; + + egpio = container_of(chip, struct egpio_chip, chip); + if (test_bit(offset, &egpio->is_out)) { + egpio_set(chip, offset, value); + return 0; + } else { + return -EINVAL; + } +} + +static void egpio_write_cache(struct egpio_info *ei) +{ + int i; + struct egpio_chip *egpio; + int shift; + + for (i = 0; i < ei->nchips; i++) { + egpio = &(ei->chip[i]); + if (!egpio->is_out) + continue; + + for (shift = 0; shift < egpio->chip.ngpio; + shift += (1<reg_shift)) { + + int reg = egpio->reg_start + egpio_pos(ei, shift); + + if (!((egpio->is_out >> shift) & ei->reg_mask)) + continue; + + pr_debug("EGPIO: setting %x to %x, was %x\n", reg, + (egpio->cached_values >> shift) & ei->reg_mask, + egpio_readw(ei, reg)); + + egpio_writew((egpio->cached_values >> shift) + & ei->reg_mask, ei, reg); + } + } +} + + +/* + * Setup + */ + +static int __init egpio_probe(struct platform_device *pdev) +{ + struct htc_egpio_platform_data *pdata = pdev->dev.platform_data; + struct resource *res; + struct egpio_info *ei; + struct gpio_chip *chip; + unsigned int irq, irq_end; + int i; + int ret; + + /* Initialize ei data structure. */ + ei = kzalloc(sizeof(*ei), GFP_KERNEL); + if (!ei) + return -ENOMEM; + + spin_lock_init(&ei->lock); + + /* Find chained irq */ + ret = -EINVAL; + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res) + ei->chained_irq = res->start; + + /* Map egpio chip into virtual address space. */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + goto fail; + ei->base_addr = ioremap_nocache(res->start, res->end - res->start); + if (!ei->base_addr) + goto fail; + pr_debug("EGPIO phys=%08x virt=%p\n", res->start, ei->base_addr); + + if ((pdata->bus_width != 16) && (pdata->bus_width != 32)) + goto fail; + ei->bus_shift = fls(pdata->bus_width - 1) - 3; + pr_debug("bus_shift = %d\n", ei->bus_shift); + + if ((pdata->reg_width != 8) && (pdata->reg_width != 16)) + goto fail; + ei->reg_shift = fls(pdata->reg_width - 1); + pr_debug("reg_shift = %d\n", ei->reg_shift); + + ei->reg_mask = (1 << pdata->reg_width) - 1; + + platform_set_drvdata(pdev, ei); + + ei->nchips = pdata->num_chips; + ei->chip = kzalloc(sizeof(struct egpio_chip) * ei->nchips, GFP_KERNEL); + if (!ei) { + ret = -ENOMEM; + goto fail; + } + for (i = 0; i < ei->nchips; i++) { + ei->chip[i].reg_start = pdata->chip[i].reg_start; + ei->chip[i].cached_values = pdata->chip[i].initial_values; + ei->chip[i].is_out = pdata->chip[i].direction; + ei->chip[i].dev = &(pdev->dev); + chip = &(ei->chip[i].chip); + chip->label = "htc-egpio"; + chip->get = egpio_get; + chip->set = egpio_set; + chip->direction_input = egpio_direction_input; + chip->direction_output = egpio_direction_output; + chip->base = pdata->chip[i].gpio_base; + chip->ngpio = pdata->chip[i].num_gpios; + + gpiochip_add(chip); + } + + /* Set initial pin values */ + egpio_write_cache(ei); + + ei->irq_start = pdata->irq_base; + ei->nirqs = pdata->num_irqs; + ei->ack_register = pdata->ack_register; + + if (ei->chained_irq) { + /* Setup irq handlers */ + ei->ack_write = 0xFFFF; + if (pdata->invert_acks) + ei->ack_write = 0; + irq_end = ei->irq_start + ei->nirqs; + for (irq = ei->irq_start; irq < irq_end; irq++) { + set_irq_chip(irq, &egpio_muxed_chip); + set_irq_chip_data(irq, ei); + set_irq_handler(irq, handle_simple_irq); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + } + set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING); + set_irq_data(ei->chained_irq, ei); + set_irq_chained_handler(ei->chained_irq, egpio_handler); + ack_irqs(ei); + + device_init_wakeup(&pdev->dev, 1); + } + + return 0; + +fail: + printk(KERN_ERR "EGPIO failed to setup\n"); + kfree(ei); + return ret; +} + +static int __exit egpio_remove(struct platform_device *pdev) +{ + struct egpio_info *ei = platform_get_drvdata(pdev); + unsigned int irq, irq_end; + + if (ei->chained_irq) { + irq_end = ei->irq_start + ei->nirqs; + for (irq = ei->irq_start; irq < irq_end; irq++) { + set_irq_chip(irq, NULL); + set_irq_handler(irq, NULL); + set_irq_flags(irq, 0); + } + set_irq_chained_handler(ei->chained_irq, NULL); + device_init_wakeup(&pdev->dev, 0); + } + iounmap(ei->base_addr); + kfree(ei->chip); + kfree(ei); + + return 0; +} + +#ifdef CONFIG_PM +static int egpio_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct egpio_info *ei = platform_get_drvdata(pdev); + + if (ei->chained_irq && device_may_wakeup(&pdev->dev)) + enable_irq_wake(ei->chained_irq); + return 0; +} + +static int egpio_resume(struct platform_device *pdev) +{ + struct egpio_info *ei = platform_get_drvdata(pdev); + + if (ei->chained_irq && device_may_wakeup(&pdev->dev)) + disable_irq_wake(ei->chained_irq); + + /* Update registers from the cache, in case + the CPLD was powered off during suspend */ + egpio_write_cache(ei); + return 0; +} +#else +#define egpio_suspend NULL +#define egpio_resume NULL +#endif + + +static struct platform_driver egpio_driver = { + .driver = { + .name = "htc-egpio", + }, + .remove = __exit_p(egpio_remove), + .suspend = egpio_suspend, + .resume = egpio_resume, +}; + +static int __init egpio_init(void) +{ + return platform_driver_probe(&egpio_driver, egpio_probe); +} + +static void __exit egpio_exit(void) +{ + platform_driver_unregister(&egpio_driver); +} + +/* start early for dependencies */ +subsys_initcall(egpio_init); +module_exit(egpio_exit) + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Kevin O'Connor "); diff --git a/include/linux/mfd/htc-egpio.h b/include/linux/mfd/htc-egpio.h new file mode 100644 index 000000000000..b4201c971367 --- /dev/null +++ b/include/linux/mfd/htc-egpio.h @@ -0,0 +1,57 @@ +/* + * HTC simple EGPIO irq and gpio extender + */ + +#ifndef __HTC_EGPIO_H__ +#define __HTC_EGPIO_H__ + +#include + +/* Descriptive values for all-in or all-out htc_egpio_chip descriptors. */ +#define HTC_EGPIO_OUTPUT (~0) +#define HTC_EGPIO_INPUT 0 + +/** + * struct htc_egpio_chip - descriptor to create gpio_chip for register range + * @reg_start: index of first register + * @gpio_base: gpio number of first pin in this register range + * @num_gpios: number of gpios in this register range, max BITS_PER_LONG + * (number of registers = DIV_ROUND_UP(num_gpios, reg_width)) + * @direction: bitfield, '0' = input, '1' = output, + */ +struct htc_egpio_chip { + int reg_start; + int gpio_base; + int num_gpios; + unsigned long direction; + unsigned long initial_values; +}; + +/** + * struct htc_egpio_platform_data - description provided by the arch + * @irq_base: beginning of available IRQs (eg, IRQ_BOARD_START) + * @num_irqs: number of irqs + * @reg_width: number of bits per register, either 8 or 16 bit + * @bus_width: alignment of the registers, either 16 or 32 bit + * @invert_acks: set if chip requires writing '0' to ack an irq, instead of '1' + * @ack_register: location of the irq/ack register + * @chip: pointer to array of htc_egpio_chip descriptors + * @num_chips: number of egpio chip descriptors + */ +struct htc_egpio_platform_data { + int bus_width; + int reg_width; + + int irq_base; + int num_irqs; + int invert_acks; + int ack_register; + + struct htc_egpio_chip *chip; + int num_chips; +}; + +/* Determine the wakeup irq, to be called during early resume */ +extern int htc_egpio_get_wakeup_irq(struct device *dev); + +#endif -- cgit v1.2.3-71-gd317 From 5dc3339aa5ba29593ea57814049ddca8c12831c8 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Sat, 12 Apr 2008 13:25:41 +0100 Subject: [ARM] 4964/1: htc-pasic3: MFD driver for PASIC3 LED control + DS1WM chip This driver will provide registers, clocks and GPIOs of the HTC PASIC3 (AIC3) and PASIC2 (AIC2) chips to the ds1wm and leds-pasic3 drivers. Signed-off-by: Philipp Zabel Signed-off-by: Russell King --- drivers/mfd/Kconfig | 8 ++ drivers/mfd/Makefile | 1 + drivers/mfd/htc-pasic3.c | 265 +++++++++++++++++++++++++++++++++++++++++ include/linux/mfd/htc-pasic3.h | 55 +++++++++ 4 files changed, 329 insertions(+) create mode 100644 drivers/mfd/htc-pasic3.c create mode 100644 include/linux/mfd/htc-pasic3.h (limited to 'include/linux') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 284b2dc03444..2566479937c9 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -30,6 +30,14 @@ config HTC_EGPIO several HTC phones. It provides basic support for input pins, output pins, and irqs. +config HTC_PASIC3 + tristate "HTC PASIC3 LED/DS1WM chip support" + help + This core driver provides register access for the LED/DS1WM + chips labeled "AIC2" and "AIC3", found on HTC Blueangel and + HTC Magician devices, respectively. Actual functionality is + handled by the leds-pasic3 and ds1wm drivers. + endmenu menu "Multimedia Capabilities Port drivers" diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index f81f8d2e2c03..eef4e26807df 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_MFD_SM501) += sm501.o obj-$(CONFIG_MFD_ASIC3) += asic3.o obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o +obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o obj-$(CONFIG_MCP) += mcp-core.o obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o diff --git a/drivers/mfd/htc-pasic3.c b/drivers/mfd/htc-pasic3.c new file mode 100644 index 000000000000..af66f4f28300 --- /dev/null +++ b/drivers/mfd/htc-pasic3.c @@ -0,0 +1,265 @@ +/* + * Core driver for HTC PASIC3 LED/DS1WM chip. + * + * Copyright (C) 2006 Philipp Zabel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +struct pasic3_data { + void __iomem *mapping; + unsigned int bus_shift; + struct platform_device *ds1wm_pdev; + struct platform_device *led_pdev; +}; + +#define REG_ADDR 5 +#define REG_DATA 6 +#define NUM_REGS 7 + +#define READ_MODE 0x80 + +/* + * write to a secondary register on the PASIC3 + */ +void pasic3_write_register(struct device *dev, u32 reg, u8 val) +{ + struct pasic3_data *asic = dev->driver_data; + int bus_shift = asic->bus_shift; + void __iomem *addr = asic->mapping + (REG_ADDR << bus_shift); + void __iomem *data = asic->mapping + (REG_DATA << bus_shift); + + __raw_writeb(~READ_MODE & reg, addr); + __raw_writeb(val, data); +} +EXPORT_SYMBOL(pasic3_write_register); /* for leds-pasic3 */ + +/* + * read from a secondary register on the PASIC3 + */ +u8 pasic3_read_register(struct device *dev, u32 reg) +{ + struct pasic3_data *asic = dev->driver_data; + int bus_shift = asic->bus_shift; + void __iomem *addr = asic->mapping + (REG_ADDR << bus_shift); + void __iomem *data = asic->mapping + (REG_DATA << bus_shift); + + __raw_writeb(READ_MODE | reg, addr); + return __raw_readb(data); +} +EXPORT_SYMBOL(pasic3_read_register); /* for leds-pasic3 */ + +/* + * LEDs + */ + +static int led_device_add(struct device *pasic3_dev, + const struct pasic3_leds_machinfo *pdata) +{ + struct pasic3_data *asic = pasic3_dev->driver_data; + struct platform_device *pdev; + int ret; + + pdev = platform_device_alloc("pasic3-led", -1); + if (!pdev) { + dev_dbg(pasic3_dev, "failed to allocate LED platform device\n"); + return -ENOMEM; + } + + ret = platform_device_add_data(pdev, pdata, + sizeof(struct pasic3_leds_machinfo)); + if (ret < 0) { + dev_dbg(pasic3_dev, "failed to add LED platform data\n"); + goto exit_pdev_put; + } + + pdev->dev.parent = pasic3_dev; + ret = platform_device_add(pdev); + if (ret < 0) { + dev_dbg(pasic3_dev, "failed to add LED platform device\n"); + goto exit_pdev_put; + } + + asic->led_pdev = pdev; + return 0; + +exit_pdev_put: + platform_device_put(pdev); + return ret; +} + +/* + * DS1WM + */ + +static void ds1wm_enable(struct platform_device *pdev) +{ + struct device *dev = pdev->dev.parent; + int c; + + c = pasic3_read_register(dev, 0x28); + pasic3_write_register(dev, 0x28, c & 0x7f); + + dev_dbg(dev, "DS1WM OWM_EN low (active) %02x\n", c & 0x7f); +} + +static void ds1wm_disable(struct platform_device *pdev) +{ + struct device *dev = pdev->dev.parent; + int c; + + c = pasic3_read_register(dev, 0x28); + pasic3_write_register(dev, 0x28, c | 0x80); + + dev_dbg(dev, "DS1WM OWM_EN high (inactive) %02x\n", c | 0x80); +} + +static struct ds1wm_platform_data ds1wm_pdata = { + .bus_shift = 2, + .enable = ds1wm_enable, + .disable = ds1wm_disable, +}; + +static int ds1wm_device_add(struct device *pasic3_dev, int bus_shift) +{ + struct pasic3_data *asic = pasic3_dev->driver_data; + struct platform_device *pdev; + int ret; + + pdev = platform_device_alloc("ds1wm", -1); + if (!pdev) { + dev_dbg(pasic3_dev, "failed to allocate DS1WM platform device\n"); + return -ENOMEM; + } + + ret = platform_device_add_resources(pdev, pdev->resource, + pdev->num_resources); + if (ret < 0) { + dev_dbg(pasic3_dev, "failed to add DS1WM resources\n"); + goto exit_pdev_put; + } + + ds1wm_pdata.bus_shift = asic->bus_shift; + ret = platform_device_add_data(pdev, &ds1wm_pdata, + sizeof(struct ds1wm_platform_data)); + if (ret < 0) { + dev_dbg(pasic3_dev, "failed to add DS1WM platform data\n"); + goto exit_pdev_put; + } + + pdev->dev.parent = pasic3_dev; + ret = platform_device_add(pdev); + if (ret < 0) { + dev_dbg(pasic3_dev, "failed to add DS1WM platform device\n"); + goto exit_pdev_put; + } + + asic->ds1wm_pdev = pdev; + return 0; + +exit_pdev_put: + platform_device_put(pdev); + return ret; +} + +static int __init pasic3_probe(struct platform_device *pdev) +{ + struct pasic3_platform_data *pdata = pdev->dev.platform_data; + struct device *dev = &pdev->dev; + struct pasic3_data *asic; + struct resource *r; + int ret; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) + return -ENXIO; + + if (!request_mem_region(r->start, r->end - r->start + 1, "pasic3")) + return -EBUSY; + + asic = kzalloc(sizeof(struct pasic3_data), GFP_KERNEL); + if (!asic) + return -ENOMEM; + + platform_set_drvdata(pdev, asic); + + if (pdata && pdata->bus_shift) + asic->bus_shift = pdata->bus_shift; + else + asic->bus_shift = 2; + + asic->mapping = ioremap(r->start, r->end - r->start + 1); + if (!asic->mapping) { + dev_err(dev, "couldn't ioremap PASIC3\n"); + kfree(asic); + return -ENOMEM; + } + + ret = ds1wm_device_add(dev, asic->bus_shift); + if (ret < 0) + dev_warn(dev, "failed to register DS1WM\n"); + + if (pdata->led_pdata) { + ret = led_device_add(dev, pdata->led_pdata); + if (ret < 0) + dev_warn(dev, "failed to register LED device\n"); + } + + return 0; +} + +static int pasic3_remove(struct platform_device *pdev) +{ + struct pasic3_data *asic = platform_get_drvdata(pdev); + struct resource *r; + + if (asic->led_pdev) + platform_device_unregister(asic->led_pdev); + if (asic->ds1wm_pdev) + platform_device_unregister(asic->ds1wm_pdev); + + iounmap(asic->mapping); + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(r->start, r->end - r->start + 1); + kfree(asic); + return 0; +} + +static struct platform_driver pasic3_driver = { + .driver = { + .name = "pasic3", + }, + .remove = pasic3_remove, +}; + +static int __init pasic3_base_init(void) +{ + return platform_driver_probe(&pasic3_driver, pasic3_probe); +} + +static void __exit pasic3_base_exit(void) +{ + platform_driver_unregister(&pasic3_driver); +} + +module_init(pasic3_base_init); +module_exit(pasic3_base_exit); + +MODULE_AUTHOR("Philipp Zabel "); +MODULE_DESCRIPTION("Core driver for HTC PASIC3"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/htc-pasic3.h b/include/linux/mfd/htc-pasic3.h new file mode 100644 index 000000000000..b4294f12c4f8 --- /dev/null +++ b/include/linux/mfd/htc-pasic3.h @@ -0,0 +1,55 @@ +/* + * HTC PASIC3 driver - LEDs and DS1WM + * + * Copyright (c) 2007 Philipp Zabel + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + * + */ + +#ifndef __PASIC3_H +#define __PASIC3_H + +#include +#include + +extern void pasic3_write_register(struct device *dev, u32 reg, u8 val); +extern u8 pasic3_read_register(struct device *dev, u32 reg); + +/* + * mask for registers 0x20,0x21,0x22 + */ +#define PASIC3_MASK_LED0 0x04 +#define PASIC3_MASK_LED1 0x08 +#define PASIC3_MASK_LED2 0x40 + +/* + * bits in register 0x06 + */ +#define PASIC3_BIT2_LED0 0x08 +#define PASIC3_BIT2_LED1 0x10 +#define PASIC3_BIT2_LED2 0x20 + +struct pasic3_led { + struct led_classdev led; + unsigned int hw_num; + unsigned int bit2; + unsigned int mask; + struct pasic3_leds_machinfo *pdata; +}; + +struct pasic3_leds_machinfo { + unsigned int num_leds; + unsigned int power_gpio; + struct pasic3_led *leds; +}; + +struct pasic3_platform_data { + struct pasic3_leds_machinfo *led_pdata; + unsigned int bus_shift; + unsigned int clock_rate; +}; + +#endif -- cgit v1.2.3-71-gd317