From 2dc63e768ce2fbf24cb49c858f549596bb30a0a0 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 3 Mar 2022 02:00:41 +0530 Subject: clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150 Add the PCIe0 and PCIe1 GDSC defines & driver structures for SM8150. Cc: Stephen Boyd Cc: Bjorn Andersson Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220302203045.184500-4-bhupesh.sharma@linaro.org --- include/dt-bindings/clock/qcom,gcc-sm8150.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h index 3e1a91876610..ae9c16410420 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -241,6 +241,8 @@ #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 /* GCC GDSCRs */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 #define USB30_PRIM_GDSC 4 #define USB30_SEC_GDSC 5 -- cgit v1.2.3-71-gd317