From 918da95176beb743ff47b3bbfb0a4ee420658a95 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 20 Feb 2018 14:48:33 +1030 Subject: fsi: gpio: Trace busy count An observation from trace output of the existing FSI tracepoints was that the remote device was sometimes reporting as busy. Add a new tracepoint reporting the busy count in order to get a better grip on how often this is the case. Signed-off-by: Andrew Jeffery Acked-by: Eddie James Signed-off-by: Benjamin Herrenschmidt Tested-by: Joel Stanley --- include/trace/events/fsi_master_gpio.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'include') diff --git a/include/trace/events/fsi_master_gpio.h b/include/trace/events/fsi_master_gpio.h index f95cf3264bf9..33e928c5acf3 100644 --- a/include/trace/events/fsi_master_gpio.h +++ b/include/trace/events/fsi_master_gpio.h @@ -64,6 +64,22 @@ TRACE_EVENT(fsi_master_gpio_break, ) ); + +TRACE_EVENT(fsi_master_gpio_poll_response_busy, + TP_PROTO(const struct fsi_master_gpio *master, int busy), + TP_ARGS(master, busy), + TP_STRUCT__entry( + __field(int, master_idx) + __field(int, busy) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + __entry->busy = busy; + ), + TP_printk("fsi-gpio%d: device reported busy %d times", + __entry->master_idx, __entry->busy) +); + #endif /* _TRACE_FSI_MASTER_GPIO_H */ #include -- cgit v1.2.3-71-gd317 From 4e56828a5db19e2de8f8dc464c6df2e7e9ff4e13 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 15 May 2018 16:14:43 +1000 Subject: fsi/fsi-master-gpio: Implement CRC error recovery The FSI protocol defines two modes of recovery from CRC errors, this implements both: - If the device returns an ECRC (it detected a CRC error in the command), then we simply issue the command again. - If the master detects a CRC error in the response, we send an E_POLL command which requests a resend of the response without actually re-executing the command (which could otherwise have unwanted side effects such as dequeuing a FIFO twice). Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Christopher Bostic Tested-by: Joel Stanley --- Note: This was actually tested by removing some of my fixes, thus causing us to hit occasional CRC errors during high LPC activity. --- drivers/fsi/fsi-master-gpio.c | 90 +++++++++++++++++++++++++++------- include/trace/events/fsi_master_gpio.h | 27 ++++++++++ 2 files changed, 99 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/drivers/fsi/fsi-master-gpio.c b/drivers/fsi/fsi-master-gpio.c index 0a6799bda294..351c12f2ac55 100644 --- a/drivers/fsi/fsi-master-gpio.c +++ b/drivers/fsi/fsi-master-gpio.c @@ -22,20 +22,23 @@ #define FSI_BREAK_CLOCKS 256 /* Number of clocks to issue break */ #define FSI_POST_BREAK_CLOCKS 16000 /* Number clocks to set up cfam */ #define FSI_INIT_CLOCKS 5000 /* Clock out any old data */ +#define FSI_GPIO_DPOLL_CLOCKS 50 /* < 21 will cause slave to hang */ +#define FSI_GPIO_EPOLL_CLOCKS 50 /* Number of clocks for E_POLL retry */ #define FSI_GPIO_STD_DELAY 10 /* Standard GPIO delay in nS */ /* todo: adjust down as low as */ /* possible or eliminate */ +#define FSI_CRC_ERR_RETRIES 10 + #define FSI_GPIO_CMD_DPOLL 0x2 +#define FSI_GPIO_CMD_EPOLL 0x3 #define FSI_GPIO_CMD_TERM 0x3f #define FSI_GPIO_CMD_ABS_AR 0x4 #define FSI_GPIO_CMD_REL_AR 0x5 #define FSI_GPIO_CMD_SAME_AR 0x3 /* but only a 2-bit opcode... */ - -#define FSI_GPIO_DPOLL_CLOCKS 50 /* < 21 will cause slave to hang */ - -/* Bus errors */ -#define FSI_GPIO_ERR_BUSY 1 /* Slave stuck in busy state */ +/* Slave responses */ +#define FSI_GPIO_RESP_ACK 0 /* Success */ +#define FSI_GPIO_RESP_BUSY 1 /* Slave busy */ #define FSI_GPIO_RESP_ERRA 2 /* Any (misc) Error */ #define FSI_GPIO_RESP_ERRC 3 /* Slave reports master CRC error */ #define FSI_GPIO_MTOE 4 /* Master time out error */ @@ -330,6 +333,16 @@ static void build_dpoll_command(struct fsi_gpio_msg *cmd, uint8_t slave_id) msg_push_crc(cmd); } +static void build_epoll_command(struct fsi_gpio_msg *cmd, uint8_t slave_id) +{ + cmd->bits = 0; + cmd->msg = 0; + + msg_push_bits(cmd, slave_id, 2); + msg_push_bits(cmd, FSI_GPIO_CMD_EPOLL, 3); + msg_push_crc(cmd); +} + static void echo_delay(struct fsi_master_gpio *master) { set_sda_output(master, 1); @@ -355,6 +368,12 @@ static void fsi_master_gpio_error(struct fsi_master_gpio *master, int error) } +/* + * Note: callers rely specifically on this returning -EAGAIN for + * a CRC error detected in the response. Use other error code + * for other situations. It will be converted to something else + * higher up the stack before it reaches userspace. + */ static int read_one_response(struct fsi_master_gpio *master, uint8_t data_size, struct fsi_gpio_msg *msgp, uint8_t *tagp) { @@ -379,7 +398,7 @@ static int read_one_response(struct fsi_master_gpio *master, "Master time out waiting for response\n"); fsi_master_gpio_error(master, FSI_GPIO_MTOE); spin_unlock_irqrestore(&master->bit_lock, flags); - return -EIO; + return -ETIMEDOUT; } msg.bits = 0; @@ -405,7 +424,7 @@ static int read_one_response(struct fsi_master_gpio *master, if (crc) { dev_dbg(master->dev, "ERR response CRC\n"); fsi_master_gpio_error(master, FSI_GPIO_CRC_INVAL); - return -EIO; + return -EAGAIN; } if (msgp) @@ -451,11 +470,33 @@ static int poll_for_response(struct fsi_master_gpio *master, unsigned long flags; uint8_t tag; uint8_t *data_byte = data; - + int crc_err_retries = 0; retry: rc = read_one_response(master, size, &response, &tag); - if (rc) - return rc; + + /* Handle retries on CRC errors */ + if (rc == -EAGAIN) { + /* Too many retries ? */ + if (crc_err_retries++ > FSI_CRC_ERR_RETRIES) { + /* + * Pass it up as a -EIO otherwise upper level will retry + * the whole command which isn't what we want here. + */ + rc = -EIO; + goto fail; + } + dev_dbg(master->dev, + "CRC error retry %d\n", crc_err_retries); + trace_fsi_master_gpio_crc_rsp_error(master); + build_epoll_command(&cmd, slave); + spin_lock_irqsave(&master->bit_lock, flags); + clock_zeros(master, FSI_GPIO_EPOLL_CLOCKS); + serial_out(master, &cmd); + echo_delay(master); + spin_unlock_irqrestore(&master->bit_lock, flags); + goto retry; + } else if (rc) + goto fail; switch (tag) { case FSI_GPIO_RESP_ACK: @@ -496,18 +537,21 @@ retry: break; case FSI_GPIO_RESP_ERRA: - case FSI_GPIO_RESP_ERRC: - dev_dbg(master->dev, "ERR%c received: 0x%x\n", - tag == FSI_GPIO_RESP_ERRA ? 'A' : 'C', - (int)response.msg); + dev_dbg(master->dev, "ERRA received: 0x%x\n", (int)response.msg); fsi_master_gpio_error(master, response.msg); rc = -EIO; break; + case FSI_GPIO_RESP_ERRC: + dev_dbg(master->dev, "ERRC received: 0x%x\n", (int)response.msg); + fsi_master_gpio_error(master, response.msg); + trace_fsi_master_gpio_crc_cmd_error(master); + rc = -EAGAIN; + break; } if (busy_count > 0) trace_fsi_master_gpio_poll_response_busy(master, busy_count); - + fail: /* Clock the slave enough to be ready for next operation */ spin_lock_irqsave(&master->bit_lock, flags); clock_zeros(master, FSI_GPIO_PRIME_SLAVE_CLOCKS); @@ -536,11 +580,21 @@ static int send_request(struct fsi_master_gpio *master, static int fsi_master_gpio_xfer(struct fsi_master_gpio *master, uint8_t slave, struct fsi_gpio_msg *cmd, size_t resp_len, void *resp) { - int rc; + int rc = -EAGAIN, retries = 0; - rc = send_request(master, cmd); - if (!rc) + while ((retries++) < FSI_CRC_ERR_RETRIES) { + rc = send_request(master, cmd); + if (rc) + break; rc = poll_for_response(master, slave, resp_len, resp); + if (rc != -EAGAIN) + break; + rc = -EIO; + dev_warn(master->dev, "ECRC retry %d\n", retries); + + /* Pace it a bit before retry */ + msleep(1); + } return rc; } diff --git a/include/trace/events/fsi_master_gpio.h b/include/trace/events/fsi_master_gpio.h index 33e928c5acf3..389082132433 100644 --- a/include/trace/events/fsi_master_gpio.h +++ b/include/trace/events/fsi_master_gpio.h @@ -64,6 +64,33 @@ TRACE_EVENT(fsi_master_gpio_break, ) ); +TRACE_EVENT(fsi_master_gpio_crc_cmd_error, + TP_PROTO(const struct fsi_master_gpio *master), + TP_ARGS(master), + TP_STRUCT__entry( + __field(int, master_idx) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + ), + TP_printk("fsi-gpio%d ----CRC command retry---", + __entry->master_idx + ) +); + +TRACE_EVENT(fsi_master_gpio_crc_rsp_error, + TP_PROTO(const struct fsi_master_gpio *master), + TP_ARGS(master), + TP_STRUCT__entry( + __field(int, master_idx) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + ), + TP_printk("fsi-gpio%d ----CRC response---", + __entry->master_idx + ) +); TRACE_EVENT(fsi_master_gpio_poll_response_busy, TP_PROTO(const struct fsi_master_gpio *master, int busy), -- cgit v1.2.3-71-gd317 From 9f4a8a2d7f9d71093f41c4bb0ef8707e8145bad3 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 17 May 2018 15:58:00 +1000 Subject: fsi/sbefifo: Add driver for the SBE FIFO This driver provides an in-kernel and a user API for accessing the command FIFO of the SBE (Self Boot Engine) of the POWER9 processor, via the FSI bus. It provides an in-kernel interface to submit command and receive responses, along with a helper to locate and analyse the response status block. It's a simple synchronous submit() type API. The user interface uses the write/read interface that an earlier version of this driver already provided, however it has some specific limitations in order to keep the driver simple and avoid using up a lot of kernel memory: - The user should perform a single write() with the command and a single read() to get the response (with a buffer big enough to hold the entire response). - On a write() the command is simply "stored" into a kernel buffer, it is submitted as one operation on the subsequent read(). This allows to have the code write directly from the FIFO into the user buffer and avoid hogging the SBE between the write() and read() syscall as it's critical that the SBE be freed asap to respond to the host. An extra write() will simply replace the previously written command. - A write of a single 4 bytes containing the value 0x52534554 in big endian will trigger a reset request. No read is necessary, the write() call will return when the reset has been acknowledged or times out. - The command is limited to 4K bytes. Signed-off-by: Benjamin Herrenschmidt Tested-by: Joel Stanley --- --- drivers/fsi/Kconfig | 7 + drivers/fsi/Makefile | 1 + drivers/fsi/fsi-sbefifo.c | 1005 +++++++++++++++++++++++++++++++++++++++++++ include/linux/fsi-sbefifo.h | 33 ++ 4 files changed, 1046 insertions(+) create mode 100644 drivers/fsi/fsi-sbefifo.c create mode 100644 include/linux/fsi-sbefifo.h (limited to 'include') diff --git a/drivers/fsi/Kconfig b/drivers/fsi/Kconfig index a326ed663d3c..24f84a96b8b9 100644 --- a/drivers/fsi/Kconfig +++ b/drivers/fsi/Kconfig @@ -32,4 +32,11 @@ config FSI_SCOM ---help--- This option enables an FSI based SCOM device driver. +config FSI_SBEFIFO + tristate "SBEFIFO FSI client device driver" + ---help--- + This option enables an FSI based SBEFIFO device driver. The SBEFIFO is + a pipe-like FSI device for communicating with the self boot engine + (SBE) on POWER processors. + endif diff --git a/drivers/fsi/Makefile b/drivers/fsi/Makefile index 65eb99dfafdb..851182e1cd9e 100644 --- a/drivers/fsi/Makefile +++ b/drivers/fsi/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_FSI) += fsi-core.o obj-$(CONFIG_FSI_MASTER_HUB) += fsi-master-hub.o obj-$(CONFIG_FSI_MASTER_GPIO) += fsi-master-gpio.o obj-$(CONFIG_FSI_SCOM) += fsi-scom.o +obj-$(CONFIG_FSI_SBEFIFO) += fsi-sbefifo.o diff --git a/drivers/fsi/fsi-sbefifo.c b/drivers/fsi/fsi-sbefifo.c new file mode 100644 index 000000000000..9b8b6b346af6 --- /dev/null +++ b/drivers/fsi/fsi-sbefifo.c @@ -0,0 +1,1005 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) IBM Corporation 2017 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERGCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The SBEFIFO is a pipe-like FSI device for communicating with + * the self boot engine on POWER processors. + */ + +#define DEVICE_NAME "sbefifo" +#define FSI_ENGID_SBE 0x22 + +/* + * Register layout + */ + +/* Register banks */ +#define SBEFIFO_UP 0x00 /* FSI -> Host */ +#define SBEFIFO_DOWN 0x40 /* Host -> FSI */ + +/* Per-bank registers */ +#define SBEFIFO_FIFO 0x00 /* The FIFO itself */ +#define SBEFIFO_STS 0x04 /* Status register */ +#define SBEFIFO_STS_PARITY_ERR 0x20000000 +#define SBEFIFO_STS_RESET_REQ 0x02000000 +#define SBEFIFO_STS_GOT_EOT 0x00800000 +#define SBEFIFO_STS_MAX_XFER_LIMIT 0x00400000 +#define SBEFIFO_STS_FULL 0x00200000 +#define SBEFIFO_STS_EMPTY 0x00100000 +#define SBEFIFO_STS_ECNT_MASK 0x000f0000 +#define SBEFIFO_STS_ECNT_SHIFT 16 +#define SBEFIFO_STS_VALID_MASK 0x0000ff00 +#define SBEFIFO_STS_VALID_SHIFT 8 +#define SBEFIFO_STS_EOT_MASK 0x000000ff +#define SBEFIFO_STS_EOT_SHIFT 0 +#define SBEFIFO_EOT_RAISE 0x08 /* (Up only) Set End Of Transfer */ +#define SBEFIFO_REQ_RESET 0x0C /* (Up only) Reset Request */ +#define SBEFIFO_PERFORM_RESET 0x10 /* (Down only) Perform Reset */ +#define SBEFIFO_EOT_ACK 0x14 /* (Down only) Acknowledge EOT */ +#define SBEFIFO_DOWN_MAX 0x18 /* (Down only) Max transfer */ + +/* CFAM GP Mailbox SelfBoot Message register */ +#define CFAM_GP_MBOX_SBM_ADDR 0x2824 /* Converted 0x2809 */ + +#define CFAM_SBM_SBE_BOOTED 0x80000000 +#define CFAM_SBM_SBE_ASYNC_FFDC 0x40000000 +#define CFAM_SBM_SBE_STATE_MASK 0x00f00000 +#define CFAM_SBM_SBE_STATE_SHIFT 20 + +enum sbe_state +{ + SBE_STATE_UNKNOWN = 0x0, // Unkown, initial state + SBE_STATE_IPLING = 0x1, // IPL'ing - autonomous mode (transient) + SBE_STATE_ISTEP = 0x2, // ISTEP - Running IPL by steps (transient) + SBE_STATE_MPIPL = 0x3, // MPIPL + SBE_STATE_RUNTIME = 0x4, // SBE Runtime + SBE_STATE_DMT = 0x5, // Dead Man Timer State (transient) + SBE_STATE_DUMP = 0x6, // Dumping + SBE_STATE_FAILURE = 0x7, // Internal SBE failure + SBE_STATE_QUIESCE = 0x8, // Final state - needs SBE reset to get out +}; + +/* FIFO depth */ +#define SBEFIFO_FIFO_DEPTH 8 + +/* Helpers */ +#define sbefifo_empty(sts) ((sts) & SBEFIFO_STS_EMPTY) +#define sbefifo_full(sts) ((sts) & SBEFIFO_STS_FULL) +#define sbefifo_parity_err(sts) ((sts) & SBEFIFO_STS_PARITY_ERR) +#define sbefifo_populated(sts) (((sts) & SBEFIFO_STS_ECNT_MASK) >> SBEFIFO_STS_ECNT_SHIFT) +#define sbefifo_vacant(sts) (SBEFIFO_FIFO_DEPTH - sbefifo_populated(sts)) +#define sbefifo_eot_set(sts) (((sts) & SBEFIFO_STS_EOT_MASK) >> SBEFIFO_STS_EOT_SHIFT) + +/* Reset request timeout in ms */ +#define SBEFIFO_RESET_TIMEOUT 10000 + +/* Timeouts for commands in ms */ +#define SBEFIFO_TIMEOUT_START_CMD 10000 +#define SBEFIFO_TIMEOUT_IN_CMD 1000 +#define SBEFIFO_TIMEOUT_START_RSP 10000 +#define SBEFIFO_TIMEOUT_IN_RSP 1000 + +/* Other constants */ +#define SBEFIFO_MAX_CMD_LEN PAGE_SIZE +#define SBEFIFO_RESET_MAGIC 0x52534554 /* "RSET" */ + +struct sbefifo { + uint32_t magic; +#define SBEFIFO_MAGIC 0x53424546 /* "SBEF" */ + struct fsi_device *fsi_dev; + struct miscdevice mdev; + struct mutex lock; + char name[32]; + int idx; + bool broken; + bool async_ffdc; +}; + +struct sbefifo_user { + struct sbefifo *sbefifo; + struct mutex file_lock; + void *pending_cmd; + size_t pending_len; +}; + +static DEFINE_IDA(sbefifo_ida); +static DEFINE_MUTEX(sbefifo_ffdc_mutex); + + +static void sbefifo_dump_ffdc(struct device *dev, const __be32 *ffdc, + size_t ffdc_sz, bool internal) +{ + int pack = 0; +#define FFDC_LSIZE 60 + static char ffdc_line[FFDC_LSIZE]; + char *p = ffdc_line; + + mutex_lock(&sbefifo_ffdc_mutex); + while (ffdc_sz) { + u32 w0, w1, w2, i; + if (ffdc_sz < 3) { + dev_err(dev, "SBE invalid FFDC package size %zd\n", ffdc_sz); + return; + } + w0 = be32_to_cpu(*(ffdc++)); + w1 = be32_to_cpu(*(ffdc++)); + w2 = be32_to_cpu(*(ffdc++)); + ffdc_sz -= 3; + if ((w0 >> 16) != 0xFFDC) { + dev_err(dev, "SBE invalid FFDC package signature %08x %08x %08x\n", + w0, w1, w2); + break; + } + w0 &= 0xffff; + if (w0 > ffdc_sz) { + dev_err(dev, "SBE FFDC package len %d words but only %zd remaining\n", + w0, ffdc_sz); + w0 = ffdc_sz; + break; + } + if (internal) { + dev_warn(dev, "+---- SBE FFDC package %d for async err -----+\n", + pack++); + } else { + dev_warn(dev, "+---- SBE FFDC package %d for cmd %02x:%02x -----+\n", + pack++, (w1 >> 8) & 0xff, w1 & 0xff); + } + dev_warn(dev, "| Response code: %08x |\n", w2); + dev_warn(dev, "|-------------------------------------------|\n"); + for (i = 0; i < w0; i++) { + if ((i & 3) == 0) { + p = ffdc_line; + p += sprintf(p, "| %04x:", i << 4); + } + p += sprintf(p, " %08x", be32_to_cpu(*(ffdc++))); + ffdc_sz--; + if ((i & 3) == 3 || i == (w0 - 1)) { + while ((i & 3) < 3) { + p += sprintf(p, " "); + i++; + } + dev_warn(dev, "%s |\n", ffdc_line); + } + } + dev_warn(dev, "+-------------------------------------------+\n"); + } +} + +int sbefifo_parse_status(struct device *dev, u16 cmd, __be32 *response, + size_t resp_len, size_t *data_len) +{ + u32 dh, s0, s1; + size_t ffdc_sz; + + if (resp_len < 3) { + pr_debug("sbefifo: cmd %04x, response too small: %zd\n", + cmd, resp_len); + return -ENXIO; + } + dh = be32_to_cpu(response[resp_len - 1]); + if (dh > resp_len || dh < 3) { + dev_err(dev, "SBE cmd %02x:%02x status offset out of range: %d/%zd\n", + cmd >> 8, cmd & 0xff, dh, resp_len); + return -ENXIO; + } + s0 = be32_to_cpu(response[resp_len - dh]); + s1 = be32_to_cpu(response[resp_len - dh + 1]); + if (((s0 >> 16) != 0xC0DE) || ((s0 & 0xffff) != cmd)) { + dev_err(dev, "SBE cmd %02x:%02x, status signature invalid: 0x%08x 0x%08x\n", + cmd >> 8, cmd & 0xff, s0, s1); + return -ENXIO; + } + if (s1 != 0) { + ffdc_sz = dh - 3; + dev_warn(dev, "SBE error cmd %02x:%02x status=%04x:%04x\n", + cmd >> 8, cmd & 0xff, s1 >> 16, s1 & 0xffff); + if (ffdc_sz) + sbefifo_dump_ffdc(dev, &response[resp_len - dh + 2], + ffdc_sz, false); + } + if (data_len) + *data_len = resp_len - dh; + + /* + * Primary status don't have the top bit set, so can't be confused with + * Linux negative error codes, so return the status word whole. + */ + return s1; +} +EXPORT_SYMBOL_GPL(sbefifo_parse_status); + +static int sbefifo_regr(struct sbefifo *sbefifo, int reg, u32 *word) +{ + __be32 raw_word; + int rc; + + rc = fsi_device_read(sbefifo->fsi_dev, reg, &raw_word, + sizeof(raw_word)); + if (rc) + return rc; + + *word = be32_to_cpu(raw_word); + + return 0; +} + +static int sbefifo_regw(struct sbefifo *sbefifo, int reg, u32 word) +{ + __be32 raw_word = cpu_to_be32(word); + + return fsi_device_write(sbefifo->fsi_dev, reg, &raw_word, + sizeof(raw_word)); +} + +static int sbefifo_check_sbe_state(struct sbefifo *sbefifo) +{ + __be32 raw_word; + u32 sbm; + int rc; + + rc = fsi_slave_read(sbefifo->fsi_dev->slave, CFAM_GP_MBOX_SBM_ADDR, + &raw_word, sizeof(raw_word)); + if (rc) + return rc; + sbm = be32_to_cpu(raw_word); + + /* SBE booted at all ? */ + if (!(sbm & CFAM_SBM_SBE_BOOTED)) + return -ESHUTDOWN; + + /* Check its state */ + switch ((sbm & CFAM_SBM_SBE_STATE_MASK) >> CFAM_SBM_SBE_STATE_SHIFT) { + case SBE_STATE_UNKNOWN: + return -ESHUTDOWN; + case SBE_STATE_IPLING: + case SBE_STATE_ISTEP: + case SBE_STATE_MPIPL: + case SBE_STATE_DMT: + return -EBUSY; + case SBE_STATE_RUNTIME: + case SBE_STATE_DUMP: /* Not sure about that one */ + break; + case SBE_STATE_FAILURE: + case SBE_STATE_QUIESCE: + return -ESHUTDOWN; + } + + /* Is there async FFDC available ? Remember it */ + if (sbm & CFAM_SBM_SBE_ASYNC_FFDC) + sbefifo->async_ffdc = true; + + return 0; +} + +/* Don't flip endianness of data to/from FIFO, just pass through. */ +static int sbefifo_down_read(struct sbefifo *sbefifo, __be32 *word) +{ + return fsi_device_read(sbefifo->fsi_dev, SBEFIFO_DOWN, word, + sizeof(*word)); +} + +static int sbefifo_up_write(struct sbefifo *sbefifo, __be32 word) +{ + return fsi_device_write(sbefifo->fsi_dev, SBEFIFO_UP, &word, + sizeof(word)); +} + +static int sbefifo_request_reset(struct sbefifo *sbefifo) +{ + struct device *dev = &sbefifo->fsi_dev->dev; + u32 status, timeout; + int rc; + + dev_dbg(dev, "Requesting FIFO reset\n"); + + /* Mark broken first, will be cleared if reset succeeds */ + sbefifo->broken = true; + + /* Send reset request */ + rc = sbefifo_regw(sbefifo, SBEFIFO_UP | SBEFIFO_REQ_RESET, 1); + if (rc) { + dev_err(dev, "Sending reset request failed, rc=%d\n", rc); + return rc; + } + + /* Wait for it to complete */ + for (timeout = 0; timeout < SBEFIFO_RESET_TIMEOUT; timeout++) { + rc = sbefifo_regr(sbefifo, SBEFIFO_UP | SBEFIFO_STS, &status); + if (rc) { + dev_err(dev, "Failed to read UP fifo status during reset" + " , rc=%d\n", rc); + return rc; + } + + if (!(status & SBEFIFO_STS_RESET_REQ)) { + dev_dbg(dev, "FIFO reset done\n"); + sbefifo->broken = false; + return 0; + } + + msleep(1); + } + dev_err(dev, "FIFO reset timed out\n"); + + return -ETIMEDOUT; +} + +static int sbefifo_cleanup_hw(struct sbefifo *sbefifo) +{ + struct device *dev = &sbefifo->fsi_dev->dev; + u32 up_status, down_status; + bool need_reset = false; + int rc; + + rc = sbefifo_check_sbe_state(sbefifo); + if (rc) { + dev_dbg(dev, "SBE state=%d\n", rc); + return rc; + } + + /* If broken, we don't need to look at status, go straight to reset */ + if (sbefifo->broken) + goto do_reset; + + rc = sbefifo_regr(sbefifo, SBEFIFO_UP | SBEFIFO_STS, &up_status); + if (rc) { + dev_err(dev, "Cleanup: Reading UP status failed, rc=%d\n", rc); + + /* Will try reset again on next attempt at using it */ + sbefifo->broken = true; + return rc; + } + + rc = sbefifo_regr(sbefifo, SBEFIFO_DOWN | SBEFIFO_STS, &down_status); + if (rc) { + dev_err(dev, "Cleanup: Reading DOWN status failed, rc=%d\n", rc); + + /* Will try reset again on next attempt at using it */ + sbefifo->broken = true; + return rc; + } + + /* The FIFO already contains a reset request from the SBE ? */ + if (down_status & SBEFIFO_STS_RESET_REQ) { + dev_info(dev, "Cleanup: FIFO reset request set, resetting\n"); + rc = sbefifo_regw(sbefifo, SBEFIFO_UP, SBEFIFO_PERFORM_RESET); + if (rc) { + sbefifo->broken = true; + dev_err(dev, "Cleanup: Reset reg write failed, rc=%d\n", rc); + return rc; + } + sbefifo->broken = false; + return 0; + } + + /* Parity error on either FIFO ? */ + if ((up_status | down_status) & SBEFIFO_STS_PARITY_ERR) + need_reset = true; + + /* Either FIFO not empty ? */ + if (!((up_status & down_status) & SBEFIFO_STS_EMPTY)) + need_reset = true; + + if (!need_reset) + return 0; + + dev_info(dev, "Cleanup: FIFO not clean (up=0x%08x down=0x%08x)\n", + up_status, down_status); + + do_reset: + + /* Mark broken, will be cleared if/when reset succeeds */ + return sbefifo_request_reset(sbefifo); +} + +static int sbefifo_wait(struct sbefifo *sbefifo, bool up, + u32 *status, unsigned long timeout) +{ + struct device *dev = &sbefifo->fsi_dev->dev; + unsigned long end_time; + bool ready = false; + u32 addr, sts = 0; + int rc; + + dev_vdbg(dev, "Wait on %s fifo...\n", up ? "up" : "down"); + + addr = (up ? SBEFIFO_UP : SBEFIFO_DOWN) | SBEFIFO_STS; + + end_time = jiffies + timeout; + while (!time_after(jiffies, end_time)) { + cond_resched(); + rc = sbefifo_regr(sbefifo, addr, &sts); + if (rc < 0) { + dev_err(dev, "FSI error %d reading status register\n", rc); + return rc; + } + if (!up && sbefifo_parity_err(sts)) { + dev_err(dev, "Parity error in DOWN FIFO\n"); + return -ENXIO; + } + ready = !(up ? sbefifo_full(sts) : sbefifo_empty(sts)); + if (ready) + break; + } + if (!ready) { + dev_err(dev, "%s FIFO Timeout ! status=%08x\n", up ? "UP" : "DOWN", sts); + return -ETIMEDOUT; + } + dev_vdbg(dev, "End of wait status: %08x\n", sts); + + *status = sts; + + return 0; +} + +static int sbefifo_send_command(struct sbefifo *sbefifo, + const __be32 *command, size_t cmd_len) +{ + struct device *dev = &sbefifo->fsi_dev->dev; + size_t len, chunk, vacant = 0, remaining = cmd_len; + unsigned long timeout; + u32 status; + int rc; + + dev_vdbg(dev, "sending command (%zd words, cmd=%04x)\n", + cmd_len, be32_to_cpu(command[1])); + + /* As long as there's something to send */ + timeout = msecs_to_jiffies(SBEFIFO_TIMEOUT_START_CMD); + while (remaining) { + /* Wait for room in the FIFO */ + rc = sbefifo_wait(sbefifo, true, &status, timeout); + if (rc < 0) + return rc; + timeout = msecs_to_jiffies(SBEFIFO_TIMEOUT_IN_CMD); + + vacant = sbefifo_vacant(status); + len = chunk = min(vacant, remaining); + + dev_vdbg(dev, " status=%08x vacant=%zd chunk=%zd\n", + status, vacant, chunk); + + /* Write as much as we can */ + while (len--) { + rc = sbefifo_up_write(sbefifo, *(command++)); + if (rc) { + dev_err(dev, "FSI error %d writing UP FIFO\n", rc); + return rc; + } + } + remaining -= chunk; + vacant -= chunk; + } + + /* If there's no room left, wait for some to write EOT */ + if (!vacant) { + rc = sbefifo_wait(sbefifo, true, &status, timeout); + if (rc) + return rc; + } + + /* Send an EOT */ + rc = sbefifo_regw(sbefifo, SBEFIFO_UP | SBEFIFO_EOT_RAISE, 0); + if (rc) + dev_err(dev, "FSI error %d writing EOT\n", rc); + return rc; +} + +static int sbefifo_read_response(struct sbefifo *sbefifo, struct iov_iter *response) +{ + struct device *dev = &sbefifo->fsi_dev->dev; + u32 data, status, eot_set; + unsigned long timeout; + bool overflow = false; + size_t len; + int rc; + + dev_vdbg(dev, "reading response, buflen = %zd\n", iov_iter_count(response)); + + timeout = msecs_to_jiffies(SBEFIFO_TIMEOUT_START_RSP); + for (;;) { + /* Grab FIFO status (this will handle parity errors) */ + rc = sbefifo_wait(sbefifo, false, &status, timeout); + if (rc < 0) + return rc; + timeout = msecs_to_jiffies(SBEFIFO_TIMEOUT_IN_RSP); + + /* Decode status */ + len = sbefifo_populated(status); + eot_set = sbefifo_eot_set(status); + + dev_vdbg(dev, " chunk size %zd eot_set=0x%x\n", len, eot_set); + + /* Go through the chunk */ + while(len--) { + /* Read the data */ + rc = sbefifo_down_read(sbefifo, &data); + if (rc < 0) + return rc; + + /* Was it an EOT ? */ + if (eot_set & 0x80) { + /* + * There should be nothing else in the FIFO, + * if there is, mark broken, this will force + * a reset on next use, but don't fail the + * command. + */ + if (len) { + dev_warn(dev, "FIFO read hit" + " EOT with still %zd data\n", + len); + sbefifo->broken = true; + } + + /* We are done */ + rc = sbefifo_regw(sbefifo, + SBEFIFO_DOWN | SBEFIFO_EOT_ACK, 0); + + /* + * If that write fail, still complete the request but mark + * the fifo as broken for subsequent reset (not much else + * we can do here). + */ + if (rc) { + dev_err(dev, "FSI error %d ack'ing EOT\n", rc); + sbefifo->broken = true; + } + + /* Tell whether we overflowed */ + return overflow ? -EOVERFLOW : 0; + } + + /* Store it if there is room */ + if (iov_iter_count(response) >= sizeof(__be32)) { + if (copy_to_iter(&data, sizeof(__be32), response) < sizeof(__be32)) + return -EFAULT; + } else { + dev_vdbg(dev, "Response overflowed !\n"); + + overflow = true; + } + + /* Next EOT bit */ + eot_set <<= 1; + } + } + /* Shouldn't happen */ + return -EIO; +} + +static int sbefifo_do_command(struct sbefifo *sbefifo, + const __be32 *command, size_t cmd_len, + struct iov_iter *response) +{ + /* Try sending the command */ + int rc = sbefifo_send_command(sbefifo, command, cmd_len); + if (rc) + return rc; + + /* Now, get the response */ + return sbefifo_read_response(sbefifo, response); +} + +static void sbefifo_collect_async_ffdc(struct sbefifo *sbefifo) +{ + struct device *dev = &sbefifo->fsi_dev->dev; + struct iov_iter ffdc_iter; + struct kvec ffdc_iov; + __be32 *ffdc; + size_t ffdc_sz; + u32 cmd[2]; + int rc; + + sbefifo->async_ffdc = false; + ffdc = vmalloc(SBEFIFO_MAX_FFDC_SIZE); + if (!ffdc) { + dev_err(dev, "Failed to allocate SBE FFDC buffer\n"); + return; + } + ffdc_iov.iov_base = ffdc; + ffdc_iov.iov_len = SBEFIFO_MAX_FFDC_SIZE;; + iov_iter_kvec(&ffdc_iter, WRITE | ITER_KVEC, &ffdc_iov, 1, SBEFIFO_MAX_FFDC_SIZE); + cmd[0] = cpu_to_be32(2); + cmd[1] = cpu_to_be32(SBEFIFO_CMD_GET_SBE_FFDC); + rc = sbefifo_do_command(sbefifo, cmd, 2, &ffdc_iter); + if (rc != 0) { + dev_err(dev, "Error %d retrieving SBE FFDC\n", rc); + goto bail; + } + ffdc_sz = SBEFIFO_MAX_FFDC_SIZE - iov_iter_count(&ffdc_iter); + ffdc_sz /= sizeof(__be32); + rc = sbefifo_parse_status(dev, SBEFIFO_CMD_GET_SBE_FFDC, ffdc, + ffdc_sz, &ffdc_sz); + if (rc != 0) { + dev_err(dev, "Error %d decoding SBE FFDC\n", rc); + goto bail; + } + if (ffdc_sz > 0) + sbefifo_dump_ffdc(dev, ffdc, ffdc_sz, true); + bail: + vfree(ffdc); + +} + +static int __sbefifo_submit(struct sbefifo *sbefifo, + const __be32 *command, size_t cmd_len, + struct iov_iter *response) +{ + struct device *dev = &sbefifo->fsi_dev->dev; + int rc; + + if (cmd_len < 2 || be32_to_cpu(command[0]) != cmd_len) { + dev_vdbg(dev, "Invalid command len %zd (header: %d)\n", + cmd_len, be32_to_cpu(command[0])); + return -EINVAL; + } + + /* First ensure the HW is in a clean state */ + rc = sbefifo_cleanup_hw(sbefifo); + if (rc) + return rc; + + /* Look for async FFDC first if any */ + if (sbefifo->async_ffdc) + sbefifo_collect_async_ffdc(sbefifo); + + rc = sbefifo_do_command(sbefifo, command, cmd_len, response); + if (rc != 0 && rc != -EOVERFLOW) + goto fail; + return rc; + fail: + /* + * On failure, attempt a reset. Ignore the result, it will mark + * the fifo broken if the reset fails + */ + sbefifo_request_reset(sbefifo); + + /* Return original error */ + return rc; +} + +/** + * sbefifo_submit() - Submit and SBE fifo command and receive response + * @dev: The sbefifo device + * @command: The raw command data + * @cmd_len: The command size (in 32-bit words) + * @response: The output response buffer + * @resp_len: In: Response buffer size, Out: Response size + * + * This will perform the entire operation. If the reponse buffer + * overflows, returns -EOVERFLOW + */ +int sbefifo_submit(struct device *dev, const __be32 *command, size_t cmd_len, + __be32 *response, size_t *resp_len) +{ + struct sbefifo *sbefifo = dev_get_drvdata(dev); + struct iov_iter resp_iter; + struct kvec resp_iov; + size_t rbytes; + int rc; + + if (!dev || !sbefifo) + return -ENODEV; + if (WARN_ON_ONCE(sbefifo->magic != SBEFIFO_MAGIC)) + return -ENODEV; + if (!resp_len || !command || !response || cmd_len > SBEFIFO_MAX_CMD_LEN) + return -EINVAL; + + /* Prepare iov iterator */ + rbytes = (*resp_len) * sizeof(__be32); + resp_iov.iov_base = response; + resp_iov.iov_len = rbytes; + iov_iter_kvec(&resp_iter, WRITE | ITER_KVEC, &resp_iov, 1, rbytes); + + /* Perform the command */ + mutex_lock(&sbefifo->lock); + rc = __sbefifo_submit(sbefifo, command, cmd_len, &resp_iter); + mutex_unlock(&sbefifo->lock); + + /* Extract the response length */ + rbytes -= iov_iter_count(&resp_iter); + *resp_len = rbytes / sizeof(__be32); + + return rc; +} +EXPORT_SYMBOL_GPL(sbefifo_submit); + +/* + * Char device interface + */ +static int sbefifo_user_open(struct inode *inode, struct file *file) +{ + struct sbefifo *sbefifo = container_of(file->private_data, + struct sbefifo, mdev); + struct sbefifo_user *user; + + user = kzalloc(sizeof(struct sbefifo_user), GFP_KERNEL); + if (!user) + return -ENOMEM; + + file->private_data = user; + user->sbefifo = sbefifo; + user->pending_cmd = (void *)__get_free_page(GFP_KERNEL); + if (!user->pending_cmd) { + kfree(user); + return -ENOMEM; + } + mutex_init(&user->file_lock); + + return 0; +} + +static ssize_t sbefifo_user_read(struct file *file, char __user *buf, + size_t len, loff_t *offset) +{ + struct sbefifo_user *user = file->private_data; + struct sbefifo *sbefifo; + struct iov_iter resp_iter; + struct iovec resp_iov; + size_t cmd_len; + int rc; + + if (!user) + return -EINVAL; + sbefifo = user->sbefifo; + if (len & 3) + return -EINVAL; + + mutex_lock(&user->file_lock); + + /* Cronus relies on -EAGAIN after a short read */ + if (user->pending_len == 0) { + rc = -EAGAIN; + goto bail; + } + if (user->pending_len < 8) { + rc = -EINVAL; + goto bail; + } + cmd_len = user->pending_len >> 2; + + /* Prepare iov iterator */ + resp_iov.iov_base = buf; + resp_iov.iov_len = len; + iov_iter_init(&resp_iter, WRITE, &resp_iov, 1, len); + + /* Perform the command */ + mutex_lock(&sbefifo->lock); + rc = __sbefifo_submit(sbefifo, user->pending_cmd, cmd_len, &resp_iter); + mutex_unlock(&sbefifo->lock); + if (rc < 0) + goto bail; + + /* Extract the response length */ + rc = len - iov_iter_count(&resp_iter); + bail: + user->pending_len = 0; + mutex_unlock(&user->file_lock); + return rc; +} + +static ssize_t sbefifo_user_write(struct file *file, const char __user *buf, + size_t len, loff_t *offset) +{ + struct sbefifo_user *user = file->private_data; + struct sbefifo *sbefifo; + int rc = len; + + if (!user) + return -EINVAL; + sbefifo = user->sbefifo; + if (len > SBEFIFO_MAX_CMD_LEN) + return -EINVAL; + if (len & 3) + return -EINVAL; + + mutex_lock(&user->file_lock); + + /* Copy the command into the staging buffer */ + if (copy_from_user(user->pending_cmd, buf, len)) { + rc = -EFAULT; + goto bail; + } + + /* Check for the magic reset command */ + if (len == 4 && be32_to_cpu(*(__be32 *)user->pending_cmd) == + SBEFIFO_RESET_MAGIC) { + + /* Clear out any pending command */ + user->pending_len = 0; + + /* Trigger reset request */ + mutex_lock(&sbefifo->lock); + rc = sbefifo_request_reset(user->sbefifo); + mutex_unlock(&sbefifo->lock); + if (rc == 0) + rc = 4; + goto bail; + } + + /* Update the staging buffer size */ + user->pending_len = len; + bail: + mutex_unlock(&user->file_lock); + + /* And that's it, we'll issue the command on a read */ + return rc; +} + +static int sbefifo_user_release(struct inode *inode, struct file *file) +{ + struct sbefifo_user *user = file->private_data; + + if (!user) + return -EINVAL; + + free_page((unsigned long)user->pending_cmd); + kfree(user); + + return 0; +} + +static const struct file_operations sbefifo_fops = { + .owner = THIS_MODULE, + .open = sbefifo_user_open, + .read = sbefifo_user_read, + .write = sbefifo_user_write, + .release = sbefifo_user_release, +}; + +/* + * Probe/remove + */ + +static int sbefifo_probe(struct device *dev) +{ + struct fsi_device *fsi_dev = to_fsi_dev(dev); + struct sbefifo *sbefifo; + struct device_node *np; + struct platform_device *child; + char child_name[32]; + int rc, child_idx = 0; + + dev_dbg(dev, "Found sbefifo device\n"); + + sbefifo = devm_kzalloc(dev, sizeof(*sbefifo), GFP_KERNEL); + if (!sbefifo) + return -ENOMEM; + sbefifo->magic = SBEFIFO_MAGIC; + sbefifo->fsi_dev = fsi_dev; + mutex_init(&sbefifo->lock); + + /* + * Try cleaning up the FIFO. If this fails, we still register the + * driver and will try cleaning things up again on the next access. + */ + rc = sbefifo_cleanup_hw(sbefifo); + if (rc && rc != -ESHUTDOWN) + dev_err(dev, "Initial HW cleanup failed, will retry later\n"); + + sbefifo->idx = ida_simple_get(&sbefifo_ida, 1, INT_MAX, GFP_KERNEL); + snprintf(sbefifo->name, sizeof(sbefifo->name), "sbefifo%d", + sbefifo->idx); + + dev_set_drvdata(dev, sbefifo); + + /* Create misc chardev for userspace access */ + sbefifo->mdev.minor = MISC_DYNAMIC_MINOR; + sbefifo->mdev.fops = &sbefifo_fops; + sbefifo->mdev.name = sbefifo->name; + sbefifo->mdev.parent = dev; + rc = misc_register(&sbefifo->mdev); + if (rc) { + dev_err(dev, "Failed to register miscdevice: %d\n", rc); + ida_simple_remove(&sbefifo_ida, sbefifo->idx); + return rc; + } + + /* Create platform devs for dts child nodes (occ, etc) */ + for_each_available_child_of_node(dev->of_node, np) { + snprintf(child_name, sizeof(child_name), "%s-dev%d", + sbefifo->name, child_idx++); + child = of_platform_device_create(np, child_name, dev); + if (!child) + dev_warn(dev, "failed to create child %s dev\n", + child_name); + } + + return 0; +} + +static int sbefifo_unregister_child(struct device *dev, void *data) +{ + struct platform_device *child = to_platform_device(dev); + + of_device_unregister(child); + if (dev->of_node) + of_node_clear_flag(dev->of_node, OF_POPULATED); + + return 0; +} + +static int sbefifo_remove(struct device *dev) +{ + struct sbefifo *sbefifo = dev_get_drvdata(dev); + + dev_dbg(dev, "Removing sbefifo device...\n"); + + misc_deregister(&sbefifo->mdev); + device_for_each_child(dev, NULL, sbefifo_unregister_child); + + ida_simple_remove(&sbefifo_ida, sbefifo->idx); + + return 0; +} + +static struct fsi_device_id sbefifo_ids[] = { + { + .engine_type = FSI_ENGID_SBE, + .version = FSI_VERSION_ANY, + }, + { 0 } +}; + +static struct fsi_driver sbefifo_drv = { + .id_table = sbefifo_ids, + .drv = { + .name = DEVICE_NAME, + .bus = &fsi_bus_type, + .probe = sbefifo_probe, + .remove = sbefifo_remove, + } +}; + +static int sbefifo_init(void) +{ + return fsi_driver_register(&sbefifo_drv); +} + +static void sbefifo_exit(void) +{ + fsi_driver_unregister(&sbefifo_drv); + + ida_destroy(&sbefifo_ida); +} + +module_init(sbefifo_init); +module_exit(sbefifo_exit); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Brad Bishop "); +MODULE_AUTHOR("Eddie James "); +MODULE_AUTHOR("Andrew Jeffery "); +MODULE_AUTHOR("Benjamin Herrenschmidt "); +MODULE_DESCRIPTION("Linux device interface to the POWER Self Boot Engine"); diff --git a/include/linux/fsi-sbefifo.h b/include/linux/fsi-sbefifo.h new file mode 100644 index 000000000000..13f9ebeaa25e --- /dev/null +++ b/include/linux/fsi-sbefifo.h @@ -0,0 +1,33 @@ +/* + * SBEFIFO FSI Client device driver + * + * Copyright (C) IBM Corporation 2017 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERGCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef LINUX_FSI_SBEFIFO_H +#define LINUX_FSI_SBEFIFO_H + +#define SBEFIFO_CMD_PUT_OCC_SRAM 0xa404 +#define SBEFIFO_CMD_GET_OCC_SRAM 0xa403 +#define SBEFIFO_CMD_GET_SBE_FFDC 0xa801 + +#define SBEFIFO_MAX_FFDC_SIZE 0x2000 + +struct device; + +int sbefifo_submit(struct device *dev, const __be32 *command, size_t cmd_len, + __be32 *response, size_t *resp_len); + +int sbefifo_parse_status(struct device *dev, u16 cmd, __be32 *response, + size_t resp_len, size_t *data_len); + +#endif /* LINUX_FSI_SBEFIFO_H */ -- cgit v1.2.3-71-gd317 From 6b293258cded9c8ee44cce4081d9170d6d1b5f5d Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 Jun 2018 15:19:11 +1000 Subject: fsi: scom: Major overhaul This was too hard to split ... this adds a number of features to the SCOM user interface: - Support for indirect SCOMs - read()/write() interface now handle errors and retries - New ioctl() "raw" interface for use by debuggers Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Eddie James Reviewed-by: Alistair Popple --- drivers/fsi/fsi-scom.c | 424 +++++++++++++++++++++++++++++++++++++++++++---- include/uapi/linux/fsi.h | 58 +++++++ 2 files changed, 452 insertions(+), 30 deletions(-) create mode 100644 include/uapi/linux/fsi.h (limited to 'include') diff --git a/drivers/fsi/fsi-scom.c b/drivers/fsi/fsi-scom.c index e98573ecdae1..39c74351f1bf 100644 --- a/drivers/fsi/fsi-scom.c +++ b/drivers/fsi/fsi-scom.c @@ -24,6 +24,8 @@ #include #include +#include + #define FSI_ENGID_SCOM 0x5 /* SCOM engine register set */ @@ -41,14 +43,36 @@ /* Status register bits */ #define SCOM_STATUS_ERR_SUMMARY 0x80000000 #define SCOM_STATUS_PROTECTION 0x01000000 +#define SCOM_STATUS_PARITY 0x04000000 #define SCOM_STATUS_PIB_ABORT 0x00100000 #define SCOM_STATUS_PIB_RESP_MASK 0x00007000 #define SCOM_STATUS_PIB_RESP_SHIFT 12 #define SCOM_STATUS_ANY_ERR (SCOM_STATUS_ERR_SUMMARY | \ SCOM_STATUS_PROTECTION | \ + SCOM_STATUS_PARITY | \ SCOM_STATUS_PIB_ABORT | \ SCOM_STATUS_PIB_RESP_MASK) +/* SCOM address encodings */ +#define XSCOM_ADDR_IND_FLAG BIT_ULL(63) +#define XSCOM_ADDR_INF_FORM1 BIT_ULL(60) + +/* SCOM indirect stuff */ +#define XSCOM_ADDR_DIRECT_PART 0x7fffffffull +#define XSCOM_ADDR_INDIRECT_PART 0x000fffff00000000ull +#define XSCOM_DATA_IND_READ BIT_ULL(63) +#define XSCOM_DATA_IND_COMPLETE BIT_ULL(31) +#define XSCOM_DATA_IND_ERR_MASK 0x70000000ull +#define XSCOM_DATA_IND_ERR_SHIFT 28 +#define XSCOM_DATA_IND_DATA 0x0000ffffull +#define XSCOM_DATA_IND_FORM1_DATA 0x000fffffffffffffull +#define XSCOM_ADDR_FORM1_LOW 0x000ffffffffull +#define XSCOM_ADDR_FORM1_HI 0xfff00000000ull +#define XSCOM_ADDR_FORM1_HI_SHIFT 20 + +/* Retries */ +#define SCOM_MAX_RETRIES 100 /* Retries on busy */ +#define SCOM_MAX_IND_RETRIES 10 /* Retries indirect not ready */ struct scom_device { struct list_head link; @@ -56,7 +80,7 @@ struct scom_device { struct miscdevice mdev; struct mutex lock; char name[32]; - int idx; + int idx; }; #define to_scom_dev(x) container_of((x), struct scom_device, mdev) @@ -65,80 +89,304 @@ static struct list_head scom_devices; static DEFINE_IDA(scom_ida); -static int put_scom(struct scom_device *scom_dev, uint64_t value, - uint32_t addr) +static int __put_scom(struct scom_device *scom_dev, uint64_t value, + uint32_t addr, uint32_t *status) { - __be32 data; + __be32 data, raw_status; int rc; - mutex_lock(&scom_dev->lock); - data = cpu_to_be32((value >> 32) & 0xffffffff); rc = fsi_device_write(scom_dev->fsi_dev, SCOM_DATA0_REG, &data, sizeof(uint32_t)); if (rc) - goto bail; + return rc; data = cpu_to_be32(value & 0xffffffff); rc = fsi_device_write(scom_dev->fsi_dev, SCOM_DATA1_REG, &data, sizeof(uint32_t)); if (rc) - goto bail; + return rc; data = cpu_to_be32(SCOM_WRITE_CMD | addr); rc = fsi_device_write(scom_dev->fsi_dev, SCOM_CMD_REG, &data, sizeof(uint32_t)); - bail: - mutex_unlock(&scom_dev->lock); - return rc; + if (rc) + return rc; + rc = fsi_device_read(scom_dev->fsi_dev, SCOM_STATUS_REG, &raw_status, + sizeof(uint32_t)); + if (rc) + return rc; + *status = be32_to_cpu(raw_status); + + return 0; } -static int get_scom(struct scom_device *scom_dev, uint64_t *value, - uint32_t addr) +static int __get_scom(struct scom_device *scom_dev, uint64_t *value, + uint32_t addr, uint32_t *status) { - __be32 result, data; + __be32 data, raw_status; int rc; - mutex_lock(&scom_dev->lock); *value = 0ULL; data = cpu_to_be32(SCOM_READ_CMD | addr); rc = fsi_device_write(scom_dev->fsi_dev, SCOM_CMD_REG, &data, sizeof(uint32_t)); if (rc) - goto bail; + return rc; + rc = fsi_device_read(scom_dev->fsi_dev, SCOM_STATUS_REG, &raw_status, + sizeof(uint32_t)); + if (rc) + return rc; - rc = fsi_device_read(scom_dev->fsi_dev, SCOM_DATA0_REG, &result, + /* + * Read the data registers even on error, so we don't have + * to interpret the status register here. + */ + rc = fsi_device_read(scom_dev->fsi_dev, SCOM_DATA0_REG, &data, sizeof(uint32_t)); if (rc) - goto bail; - - *value |= (uint64_t)be32_to_cpu(result) << 32; - rc = fsi_device_read(scom_dev->fsi_dev, SCOM_DATA1_REG, &result, + return rc; + *value |= (uint64_t)be32_to_cpu(data) << 32; + rc = fsi_device_read(scom_dev->fsi_dev, SCOM_DATA1_REG, &data, sizeof(uint32_t)); if (rc) - goto bail; + return rc; + *value |= be32_to_cpu(data); + *status = be32_to_cpu(raw_status); + + return rc; +} + +static int put_indirect_scom_form0(struct scom_device *scom, uint64_t value, + uint64_t addr, uint32_t *status) +{ + uint64_t ind_data, ind_addr; + int rc, retries, err = 0; + + if (value & ~XSCOM_DATA_IND_DATA) + return -EINVAL; + + ind_addr = addr & XSCOM_ADDR_DIRECT_PART; + ind_data = (addr & XSCOM_ADDR_INDIRECT_PART) | value; + rc = __put_scom(scom, ind_data, ind_addr, status); + if (rc || (*status & SCOM_STATUS_ANY_ERR)) + return rc; + + for (retries = 0; retries < SCOM_MAX_IND_RETRIES; retries++) { + rc = __get_scom(scom, &ind_data, addr, status); + if (rc || (*status & SCOM_STATUS_ANY_ERR)) + return rc; + + err = (ind_data & XSCOM_DATA_IND_ERR_MASK) >> XSCOM_DATA_IND_ERR_SHIFT; + *status = err << SCOM_STATUS_PIB_RESP_SHIFT; + if ((ind_data & XSCOM_DATA_IND_COMPLETE) || (err != SCOM_PIB_BLOCKED)) + return 0; + + msleep(1); + } + return rc; +} + +static int put_indirect_scom_form1(struct scom_device *scom, uint64_t value, + uint64_t addr, uint32_t *status) +{ + uint64_t ind_data, ind_addr; + + if (value & ~XSCOM_DATA_IND_FORM1_DATA) + return -EINVAL; + + ind_addr = addr & XSCOM_ADDR_FORM1_LOW; + ind_data = value | (addr & XSCOM_ADDR_FORM1_HI) << XSCOM_ADDR_FORM1_HI_SHIFT; + return __put_scom(scom, ind_data, ind_addr, status); +} + +static int get_indirect_scom_form0(struct scom_device *scom, uint64_t *value, + uint64_t addr, uint32_t *status) +{ + uint64_t ind_data, ind_addr; + int rc, retries, err = 0; + + ind_addr = addr & XSCOM_ADDR_DIRECT_PART; + ind_data = (addr & XSCOM_ADDR_INDIRECT_PART) | XSCOM_DATA_IND_READ; + rc = __put_scom(scom, ind_data, ind_addr, status); + if (rc || (*status & SCOM_STATUS_ANY_ERR)) + return rc; + + for (retries = 0; retries < SCOM_MAX_IND_RETRIES; retries++) { + rc = __get_scom(scom, &ind_data, addr, status); + if (rc || (*status & SCOM_STATUS_ANY_ERR)) + return rc; + + err = (ind_data & XSCOM_DATA_IND_ERR_MASK) >> XSCOM_DATA_IND_ERR_SHIFT; + *status = err << SCOM_STATUS_PIB_RESP_SHIFT; + *value = ind_data & XSCOM_DATA_IND_DATA; + + if ((ind_data & XSCOM_DATA_IND_COMPLETE) || (err != SCOM_PIB_BLOCKED)) + return 0; + + msleep(1); + } + return rc; +} + +static int raw_put_scom(struct scom_device *scom, uint64_t value, + uint64_t addr, uint32_t *status) +{ + if (addr & XSCOM_ADDR_IND_FLAG) { + if (addr & XSCOM_ADDR_INF_FORM1) + return put_indirect_scom_form1(scom, value, addr, status); + else + return put_indirect_scom_form0(scom, value, addr, status); + } else + return __put_scom(scom, value, addr, status); +} + +static int raw_get_scom(struct scom_device *scom, uint64_t *value, + uint64_t addr, uint32_t *status) +{ + if (addr & XSCOM_ADDR_IND_FLAG) { + if (addr & XSCOM_ADDR_INF_FORM1) + return -ENXIO; + return get_indirect_scom_form0(scom, value, addr, status); + } else + return __get_scom(scom, value, addr, status); +} + +static int handle_fsi2pib_status(struct scom_device *scom, uint32_t status) +{ + uint32_t dummy = -1; + + if (status & SCOM_STATUS_PROTECTION) + return -EPERM; + if (status & SCOM_STATUS_PARITY) { + fsi_device_write(scom->fsi_dev, SCOM_FSI2PIB_RESET_REG, &dummy, + sizeof(uint32_t)); + return -EIO; + } + /* Return -EBUSY on PIB abort to force a retry */ + if (status & SCOM_STATUS_PIB_ABORT) + return -EBUSY; + if (status & SCOM_STATUS_ERR_SUMMARY) { + fsi_device_write(scom->fsi_dev, SCOM_FSI2PIB_RESET_REG, &dummy, + sizeof(uint32_t)); + return -EIO; + } + return 0; +} + +static int handle_pib_status(struct scom_device *scom, uint8_t status) +{ + uint32_t dummy = -1; + + if (status == SCOM_PIB_SUCCESS) + return 0; + if (status == SCOM_PIB_BLOCKED) + return -EBUSY; + + /* Reset the bridge */ + fsi_device_write(scom->fsi_dev, SCOM_FSI2PIB_RESET_REG, &dummy, + sizeof(uint32_t)); + + switch(status) { + case SCOM_PIB_OFFLINE: + return -ENODEV; + case SCOM_PIB_BAD_ADDR: + return -ENXIO; + case SCOM_PIB_TIMEOUT: + return -ETIMEDOUT; + case SCOM_PIB_PARTIAL: + case SCOM_PIB_CLK_ERR: + case SCOM_PIB_PARITY_ERR: + default: + return -EIO; + } +} - *value |= be32_to_cpu(result); - bail: - mutex_unlock(&scom_dev->lock); +static int put_scom(struct scom_device *scom, uint64_t value, + uint64_t addr) +{ + uint32_t status, dummy = -1; + int rc, retries; + + for (retries = 0; retries < SCOM_MAX_RETRIES; retries++) { + rc = raw_put_scom(scom, value, addr, &status); + if (rc) { + /* Try resetting the bridge if FSI fails */ + if (rc != -ENODEV && retries == 0) { + fsi_device_write(scom->fsi_dev, SCOM_FSI2PIB_RESET_REG, + &dummy, sizeof(uint32_t)); + rc = -EBUSY; + } else + return rc; + } else + rc = handle_fsi2pib_status(scom, status); + if (rc && rc != -EBUSY) + break; + if (rc == 0) { + rc = handle_pib_status(scom, + (status & SCOM_STATUS_PIB_RESP_MASK) + >> SCOM_STATUS_PIB_RESP_SHIFT); + if (rc && rc != -EBUSY) + break; + } + if (rc == 0) + break; + msleep(1); + } + return rc; +} + +static int get_scom(struct scom_device *scom, uint64_t *value, + uint64_t addr) +{ + uint32_t status, dummy = -1; + int rc, retries; + + for (retries = 0; retries < SCOM_MAX_RETRIES; retries++) { + rc = raw_get_scom(scom, value, addr, &status); + if (rc) { + /* Try resetting the bridge if FSI fails */ + if (rc != -ENODEV && retries == 0) { + fsi_device_write(scom->fsi_dev, SCOM_FSI2PIB_RESET_REG, + &dummy, sizeof(uint32_t)); + rc = -EBUSY; + } else + return rc; + } else + rc = handle_fsi2pib_status(scom, status); + if (rc && rc != -EBUSY) + break; + if (rc == 0) { + rc = handle_pib_status(scom, + (status & SCOM_STATUS_PIB_RESP_MASK) + >> SCOM_STATUS_PIB_RESP_SHIFT); + if (rc && rc != -EBUSY) + break; + } + if (rc == 0) + break; + msleep(1); + } return rc; } static ssize_t scom_read(struct file *filep, char __user *buf, size_t len, loff_t *offset) { - int rc; struct miscdevice *mdev = (struct miscdevice *)filep->private_data; struct scom_device *scom = to_scom_dev(mdev); struct device *dev = &scom->fsi_dev->dev; uint64_t val; + int rc; if (len != sizeof(uint64_t)) return -EINVAL; + mutex_lock(&scom->lock); rc = get_scom(scom, &val, *offset); + mutex_unlock(&scom->lock); if (rc) { dev_dbg(dev, "get_scom fail:%d\n", rc); return rc; @@ -169,7 +417,9 @@ static ssize_t scom_write(struct file *filep, const char __user *buf, return -EINVAL; } + mutex_lock(&scom->lock); rc = put_scom(scom, val, *offset); + mutex_unlock(&scom->lock); if (rc) { dev_dbg(dev, "put_scom failed with:%d\n", rc); return rc; @@ -193,11 +443,125 @@ static loff_t scom_llseek(struct file *file, loff_t offset, int whence) return offset; } +static void raw_convert_status(struct scom_access *acc, uint32_t status) +{ + acc->pib_status = (status & SCOM_STATUS_PIB_RESP_MASK) >> + SCOM_STATUS_PIB_RESP_SHIFT; + acc->intf_errors = 0; + + if (status & SCOM_STATUS_PROTECTION) + acc->intf_errors |= SCOM_INTF_ERR_PROTECTION; + else if (status & SCOM_STATUS_PARITY) + acc->intf_errors |= SCOM_INTF_ERR_PARITY; + else if (status & SCOM_STATUS_PIB_ABORT) + acc->intf_errors |= SCOM_INTF_ERR_ABORT; + else if (status & SCOM_STATUS_ERR_SUMMARY) + acc->intf_errors |= SCOM_INTF_ERR_UNKNOWN; +} + +static int scom_raw_read(struct scom_device *scom, void __user *argp) +{ + struct scom_access acc; + uint32_t status; + int rc; + + if (copy_from_user(&acc, argp, sizeof(struct scom_access))) + return -EFAULT; + + rc = raw_get_scom(scom, &acc.data, acc.addr, &status); + if (rc) + return rc; + raw_convert_status(&acc, status); + if (copy_to_user(argp, &acc, sizeof(struct scom_access))) + return -EFAULT; + return 0; +} + +static int scom_raw_write(struct scom_device *scom, void __user *argp) +{ + u64 prev_data, mask, data; + struct scom_access acc; + uint32_t status; + int rc; + + if (copy_from_user(&acc, argp, sizeof(struct scom_access))) + return -EFAULT; + + if (acc.mask) { + rc = raw_get_scom(scom, &prev_data, acc.addr, &status); + if (rc) + return rc; + if (status & SCOM_STATUS_ANY_ERR) + goto fail; + mask = acc.mask; + } else { + prev_data = mask = -1ull; + } + data = (prev_data & ~mask) | (acc.data & mask); + rc = raw_put_scom(scom, data, acc.addr, &status); + if (rc) + return rc; + fail: + raw_convert_status(&acc, status); + if (copy_to_user(argp, &acc, sizeof(struct scom_access))) + return -EFAULT; + return 0; +} + +static int scom_reset(struct scom_device *scom, void __user *argp) +{ + uint32_t flags, dummy = -1; + int rc = 0; + + if (get_user(flags, (__u32 __user *)argp)) + return -EFAULT; + if (flags & SCOM_RESET_PIB) + rc = fsi_device_write(scom->fsi_dev, SCOM_PIB_RESET_REG, &dummy, + sizeof(uint32_t)); + if (!rc && (flags & (SCOM_RESET_PIB | SCOM_RESET_INTF))) + rc = fsi_device_write(scom->fsi_dev, SCOM_FSI2PIB_RESET_REG, &dummy, + sizeof(uint32_t)); + return rc; +} + +static int scom_check(struct scom_device *scom, void __user *argp) +{ + /* Still need to find out how to get "protected" */ + return put_user(SCOM_CHECK_SUPPORTED, (__u32 __user *)argp); +} + +static long scom_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + struct miscdevice *mdev = file->private_data; + struct scom_device *scom = to_scom_dev(mdev); + void __user *argp = (void __user *)arg; + int rc = -ENOTTY; + + mutex_lock(&scom->lock); + switch(cmd) { + case FSI_SCOM_CHECK: + rc = scom_check(scom, argp); + break; + case FSI_SCOM_READ: + rc = scom_raw_read(scom, argp); + break; + case FSI_SCOM_WRITE: + rc = scom_raw_write(scom, argp); + break; + case FSI_SCOM_RESET: + rc = scom_reset(scom, argp); + break; + } + mutex_unlock(&scom->lock); + return rc; +} + static const struct file_operations scom_fops = { - .owner = THIS_MODULE, - .llseek = scom_llseek, - .read = scom_read, - .write = scom_write, + .owner = THIS_MODULE, + .llseek = scom_llseek, + .read = scom_read, + .write = scom_write, + .unlocked_ioctl = scom_ioctl, }; static int scom_probe(struct device *dev) diff --git a/include/uapi/linux/fsi.h b/include/uapi/linux/fsi.h new file mode 100644 index 000000000000..da577ecd90e7 --- /dev/null +++ b/include/uapi/linux/fsi.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ +#ifndef _UAPI_LINUX_FSI_H +#define _UAPI_LINUX_FSI_H + +#include +#include + +/* + * /dev/scom "raw" ioctl interface + * + * The driver supports a high level "read/write" interface which + * handles retries and converts the status to Linux error codes, + * however low level tools an debugger need to access the "raw" + * HW status information and interpret it themselves, so this + * ioctl interface is also provided for their use case. + */ + +/* Structure for SCOM read/write */ +struct scom_access { + __u64 addr; /* SCOM address, supports indirect */ + __u64 data; /* SCOM data (in for write, out for read) */ + __u64 mask; /* Data mask for writes */ + __u32 intf_errors; /* Interface error flags */ +#define SCOM_INTF_ERR_PARITY 0x00000001 /* Parity error */ +#define SCOM_INTF_ERR_PROTECTION 0x00000002 /* Blocked by secure boot */ +#define SCOM_INTF_ERR_ABORT 0x00000004 /* PIB reset during access */ +#define SCOM_INTF_ERR_UNKNOWN 0x80000000 /* Unknown error */ + /* + * Note: Any other bit set in intf_errors need to be considered as an + * error. Future implementations may define new error conditions. The + * pib_status below is only valid if intf_errors is 0. + */ + __u8 pib_status; /* 3-bit PIB status */ +#define SCOM_PIB_SUCCESS 0 /* Access successful */ +#define SCOM_PIB_BLOCKED 1 /* PIB blocked, pls retry */ +#define SCOM_PIB_OFFLINE 2 /* Chiplet offline */ +#define SCOM_PIB_PARTIAL 3 /* Partial good */ +#define SCOM_PIB_BAD_ADDR 4 /* Invalid address */ +#define SCOM_PIB_CLK_ERR 5 /* Clock error */ +#define SCOM_PIB_PARITY_ERR 6 /* Parity error on the PIB bus */ +#define SCOM_PIB_TIMEOUT 7 /* Bus timeout */ + __u8 pad; +}; + +/* Flags for SCOM check */ +#define SCOM_CHECK_SUPPORTED 0x00000001 /* Interface supported */ +#define SCOM_CHECK_PROTECTED 0x00000002 /* Interface blocked by secure boot */ + +/* Flags for SCOM reset */ +#define SCOM_RESET_INTF 0x00000001 /* Reset interface */ +#define SCOM_RESET_PIB 0x00000002 /* Reset PIB */ + +#define FSI_SCOM_CHECK _IOR('s', 0x00, __u32) +#define FSI_SCOM_READ _IOWR('s', 0x01, struct scom_access) +#define FSI_SCOM_WRITE _IOWR('s', 0x02, struct scom_access) +#define FSI_SCOM_RESET _IOW('s', 0x03, __u32) + +#endif /* _UAPI_LINUX_FSI_H */ -- cgit v1.2.3-71-gd317 From 2b6a440351436d792b1960822da4b7d6e673f568 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 1 Jun 2018 10:22:52 +0200 Subject: gnss: add GNSS receiver subsystem Add a new subsystem for GNSS (e.g. GPS) receivers. While GNSS receivers are typically accessed using a UART interface they often also support other I/O interfaces such as I2C, SPI and USB, while yet other devices use iomem or even some form of remote-processor messaging (rpmsg). The new GNSS subsystem abstracts the underlying interface and provides a new "gnss" class type, which exposes a character-device interface (e.g. /dev/gnss0) to user space. This allows GNSS receivers to have a representation in the Linux device model, something which is important not least for power management purposes. Note that the character-device interface provides raw access to whatever protocol the receiver is (currently) using, such as NMEA 0183, UBX or SiRF Binary. These protocols are expected to be continued to be handled by user space for the time being, even if some hybrid solutions are also conceivable (e.g. to have kernel drivers issue management commands). This will still allow for better platform integration by allowing GNSS devices and their resources (e.g. regulators and enable-gpios) to be described by firmware and managed by kernel drivers rather than platform-specific scripts and services. While the current interface is kept minimal, it could be extended using IOCTLs, sysfs or uevents as needs and proper abstraction levels are identified and determined (e.g. for device and feature identification). Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- MAINTAINERS | 6 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/gnss/Kconfig | 11 ++ drivers/gnss/Makefile | 7 + drivers/gnss/core.c | 371 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/gnss.h | 66 +++++++++ 7 files changed, 464 insertions(+) create mode 100644 drivers/gnss/Kconfig create mode 100644 drivers/gnss/Makefile create mode 100644 drivers/gnss/core.c create mode 100644 include/linux/gnss.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 6cfd16790add..436e6dcabf34 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6038,6 +6038,12 @@ F: Documentation/isdn/README.gigaset F: drivers/isdn/gigaset/ F: include/uapi/linux/gigaset_dev.h +GNSS SUBSYSTEM +M: Johan Hovold +S: Maintained +F: drivers/gnss/ +F: include/linux/gnss.h + GO7007 MPEG CODEC M: Hans Verkuil L: linux-media@vger.kernel.org diff --git a/drivers/Kconfig b/drivers/Kconfig index 95b9ccc08165..ab4d43923c4d 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -9,6 +9,8 @@ source "drivers/bus/Kconfig" source "drivers/connector/Kconfig" +source "drivers/gnss/Kconfig" + source "drivers/mtd/Kconfig" source "drivers/of/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 24cd47014657..cc9a7c5f7d2c 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -185,3 +185,4 @@ obj-$(CONFIG_TEE) += tee/ obj-$(CONFIG_MULTIPLEXER) += mux/ obj-$(CONFIG_UNISYS_VISORBUS) += visorbus/ obj-$(CONFIG_SIOX) += siox/ +obj-$(CONFIG_GNSS) += gnss/ diff --git a/drivers/gnss/Kconfig b/drivers/gnss/Kconfig new file mode 100644 index 000000000000..103fcc70992e --- /dev/null +++ b/drivers/gnss/Kconfig @@ -0,0 +1,11 @@ +# +# GNSS receiver configuration +# + +menuconfig GNSS + tristate "GNSS receiver support" + ---help--- + Say Y here if you have a GNSS receiver (e.g. a GPS receiver). + + To compile this driver as a module, choose M here: the module will + be called gnss. diff --git a/drivers/gnss/Makefile b/drivers/gnss/Makefile new file mode 100644 index 000000000000..1f7a7baab1d9 --- /dev/null +++ b/drivers/gnss/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the GNSS subsystem. +# + +obj-$(CONFIG_GNSS) += gnss.o +gnss-y := core.o diff --git a/drivers/gnss/core.c b/drivers/gnss/core.c new file mode 100644 index 000000000000..307894ca2725 --- /dev/null +++ b/drivers/gnss/core.c @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GNSS receiver core + * + * Copyright (C) 2018 Johan Hovold + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GNSS_FLAG_HAS_WRITE_RAW BIT(0) + +#define GNSS_MINORS 16 + +static DEFINE_IDA(gnss_minors); +static dev_t gnss_first; + +/* FIFO size must be a power of two */ +#define GNSS_READ_FIFO_SIZE 4096 +#define GNSS_WRITE_BUF_SIZE 1024 + +#define to_gnss_device(d) container_of((d), struct gnss_device, dev) + +static int gnss_open(struct inode *inode, struct file *file) +{ + struct gnss_device *gdev; + int ret = 0; + + gdev = container_of(inode->i_cdev, struct gnss_device, cdev); + + get_device(&gdev->dev); + + nonseekable_open(inode, file); + file->private_data = gdev; + + down_write(&gdev->rwsem); + if (gdev->disconnected) { + ret = -ENODEV; + goto unlock; + } + + if (gdev->count++ == 0) { + ret = gdev->ops->open(gdev); + if (ret) + gdev->count--; + } +unlock: + up_write(&gdev->rwsem); + + if (ret) + put_device(&gdev->dev); + + return ret; +} + +static int gnss_release(struct inode *inode, struct file *file) +{ + struct gnss_device *gdev = file->private_data; + + down_write(&gdev->rwsem); + if (gdev->disconnected) + goto unlock; + + if (--gdev->count == 0) { + gdev->ops->close(gdev); + kfifo_reset(&gdev->read_fifo); + } +unlock: + up_write(&gdev->rwsem); + + put_device(&gdev->dev); + + return 0; +} + +static ssize_t gnss_read(struct file *file, char __user *buf, + size_t count, loff_t *pos) +{ + struct gnss_device *gdev = file->private_data; + unsigned int copied; + int ret; + + mutex_lock(&gdev->read_mutex); + while (kfifo_is_empty(&gdev->read_fifo)) { + mutex_unlock(&gdev->read_mutex); + + if (gdev->disconnected) + return 0; + + if (file->f_flags & O_NONBLOCK) + return -EAGAIN; + + ret = wait_event_interruptible(gdev->read_queue, + gdev->disconnected || + !kfifo_is_empty(&gdev->read_fifo)); + if (ret) + return -ERESTARTSYS; + + mutex_lock(&gdev->read_mutex); + } + + ret = kfifo_to_user(&gdev->read_fifo, buf, count, &copied); + if (ret == 0) + ret = copied; + + mutex_unlock(&gdev->read_mutex); + + return ret; +} + +static ssize_t gnss_write(struct file *file, const char __user *buf, + size_t count, loff_t *pos) +{ + struct gnss_device *gdev = file->private_data; + size_t written = 0; + int ret; + + if (gdev->disconnected) + return -EIO; + + if (!count) + return 0; + + if (!(gdev->flags & GNSS_FLAG_HAS_WRITE_RAW)) + return -EIO; + + /* Ignoring O_NONBLOCK, write_raw() is synchronous. */ + + ret = mutex_lock_interruptible(&gdev->write_mutex); + if (ret) + return -ERESTARTSYS; + + for (;;) { + size_t n = count - written; + + if (n > GNSS_WRITE_BUF_SIZE) + n = GNSS_WRITE_BUF_SIZE; + + if (copy_from_user(gdev->write_buf, buf, n)) { + ret = -EFAULT; + goto out_unlock; + } + + /* + * Assumes write_raw can always accept GNSS_WRITE_BUF_SIZE + * bytes. + * + * FIXME: revisit + */ + down_read(&gdev->rwsem); + if (!gdev->disconnected) + ret = gdev->ops->write_raw(gdev, gdev->write_buf, n); + else + ret = -EIO; + up_read(&gdev->rwsem); + + if (ret < 0) + break; + + written += ret; + buf += ret; + + if (written == count) + break; + } + + if (written) + ret = written; +out_unlock: + mutex_unlock(&gdev->write_mutex); + + return ret; +} + +static __poll_t gnss_poll(struct file *file, poll_table *wait) +{ + struct gnss_device *gdev = file->private_data; + __poll_t mask = 0; + + poll_wait(file, &gdev->read_queue, wait); + + if (!kfifo_is_empty(&gdev->read_fifo)) + mask |= EPOLLIN | EPOLLRDNORM; + if (gdev->disconnected) + mask |= EPOLLHUP; + + return mask; +} + +static const struct file_operations gnss_fops = { + .owner = THIS_MODULE, + .open = gnss_open, + .release = gnss_release, + .read = gnss_read, + .write = gnss_write, + .poll = gnss_poll, + .llseek = no_llseek, +}; + +static struct class *gnss_class; + +static void gnss_device_release(struct device *dev) +{ + struct gnss_device *gdev = to_gnss_device(dev); + + kfree(gdev->write_buf); + kfifo_free(&gdev->read_fifo); + ida_simple_remove(&gnss_minors, gdev->id); + kfree(gdev); +} + +struct gnss_device *gnss_allocate_device(struct device *parent) +{ + struct gnss_device *gdev; + struct device *dev; + int id; + int ret; + + gdev = kzalloc(sizeof(*gdev), GFP_KERNEL); + if (!gdev) + return NULL; + + id = ida_simple_get(&gnss_minors, 0, GNSS_MINORS, GFP_KERNEL); + if (id < 0) { + kfree(gdev); + return ERR_PTR(id); + } + + gdev->id = id; + + dev = &gdev->dev; + device_initialize(dev); + dev->devt = gnss_first + id; + dev->class = gnss_class; + dev->parent = parent; + dev->release = gnss_device_release; + dev_set_drvdata(dev, gdev); + dev_set_name(dev, "gnss%d", id); + + init_rwsem(&gdev->rwsem); + mutex_init(&gdev->read_mutex); + mutex_init(&gdev->write_mutex); + init_waitqueue_head(&gdev->read_queue); + + ret = kfifo_alloc(&gdev->read_fifo, GNSS_READ_FIFO_SIZE, GFP_KERNEL); + if (ret) + goto err_put_device; + + gdev->write_buf = kzalloc(GNSS_WRITE_BUF_SIZE, GFP_KERNEL); + if (!gdev->write_buf) + goto err_put_device; + + cdev_init(&gdev->cdev, &gnss_fops); + gdev->cdev.owner = THIS_MODULE; + + return gdev; + +err_put_device: + put_device(dev); + + return ERR_PTR(-ENOMEM); +} +EXPORT_SYMBOL_GPL(gnss_allocate_device); + +void gnss_put_device(struct gnss_device *gdev) +{ + put_device(&gdev->dev); +} +EXPORT_SYMBOL_GPL(gnss_put_device); + +int gnss_register_device(struct gnss_device *gdev) +{ + int ret; + + /* Set a flag which can be accessed without holding the rwsem. */ + if (gdev->ops->write_raw != NULL) + gdev->flags |= GNSS_FLAG_HAS_WRITE_RAW; + + ret = cdev_device_add(&gdev->cdev, &gdev->dev); + if (ret) { + dev_err(&gdev->dev, "failed to add device: %d\n", ret); + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(gnss_register_device); + +void gnss_deregister_device(struct gnss_device *gdev) +{ + down_write(&gdev->rwsem); + gdev->disconnected = true; + if (gdev->count) { + wake_up_interruptible(&gdev->read_queue); + gdev->ops->close(gdev); + } + up_write(&gdev->rwsem); + + cdev_device_del(&gdev->cdev, &gdev->dev); +} +EXPORT_SYMBOL_GPL(gnss_deregister_device); + +/* + * Caller guarantees serialisation. + * + * Must not be called for a closed device. + */ +int gnss_insert_raw(struct gnss_device *gdev, const unsigned char *buf, + size_t count) +{ + int ret; + + ret = kfifo_in(&gdev->read_fifo, buf, count); + + wake_up_interruptible(&gdev->read_queue); + + return ret; +} +EXPORT_SYMBOL_GPL(gnss_insert_raw); + +static int __init gnss_module_init(void) +{ + int ret; + + ret = alloc_chrdev_region(&gnss_first, 0, GNSS_MINORS, "gnss"); + if (ret < 0) { + pr_err("failed to allocate device numbers: %d\n", ret); + return ret; + } + + gnss_class = class_create(THIS_MODULE, "gnss"); + if (IS_ERR(gnss_class)) { + ret = PTR_ERR(gnss_class); + pr_err("failed to create class: %d\n", ret); + goto err_unregister_chrdev; + } + + pr_info("GNSS driver registered with major %d\n", MAJOR(gnss_first)); + + return 0; + +err_unregister_chrdev: + unregister_chrdev_region(gnss_first, GNSS_MINORS); + + return ret; +} +module_init(gnss_module_init); + +static void __exit gnss_module_exit(void) +{ + class_destroy(gnss_class); + unregister_chrdev_region(gnss_first, GNSS_MINORS); + ida_destroy(&gnss_minors); +} +module_exit(gnss_module_exit); + +MODULE_AUTHOR("Johan Hovold "); +MODULE_DESCRIPTION("GNSS receiver core"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/gnss.h b/include/linux/gnss.h new file mode 100644 index 000000000000..e26aeac1e0e2 --- /dev/null +++ b/include/linux/gnss.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * GNSS receiver support + * + * Copyright (C) 2018 Johan Hovold + */ + +#ifndef _LINUX_GNSS_H +#define _LINUX_GNSS_H + +#include +#include +#include +#include +#include +#include +#include + +struct gnss_device; + +struct gnss_operations { + int (*open)(struct gnss_device *gdev); + void (*close)(struct gnss_device *gdev); + int (*write_raw)(struct gnss_device *gdev, const unsigned char *buf, + size_t count); +}; + +struct gnss_device { + struct device dev; + struct cdev cdev; + int id; + + unsigned long flags; + + struct rw_semaphore rwsem; + const struct gnss_operations *ops; + unsigned int count; + unsigned int disconnected:1; + + struct mutex read_mutex; + struct kfifo read_fifo; + wait_queue_head_t read_queue; + + struct mutex write_mutex; + char *write_buf; +}; + +struct gnss_device *gnss_allocate_device(struct device *parent); +void gnss_put_device(struct gnss_device *gdev); +int gnss_register_device(struct gnss_device *gdev); +void gnss_deregister_device(struct gnss_device *gdev); + +int gnss_insert_raw(struct gnss_device *gdev, const unsigned char *buf, + size_t count); + +static inline void gnss_set_drvdata(struct gnss_device *gdev, void *data) +{ + dev_set_drvdata(&gdev->dev, data); +} + +static inline void *gnss_get_drvdata(struct gnss_device *gdev) +{ + return dev_get_drvdata(&gdev->dev); +} + +#endif /* _LINUX_GNSS_H */ -- cgit v1.2.3-71-gd317 From 10f146639fee5ffaf7cf0081c1af518f7d0c533c Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 1 Jun 2018 10:22:59 +0200 Subject: gnss: add receiver type support Add a "type" device attribute and a "GNSS_TYPE" uevent variable which can be used to determine the type of a GNSS receiver. The currently identified types reflect the protocol(s) supported by a receiver: "NMEA" NMEA 0183 "SiRF" SiRF Binary "UBX" UBX Note that both SiRF and UBX type receivers typically support a subset of NMEA 0183 with vendor extensions (e.g. to allow switching to the vendor protocol). Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- Documentation/ABI/testing/sysfs-class-gnss | 15 +++++++++ MAINTAINERS | 1 + drivers/gnss/core.c | 49 ++++++++++++++++++++++++++++++ drivers/gnss/sirf.c | 1 + drivers/gnss/ubx.c | 2 ++ include/linux/gnss.h | 9 ++++++ 6 files changed, 77 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-class-gnss (limited to 'include') diff --git a/Documentation/ABI/testing/sysfs-class-gnss b/Documentation/ABI/testing/sysfs-class-gnss new file mode 100644 index 000000000000..2467b6900eae --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-gnss @@ -0,0 +1,15 @@ +What: /sys/class/gnss/gnssN/type +Date: May 2018 +KernelVersion: 4.18 +Contact: Johan Hovold +Description: + The GNSS receiver type. The currently identified types reflect + the protocol(s) supported by the receiver: + + "NMEA" NMEA 0183 + "SiRF" SiRF Binary + "UBX" UBX + + Note that also non-"NMEA" type receivers typically support a + subset of NMEA 0183 with vendor extensions (e.g. to allow + switching to a vendor protocol). diff --git a/MAINTAINERS b/MAINTAINERS index f980c6186094..e01d220a6f05 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6041,6 +6041,7 @@ F: include/uapi/linux/gigaset_dev.h GNSS SUBSYSTEM M: Johan Hovold S: Maintained +F: Documentation/ABI/testing/sysfs-class-gnss F: Documentation/devicetree/bindings/gnss/ F: drivers/gnss/ F: include/linux/gnss.h diff --git a/drivers/gnss/core.c b/drivers/gnss/core.c index 307894ca2725..f30ef8338b3a 100644 --- a/drivers/gnss/core.c +++ b/drivers/gnss/core.c @@ -330,6 +330,52 @@ int gnss_insert_raw(struct gnss_device *gdev, const unsigned char *buf, } EXPORT_SYMBOL_GPL(gnss_insert_raw); +static const char * const gnss_type_names[GNSS_TYPE_COUNT] = { + [GNSS_TYPE_NMEA] = "NMEA", + [GNSS_TYPE_SIRF] = "SiRF", + [GNSS_TYPE_UBX] = "UBX", +}; + +static const char *gnss_type_name(struct gnss_device *gdev) +{ + const char *name = NULL; + + if (gdev->type < GNSS_TYPE_COUNT) + name = gnss_type_names[gdev->type]; + + if (!name) + dev_WARN(&gdev->dev, "type name not defined\n"); + + return name; +} + +static ssize_t type_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct gnss_device *gdev = to_gnss_device(dev); + + return sprintf(buf, "%s\n", gnss_type_name(gdev)); +} +static DEVICE_ATTR_RO(type); + +static struct attribute *gnss_attrs[] = { + &dev_attr_type.attr, + NULL, +}; +ATTRIBUTE_GROUPS(gnss); + +static int gnss_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + struct gnss_device *gdev = to_gnss_device(dev); + int ret; + + ret = add_uevent_var(env, "GNSS_TYPE=%s", gnss_type_name(gdev)); + if (ret) + return ret; + + return 0; +} + static int __init gnss_module_init(void) { int ret; @@ -347,6 +393,9 @@ static int __init gnss_module_init(void) goto err_unregister_chrdev; } + gnss_class->dev_groups = gnss_groups; + gnss_class->dev_uevent = gnss_uevent; + pr_info("GNSS driver registered with major %d\n", MAJOR(gnss_first)); return 0; diff --git a/drivers/gnss/sirf.c b/drivers/gnss/sirf.c index 5fb0f730db48..79cb98950013 100644 --- a/drivers/gnss/sirf.c +++ b/drivers/gnss/sirf.c @@ -267,6 +267,7 @@ static int sirf_probe(struct serdev_device *serdev) if (!gdev) return -ENOMEM; + gdev->type = GNSS_TYPE_SIRF; gdev->ops = &sirf_gnss_ops; gnss_set_drvdata(gdev, data); diff --git a/drivers/gnss/ubx.c b/drivers/gnss/ubx.c index ecddfb362a6f..902b6854b7db 100644 --- a/drivers/gnss/ubx.c +++ b/drivers/gnss/ubx.c @@ -77,6 +77,8 @@ static int ubx_probe(struct serdev_device *serdev) gserial->ops = &ubx_gserial_ops; + gserial->gdev->type = GNSS_TYPE_UBX; + data = gnss_serial_get_drvdata(gserial); data->vcc = devm_regulator_get(&serdev->dev, "vcc"); diff --git a/include/linux/gnss.h b/include/linux/gnss.h index e26aeac1e0e2..43546977098c 100644 --- a/include/linux/gnss.h +++ b/include/linux/gnss.h @@ -18,6 +18,14 @@ struct gnss_device; +enum gnss_type { + GNSS_TYPE_NMEA = 0, + GNSS_TYPE_SIRF, + GNSS_TYPE_UBX, + + GNSS_TYPE_COUNT +}; + struct gnss_operations { int (*open)(struct gnss_device *gdev); void (*close)(struct gnss_device *gdev); @@ -30,6 +38,7 @@ struct gnss_device { struct cdev cdev; int id; + enum gnss_type type; unsigned long flags; struct rw_semaphore rwsem; -- cgit v1.2.3-71-gd317 From 71b38245acb05a38d2d861792bdd99cd9f6a0f78 Mon Sep 17 00:00:00 2001 From: Michael Kelley Date: Tue, 5 Jun 2018 13:37:51 -0700 Subject: Drivers: hv: vmbus: Add comments on ring buffer signaling Add comments describing intricacies of Hyper-V ring buffer signaling code. This information is not in Hyper-V public documents, so include here to capture the knowledge for future coders. There are no code changes in this commit. Signed-off-by: Michael Kelley Signed-off-by: K. Y. Srinivasan Signed-off-by: Greg Kroah-Hartman --- drivers/hv/ring_buffer.c | 65 ++++++++++++++++++++++++++++++++++++++++-------- include/linux/hyperv.h | 31 +++++++++++++++++------ 2 files changed, 77 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/drivers/hv/ring_buffer.c b/drivers/hv/ring_buffer.c index be3c8b10b84a..3e90eb91db45 100644 --- a/drivers/hv/ring_buffer.c +++ b/drivers/hv/ring_buffer.c @@ -431,7 +431,24 @@ static u32 hv_pkt_iter_bytes_read(const struct hv_ring_buffer_info *rbi, } /* - * Update host ring buffer after iterating over packets. + * Update host ring buffer after iterating over packets. If the host has + * stopped queuing new entries because it found the ring buffer full, and + * sufficient space is being freed up, signal the host. But be careful to + * only signal the host when necessary, both for performance reasons and + * because Hyper-V protects itself by throttling guests that signal + * inappropriately. + * + * Determining when to signal is tricky. There are three key data inputs + * that must be handled in this order to avoid race conditions: + * + * 1. Update the read_index + * 2. Read the pending_send_sz + * 3. Read the current write_index + * + * The interrupt_mask is not used to determine when to signal. The + * interrupt_mask is used only on the guest->host ring buffer when + * sending requests to the host. The host does not use it on the host-> + * guest ring buffer to indicate whether it should be signaled. */ void hv_pkt_iter_close(struct vmbus_channel *channel) { @@ -447,22 +464,30 @@ void hv_pkt_iter_close(struct vmbus_channel *channel) start_read_index = rbi->ring_buffer->read_index; rbi->ring_buffer->read_index = rbi->priv_read_index; + /* + * Older versions of Hyper-V (before WS2102 and Win8) do not + * implement pending_send_sz and simply poll if the host->guest + * ring buffer is full. No signaling is needed or expected. + */ if (!rbi->ring_buffer->feature_bits.feat_pending_send_sz) return; /* * Issue a full memory barrier before making the signaling decision. - * Here is the reason for having this barrier: - * If the reading of the pend_sz (in this function) - * were to be reordered and read before we commit the new read - * index (in the calling function) we could - * have a problem. If the host were to set the pending_sz after we - * have sampled pending_sz and go to sleep before we commit the + * If reading pending_send_sz were to be reordered and happen + * before we commit the new read_index, a race could occur. If the + * host were to set the pending_send_sz after we have sampled + * pending_send_sz, and the ring buffer blocks before we commit the * read index, we could miss sending the interrupt. Issue a full * memory barrier to address this. */ virt_mb(); + /* + * If the pending_send_sz is zero, then the ring buffer is not + * blocked and there is no need to signal. This is far by the + * most common case, so exit quickly for best performance. + */ pending_sz = READ_ONCE(rbi->ring_buffer->pending_send_sz); if (!pending_sz) return; @@ -476,14 +501,32 @@ void hv_pkt_iter_close(struct vmbus_channel *channel) bytes_read = hv_pkt_iter_bytes_read(rbi, start_read_index); /* - * If there was space before we began iteration, - * then host was not blocked. + * We want to signal the host only if we're transitioning + * from a "not enough free space" state to a "enough free + * space" state. For example, it's possible that this function + * could run and free up enough space to signal the host, and then + * run again and free up additional space before the host has a + * chance to clear the pending_send_sz. The 2nd invocation would + * be a null transition from "enough free space" to "enough free + * space", which doesn't warrant a signal. + * + * Exactly filling the ring buffer is treated as "not enough + * space". The ring buffer always must have at least one byte + * empty so the empty and full conditions are distinguishable. + * hv_get_bytes_to_write() doesn't fully tell the truth in + * this regard. + * + * So first check if we were in the "enough free space" state + * before we began the iteration. If so, the host was not + * blocked, and there's no need to signal. */ - if (curr_write_sz - bytes_read > pending_sz) return; - /* If pending write will not fit, don't give false hope. */ + /* + * Similarly, if the new state is "not enough space", then + * there's no need to signal. + */ if (curr_write_sz <= pending_sz) return; diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h index 3a3012f57be4..2330f08062c7 100644 --- a/include/linux/hyperv.h +++ b/include/linux/hyperv.h @@ -89,18 +89,33 @@ struct hv_ring_buffer { u32 interrupt_mask; /* - * Win8 uses some of the reserved bits to implement - * interrupt driven flow management. On the send side - * we can request that the receiver interrupt the sender - * when the ring transitions from being full to being able - * to handle a message of size "pending_send_sz". + * WS2012/Win8 and later versions of Hyper-V implement interrupt + * driven flow management. The feature bit feat_pending_send_sz + * is set by the host on the host->guest ring buffer, and by the + * guest on the guest->host ring buffer. * - * Add necessary state for this enhancement. + * The meaning of the feature bit is a bit complex in that it has + * semantics that apply to both ring buffers. If the guest sets + * the feature bit in the guest->host ring buffer, the guest is + * telling the host that: + * 1) It will set the pending_send_sz field in the guest->host ring + * buffer when it is waiting for space to become available, and + * 2) It will read the pending_send_sz field in the host->guest + * ring buffer and interrupt the host when it frees enough space + * + * Similarly, if the host sets the feature bit in the host->guest + * ring buffer, the host is telling the guest that: + * 1) It will set the pending_send_sz field in the host->guest ring + * buffer when it is waiting for space to become available, and + * 2) It will read the pending_send_sz field in the guest->host + * ring buffer and interrupt the guest when it frees enough space + * + * If either the guest or host does not set the feature bit that it + * owns, that guest or host must do polling if it encounters a full + * ring buffer, and not signal the other end with an interrupt. */ u32 pending_send_sz; - u32 reserved1[12]; - union { struct { u32 feat_pending_send_sz:1; -- cgit v1.2.3-71-gd317 From e0772de8a48b69d39624cdf99fac8f4a3fcc387b Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 19 Jun 2018 17:12:57 +0100 Subject: slimbus: core: add of_slim_device_get() helper On SLIMBus controllers like Qcom NGD(non ported device), controller can request logical address once the remote side is powered, having a helper function like this to explicitly enumerate the bus is helpful. Also codec drivers which are taking to interface device would need such a helper too. Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- drivers/slimbus/core.c | 39 +++++++++++++++++++++++++++++++++++++++ include/linux/slimbus.h | 2 ++ 2 files changed, 41 insertions(+) (limited to 'include') diff --git a/drivers/slimbus/core.c b/drivers/slimbus/core.c index 7ddfc675b131..88248a4ecad9 100644 --- a/drivers/slimbus/core.c +++ b/drivers/slimbus/core.c @@ -356,6 +356,45 @@ struct slim_device *slim_get_device(struct slim_controller *ctrl, } EXPORT_SYMBOL_GPL(slim_get_device); +static int of_slim_match_dev(struct device *dev, void *data) +{ + struct device_node *np = data; + struct slim_device *sbdev = to_slim_device(dev); + + return (sbdev->dev.of_node == np); +} + +static struct slim_device *of_find_slim_device(struct slim_controller *ctrl, + struct device_node *np) +{ + struct slim_device *sbdev; + struct device *dev; + + dev = device_find_child(ctrl->dev, np, of_slim_match_dev); + if (dev) { + sbdev = to_slim_device(dev); + return sbdev; + } + + return NULL; +} + +/** + * of_slim_get_device() - get handle to a device using dt node. + * + * @ctrl: Controller on which this device will be added/queried + * @np: node pointer to device + * + * Return: pointer to a device if it has already reported. Creates a new + * device and returns pointer to it if the device has not yet enumerated. + */ +struct slim_device *of_slim_get_device(struct slim_controller *ctrl, + struct device_node *np) +{ + return of_find_slim_device(ctrl, np); +} +EXPORT_SYMBOL_GPL(of_slim_get_device); + static int slim_device_alloc_laddr(struct slim_device *sbdev, bool report_present) { diff --git a/include/linux/slimbus.h b/include/linux/slimbus.h index c36cf121d2cd..efa36a852dc3 100644 --- a/include/linux/slimbus.h +++ b/include/linux/slimbus.h @@ -138,6 +138,8 @@ static inline void slim_set_devicedata(struct slim_device *dev, void *data) dev_set_drvdata(&dev->dev, data); } +struct slim_device *of_slim_get_device(struct slim_controller *ctrl, + struct device_node *np); struct slim_device *slim_get_device(struct slim_controller *ctrl, struct slim_eaddr *e_addr); int slim_get_logical_addr(struct slim_device *sbdev); -- cgit v1.2.3-71-gd317 From db455d66b9900a8a81fe474f11c78c8c8a95eefa Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 19 Jun 2018 17:12:58 +0100 Subject: slimbus: core: rearrange slim_eaddr structure Rearrange struct slim_eaddr so that the structure is packed correctly to be able to send in SLIMBus messages. Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- include/linux/slimbus.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/linux/slimbus.h b/include/linux/slimbus.h index efa36a852dc3..63801bcc5e60 100644 --- a/include/linux/slimbus.h +++ b/include/linux/slimbus.h @@ -14,16 +14,16 @@ extern struct bus_type slimbus_bus; /** * struct slim_eaddr - Enumeration address for a SLIMbus device - * @manf_id: Manufacturer Id for the device - * @prod_code: Product code - * @dev_index: Device index * @instance: Instance value + * @dev_index: Device index + * @prod_code: Product code + * @manf_id: Manufacturer Id for the device */ struct slim_eaddr { - u16 manf_id; - u16 prod_code; - u8 dev_index; u8 instance; + u8 dev_index; + u16 prod_code; + u16 manf_id; } __packed; /** -- cgit v1.2.3-71-gd317 From abb9c9b8b51ba53b47ad7685ad2a0a64dbbf7bf5 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 5 Jul 2018 14:54:25 +0100 Subject: slimbus: stream: add stream support This patch adds support to SLIMbus stream apis for slimbus device. SLIMbus streaming involves adding support to Data Channel Management and channel Reconfiguration Messages to slim core plus few stream apis. >From slim device side the apis are very simple mostly inline with other stream apis. Currently it only supports Isochronous and Push/Pull transport protocols, which are sufficient for audio use cases. Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- Documentation/driver-api/slimbus.rst | 5 + drivers/slimbus/Makefile | 2 +- drivers/slimbus/core.c | 2 + drivers/slimbus/slimbus.h | 189 ++++++++++++++ drivers/slimbus/stream.c | 477 +++++++++++++++++++++++++++++++++++ include/linux/slimbus.h | 46 ++++ 6 files changed, 720 insertions(+), 1 deletion(-) create mode 100644 drivers/slimbus/stream.c (limited to 'include') diff --git a/Documentation/driver-api/slimbus.rst b/Documentation/driver-api/slimbus.rst index a97449cf603a..410eec79b2a1 100644 --- a/Documentation/driver-api/slimbus.rst +++ b/Documentation/driver-api/slimbus.rst @@ -125,3 +125,8 @@ Messaging APIs: ~~~~~~~~~~~~~~~ .. kernel-doc:: drivers/slimbus/messaging.c :export: + +Streaming APIs: +~~~~~~~~~~~~~~~ +.. kernel-doc:: drivers/slimbus/stream.c + :export: diff --git a/drivers/slimbus/Makefile b/drivers/slimbus/Makefile index c78c6e16c2df..d9aa011b6804 100644 --- a/drivers/slimbus/Makefile +++ b/drivers/slimbus/Makefile @@ -3,7 +3,7 @@ # Makefile for kernel SLIMbus framework. # obj-$(CONFIG_SLIMBUS) += slimbus.o -slimbus-y := core.o messaging.o sched.o +slimbus-y := core.o messaging.o sched.o stream.o #Controllers obj-$(CONFIG_SLIM_QCOM_CTRL) += slim-qcom-ctrl.o diff --git a/drivers/slimbus/core.c b/drivers/slimbus/core.c index 88248a4ecad9..95b00d28ad6e 100644 --- a/drivers/slimbus/core.c +++ b/drivers/slimbus/core.c @@ -114,6 +114,8 @@ static int slim_add_device(struct slim_controller *ctrl, sbdev->dev.release = slim_dev_release; sbdev->dev.driver = NULL; sbdev->ctrl = ctrl; + INIT_LIST_HEAD(&sbdev->stream_list); + spin_lock_init(&sbdev->stream_list_lock); if (node) sbdev->dev.of_node = of_node_get(node); diff --git a/drivers/slimbus/slimbus.h b/drivers/slimbus/slimbus.h index 63229e8cd050..6dbc2b320704 100644 --- a/drivers/slimbus/slimbus.h +++ b/drivers/slimbus/slimbus.h @@ -45,9 +45,20 @@ #define SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS 0x2 #define SLIM_MSG_MC_REPORT_ABSENT 0xF +/* Data channel management messages */ +#define SLIM_MSG_MC_CONNECT_SOURCE 0x10 +#define SLIM_MSG_MC_CONNECT_SINK 0x11 +#define SLIM_MSG_MC_DISCONNECT_PORT 0x14 +#define SLIM_MSG_MC_CHANGE_CONTENT 0x18 + /* Clock pause Reconfiguration messages */ #define SLIM_MSG_MC_BEGIN_RECONFIGURATION 0x40 #define SLIM_MSG_MC_NEXT_PAUSE_CLOCK 0x4A +#define SLIM_MSG_MC_NEXT_DEFINE_CHANNEL 0x50 +#define SLIM_MSG_MC_NEXT_DEFINE_CONTENT 0x51 +#define SLIM_MSG_MC_NEXT_ACTIVATE_CHANNEL 0x54 +#define SLIM_MSG_MC_NEXT_DEACTIVATE_CHANNEL 0x55 +#define SLIM_MSG_MC_NEXT_REMOVE_CHANNEL 0x58 #define SLIM_MSG_MC_RECONFIGURE_NOW 0x5F /* @@ -69,7 +80,15 @@ /* Standard values per SLIMbus spec needed by controllers and devices */ #define SLIM_MAX_CLK_GEAR 10 #define SLIM_MIN_CLK_GEAR 1 +#define SLIM_SLOT_LEN_BITS 4 + +/* Indicate that the frequency of the flow and the bus frequency are locked */ +#define SLIM_CHANNEL_CONTENT_FL BIT(7) +/* Standard values per SLIMbus spec needed by controllers and devices */ +#define SLIM_CL_PER_SUPERFRAME 6144 +#define SLIM_SLOTS_PER_SUPERFRAME (SLIM_CL_PER_SUPERFRAME >> 2) +#define SLIM_SL_PER_SUPERFRAME (SLIM_CL_PER_SUPERFRAME >> 2) /* Manager's logical address is set to 0xFF per spec */ #define SLIM_LA_MANAGER 0xFF @@ -167,6 +186,170 @@ struct slim_sched { struct mutex m_reconf; }; +/** + * enum slim_port_direction: SLIMbus port direction + * + * @SLIM_PORT_SINK: SLIMbus port is a sink + * @SLIM_PORT_SOURCE: SLIMbus port is a source + */ +enum slim_port_direction { + SLIM_PORT_SINK = 0, + SLIM_PORT_SOURCE, +}; +/** + * enum slim_port_state: SLIMbus Port/Endpoint state machine + * according to SLIMbus Spec 2.0 + * @SLIM_PORT_DISCONNECTED: SLIMbus port is disconnected + * entered from Unconfigure/configured state after + * DISCONNECT_PORT or REMOVE_CHANNEL core command + * @SLIM_PORT_UNCONFIGURED: SLIMbus port is in unconfigured state. + * entered from disconnect state after CONNECT_SOURCE/SINK core command + * @SLIM_PORT_CONFIGURED: SLIMbus port is in configured state. + * entered from unconfigured state after DEFINE_CHANNEL, DEFINE_CONTENT + * and ACTIVATE_CHANNEL core commands. Ready for data transmission. + */ +enum slim_port_state { + SLIM_PORT_DISCONNECTED = 0, + SLIM_PORT_UNCONFIGURED, + SLIM_PORT_CONFIGURED, +}; + +/** + * enum slim_channel_state: SLIMbus channel state machine used by core. + * @SLIM_CH_STATE_DISCONNECTED: SLIMbus channel is disconnected + * @SLIM_CH_STATE_ALLOCATED: SLIMbus channel is allocated + * @SLIM_CH_STATE_ASSOCIATED: SLIMbus channel is associated with port + * @SLIM_CH_STATE_DEFINED: SLIMbus channel parameters are defined + * @SLIM_CH_STATE_CONTENT_DEFINED: SLIMbus channel content is defined + * @SLIM_CH_STATE_ACTIVE: SLIMbus channel is active and ready for data + * @SLIM_CH_STATE_REMOVED: SLIMbus channel is inactive and removed + */ +enum slim_channel_state { + SLIM_CH_STATE_DISCONNECTED = 0, + SLIM_CH_STATE_ALLOCATED, + SLIM_CH_STATE_ASSOCIATED, + SLIM_CH_STATE_DEFINED, + SLIM_CH_STATE_CONTENT_DEFINED, + SLIM_CH_STATE_ACTIVE, + SLIM_CH_STATE_REMOVED, +}; + +/** + * enum slim_ch_data_fmt: SLIMbus channel data Type identifiers according to + * Table 60 of SLIMbus Spec 1.01.01 + * @SLIM_CH_DATA_FMT_NOT_DEFINED: Undefined + * @SLIM_CH_DATA_FMT_LPCM_AUDIO: LPCM audio + * @SLIM_CH_DATA_FMT_IEC61937_COMP_AUDIO: IEC61937 Compressed audio + * @SLIM_CH_DATA_FMT_PACKED_PDM_AUDIO: Packed PDM audio + */ +enum slim_ch_data_fmt { + SLIM_CH_DATA_FMT_NOT_DEFINED = 0, + SLIM_CH_DATA_FMT_LPCM_AUDIO = 1, + SLIM_CH_DATA_FMT_IEC61937_COMP_AUDIO = 2, + SLIM_CH_DATA_FMT_PACKED_PDM_AUDIO = 3, +}; + +/** + * enum slim_ch_aux_fmt: SLIMbus channel Aux Field format IDs according to + * Table 63 of SLIMbus Spec 2.0 + * @SLIM_CH_AUX_FMT_NOT_APPLICABLE: Undefined + * @SLIM_CH_AUX_FMT_ZCUV_TUNNEL_IEC60958: ZCUV for tunneling IEC60958 + * @SLIM_CH_AUX_FMT_USER_DEFINED: User defined + */ +enum slim_ch_aux_bit_fmt { + SLIM_CH_AUX_FMT_NOT_APPLICABLE = 0, + SLIM_CH_AUX_FMT_ZCUV_TUNNEL_IEC60958 = 1, + SLIM_CH_AUX_FMT_USER_DEFINED = 0xF, +}; + +/** + * struct slim_channel - SLIMbus channel, used for state machine + * + * @id: ID of channel + * @prrate: Presense rate of channel from Table 66 of SLIMbus 2.0 Specs + * @seg_dist: segment distribution code from Table 20 of SLIMbus 2.0 Specs + * @data_fmt: Data format of channel. + * @aux_fmt: Aux format for this channel. + * @state: channel state machine + */ +struct slim_channel { + int id; + int prrate; + int seg_dist; + enum slim_ch_data_fmt data_fmt; + enum slim_ch_aux_bit_fmt aux_fmt; + enum slim_channel_state state; +}; + +/** + * struct slim_port - SLIMbus port + * + * @id: Port id + * @direction: Port direction, Source or Sink. + * @state: state machine of port. + * @ch: channel associated with this port. + */ +struct slim_port { + int id; + enum slim_port_direction direction; + enum slim_port_state state; + struct slim_channel ch; +}; + +/** + * enum slim_transport_protocol: SLIMbus Transport protocol list from + * Table 47 of SLIMbus 2.0 specs. + * @SLIM_PROTO_ISO: Isochronous Protocol, no flow control as data rate match + * channel rate flow control embedded in the data. + * @SLIM_PROTO_PUSH: Pushed Protocol, includes flow control, Used to carry + * data whose rate is equal to, or lower than the channel rate. + * @SLIM_PROTO_PULL: Pulled Protocol, similar usage as pushed protocol + * but pull is a unicast. + * @SLIM_PROTO_LOCKED: Locked Protocol + * @SLIM_PROTO_ASYNC_SMPLX: Asynchronous Protocol-Simplex + * @SLIM_PROTO_ASYNC_HALF_DUP: Asynchronous Protocol-Half-duplex + * @SLIM_PROTO_EXT_SMPLX: Extended Asynchronous Protocol-Simplex + * @SLIM_PROTO_EXT_HALF_DUP: Extended Asynchronous Protocol-Half-duplex + */ +enum slim_transport_protocol { + SLIM_PROTO_ISO = 0, + SLIM_PROTO_PUSH, + SLIM_PROTO_PULL, + SLIM_PROTO_LOCKED, + SLIM_PROTO_ASYNC_SMPLX, + SLIM_PROTO_ASYNC_HALF_DUP, + SLIM_PROTO_EXT_SMPLX, + SLIM_PROTO_EXT_HALF_DUP, +}; + +/** + * struct slim_stream_runtime - SLIMbus stream runtime instance + * + * @dev: Name of the stream + * @dev: SLIM Device instance associated with this stream + * @state: state of stream + * @direction: direction of stream + * @prot: Transport protocol used in this stream + * @rate: Data rate of samples * + * @bps: bits per sample + * @ratem: rate multipler which is super frame rate/data rate + * @num_ports: number of ports + * @ports: pointer to instance of ports + * @node: list head for stream associated with slim device. + */ +struct slim_stream_runtime { + const char *name; + struct slim_device *dev; + int direction; + enum slim_transport_protocol prot; + unsigned int rate; + unsigned int bps; + unsigned int ratem; + int num_ports; + struct slim_port *ports; + struct list_head node; +}; + /** * struct slim_controller - Controls every instance of SLIMbus * (similar to 'master' on SPI) @@ -196,6 +379,10 @@ struct slim_sched { * @wakeup: This function pointer implements controller-specific procedure * to wake it up from clock-pause. Framework will call this to bring * the controller out of clock pause. + * @enable_stream: This function pointer implements controller-specific procedure + * to enable a stream. + * @disable_stream: This function pointer implements controller-specific procedure + * to disable stream. * * 'Manager device' is responsible for device management, bandwidth * allocation, channel setup, and port associations per channel. @@ -237,6 +424,8 @@ struct slim_controller { struct slim_eaddr *ea, u8 laddr); int (*get_laddr)(struct slim_controller *ctrl, struct slim_eaddr *ea, u8 *laddr); + int (*enable_stream)(struct slim_stream_runtime *rt); + int (*disable_stream)(struct slim_stream_runtime *rt); int (*wakeup)(struct slim_controller *ctrl); }; diff --git a/drivers/slimbus/stream.c b/drivers/slimbus/stream.c new file mode 100644 index 000000000000..2fa05324ed07 --- /dev/null +++ b/drivers/slimbus/stream.c @@ -0,0 +1,477 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, Linaro Limited + +#include +#include +#include +#include +#include +#include +#include "slimbus.h" + +/** + * struct segdist_code - Segment Distributions code from + * Table 20 of SLIMbus Specs Version 2.0 + * + * @ratem: Channel Rate Multipler(Segments per Superframe) + * @seg_interval: Number of slots between the first Slot of Segment + * and the first slot of the next consecutive Segment. + * @segdist_code: Segment Distribution Code SD[11:0] + * @seg_offset_mask: Segment offset mask in SD[11:0] + * @segdist_codes: List of all possible Segmet Distribution codes. + */ +static const struct segdist_code { + int ratem; + int seg_interval; + int segdist_code; + u32 seg_offset_mask; + +} segdist_codes[] = { + {1, 1536, 0x200, 0xdff}, + {2, 768, 0x100, 0xcff}, + {4, 384, 0x080, 0xc7f}, + {8, 192, 0x040, 0xc3f}, + {16, 96, 0x020, 0xc1f}, + {32, 48, 0x010, 0xc0f}, + {64, 24, 0x008, 0xc07}, + {128, 12, 0x004, 0xc03}, + {256, 6, 0x002, 0xc01}, + {512, 3, 0x001, 0xc00}, + {3, 512, 0xe00, 0x1ff}, + {6, 256, 0xd00, 0x0ff}, + {12, 128, 0xc80, 0x07f}, + {24, 64, 0xc40, 0x03f}, + {48, 32, 0xc20, 0x01f}, + {96, 16, 0xc10, 0x00f}, + {192, 8, 0xc08, 0x007}, + {364, 4, 0xc04, 0x003}, + {768, 2, 0xc02, 0x001}, +}; + +/* + * Presence Rate table for all Natural Frequencies + * The Presence rate of a constant bitrate stream is mean flow rate of the + * stream expressed in occupied Segments of that Data Channel per second. + * Table 66 from SLIMbus 2.0 Specs + * + * Index of the table corresponds to Presence rate code for the respective rate + * in the table. + */ +static const int slim_presence_rate_table[] = { + 0, /* Not Indicated */ + 12000, + 24000, + 48000, + 96000, + 192000, + 384000, + 768000, + 0, /* Reserved */ + 110250, + 220500, + 441000, + 882000, + 176400, + 352800, + 705600, + 4000, + 8000, + 16000, + 32000, + 64000, + 128000, + 256000, + 512000, +}; + +/* + * slim_stream_allocate() - Allocate a new SLIMbus Stream + * @dev:Slim device to be associated with + * @name: name of the stream + * + * This is very first call for SLIMbus streaming, this API will allocate + * a new SLIMbus stream and return a valid stream runtime pointer for client + * to use it in subsequent stream apis. state of stream is set to ALLOCATED + * + * Return: valid pointer on success and error code on failure. + * From ASoC DPCM framework, this state is linked to startup() operation. + */ +struct slim_stream_runtime *slim_stream_allocate(struct slim_device *dev, + const char *name) +{ + struct slim_stream_runtime *rt; + + rt = kzalloc(sizeof(*rt), GFP_KERNEL); + if (!rt) + return ERR_PTR(-ENOMEM); + + rt->name = kasprintf(GFP_KERNEL, "slim-%s", name); + if (!rt->name) { + kfree(rt); + return ERR_PTR(-ENOMEM); + } + + rt->dev = dev; + spin_lock(&dev->stream_list_lock); + list_add_tail(&rt->node, &dev->stream_list); + spin_unlock(&dev->stream_list_lock); + + return rt; +} +EXPORT_SYMBOL_GPL(slim_stream_allocate); + +static int slim_connect_port_channel(struct slim_stream_runtime *stream, + struct slim_port *port) +{ + struct slim_device *sdev = stream->dev; + u8 wbuf[2]; + struct slim_val_inf msg = {0, 2, NULL, wbuf, NULL}; + u8 mc = SLIM_MSG_MC_CONNECT_SOURCE; + DEFINE_SLIM_LDEST_TXN(txn, mc, 6, stream->dev->laddr, &msg); + + if (port->direction == SLIM_PORT_SINK) + txn.mc = SLIM_MSG_MC_CONNECT_SINK; + + wbuf[0] = port->id; + wbuf[1] = port->ch.id; + port->ch.state = SLIM_CH_STATE_ASSOCIATED; + port->state = SLIM_PORT_UNCONFIGURED; + + return slim_do_transfer(sdev->ctrl, &txn); +} + +static int slim_disconnect_port(struct slim_stream_runtime *stream, + struct slim_port *port) +{ + struct slim_device *sdev = stream->dev; + u8 wbuf[1]; + struct slim_val_inf msg = {0, 1, NULL, wbuf, NULL}; + u8 mc = SLIM_MSG_MC_DISCONNECT_PORT; + DEFINE_SLIM_LDEST_TXN(txn, mc, 5, stream->dev->laddr, &msg); + + wbuf[0] = port->id; + port->ch.state = SLIM_CH_STATE_DISCONNECTED; + port->state = SLIM_PORT_DISCONNECTED; + + return slim_do_transfer(sdev->ctrl, &txn); +} + +static int slim_deactivate_remove_channel(struct slim_stream_runtime *stream, + struct slim_port *port) +{ + struct slim_device *sdev = stream->dev; + u8 wbuf[1]; + struct slim_val_inf msg = {0, 1, NULL, wbuf, NULL}; + u8 mc = SLIM_MSG_MC_NEXT_DEACTIVATE_CHANNEL; + DEFINE_SLIM_LDEST_TXN(txn, mc, 5, stream->dev->laddr, &msg); + int ret; + + wbuf[0] = port->ch.id; + ret = slim_do_transfer(sdev->ctrl, &txn); + if (ret) + return ret; + + txn.mc = SLIM_MSG_MC_NEXT_REMOVE_CHANNEL; + port->ch.state = SLIM_CH_STATE_REMOVED; + + return slim_do_transfer(sdev->ctrl, &txn); +} + +static int slim_get_prate_code(int rate) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(slim_presence_rate_table); i++) { + if (rate == slim_presence_rate_table[i]) + return i; + } + + return -EINVAL; +} + +/* + * slim_stream_prepare() - Prepare a SLIMbus Stream + * + * @rt: instance of slim stream runtime to configure + * @cfg: new configuration for the stream + * + * This API will configure SLIMbus stream with config parameters from cfg. + * return zero on success and error code on failure. From ASoC DPCM framework, + * this state is linked to hw_params() operation. + */ +int slim_stream_prepare(struct slim_stream_runtime *rt, + struct slim_stream_config *cfg) +{ + struct slim_controller *ctrl = rt->dev->ctrl; + struct slim_port *port; + int num_ports, i, port_id; + + if (rt->ports) { + dev_err(&rt->dev->dev, "Stream already Prepared\n"); + return -EINVAL; + } + + num_ports = hweight32(cfg->port_mask); + rt->ports = kcalloc(num_ports, sizeof(*port), GFP_KERNEL); + if (!rt->ports) + return -ENOMEM; + + rt->num_ports = num_ports; + rt->rate = cfg->rate; + rt->bps = cfg->bps; + rt->direction = cfg->direction; + + if (cfg->rate % ctrl->a_framer->superfreq) { + /* + * data rate not exactly multiple of super frame, + * use PUSH/PULL protocol + */ + if (cfg->direction == SNDRV_PCM_STREAM_PLAYBACK) + rt->prot = SLIM_PROTO_PUSH; + else + rt->prot = SLIM_PROTO_PULL; + } else { + rt->prot = SLIM_PROTO_ISO; + } + + rt->ratem = cfg->rate/ctrl->a_framer->superfreq; + + i = 0; + for_each_set_bit(port_id, &cfg->port_mask, SLIM_DEVICE_MAX_PORTS) { + port = &rt->ports[i]; + port->state = SLIM_PORT_DISCONNECTED; + port->id = port_id; + port->ch.prrate = slim_get_prate_code(cfg->rate); + port->ch.id = cfg->chs[i]; + port->ch.data_fmt = SLIM_CH_DATA_FMT_NOT_DEFINED; + port->ch.aux_fmt = SLIM_CH_AUX_FMT_NOT_APPLICABLE; + port->ch.state = SLIM_CH_STATE_ALLOCATED; + + if (cfg->direction == SNDRV_PCM_STREAM_PLAYBACK) + port->direction = SLIM_PORT_SINK; + else + port->direction = SLIM_PORT_SOURCE; + + slim_connect_port_channel(rt, port); + i++; + } + + return 0; +} +EXPORT_SYMBOL_GPL(slim_stream_prepare); + +static int slim_define_channel_content(struct slim_stream_runtime *stream, + struct slim_port *port) +{ + struct slim_device *sdev = stream->dev; + u8 wbuf[4]; + struct slim_val_inf msg = {0, 4, NULL, wbuf, NULL}; + u8 mc = SLIM_MSG_MC_NEXT_DEFINE_CONTENT; + DEFINE_SLIM_LDEST_TXN(txn, mc, 8, stream->dev->laddr, &msg); + + wbuf[0] = port->ch.id; + wbuf[1] = port->ch.prrate; + + /* Frequency Locked for ISO Protocol */ + if (stream->prot != SLIM_PROTO_ISO) + wbuf[1] |= SLIM_CHANNEL_CONTENT_FL; + + wbuf[2] = port->ch.data_fmt | (port->ch.aux_fmt << 4); + wbuf[3] = stream->bps/SLIM_SLOT_LEN_BITS; + port->ch.state = SLIM_CH_STATE_CONTENT_DEFINED; + + return slim_do_transfer(sdev->ctrl, &txn); +} + +static int slim_get_segdist_code(int ratem) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(segdist_codes); i++) { + if (segdist_codes[i].ratem == ratem) + return segdist_codes[i].segdist_code; + } + + return -EINVAL; +} + +static int slim_define_channel(struct slim_stream_runtime *stream, + struct slim_port *port) +{ + struct slim_device *sdev = stream->dev; + u8 wbuf[4]; + struct slim_val_inf msg = {0, 4, NULL, wbuf, NULL}; + u8 mc = SLIM_MSG_MC_NEXT_DEFINE_CHANNEL; + DEFINE_SLIM_LDEST_TXN(txn, mc, 8, stream->dev->laddr, &msg); + + port->ch.seg_dist = slim_get_segdist_code(stream->ratem); + + wbuf[0] = port->ch.id; + wbuf[1] = port->ch.seg_dist & 0xFF; + wbuf[2] = (stream->prot << 4) | ((port->ch.seg_dist & 0xF00) >> 8); + if (stream->prot == SLIM_PROTO_ISO) + wbuf[3] = stream->bps/SLIM_SLOT_LEN_BITS; + else + wbuf[3] = stream->bps/SLIM_SLOT_LEN_BITS + 1; + + port->ch.state = SLIM_CH_STATE_DEFINED; + + return slim_do_transfer(sdev->ctrl, &txn); +} + +static int slim_activate_channel(struct slim_stream_runtime *stream, + struct slim_port *port) +{ + struct slim_device *sdev = stream->dev; + u8 wbuf[1]; + struct slim_val_inf msg = {0, 1, NULL, wbuf, NULL}; + u8 mc = SLIM_MSG_MC_NEXT_ACTIVATE_CHANNEL; + DEFINE_SLIM_LDEST_TXN(txn, mc, 5, stream->dev->laddr, &msg); + + txn.msg->num_bytes = 1; + txn.msg->wbuf = wbuf; + wbuf[0] = port->ch.id; + port->ch.state = SLIM_CH_STATE_ACTIVE; + + return slim_do_transfer(sdev->ctrl, &txn); +} + +/* + * slim_stream_enable() - Enable a prepared SLIMbus Stream + * + * @stream: instance of slim stream runtime to enable + * + * This API will enable all the ports and channels associated with + * SLIMbus stream + * + * Return: zero on success and error code on failure. From ASoC DPCM framework, + * this state is linked to trigger() start operation. + */ +int slim_stream_enable(struct slim_stream_runtime *stream) +{ + DEFINE_SLIM_BCAST_TXN(txn, SLIM_MSG_MC_BEGIN_RECONFIGURATION, + 3, SLIM_LA_MANAGER, NULL); + struct slim_controller *ctrl = stream->dev->ctrl; + int ret, i; + + if (ctrl->enable_stream) { + ret = ctrl->enable_stream(stream); + if (ret) + return ret; + + for (i = 0; i < stream->num_ports; i++) + stream->ports[i].ch.state = SLIM_CH_STATE_ACTIVE; + + return ret; + } + + ret = slim_do_transfer(ctrl, &txn); + if (ret) + return ret; + + /* define channels first before activating them */ + for (i = 0; i < stream->num_ports; i++) { + struct slim_port *port = &stream->ports[i]; + + slim_define_channel(stream, port); + slim_define_channel_content(stream, port); + } + + for (i = 0; i < stream->num_ports; i++) { + struct slim_port *port = &stream->ports[i]; + + slim_activate_channel(stream, port); + port->state = SLIM_PORT_CONFIGURED; + } + txn.mc = SLIM_MSG_MC_RECONFIGURE_NOW; + + return slim_do_transfer(ctrl, &txn); +} +EXPORT_SYMBOL_GPL(slim_stream_enable); + +/* + * slim_stream_disable() - Disable a SLIMbus Stream + * + * @stream: instance of slim stream runtime to disable + * + * This API will disable all the ports and channels associated with + * SLIMbus stream + * + * Return: zero on success and error code on failure. From ASoC DPCM framework, + * this state is linked to trigger() pause operation. + */ +int slim_stream_disable(struct slim_stream_runtime *stream) +{ + DEFINE_SLIM_BCAST_TXN(txn, SLIM_MSG_MC_BEGIN_RECONFIGURATION, + 3, SLIM_LA_MANAGER, NULL); + struct slim_controller *ctrl = stream->dev->ctrl; + int ret, i; + + if (ctrl->disable_stream) + ctrl->disable_stream(stream); + + ret = slim_do_transfer(ctrl, &txn); + if (ret) + return ret; + + for (i = 0; i < stream->num_ports; i++) + slim_deactivate_remove_channel(stream, &stream->ports[i]); + + txn.mc = SLIM_MSG_MC_RECONFIGURE_NOW; + + return slim_do_transfer(ctrl, &txn); +} +EXPORT_SYMBOL_GPL(slim_stream_disable); + +/* + * slim_stream_unprepare() - Un-prepare a SLIMbus Stream + * + * @stream: instance of slim stream runtime to unprepare + * + * This API will un allocate all the ports and channels associated with + * SLIMbus stream + * + * Return: zero on success and error code on failure. From ASoC DPCM framework, + * this state is linked to trigger() stop operation. + */ +int slim_stream_unprepare(struct slim_stream_runtime *stream) +{ + int i; + + for (i = 0; i < stream->num_ports; i++) + slim_disconnect_port(stream, &stream->ports[i]); + + kfree(stream->ports); + stream->ports = NULL; + stream->num_ports = 0; + + return 0; +} +EXPORT_SYMBOL_GPL(slim_stream_unprepare); + +/* + * slim_stream_free() - Free a SLIMbus Stream + * + * @stream: instance of slim stream runtime to free + * + * This API will un allocate all the memory associated with + * slim stream runtime, user is not allowed to make an dereference + * to stream after this call. + * + * Return: zero on success and error code on failure. From ASoC DPCM framework, + * this state is linked to shutdown() operation. + */ +int slim_stream_free(struct slim_stream_runtime *stream) +{ + struct slim_device *sdev = stream->dev; + + spin_lock(&sdev->stream_list_lock); + list_del(&stream->node); + spin_unlock(&sdev->stream_list_lock); + + kfree(stream->name); + kfree(stream); + + return 0; +} +EXPORT_SYMBOL_GPL(slim_stream_free); diff --git a/include/linux/slimbus.h b/include/linux/slimbus.h index 63801bcc5e60..12c9719b2a55 100644 --- a/include/linux/slimbus.h +++ b/include/linux/slimbus.h @@ -48,6 +48,8 @@ struct slim_controller; * @ctrl: slim controller instance. * @laddr: 1-byte Logical address of this device. * @is_laddr_valid: indicates if the laddr is valid or not + * @stream_list: List of streams on this device + * @stream_list_lock: lock to protect the stream list * * This is the client/device handle returned when a SLIMbus * device is registered with a controller. @@ -60,6 +62,8 @@ struct slim_device { enum slim_device_status status; u8 laddr; bool is_laddr_valid; + struct list_head stream_list; + spinlock_t stream_list_lock; }; #define to_slim_device(d) container_of(d, struct slim_device, dev) @@ -108,6 +112,36 @@ struct slim_val_inf { struct completion *comp; }; +#define SLIM_DEVICE_MAX_CHANNELS 256 +/* A SLIMBus Device may have frmo 0 to 31 Ports (inclusive) */ +#define SLIM_DEVICE_MAX_PORTS 32 + +/** + * struct slim_stream_config - SLIMbus stream configuration + * Configuring a stream is done at hw_params or prepare call + * from audio drivers where they have all the required information + * regarding rate, number of channels and so on. + * There is a 1:1 mapping of channel and ports. + * + * @rate: data rate + * @bps: bits per data sample + * @ch_count: number of channels + * @chs: pointer to list of channel numbers + * @port_mask: port mask of ports to use for this stream + * @direction: direction of the stream, SNDRV_PCM_STREAM_PLAYBACK + * or SNDRV_PCM_STREAM_CAPTURE. + */ +struct slim_stream_config { + unsigned int rate; + unsigned int bps; + /* MAX 256 channels */ + unsigned int ch_count; + unsigned int *chs; + /* Max 32 ports per device */ + unsigned long port_mask; + int direction; +}; + /* * use a macro to avoid include chaining to get THIS_MODULE */ @@ -163,4 +197,16 @@ int slim_readb(struct slim_device *sdev, u32 addr); int slim_writeb(struct slim_device *sdev, u32 addr, u8 value); int slim_read(struct slim_device *sdev, u32 addr, size_t count, u8 *val); int slim_write(struct slim_device *sdev, u32 addr, size_t count, u8 *val); + +/* SLIMbus Stream apis */ +struct slim_stream_runtime; +struct slim_stream_runtime *slim_stream_allocate(struct slim_device *dev, + const char *sname); +int slim_stream_prepare(struct slim_stream_runtime *stream, + struct slim_stream_config *c); +int slim_stream_enable(struct slim_stream_runtime *stream); +int slim_stream_disable(struct slim_stream_runtime *stream); +int slim_stream_unprepare(struct slim_stream_runtime *stream); +int slim_stream_free(struct slim_stream_runtime *stream); + #endif /* _LINUX_SLIMBUS_H */ -- cgit v1.2.3-71-gd317 From ac3167257b9fe16c9426c2087ead1c9f1b0992b1 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Tue, 19 Jun 2018 22:47:28 -0700 Subject: headers: separate linux/mod_devicetable.h from linux/platform_device.h At over 4000 #includes, is the 9th most #included header file in the Linux kernel. It does not need , so drop that header and explicitly add to source files that need it. 4146 #include After this patch, there are 225 files that use , for a reduction of around 3900 times that does not have to be read & parsed. 225 #include This patch was build-tested on 20 different arch-es. It also makes these drivers SubmitChecklist#1 compliant. Signed-off-by: Randy Dunlap Reported-by: kbuild test robot # drivers/media/platform/vimc/ Reported-by: kbuild test robot # drivers/pinctrl/pinctrl-u300.c Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-mmp/sram.c | 1 + drivers/ata/pata_imx.c | 1 + drivers/ata/pata_samsung_cf.c | 1 + drivers/auxdisplay/hd44780.c | 1 + drivers/char/hw_random/atmel-rng.c | 1 + drivers/char/hw_random/exynos-trng.c | 1 + drivers/char/hw_random/imx-rngc.c | 1 + drivers/char/hw_random/powernv-rng.c | 1 + drivers/crypto/mediatek/mtk-platform.c | 1 + drivers/crypto/qce/core.c | 1 + drivers/crypto/stm32/stm32_crc32.c | 1 + drivers/crypto/ux500/cryp/cryp_core.c | 1 + drivers/crypto/ux500/hash/hash_core.c | 1 + drivers/devfreq/tegra-devfreq.c | 1 + drivers/dma/ep93xx_dma.c | 1 + drivers/dma/s3c24xx-dma.c | 1 + drivers/extcon/extcon-intel-cht-wc.c | 1 + drivers/extcon/extcon-qcom-spmi-misc.c | 1 + drivers/gpu/drm/mediatek/mtk_cec.c | 1 + drivers/gpu/drm/sun4i/sun6i_drc.c | 1 + drivers/hsi/controllers/omap_ssi_port.c | 1 + drivers/hwmon/max197.c | 1 + drivers/hwmon/mc13783-adc.c | 1 + drivers/media/platform/coda/imx-vdoa.c | 1 + drivers/media/platform/rcar-fcp.c | 1 + drivers/media/platform/vimc/vimc-capture.c | 1 + drivers/media/platform/vimc/vimc-debayer.c | 1 + drivers/media/platform/vimc/vimc-scaler.c | 1 + drivers/media/platform/vimc/vimc-sensor.c | 1 + drivers/memory/tegra/tegra186.c | 1 + drivers/mfd/atmel-hlcdc.c | 1 + drivers/mfd/cros_ec_dev.c | 1 + drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c | 1 + drivers/net/ethernet/calxeda/xgmac.c | 1 + drivers/net/ethernet/faraday/ftmac100.c | 1 + drivers/net/wireless/ath/ath9k/ahb.c | 1 + drivers/net/wireless/ti/wl12xx/main.c | 1 + drivers/net/wireless/ti/wl18xx/main.c | 1 + drivers/nvmem/lpc18xx_eeprom.c | 1 + drivers/nvmem/mtk-efuse.c | 1 + drivers/nvmem/qfprom.c | 1 + drivers/nvmem/uniphier-efuse.c | 1 + drivers/perf/arm-ccn.c | 1 + drivers/pinctrl/intel/pinctrl-merrifield.c | 1 + drivers/pinctrl/pinctrl-u300.c | 1 + drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c | 1 + drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 1 + drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 1 + drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 1 + drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 1 + drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 1 + drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 1 + drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 1 + drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 1 + drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 1 + drivers/platform/goldfish/goldfish_pipe.c | 1 + drivers/platform/x86/intel_bxtwc_tmu.c | 1 + drivers/power/avs/smartreflex.c | 1 + drivers/power/reset/ltc2952-poweroff.c | 1 + drivers/power/supply/max8998_charger.c | 1 + drivers/power/supply/olpc_battery.c | 1 + drivers/ptp/ptp_dte.c | 1 + drivers/regulator/tps65912-regulator.c | 1 + drivers/reset/reset-ath79.c | 1 + drivers/reset/reset-axs10x.c | 1 + drivers/reset/reset-imx7.c | 1 + drivers/rtc/rtc-coh901331.c | 1 + drivers/rtc/rtc-cpcap.c | 1 + drivers/rtc/rtc-ftrtc010.c | 1 + drivers/rtc/rtc-mc13xxx.c | 1 + drivers/rtc/rtc-mxc_v2.c | 1 + drivers/rtc/rtc-r7301.c | 1 + drivers/rtc/rtc-sh.c | 1 + drivers/rtc/rtc-tegra.c | 1 + drivers/siox/siox-bus-gpio.c | 1 + drivers/tty/goldfish.c | 1 + drivers/tty/serial/8250/8250_em.c | 1 + drivers/tty/serial/sccnxp.c | 1 + drivers/usb/gadget/udc/fsl_mxc_udc.c | 1 + drivers/video/fbdev/omap2/omapfb/displays/encoder-tpd12s015.c | 1 + drivers/w1/masters/mxc_w1.c | 1 + drivers/watchdog/coh901327_wdt.c | 1 + drivers/watchdog/davinci_wdt.c | 1 + drivers/watchdog/imgpdc_wdt.c | 1 + drivers/watchdog/max63xx_wdt.c | 1 + drivers/watchdog/max77620_wdt.c | 1 + drivers/watchdog/moxart_wdt.c | 1 + drivers/watchdog/omap_wdt.c | 1 + drivers/watchdog/tangox_wdt.c | 1 + include/linux/platform_device.h | 2 +- 90 files changed, 90 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/mach-mmp/sram.c b/arch/arm/mach-mmp/sram.c index bf5e64906e65..ba91e4fe444d 100644 --- a/arch/arm/mach-mmp/sram.c +++ b/arch/arm/mach-mmp/sram.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include diff --git a/drivers/ata/pata_imx.c b/drivers/ata/pata_imx.c index d4caa23f5a88..6f0534047c6d 100644 --- a/drivers/ata/pata_imx.c +++ b/drivers/ata/pata_imx.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #define DRV_NAME "pata_imx" diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c index bb96dc35950d..f5bd44b8bd63 100644 --- a/drivers/ata/pata_samsung_cf.c +++ b/drivers/ata/pata_samsung_cf.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include diff --git a/drivers/auxdisplay/hd44780.c b/drivers/auxdisplay/hd44780.c index 78d8f1986fec..f1a42f0f1ded 100644 --- a/drivers/auxdisplay/hd44780.c +++ b/drivers/auxdisplay/hd44780.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/char/hw_random/atmel-rng.c b/drivers/char/hw_random/atmel-rng.c index 661c82cde0f2..433426242b87 100644 --- a/drivers/char/hw_random/atmel-rng.c +++ b/drivers/char/hw_random/atmel-rng.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include diff --git a/drivers/char/hw_random/exynos-trng.c b/drivers/char/hw_random/exynos-trng.c index 1947aed7c044..94235761955c 100644 --- a/drivers/char/hw_random/exynos-trng.c +++ b/drivers/char/hw_random/exynos-trng.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include diff --git a/drivers/char/hw_random/imx-rngc.c b/drivers/char/hw_random/imx-rngc.c index 250123bc4905..14730be54edf 100644 --- a/drivers/char/hw_random/imx-rngc.c +++ b/drivers/char/hw_random/imx-rngc.c @@ -13,6 +13,7 @@ */ #include +#include #include #include #include diff --git a/drivers/char/hw_random/powernv-rng.c b/drivers/char/hw_random/powernv-rng.c index 263a5bb8e605..791182aa8e04 100644 --- a/drivers/char/hw_random/powernv-rng.c +++ b/drivers/char/hw_random/powernv-rng.c @@ -10,6 +10,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include #include #include diff --git a/drivers/crypto/mediatek/mtk-platform.c b/drivers/crypto/mediatek/mtk-platform.c index b182e941b0cd..ee0404e27a0f 100644 --- a/drivers/crypto/mediatek/mtk-platform.c +++ b/drivers/crypto/mediatek/mtk-platform.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include "mtk-platform.h" diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 718b32a3112e..1c3b36b75467 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/crypto/stm32/stm32_crc32.c b/drivers/crypto/stm32/stm32_crc32.c index 8f09b8430893..a4a21fcf1e17 100644 --- a/drivers/crypto/stm32/stm32_crc32.c +++ b/drivers/crypto/stm32/stm32_crc32.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c index cb31b59c9d53..d2663a4e1f5e 100644 --- a/drivers/crypto/ux500/cryp/cryp_core.c +++ b/drivers/crypto/ux500/cryp/cryp_core.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index 2d0a677bcc76..b141b74a084e 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include diff --git a/drivers/devfreq/tegra-devfreq.c b/drivers/devfreq/tegra-devfreq.c index ae712159246f..c59d2eee5d30 100644 --- a/drivers/devfreq/tegra-devfreq.c +++ b/drivers/devfreq/tegra-devfreq.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c index ec240592f5c8..a15592383d4e 100644 --- a/drivers/dma/ep93xx_dma.c +++ b/drivers/dma/ep93xx_dma.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include diff --git a/drivers/dma/s3c24xx-dma.c b/drivers/dma/s3c24xx-dma.c index 7056fe7513b4..64744eb88720 100644 --- a/drivers/dma/s3c24xx-dma.c +++ b/drivers/dma/s3c24xx-dma.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include diff --git a/drivers/extcon/extcon-intel-cht-wc.c b/drivers/extcon/extcon-intel-cht-wc.c index b7e9ea377d70..5e1dd2772278 100644 --- a/drivers/extcon/extcon-intel-cht-wc.c +++ b/drivers/extcon/extcon-intel-cht-wc.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/extcon/extcon-qcom-spmi-misc.c b/drivers/extcon/extcon-qcom-spmi-misc.c index 660bbf163bf5..72bc0f2478e2 100644 --- a/drivers/extcon/extcon-qcom-spmi-misc.c +++ b/drivers/extcon/extcon-qcom-spmi-misc.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c index 7a3eb8c17ef9..5ce84d0dbf81 100644 --- a/drivers/gpu/drm/mediatek/mtk_cec.c +++ b/drivers/gpu/drm/mediatek/mtk_cec.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include "mtk_cec.h" diff --git a/drivers/gpu/drm/sun4i/sun6i_drc.c b/drivers/gpu/drm/sun4i/sun6i_drc.c index b5e071a49045..88eb268fdf73 100644 --- a/drivers/gpu/drm/sun4i/sun6i_drc.c +++ b/drivers/gpu/drm/sun4i/sun6i_drc.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/hsi/controllers/omap_ssi_port.c b/drivers/hsi/controllers/omap_ssi_port.c index 7765de2f1ef1..2ada82d2ec8c 100644 --- a/drivers/hsi/controllers/omap_ssi_port.c +++ b/drivers/hsi/controllers/omap_ssi_port.c @@ -20,6 +20,7 @@ * 02110-1301 USA */ +#include #include #include #include diff --git a/drivers/hwmon/max197.c b/drivers/hwmon/max197.c index 638567fb7cd8..3d9e210beedf 100644 --- a/drivers/hwmon/max197.c +++ b/drivers/hwmon/max197.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include diff --git a/drivers/hwmon/mc13783-adc.c b/drivers/hwmon/mc13783-adc.c index 67860ad2e3d9..78fe8759d2a9 100644 --- a/drivers/hwmon/mc13783-adc.c +++ b/drivers/hwmon/mc13783-adc.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/media/platform/coda/imx-vdoa.c b/drivers/media/platform/coda/imx-vdoa.c index 85a66e4e2f9a..96ab4b61669a 100644 --- a/drivers/media/platform/coda/imx-vdoa.c +++ b/drivers/media/platform/coda/imx-vdoa.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/media/platform/rcar-fcp.c b/drivers/media/platform/rcar-fcp.c index 2988031d285d..3ad9d0dc6fa7 100644 --- a/drivers/media/platform/rcar-fcp.c +++ b/drivers/media/platform/rcar-fcp.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/media/platform/vimc/vimc-capture.c b/drivers/media/platform/vimc/vimc-capture.c index 88a1e5670c72..ec68feaac378 100644 --- a/drivers/media/platform/vimc/vimc-capture.c +++ b/drivers/media/platform/vimc/vimc-capture.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include diff --git a/drivers/media/platform/vimc/vimc-debayer.c b/drivers/media/platform/vimc/vimc-debayer.c index 6e10b63ba9ec..77887f66f323 100644 --- a/drivers/media/platform/vimc/vimc-debayer.c +++ b/drivers/media/platform/vimc/vimc-debayer.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include diff --git a/drivers/media/platform/vimc/vimc-scaler.c b/drivers/media/platform/vimc/vimc-scaler.c index e583ec7a91da..b0952ee86296 100644 --- a/drivers/media/platform/vimc/vimc-scaler.c +++ b/drivers/media/platform/vimc/vimc-scaler.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include diff --git a/drivers/media/platform/vimc/vimc-sensor.c b/drivers/media/platform/vimc/vimc-sensor.c index 605e2a2d5dd5..b2b89315e7ba 100644 --- a/drivers/media/platform/vimc/vimc-sensor.c +++ b/drivers/media/platform/vimc/vimc-sensor.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 7254fb596979..ffda903c49bb 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -8,6 +8,7 @@ #include #include +#include #include #include diff --git a/drivers/mfd/atmel-hlcdc.c b/drivers/mfd/atmel-hlcdc.c index 4b15b0840f16..e82543bcfdc8 100644 --- a/drivers/mfd/atmel-hlcdc.c +++ b/drivers/mfd/atmel-hlcdc.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include diff --git a/drivers/mfd/cros_ec_dev.c b/drivers/mfd/cros_ec_dev.c index 306e1fd109bd..27af62ed480a 100644 --- a/drivers/mfd/cros_ec_dev.c +++ b/drivers/mfd/cros_ec_dev.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c b/drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c index 5c271077ac87..489af7bc005a 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c @@ -13,6 +13,7 @@ #include #include +#include #include #include "brcmnand.h" diff --git a/drivers/net/ethernet/calxeda/xgmac.c b/drivers/net/ethernet/calxeda/xgmac.c index 2c63afff1382..13741ee49b9b 100644 --- a/drivers/net/ethernet/calxeda/xgmac.c +++ b/drivers/net/ethernet/calxeda/xgmac.c @@ -14,6 +14,7 @@ * this program. If not, see . */ #include +#include #include #include #include diff --git a/drivers/net/ethernet/faraday/ftmac100.c b/drivers/net/ethernet/faraday/ftmac100.c index aecc76504b69..a1197d3adbe0 100644 --- a/drivers/net/ethernet/faraday/ftmac100.c +++ b/drivers/net/ethernet/faraday/ftmac100.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c index 2bd982c3a479..63019c3de034 100644 --- a/drivers/net/wireless/ath/ath9k/ahb.c +++ b/drivers/net/wireless/ath/ath9k/ahb.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "ath9k.h" static const struct platform_device_id ath9k_platform_id_table[] = { diff --git a/drivers/net/wireless/ti/wl12xx/main.c b/drivers/net/wireless/ti/wl12xx/main.c index 22009e14a8fc..4a4f797bb10f 100644 --- a/drivers/net/wireless/ti/wl12xx/main.c +++ b/drivers/net/wireless/ti/wl12xx/main.c @@ -20,6 +20,7 @@ */ #include +#include #include #include diff --git a/drivers/net/wireless/ti/wl18xx/main.c b/drivers/net/wireless/ti/wl18xx/main.c index ca0f936fc119..496b9b63cea1 100644 --- a/drivers/net/wireless/ti/wl18xx/main.c +++ b/drivers/net/wireless/ti/wl18xx/main.c @@ -20,6 +20,7 @@ */ #include +#include #include #include #include diff --git a/drivers/nvmem/lpc18xx_eeprom.c b/drivers/nvmem/lpc18xx_eeprom.c index b1af966206a6..a9534a6e8636 100644 --- a/drivers/nvmem/lpc18xx_eeprom.c +++ b/drivers/nvmem/lpc18xx_eeprom.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c index e66adf17a747..58c998b2e3bc 100644 --- a/drivers/nvmem/mtk-efuse.c +++ b/drivers/nvmem/mtk-efuse.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c index 4f650baad983..fbb1f1df6fc7 100644 --- a/drivers/nvmem/qfprom.c +++ b/drivers/nvmem/qfprom.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include diff --git a/drivers/nvmem/uniphier-efuse.c b/drivers/nvmem/uniphier-efuse.c index 271f0b2ff86a..286910336ef6 100644 --- a/drivers/nvmem/uniphier-efuse.c +++ b/drivers/nvmem/uniphier-efuse.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include diff --git a/drivers/perf/arm-ccn.c b/drivers/perf/arm-ccn.c index b416ee18e6bb..860f5bd8dce8 100644 --- a/drivers/perf/arm-ccn.c +++ b/drivers/perf/arm-ccn.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c index d9357054d41d..acea41073dfd 100644 --- a/drivers/pinctrl/intel/pinctrl-merrifield.c +++ b/drivers/pinctrl/intel/pinctrl-merrifield.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c index 9cc80a500880..2b1a61dba224 100644 --- a/drivers/pinctrl/pinctrl-u300.c +++ b/drivers/pinctrl/pinctrl-u300.c @@ -13,6 +13,7 @@ */ #include #include +#include #include #include #include diff --git a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c index 3cdad8bc8f93..5702b6704137 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c @@ -13,6 +13,7 @@ */ #include +#include #include #include "pinctrl-sprd.h" diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index 58825f68b58b..c93752cd51c5 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -15,6 +15,7 @@ #include #include +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index 9f449b35e300..130ce2484705 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -15,6 +15,7 @@ #include #include +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c index 0b10ebc07eb8..5a20121d2c93 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c @@ -15,6 +15,7 @@ #include #include +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c index 8e4d45fea885..76c57b0d5d88 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c @@ -15,6 +15,7 @@ #include #include +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c index 24788a74c254..4a0027373247 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c @@ -15,6 +15,7 @@ #include #include +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index d5d5e579cb08..9a55972e9c16 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -15,6 +15,7 @@ #include #include +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index 032619ad0e73..544f4b465308 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -15,6 +15,7 @@ #include #include +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index 535bb2e935e4..9a15998b4f73 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -15,6 +15,7 @@ #include #include +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c index 0f921a653164..0402077d3b3a 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c @@ -15,6 +15,7 @@ #include #include +#include #include #include diff --git a/drivers/platform/goldfish/goldfish_pipe.c b/drivers/platform/goldfish/goldfish_pipe.c index 4866a8b12e98..2da567540c2d 100644 --- a/drivers/platform/goldfish/goldfish_pipe.c +++ b/drivers/platform/goldfish/goldfish_pipe.c @@ -48,6 +48,7 @@ #include +#include #include #include #include diff --git a/drivers/platform/x86/intel_bxtwc_tmu.c b/drivers/platform/x86/intel_bxtwc_tmu.c index ea865d4ca220..227943a20212 100644 --- a/drivers/platform/x86/intel_bxtwc_tmu.c +++ b/drivers/platform/x86/intel_bxtwc_tmu.c @@ -19,6 +19,7 @@ */ #include +#include #include #include #include diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c index cb0237143dbe..1360a7fa542c 100644 --- a/drivers/power/avs/smartreflex.c +++ b/drivers/power/avs/smartreflex.c @@ -18,6 +18,7 @@ */ #include +#include #include #include #include diff --git a/drivers/power/reset/ltc2952-poweroff.c b/drivers/power/reset/ltc2952-poweroff.c index bfcd6fba6363..6b911b6b10a6 100644 --- a/drivers/power/reset/ltc2952-poweroff.c +++ b/drivers/power/reset/ltc2952-poweroff.c @@ -62,6 +62,7 @@ #include #include #include +#include #include #include diff --git a/drivers/power/supply/max8998_charger.c b/drivers/power/supply/max8998_charger.c index b64cf0f14142..cad7d1a8feec 100644 --- a/drivers/power/supply/max8998_charger.c +++ b/drivers/power/supply/max8998_charger.c @@ -21,6 +21,7 @@ #include #include +#include #include #include #include diff --git a/drivers/power/supply/olpc_battery.c b/drivers/power/supply/olpc_battery.c index 3bc2eea7b3b7..6da79ae14860 100644 --- a/drivers/power/supply/olpc_battery.c +++ b/drivers/power/supply/olpc_battery.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include diff --git a/drivers/ptp/ptp_dte.c b/drivers/ptp/ptp_dte.c index 6edd3b9c7f01..a7dc43368df4 100644 --- a/drivers/ptp/ptp_dte.c +++ b/drivers/ptp/ptp_dte.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/regulator/tps65912-regulator.c b/drivers/regulator/tps65912-regulator.c index a4921a70da55..276faeddc370 100644 --- a/drivers/regulator/tps65912-regulator.c +++ b/drivers/regulator/tps65912-regulator.c @@ -18,6 +18,7 @@ */ #include +#include #include #include diff --git a/drivers/reset/reset-ath79.c b/drivers/reset/reset-ath79.c index 2674880e5492..a7455916e396 100644 --- a/drivers/reset/reset-ath79.c +++ b/drivers/reset/reset-ath79.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include diff --git a/drivers/reset/reset-axs10x.c b/drivers/reset/reset-axs10x.c index afb298e46bd9..a854ef41364d 100644 --- a/drivers/reset/reset-axs10x.c +++ b/drivers/reset/reset-axs10x.c @@ -10,6 +10,7 @@ #include #include +#include #include #include diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index 4db177bc89bc..14bc78d28707 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include diff --git a/drivers/rtc/rtc-coh901331.c b/drivers/rtc/rtc-coh901331.c index 2fc517498a5d..fc5cf5c44ae7 100644 --- a/drivers/rtc/rtc-coh901331.c +++ b/drivers/rtc/rtc-coh901331.c @@ -8,6 +8,7 @@ */ #include #include +#include #include #include #include diff --git a/drivers/rtc/rtc-cpcap.c b/drivers/rtc/rtc-cpcap.c index a8856f2b9bc2..6b477174a82f 100644 --- a/drivers/rtc/rtc-cpcap.c +++ b/drivers/rtc/rtc-cpcap.c @@ -24,6 +24,7 @@ */ #include #include +#include #include #include #include diff --git a/drivers/rtc/rtc-ftrtc010.c b/drivers/rtc/rtc-ftrtc010.c index 61f798c6101f..8f1dd88fa827 100644 --- a/drivers/rtc/rtc-ftrtc010.c +++ b/drivers/rtc/rtc-ftrtc010.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #define DRV_NAME "rtc-ftrtc010" diff --git a/drivers/rtc/rtc-mc13xxx.c b/drivers/rtc/rtc-mc13xxx.c index 1f892b238ddb..0fa33708fc49 100644 --- a/drivers/rtc/rtc-mc13xxx.c +++ b/drivers/rtc/rtc-mc13xxx.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include diff --git a/drivers/rtc/rtc-mxc_v2.c b/drivers/rtc/rtc-mxc_v2.c index c75f26dc8fcc..007879a5042d 100644 --- a/drivers/rtc/rtc-mxc_v2.c +++ b/drivers/rtc/rtc-mxc_v2.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include diff --git a/drivers/rtc/rtc-r7301.c b/drivers/rtc/rtc-r7301.c index 169704b2ce13..1943c8151152 100644 --- a/drivers/rtc/rtc-r7301.c +++ b/drivers/rtc/rtc-r7301.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c index 4f98543d1ea5..776b70a14e03 100644 --- a/drivers/rtc/rtc-sh.c +++ b/drivers/rtc/rtc-sh.c @@ -15,6 +15,7 @@ * for more details. */ #include +#include #include #include #include diff --git a/drivers/rtc/rtc-tegra.c b/drivers/rtc/rtc-tegra.c index 66efff60c4d5..8dc48fe7fc35 100644 --- a/drivers/rtc/rtc-tegra.c +++ b/drivers/rtc/rtc-tegra.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/siox/siox-bus-gpio.c b/drivers/siox/siox-bus-gpio.c index ea7ef982968b..46b4cda36bac 100644 --- a/drivers/siox/siox-bus-gpio.c +++ b/drivers/siox/siox-bus-gpio.c @@ -5,6 +5,7 @@ #include #include +#include #include #include diff --git a/drivers/tty/goldfish.c b/drivers/tty/goldfish.c index 37caba7c3aff..c8c5cdfc5e19 100644 --- a/drivers/tty/goldfish.c +++ b/drivers/tty/goldfish.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/tty/serial/8250/8250_em.c b/drivers/tty/serial/8250/8250_em.c index f6a86f2bc4e5..2a76e22d2ec0 100644 --- a/drivers/tty/serial/8250/8250_em.c +++ b/drivers/tty/serial/8250/8250_em.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/tty/serial/sccnxp.c b/drivers/tty/serial/sccnxp.c index d6ae3086c2a2..339befdd2f4d 100644 --- a/drivers/tty/serial/sccnxp.c +++ b/drivers/tty/serial/sccnxp.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/usb/gadget/udc/fsl_mxc_udc.c b/drivers/usb/gadget/udc/fsl_mxc_udc.c index f29cf5c6160c..5a321992decc 100644 --- a/drivers/usb/gadget/udc/fsl_mxc_udc.c +++ b/drivers/usb/gadget/udc/fsl_mxc_udc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include diff --git a/drivers/video/fbdev/omap2/omapfb/displays/encoder-tpd12s015.c b/drivers/video/fbdev/omap2/omapfb/displays/encoder-tpd12s015.c index 80dc47347e21..3079a3df8c37 100644 --- a/drivers/video/fbdev/omap2/omapfb/displays/encoder-tpd12s015.c +++ b/drivers/video/fbdev/omap2/omapfb/displays/encoder-tpd12s015.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c index 8851d441e5fd..50b46c4399ea 100644 --- a/drivers/w1/masters/mxc_w1.c +++ b/drivers/w1/masters/mxc_w1.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include diff --git a/drivers/watchdog/coh901327_wdt.c b/drivers/watchdog/coh901327_wdt.c index e3a78f927f83..f29d1edc5bad 100644 --- a/drivers/watchdog/coh901327_wdt.c +++ b/drivers/watchdog/coh901327_wdt.c @@ -7,6 +7,7 @@ * Author: Linus Walleij */ #include +#include #include #include #include diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c index 6c6594261cb7..ebb85d60b6d5 100644 --- a/drivers/watchdog/davinci_wdt.c +++ b/drivers/watchdog/davinci_wdt.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include diff --git a/drivers/watchdog/imgpdc_wdt.c b/drivers/watchdog/imgpdc_wdt.c index 6ed39dee995f..a3134ffa59f8 100644 --- a/drivers/watchdog/imgpdc_wdt.c +++ b/drivers/watchdog/imgpdc_wdt.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/watchdog/max63xx_wdt.c b/drivers/watchdog/max63xx_wdt.c index ac5840d9689a..bf6a068245ba 100644 --- a/drivers/watchdog/max63xx_wdt.c +++ b/drivers/watchdog/max63xx_wdt.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/watchdog/max77620_wdt.c b/drivers/watchdog/max77620_wdt.c index 2c9f53eaff4f..70c9cd3ba938 100644 --- a/drivers/watchdog/max77620_wdt.c +++ b/drivers/watchdog/max77620_wdt.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/watchdog/moxart_wdt.c b/drivers/watchdog/moxart_wdt.c index 2c4a73d1e214..430c3ab84c07 100644 --- a/drivers/watchdog/moxart_wdt.c +++ b/drivers/watchdog/moxart_wdt.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index ae77112ce97f..cbd752f9ac56 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -29,6 +29,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include #include #include diff --git a/drivers/watchdog/tangox_wdt.c b/drivers/watchdog/tangox_wdt.c index b1de8297fa40..d0b53f3c0d17 100644 --- a/drivers/watchdog/tangox_wdt.c +++ b/drivers/watchdog/tangox_wdt.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index 3097c943fab9..1a9f38f27f65 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -12,13 +12,13 @@ #define _PLATFORM_DEVICE_H_ #include -#include #define PLATFORM_DEVID_NONE (-1) #define PLATFORM_DEVID_AUTO (-2) struct mfd_cell; struct property_entry; +struct platform_device_id; struct platform_device { const char *name; -- cgit v1.2.3-71-gd317 From 777fd524ba197475a60198aa1666408662acbcbc Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 29 May 2018 19:28:38 +1000 Subject: fsi: master-gpio: Add more tracepoints This adds a few more tracepoints that have proven useful when debugging issues with the FSI bus. This also makes echo_delay() use clock_zeros() instead of open-code it in order to share the tracepoint. Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Joel Stanley --- drivers/fsi/fsi-master-gpio.c | 16 +++++---- include/trace/events/fsi_master_gpio.h | 59 ++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/drivers/fsi/fsi-master-gpio.c b/drivers/fsi/fsi-master-gpio.c index a8445ec21b4a..40cbaf96547c 100644 --- a/drivers/fsi/fsi-master-gpio.c +++ b/drivers/fsi/fsi-master-gpio.c @@ -130,10 +130,17 @@ static void set_sda_output(struct fsi_master_gpio *master, int value) static void clock_zeros(struct fsi_master_gpio *master, int count) { + trace_fsi_master_gpio_clock_zeros(master, count); set_sda_output(master, 1); clock_toggle(master, count); } +static void echo_delay(struct fsi_master_gpio *master) +{ + clock_zeros(master, master->t_echo_delay); +} + + static void serial_in(struct fsi_master_gpio *master, struct fsi_gpio_msg *msg, uint8_t num_bits) { @@ -279,16 +286,19 @@ static void build_ar_command(struct fsi_master_gpio *master, addr_bits = 2; opcode_bits = 2; opcode = FSI_GPIO_CMD_SAME_AR; + trace_fsi_master_gpio_cmd_same_addr(master); } else if (check_relative_address(master, id, addr, &rel_addr)) { /* 8 bits plus sign */ addr_bits = 9; addr = rel_addr; opcode = FSI_GPIO_CMD_REL_AR; + trace_fsi_master_gpio_cmd_rel_addr(master, rel_addr); } else { addr_bits = 21; opcode = FSI_GPIO_CMD_ABS_AR; + trace_fsi_master_gpio_cmd_abs_addr(master, addr); } /* @@ -337,12 +347,6 @@ static void build_epoll_command(struct fsi_gpio_msg *cmd, uint8_t slave_id) msg_push_crc(cmd); } -static void echo_delay(struct fsi_master_gpio *master) -{ - set_sda_output(master, 1); - clock_toggle(master, master->t_echo_delay); -} - static void build_term_command(struct fsi_gpio_msg *cmd, uint8_t slave_id) { cmd->bits = 0; diff --git a/include/trace/events/fsi_master_gpio.h b/include/trace/events/fsi_master_gpio.h index 389082132433..70ef66e63e84 100644 --- a/include/trace/events/fsi_master_gpio.h +++ b/include/trace/events/fsi_master_gpio.h @@ -50,6 +50,22 @@ TRACE_EVENT(fsi_master_gpio_out, ) ); +TRACE_EVENT(fsi_master_gpio_clock_zeros, + TP_PROTO(const struct fsi_master_gpio *master, int clocks), + TP_ARGS(master, clocks), + TP_STRUCT__entry( + __field(int, master_idx) + __field(int, clocks) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + __entry->clocks = clocks; + ), + TP_printk("fsi-gpio%d clock %d zeros", + __entry->master_idx, __entry->clocks + ) +); + TRACE_EVENT(fsi_master_gpio_break, TP_PROTO(const struct fsi_master_gpio *master), TP_ARGS(master), @@ -107,6 +123,49 @@ TRACE_EVENT(fsi_master_gpio_poll_response_busy, __entry->master_idx, __entry->busy) ); +TRACE_EVENT(fsi_master_gpio_cmd_abs_addr, + TP_PROTO(const struct fsi_master_gpio *master, u32 addr), + TP_ARGS(master, addr), + TP_STRUCT__entry( + __field(int, master_idx) + __field(u32, addr) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + __entry->addr = addr; + ), + TP_printk("fsi-gpio%d: Sending ABS_ADR %06x", + __entry->master_idx, __entry->addr) +); + +TRACE_EVENT(fsi_master_gpio_cmd_rel_addr, + TP_PROTO(const struct fsi_master_gpio *master, u32 rel_addr), + TP_ARGS(master, rel_addr), + TP_STRUCT__entry( + __field(int, master_idx) + __field(u32, rel_addr) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + __entry->rel_addr = rel_addr; + ), + TP_printk("fsi-gpio%d: Sending REL_ADR %03x", + __entry->master_idx, __entry->rel_addr) +); + +TRACE_EVENT(fsi_master_gpio_cmd_same_addr, + TP_PROTO(const struct fsi_master_gpio *master), + TP_ARGS(master), + TP_STRUCT__entry( + __field(int, master_idx) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + ), + TP_printk("fsi-gpio%d: Sending SAME_ADR", + __entry->master_idx) +); + #endif /* _TRACE_FSI_MASTER_GPIO_H */ #include -- cgit v1.2.3-71-gd317 From 25b4a2b909dc9fdd141ee4239cf78d1617a9d91d Mon Sep 17 00:00:00 2001 From: Mathieu Poirier Date: Wed, 11 Jul 2018 13:40:13 -0600 Subject: coresight: Remove function coresight_vpid_to_pid() Now that we prevent users from using contextID tracing when PID namespaces are involved there is no client for function coresight_vpid_to_pid(). As such simply remove it. Signed-off-by: Mathieu Poirier Reviewed-by: Kim Phillips Acked-by: "Eric W. Biederman" Signed-off-by: Greg Kroah-Hartman --- include/linux/coresight.h | 20 -------------------- 1 file changed, 20 deletions(-) (limited to 'include') diff --git a/include/linux/coresight.h b/include/linux/coresight.h index c265e0468414..e5421b83e4e6 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -267,24 +267,4 @@ static inline struct coresight_platform_data *of_get_coresight_platform_data( struct device *dev, const struct device_node *node) { return NULL; } #endif -#ifdef CONFIG_PID_NS -static inline unsigned long -coresight_vpid_to_pid(unsigned long vpid) -{ - struct task_struct *task = NULL; - unsigned long pid = 0; - - rcu_read_lock(); - task = find_task_by_vpid(vpid); - if (task) - pid = task_pid_nr(task); - rcu_read_unlock(); - - return pid; -} -#else -static inline unsigned long -coresight_vpid_to_pid(unsigned long vpid) { return vpid; } -#endif - #endif -- cgit v1.2.3-71-gd317 From 575694978247b7cc1588ec233bde3fbf66db9e50 Mon Sep 17 00:00:00 2001 From: Suzuki K Poulose Date: Wed, 11 Jul 2018 13:40:27 -0600 Subject: coresight: Cleanup platform description data Nobody uses the "clk" field in struct coresight_platform_data. Remove it. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- include/linux/coresight.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/linux/coresight.h b/include/linux/coresight.h index e5421b83e4e6..69a5c9f82469 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -87,7 +87,6 @@ struct coresight_dev_subtype { * @child_ports:child component port number the current component is connected to. * @nr_outport: number of output ports for this component. - * @clk: The clock this component is associated to. */ struct coresight_platform_data { int cpu; @@ -97,7 +96,6 @@ struct coresight_platform_data { const char **child_names; int *child_ports; int nr_outport; - struct clk *clk; }; /** -- cgit v1.2.3-71-gd317 From 00b78e8b7b003c686a8570df7d231787f514226c Mon Sep 17 00:00:00 2001 From: Suzuki K Poulose Date: Wed, 11 Jul 2018 13:40:29 -0600 Subject: coresight: Cleanup device subtype struct Clean up our struct a little bit by using a union instead of a struct for tracking the subtype of a device. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- include/linux/coresight.h | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 69a5c9f82469..7c188c2a5b3c 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -63,17 +63,20 @@ enum coresight_dev_subtype_source { }; /** - * struct coresight_dev_subtype - further characterisation of a type + * union coresight_dev_subtype - further characterisation of a type * @sink_subtype: type of sink this component is, as defined - by @coresight_dev_subtype_sink. + * by @coresight_dev_subtype_sink. * @link_subtype: type of link this component is, as defined - by @coresight_dev_subtype_link. + * by @coresight_dev_subtype_link. * @source_subtype: type of source this component is, as defined - by @coresight_dev_subtype_source. + * by @coresight_dev_subtype_source. */ -struct coresight_dev_subtype { - enum coresight_dev_subtype_sink sink_subtype; - enum coresight_dev_subtype_link link_subtype; +union coresight_dev_subtype { + /* We have some devices which acts as LINK and SINK */ + struct { + enum coresight_dev_subtype_sink sink_subtype; + enum coresight_dev_subtype_link link_subtype; + }; enum coresight_dev_subtype_source source_subtype; }; @@ -111,7 +114,7 @@ struct coresight_platform_data { */ struct coresight_desc { enum coresight_dev_type type; - struct coresight_dev_subtype subtype; + union coresight_dev_subtype subtype; const struct coresight_ops *ops; struct coresight_platform_data *pdata; struct device *dev; @@ -155,7 +158,7 @@ struct coresight_device { int nr_inport; int nr_outport; enum coresight_dev_type type; - struct coresight_dev_subtype subtype; + union coresight_dev_subtype subtype; const struct coresight_ops *ops; struct device dev; atomic_t *refcnt; -- cgit v1.2.3-71-gd317 From 8a091d847cecd1a3656172cb79b53a19e90b8c4f Mon Sep 17 00:00:00 2001 From: Suzuki K Poulose Date: Wed, 11 Jul 2018 13:40:30 -0600 Subject: coresight: Add helper device type Add a new coresight device type, which do not belong to any of the existing types, i.e, source, sink, link etc. A helper device could be connected to a coresight device, which could augment the functionality of the coresight device. This is intended to cover Coresight Address Translation Unit (CATU) devices, which provide improved Scatter Gather mechanism for TMC ETR. The idea is that the helper device could be controlled by the driver of the device it is attached to (in this case ETR), transparent to the generic coresight driver (and paths). The operations include enable(), disable(), both of which could accept a device specific "data" which the driving device and the helper device could share. Since they don't appear in the coresight "path" tracked by software, we have to ensure that they are powered up/down whenever the master device is turned on. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- drivers/hwtracing/coresight/coresight.c | 43 +++++++++++++++++++++++++++++++-- include/linux/coresight.h | 24 ++++++++++++++++++ 2 files changed, 65 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 7f2b478a048f..3e07fd335f8c 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -425,6 +425,42 @@ struct coresight_device *coresight_get_enabled_sink(bool deactivate) return dev ? to_coresight_device(dev) : NULL; } +/* + * coresight_grab_device - Power up this device and any of the helper + * devices connected to it for trace operation. Since the helper devices + * don't appear on the trace path, they should be handled along with the + * the master device. + */ +static void coresight_grab_device(struct coresight_device *csdev) +{ + int i; + + for (i = 0; i < csdev->nr_outport; i++) { + struct coresight_device *child = csdev->conns[i].child_dev; + + if (child && child->type == CORESIGHT_DEV_TYPE_HELPER) + pm_runtime_get_sync(child->dev.parent); + } + pm_runtime_get_sync(csdev->dev.parent); +} + +/* + * coresight_drop_device - Release this device and any of the helper + * devices connected to it. + */ +static void coresight_drop_device(struct coresight_device *csdev) +{ + int i; + + pm_runtime_put(csdev->dev.parent); + for (i = 0; i < csdev->nr_outport; i++) { + struct coresight_device *child = csdev->conns[i].child_dev; + + if (child && child->type == CORESIGHT_DEV_TYPE_HELPER) + pm_runtime_put(child->dev.parent); + } +} + /** * _coresight_build_path - recursively build a path from a @csdev to a sink. * @csdev: The device to start from. @@ -473,9 +509,9 @@ out: if (!node) return -ENOMEM; + coresight_grab_device(csdev); node->csdev = csdev; list_add(&node->link, path); - pm_runtime_get_sync(csdev->dev.parent); return 0; } @@ -519,7 +555,7 @@ void coresight_release_path(struct list_head *path) list_for_each_entry_safe(nd, next, path, link) { csdev = nd->csdev; - pm_runtime_put_sync(csdev->dev.parent); + coresight_drop_device(csdev); list_del(&nd->link); kfree(nd); } @@ -770,6 +806,9 @@ static struct device_type coresight_dev_type[] = { .name = "source", .groups = coresight_source_groups, }, + { + .name = "helper", + }, }; static void coresight_device_release(struct device *dev) diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 7c188c2a5b3c..3d40a2b135f1 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -40,6 +40,7 @@ enum coresight_dev_type { CORESIGHT_DEV_TYPE_LINK, CORESIGHT_DEV_TYPE_LINKSINK, CORESIGHT_DEV_TYPE_SOURCE, + CORESIGHT_DEV_TYPE_HELPER, }; enum coresight_dev_subtype_sink { @@ -62,6 +63,10 @@ enum coresight_dev_subtype_source { CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, }; +enum coresight_dev_subtype_helper { + CORESIGHT_DEV_SUBTYPE_HELPER_NONE, +}; + /** * union coresight_dev_subtype - further characterisation of a type * @sink_subtype: type of sink this component is, as defined @@ -70,6 +75,8 @@ enum coresight_dev_subtype_source { * by @coresight_dev_subtype_link. * @source_subtype: type of source this component is, as defined * by @coresight_dev_subtype_source. + * @helper_subtype: type of helper this component is, as defined + * by @coresight_dev_subtype_helper. */ union coresight_dev_subtype { /* We have some devices which acts as LINK and SINK */ @@ -78,6 +85,7 @@ union coresight_dev_subtype { enum coresight_dev_subtype_link link_subtype; }; enum coresight_dev_subtype_source source_subtype; + enum coresight_dev_subtype_helper helper_subtype; }; /** @@ -172,6 +180,7 @@ struct coresight_device { #define source_ops(csdev) csdev->ops->source_ops #define sink_ops(csdev) csdev->ops->sink_ops #define link_ops(csdev) csdev->ops->link_ops +#define helper_ops(csdev) csdev->ops->helper_ops /** * struct coresight_ops_sink - basic operations for a sink @@ -231,10 +240,25 @@ struct coresight_ops_source { struct perf_event *event); }; +/** + * struct coresight_ops_helper - Operations for a helper device. + * + * All operations could pass in a device specific data, which could + * help the helper device to determine what to do. + * + * @enable : Enable the device + * @disable : Disable the device + */ +struct coresight_ops_helper { + int (*enable)(struct coresight_device *csdev, void *data); + int (*disable)(struct coresight_device *csdev, void *data); +}; + struct coresight_ops { const struct coresight_ops_sink *sink_ops; const struct coresight_ops_link *link_ops; const struct coresight_ops_source *source_ops; + const struct coresight_ops_helper *helper_ops; }; #ifdef CONFIG_CORESIGHT -- cgit v1.2.3-71-gd317 From fcacb5c154baaeaee3d89b2a2b7cf6e4ce43f5f5 Mon Sep 17 00:00:00 2001 From: Suzuki K Poulose Date: Wed, 11 Jul 2018 13:40:31 -0600 Subject: coresight: Introduce support for Coresight Address Translation Unit Add the initial support for Coresight Address Translation Unit, which augments the TMC in Coresight SoC-600 by providing an improved Scatter Gather mechanism. CATU is always connected to a single TMC-ETR and converts the AXI address with a translated address (from a given SG table with specific format). The CATU should be programmed in pass through mode and enabled even if the ETR doesn't use the translation by CATU. This patch provides mechanism to enable/disable the CATU always in the pass through mode. We reuse the existing ports mechanism to link the TMC-ETR to the connected CATU. i.e, TMC-ETR:output_port0 -> CATU:input_port0 Reference manual for CATU component is avilable in version r2p0 of : "Arm Coresight System-on-Chip SoC-600 Technical Reference Manual". Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- drivers/hwtracing/coresight/Kconfig | 11 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-catu.c | 214 ++++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-catu.h | 84 ++++++++++ drivers/hwtracing/coresight/coresight-tmc-etr.c | 52 ++++++ include/linux/coresight.h | 1 + 6 files changed, 363 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-catu.c create mode 100644 drivers/hwtracing/coresight/coresight-catu.h (limited to 'include') diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index ef9cb3c164e1..ad34380cac49 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -31,6 +31,17 @@ config CORESIGHT_LINK_AND_SINK_TMC complies with the generic implementation of the component without special enhancement or added features. +config CORESIGHT_CATU + bool "Coresight Address Translation Unit (CATU) driver" + depends on CORESIGHT_LINK_AND_SINK_TMC + help + Enable support for the Coresight Address Translation Unit (CATU). + CATU supports a scatter gather table of 4K pages, with forward/backward + lookup. CATU helps TMC ETR to use a large physically non-contiguous trace + buffer by translating the addresses used by ETR to the physical address + by looking up the provided table. CATU can also be used in pass-through + mode where the address is not translated. + config CORESIGHT_SINK_TPIU bool "Coresight generic TPIU driver" depends on CORESIGHT_LINKS_AND_SINKS diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 61db9dd0d571..41870ded51a3 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -18,3 +18,4 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \ obj-$(CONFIG_CORESIGHT_DYNAMIC_REPLICATOR) += coresight-dynamic-replicator.o obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o +obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c new file mode 100644 index 000000000000..9d0cb1f6f16b --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Arm Limited. All rights reserved. + * + * Coresight Address Translation Unit support + * + * Author: Suzuki K Poulose + */ + +#include +#include +#include +#include +#include +#include + +#include "coresight-catu.h" +#include "coresight-priv.h" + +#define csdev_to_catu_drvdata(csdev) \ + dev_get_drvdata(csdev->dev.parent) + +coresight_simple_reg32(struct catu_drvdata, devid, CORESIGHT_DEVID); +coresight_simple_reg32(struct catu_drvdata, control, CATU_CONTROL); +coresight_simple_reg32(struct catu_drvdata, status, CATU_STATUS); +coresight_simple_reg32(struct catu_drvdata, mode, CATU_MODE); +coresight_simple_reg32(struct catu_drvdata, axictrl, CATU_AXICTRL); +coresight_simple_reg32(struct catu_drvdata, irqen, CATU_IRQEN); +coresight_simple_reg64(struct catu_drvdata, sladdr, + CATU_SLADDRLO, CATU_SLADDRHI); +coresight_simple_reg64(struct catu_drvdata, inaddr, + CATU_INADDRLO, CATU_INADDRHI); + +static struct attribute *catu_mgmt_attrs[] = { + &dev_attr_devid.attr, + &dev_attr_control.attr, + &dev_attr_status.attr, + &dev_attr_mode.attr, + &dev_attr_axictrl.attr, + &dev_attr_irqen.attr, + &dev_attr_sladdr.attr, + &dev_attr_inaddr.attr, + NULL, +}; + +static const struct attribute_group catu_mgmt_group = { + .attrs = catu_mgmt_attrs, + .name = "mgmt", +}; + +static const struct attribute_group *catu_groups[] = { + &catu_mgmt_group, + NULL, +}; + + +static inline int catu_wait_for_ready(struct catu_drvdata *drvdata) +{ + return coresight_timeout(drvdata->base, + CATU_STATUS, CATU_STATUS_READY, 1); +} + +static int catu_enable_hw(struct catu_drvdata *drvdata, void *__unused) +{ + u32 control; + + if (catu_wait_for_ready(drvdata)) + dev_warn(drvdata->dev, "Timeout while waiting for READY\n"); + + control = catu_read_control(drvdata); + if (control & BIT(CATU_CONTROL_ENABLE)) { + dev_warn(drvdata->dev, "CATU is already enabled\n"); + return -EBUSY; + } + + control |= BIT(CATU_CONTROL_ENABLE); + catu_write_mode(drvdata, CATU_MODE_PASS_THROUGH); + catu_write_control(drvdata, control); + dev_dbg(drvdata->dev, "Enabled in Pass through mode\n"); + return 0; +} + +static int catu_enable(struct coresight_device *csdev, void *data) +{ + int rc; + struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev); + + CS_UNLOCK(catu_drvdata->base); + rc = catu_enable_hw(catu_drvdata, data); + CS_LOCK(catu_drvdata->base); + return rc; +} + +static int catu_disable_hw(struct catu_drvdata *drvdata) +{ + int rc = 0; + + catu_write_control(drvdata, 0); + if (catu_wait_for_ready(drvdata)) { + dev_info(drvdata->dev, "Timeout while waiting for READY\n"); + rc = -EAGAIN; + } + + dev_dbg(drvdata->dev, "Disabled\n"); + return rc; +} + +static int catu_disable(struct coresight_device *csdev, void *__unused) +{ + int rc; + struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev); + + CS_UNLOCK(catu_drvdata->base); + rc = catu_disable_hw(catu_drvdata); + CS_LOCK(catu_drvdata->base); + return rc; +} + +const struct coresight_ops_helper catu_helper_ops = { + .enable = catu_enable, + .disable = catu_disable, +}; + +const struct coresight_ops catu_ops = { + .helper_ops = &catu_helper_ops, +}; + +static int catu_probe(struct amba_device *adev, const struct amba_id *id) +{ + int ret = 0; + u32 dma_mask; + struct catu_drvdata *drvdata; + struct coresight_desc catu_desc; + struct coresight_platform_data *pdata = NULL; + struct device *dev = &adev->dev; + struct device_node *np = dev->of_node; + void __iomem *base; + + if (np) { + pdata = of_get_coresight_platform_data(dev, np); + if (IS_ERR(pdata)) { + ret = PTR_ERR(pdata); + goto out; + } + dev->platform_data = pdata; + } + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) { + ret = -ENOMEM; + goto out; + } + + drvdata->dev = dev; + dev_set_drvdata(dev, drvdata); + base = devm_ioremap_resource(dev, &adev->res); + if (IS_ERR(base)) { + ret = PTR_ERR(base); + goto out; + } + + /* Setup dma mask for the device */ + dma_mask = readl_relaxed(base + CORESIGHT_DEVID) & 0x3f; + switch (dma_mask) { + case 32: + case 40: + case 44: + case 48: + case 52: + case 56: + case 64: + break; + default: + /* Default to the 40bits as supported by TMC-ETR */ + dma_mask = 40; + } + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(dma_mask)); + if (ret) + goto out; + + drvdata->base = base; + catu_desc.pdata = pdata; + catu_desc.dev = dev; + catu_desc.groups = catu_groups; + catu_desc.type = CORESIGHT_DEV_TYPE_HELPER; + catu_desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CATU; + catu_desc.ops = &catu_ops; + drvdata->csdev = coresight_register(&catu_desc); + if (IS_ERR(drvdata->csdev)) + ret = PTR_ERR(drvdata->csdev); +out: + pm_runtime_put(&adev->dev); + return ret; +} + +static struct amba_id catu_ids[] = { + { + .id = 0x000bb9ee, + .mask = 0x000fffff, + }, + {}, +}; + +static struct amba_driver catu_driver = { + .drv = { + .name = "coresight-catu", + .owner = THIS_MODULE, + .suppress_bind_attrs = true, + }, + .probe = catu_probe, + .id_table = catu_ids, +}; + +builtin_amba_driver(catu_driver); diff --git a/drivers/hwtracing/coresight/coresight-catu.h b/drivers/hwtracing/coresight/coresight-catu.h new file mode 100644 index 000000000000..4f221fccffca --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-catu.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Arm Limited. All rights reserved. + * + * Author: Suzuki K Poulose + */ + +#ifndef _CORESIGHT_CATU_H +#define _CORESIGHT_CATU_H + +#include "coresight-priv.h" + +/* Register offset from base */ +#define CATU_CONTROL 0x000 +#define CATU_MODE 0x004 +#define CATU_AXICTRL 0x008 +#define CATU_IRQEN 0x00c +#define CATU_SLADDRLO 0x020 +#define CATU_SLADDRHI 0x024 +#define CATU_INADDRLO 0x028 +#define CATU_INADDRHI 0x02c +#define CATU_STATUS 0x100 +#define CATU_DEVARCH 0xfbc + +#define CATU_CONTROL_ENABLE 0 + +#define CATU_MODE_PASS_THROUGH 0U +#define CATU_MODE_TRANSLATE 1U + +#define CATU_STATUS_READY 8 +#define CATU_STATUS_ADRERR 0 +#define CATU_STATUS_AXIERR 4 + +#define CATU_IRQEN_ON 0x1 +#define CATU_IRQEN_OFF 0x0 + +struct catu_drvdata { + struct device *dev; + void __iomem *base; + struct coresight_device *csdev; + int irq; +}; + +#define CATU_REG32(name, offset) \ +static inline u32 \ +catu_read_##name(struct catu_drvdata *drvdata) \ +{ \ + return coresight_read_reg_pair(drvdata->base, offset, -1); \ +} \ +static inline void \ +catu_write_##name(struct catu_drvdata *drvdata, u32 val) \ +{ \ + coresight_write_reg_pair(drvdata->base, val, offset, -1); \ +} + +#define CATU_REG_PAIR(name, lo_off, hi_off) \ +static inline u64 \ +catu_read_##name(struct catu_drvdata *drvdata) \ +{ \ + return coresight_read_reg_pair(drvdata->base, lo_off, hi_off); \ +} \ +static inline void \ +catu_write_##name(struct catu_drvdata *drvdata, u64 val) \ +{ \ + coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \ +} + +CATU_REG32(control, CATU_CONTROL); +CATU_REG32(mode, CATU_MODE); +CATU_REG_PAIR(sladdr, CATU_SLADDRLO, CATU_SLADDRHI) +CATU_REG_PAIR(inaddr, CATU_INADDRLO, CATU_INADDRHI) + +static inline bool coresight_is_catu_device(struct coresight_device *csdev) +{ + if (!IS_ENABLED(CONFIG_CORESIGHT_CATU)) + return false; + if (csdev->type != CORESIGHT_DEV_TYPE_HELPER) + return false; + if (csdev->subtype.helper_subtype != CORESIGHT_DEV_SUBTYPE_HELPER_CATU) + return false; + return true; +} + +#endif diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 8af451230121..e37923acb725 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -9,6 +9,7 @@ #include #include #include +#include "coresight-catu.h" #include "coresight-priv.h" #include "coresight-tmc.h" @@ -701,6 +702,48 @@ static const struct etr_buf_operations etr_sg_buf_ops = { .get_data = tmc_etr_get_data_sg_buf, }; +/* + * TMC ETR could be connected to a CATU device, which can provide address + * translation service. This is represented by the Output port of the TMC + * (ETR) connected to the input port of the CATU. + * + * Returns : coresight_device ptr for the CATU device if a CATU is found. + * : NULL otherwise. + */ +static inline struct coresight_device * +tmc_etr_get_catu_device(struct tmc_drvdata *drvdata) +{ + int i; + struct coresight_device *tmp, *etr = drvdata->csdev; + + if (!IS_ENABLED(CONFIG_CORESIGHT_CATU)) + return NULL; + + for (i = 0; i < etr->nr_outport; i++) { + tmp = etr->conns[i].child_dev; + if (tmp && coresight_is_catu_device(tmp)) + return tmp; + } + + return NULL; +} + +static inline void tmc_etr_enable_catu(struct tmc_drvdata *drvdata) +{ + struct coresight_device *catu = tmc_etr_get_catu_device(drvdata); + + if (catu && helper_ops(catu)->enable) + helper_ops(catu)->enable(catu, NULL); +} + +static inline void tmc_etr_disable_catu(struct tmc_drvdata *drvdata) +{ + struct coresight_device *catu = tmc_etr_get_catu_device(drvdata); + + if (catu && helper_ops(catu)->disable) + helper_ops(catu)->disable(catu, NULL); +} + static const struct etr_buf_operations *etr_buf_ops[] = { [ETR_MODE_FLAT] = &etr_flat_buf_ops, [ETR_MODE_ETR_SG] = &etr_sg_buf_ops, @@ -844,6 +887,12 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata) u32 axictl, sts; struct etr_buf *etr_buf = drvdata->etr_buf; + /* + * If this ETR is connected to a CATU, enable it before we turn + * this on + */ + tmc_etr_enable_catu(drvdata); + CS_UNLOCK(drvdata->base); /* Wait for TMCSReady bit to be set */ @@ -952,6 +1001,9 @@ static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) tmc_disable_hw(drvdata); CS_LOCK(drvdata->base); + + /* Disable CATU device if this ETR is connected to one */ + tmc_etr_disable_catu(drvdata); } static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 3d40a2b135f1..d828a6efe0b1 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -65,6 +65,7 @@ enum coresight_dev_subtype_source { enum coresight_dev_subtype_helper { CORESIGHT_DEV_SUBTYPE_HELPER_NONE, + CORESIGHT_DEV_SUBTYPE_HELPER_CATU, }; /** -- cgit v1.2.3-71-gd317 From 571d78bd458a831cf51dff2afa1dda3309bd82b2 Mon Sep 17 00:00:00 2001 From: Wu Hao Date: Sat, 30 Jun 2018 08:53:09 +0800 Subject: fpga: mgr: add region_id to fpga_image_info This patch adds region_id to fpga_image_info data structure, it allows driver to pass region id information to fpga-mgr via fpga_image_info for fpga reconfiguration function. Signed-off-by: Wu Hao Acked-by: Moritz Fischer Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman --- include/linux/fpga/fpga-mgr.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index eec7c2478b0d..3eb6b9d60d65 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -77,6 +77,7 @@ enum fpga_mgr_states { * @sgt: scatter/gather table containing FPGA image * @buf: contiguous buffer containing FPGA image * @count: size of buf + * @region_id: id of target region * @dev: device that owns this * @overlay: Device Tree overlay */ @@ -89,6 +90,7 @@ struct fpga_image_info { struct sg_table *sgt; const char *buf; size_t count; + int region_id; struct device *dev; #ifdef CONFIG_OF struct device_node *overlay; -- cgit v1.2.3-71-gd317 From ecb5fbe299dfaad778033259f35bc696fa1fb743 Mon Sep 17 00:00:00 2001 From: Wu Hao Date: Sat, 30 Jun 2018 08:53:10 +0800 Subject: fpga: mgr: add status for fpga-manager This patch adds status sysfs interface for fpga manager, it's a read only interface which allows user to get fpga manager status, including full/partial reconfiguration error and other status information. It adds a status callback to fpga_manager_ops too, allows each fpga_manager driver to define its own method to collect latest status from hardware. The following sysfs file is created: * /sys/class/fpga_manager//status Return status of fpga manager, including reconfiguration errors. Signed-off-by: Wu Hao Acked-by: Alan Tull Acked-by: Moritz Fischer Signed-off-by: Greg Kroah-Hartman --- Documentation/ABI/testing/sysfs-class-fpga-manager | 24 +++++++++++++++++++ drivers/fpga/fpga-mgr.c | 28 ++++++++++++++++++++++ include/linux/fpga/fpga-mgr.h | 9 +++++++ 3 files changed, 61 insertions(+) (limited to 'include') diff --git a/Documentation/ABI/testing/sysfs-class-fpga-manager b/Documentation/ABI/testing/sysfs-class-fpga-manager index 23056c532fdd..5284fa33d4c5 100644 --- a/Documentation/ABI/testing/sysfs-class-fpga-manager +++ b/Documentation/ABI/testing/sysfs-class-fpga-manager @@ -35,3 +35,27 @@ Description: Read fpga manager state as a string. * write complete = Doing post programming steps * write complete error = Error while doing post programming * operating = FPGA is programmed and operating + +What: /sys/class/fpga_manager//status +Date: June 2018 +KernelVersion: 4.19 +Contact: Wu Hao +Description: Read fpga manager status as a string. + If FPGA programming operation fails, it could be caused by crc + error or incompatible bitstream image. The intent of this + interface is to provide more detailed information for FPGA + programming errors to userspace. This is a list of strings for + the supported status. + + * reconfig operation error - invalid operations detected by + reconfiguration hardware. + e.g. start reconfiguration + with errors not cleared + * reconfig CRC error - CRC error detected by + reconfiguration hardware. + * reconfig incompatible image - reconfiguration image is + incompatible with hardware + * reconfig IP protocol error - protocol errors detected by + reconfiguration hardware + * reconfig fifo overflow error - FIFO overflow detected by + reconfiguration hardware diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index c1564cf827fe..a41b07e37884 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -406,12 +406,40 @@ static ssize_t state_show(struct device *dev, return sprintf(buf, "%s\n", state_str[mgr->state]); } +static ssize_t status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fpga_manager *mgr = to_fpga_manager(dev); + u64 status; + int len = 0; + + if (!mgr->mops->status) + return -ENOENT; + + status = mgr->mops->status(mgr); + + if (status & FPGA_MGR_STATUS_OPERATION_ERR) + len += sprintf(buf + len, "reconfig operation error\n"); + if (status & FPGA_MGR_STATUS_CRC_ERR) + len += sprintf(buf + len, "reconfig CRC error\n"); + if (status & FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR) + len += sprintf(buf + len, "reconfig incompatible image\n"); + if (status & FPGA_MGR_STATUS_IP_PROTOCOL_ERR) + len += sprintf(buf + len, "reconfig IP protocol error\n"); + if (status & FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR) + len += sprintf(buf + len, "reconfig fifo overflow error\n"); + + return len; +} + static DEVICE_ATTR_RO(name); static DEVICE_ATTR_RO(state); +static DEVICE_ATTR_RO(status); static struct attribute *fpga_mgr_attrs[] = { &dev_attr_name.attr, &dev_attr_state.attr, + &dev_attr_status.attr, NULL, }; ATTRIBUTE_GROUPS(fpga_mgr); diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index 3eb6b9d60d65..e249b7250345 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -101,6 +101,7 @@ struct fpga_image_info { * struct fpga_manager_ops - ops for low level fpga manager drivers * @initial_header_size: Maximum number of bytes that should be passed into write_init * @state: returns an enum value of the FPGA's state + * @status: returns status of the FPGA, including reconfiguration error code * @write_init: prepare the FPGA to receive confuration data * @write: write count bytes of configuration data to the FPGA * @write_sg: write the scatter list of configuration data to the FPGA @@ -115,6 +116,7 @@ struct fpga_image_info { struct fpga_manager_ops { size_t initial_header_size; enum fpga_mgr_states (*state)(struct fpga_manager *mgr); + u64 (*status)(struct fpga_manager *mgr); int (*write_init)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); @@ -126,6 +128,13 @@ struct fpga_manager_ops { const struct attribute_group **groups; }; +/* FPGA manager status: Partial/Full Reconfiguration errors */ +#define FPGA_MGR_STATUS_OPERATION_ERR BIT(0) +#define FPGA_MGR_STATUS_CRC_ERR BIT(1) +#define FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR BIT(2) +#define FPGA_MGR_STATUS_IP_PROTOCOL_ERR BIT(3) +#define FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR BIT(4) + /** * struct fpga_manager - fpga manager structure * @name: name of low level fpga manager -- cgit v1.2.3-71-gd317 From 99a560bde313892f87ca81db568a829d3d205882 Mon Sep 17 00:00:00 2001 From: Wu Hao Date: Sat, 30 Jun 2018 08:53:11 +0800 Subject: fpga: mgr: add compat_id support This patch introduces compat_id support to fpga manager, it adds a fpga_compat_id pointer to fpga manager data structure to allow fpga manager drivers to save the compatibility id. This compat_id could be used for compatibility checking before doing partial reconfiguration to associated fpga regions. Signed-off-by: Wu Hao Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman --- include/linux/fpga/fpga-mgr.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include') diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index e249b7250345..8942e61f0028 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -135,12 +135,24 @@ struct fpga_manager_ops { #define FPGA_MGR_STATUS_IP_PROTOCOL_ERR BIT(3) #define FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR BIT(4) +/** + * struct fpga_compat_id - id for compatibility check + * + * @id_h: high 64bit of the compat_id + * @id_l: low 64bit of the compat_id + */ +struct fpga_compat_id { + u64 id_h; + u64 id_l; +}; + /** * struct fpga_manager - fpga manager structure * @name: name of low level fpga manager * @dev: fpga manager device * @ref_mutex: only allows one reference to fpga manager * @state: state of fpga manager + * @compat_id: FPGA manager id for compatibility check. * @mops: pointer to struct of fpga manager ops * @priv: low level driver private date */ @@ -149,6 +161,7 @@ struct fpga_manager { struct device dev; struct mutex ref_mutex; enum fpga_mgr_states state; + struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; void *priv; }; -- cgit v1.2.3-71-gd317 From 41a8b2c56470b7e4e3e2db93324d50bbbf60cdc4 Mon Sep 17 00:00:00 2001 From: Wu Hao Date: Sat, 30 Jun 2018 08:53:12 +0800 Subject: fpga: region: add compat_id support This patch introduces a compat_id pointer member and sysfs interface for each fpga region, similar as compat_id for fpga manager, it allows applications to read the per region compat_id for compatibility checking before other actions on this fpga-region (e.g. PR). Signed-off-by: Wu Hao Acked-by: Alan Tull Acked-by: Moritz Fischer Signed-off-by: Greg Kroah-Hartman --- Documentation/ABI/testing/sysfs-class-fpga-region | 9 +++++++++ drivers/fpga/fpga-region.c | 22 ++++++++++++++++++++++ include/linux/fpga/fpga-region.h | 2 ++ 3 files changed, 33 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-class-fpga-region (limited to 'include') diff --git a/Documentation/ABI/testing/sysfs-class-fpga-region b/Documentation/ABI/testing/sysfs-class-fpga-region new file mode 100644 index 000000000000..bc7ec644acc9 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-fpga-region @@ -0,0 +1,9 @@ +What: /sys/class/fpga_region//compat_id +Date: June 2018 +KernelVersion: 4.19 +Contact: Wu Hao +Description: FPGA region id for compatibility check, e.g. compatibility + of the FPGA reconfiguration hardware and image. This value + is defined or calculated by the layer that is creating the + FPGA region. This interface returns the compat_id value or + just error code -ENOENT in case compat_id is not used. diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c index 6d214d75c7be..0d65220d5ec5 100644 --- a/drivers/fpga/fpga-region.c +++ b/drivers/fpga/fpga-region.c @@ -158,6 +158,27 @@ err_put_region: } EXPORT_SYMBOL_GPL(fpga_region_program_fpga); +static ssize_t compat_id_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fpga_region *region = to_fpga_region(dev); + + if (!region->compat_id) + return -ENOENT; + + return sprintf(buf, "%016llx%016llx\n", + (unsigned long long)region->compat_id->id_h, + (unsigned long long)region->compat_id->id_l); +} + +static DEVICE_ATTR_RO(compat_id); + +static struct attribute *fpga_region_attrs[] = { + &dev_attr_compat_id.attr, + NULL, +}; +ATTRIBUTE_GROUPS(fpga_region); + /** * fpga_region_create - alloc and init a struct fpga_region * @dev: device parent @@ -258,6 +279,7 @@ static int __init fpga_region_init(void) if (IS_ERR(fpga_region_class)) return PTR_ERR(fpga_region_class); + fpga_region_class->dev_groups = fpga_region_groups; fpga_region_class->dev_release = fpga_region_dev_release; return 0; diff --git a/include/linux/fpga/fpga-region.h b/include/linux/fpga/fpga-region.h index d7071cddd727..0521b7f577a4 100644 --- a/include/linux/fpga/fpga-region.h +++ b/include/linux/fpga/fpga-region.h @@ -14,6 +14,7 @@ * @bridge_list: list of FPGA bridges specified in region * @mgr: FPGA manager * @info: FPGA image info + * @compat_id: FPGA region id for compatibility check. * @priv: private data * @get_bridges: optional function to get bridges to a list */ @@ -23,6 +24,7 @@ struct fpga_region { struct list_head bridge_list; struct fpga_manager *mgr; struct fpga_image_info *info; + struct fpga_compat_id *compat_id; void *priv; int (*get_bridges)(struct fpga_region *region); }; -- cgit v1.2.3-71-gd317 From 620e1902f6fe57ddacdabd9e33fadbd290be9652 Mon Sep 17 00:00:00 2001 From: Wu Hao Date: Sat, 30 Jun 2018 08:53:23 +0800 Subject: fpga: dfl: fme: add DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support DFL_FPGA_GET_API_VERSION and DFL_FPGA_CHECK_EXTENSION ioctls are common ones which need to be supported by all feature devices drivers including FME and AFU. Userspace application can use these ioctl interfaces to get the API info and check if specific extension is supported or not in current driver. This patch implements above 2 ioctls in FPGA Management Engine (FME) driver. Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Xiao Guangrong Signed-off-by: Wu Hao Acked-by: Alan Tull Acked-by: Moritz Fischer Signed-off-by: Greg Kroah-Hartman --- Documentation/ioctl/ioctl-number.txt | 1 + drivers/fpga/dfl-fme-main.c | 12 +++++++++ include/uapi/linux/fpga-dfl.h | 50 ++++++++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+) create mode 100644 include/uapi/linux/fpga-dfl.h (limited to 'include') diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt index 480c8609dc58..db9afea24299 100644 --- a/Documentation/ioctl/ioctl-number.txt +++ b/Documentation/ioctl/ioctl-number.txt @@ -322,6 +322,7 @@ Code Seq#(hex) Include File Comments 0xB3 00 linux/mmc/ioctl.h 0xB4 00-0F linux/gpio.h 0xB5 00-0F uapi/linux/rpmsg.h +0xB6 all linux/fpga-dfl.h 0xC0 00-0F linux/usb/iowarrior.h 0xCA 00-0F uapi/misc/cxl.h 0xCA 10-2F uapi/misc/ocxl.h diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c index c23c56fe3f4b..c83ff88e3bbb 100644 --- a/drivers/fpga/dfl-fme-main.c +++ b/drivers/fpga/dfl-fme-main.c @@ -16,6 +16,7 @@ #include #include +#include #include "dfl.h" @@ -116,6 +117,13 @@ static struct dfl_feature_driver fme_feature_drvs[] = { }, }; +static long fme_ioctl_check_extension(struct dfl_feature_platform_data *pdata, + unsigned long arg) +{ + /* No extension support for now */ + return 0; +} + static int fme_open(struct inode *inode, struct file *filp) { struct platform_device *fdev = dfl_fpga_inode_to_feature_dev(inode); @@ -156,6 +164,10 @@ static long fme_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) dev_dbg(&pdev->dev, "%s cmd 0x%x\n", __func__, cmd); switch (cmd) { + case DFL_FPGA_GET_API_VERSION: + return DFL_FPGA_API_VERSION; + case DFL_FPGA_CHECK_EXTENSION: + return fme_ioctl_check_extension(pdata, arg); default: /* * Let sub-feature's ioctl function to handle the cmd. diff --git a/include/uapi/linux/fpga-dfl.h b/include/uapi/linux/fpga-dfl.h new file mode 100644 index 000000000000..858e4437c31c --- /dev/null +++ b/include/uapi/linux/fpga-dfl.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Header File for FPGA DFL User API + * + * Copyright (C) 2017-2018 Intel Corporation, Inc. + * + * Authors: + * Kang Luwei + * Zhang Yi + * Wu Hao + * Xiao Guangrong + */ + +#ifndef _UAPI_LINUX_FPGA_DFL_H +#define _UAPI_LINUX_FPGA_DFL_H + +#include + +#define DFL_FPGA_API_VERSION 0 + +/* + * The IOCTL interface for DFL based FPGA is designed for extensibility by + * embedding the structure length (argsz) and flags into structures passed + * between kernel and userspace. This design referenced the VFIO IOCTL + * interface (include/uapi/linux/vfio.h). + */ + +#define DFL_FPGA_MAGIC 0xB6 + +#define DFL_FPGA_BASE 0 + +/** + * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) + * + * Report the version of the driver API. + * Return: Driver API Version. + */ + +#define DFL_FPGA_GET_API_VERSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) + +/** + * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) + * + * Check whether an extension is supported. + * Return: 0 if not supported, otherwise the extension is supported. + */ + +#define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) + +#endif /* _UAPI_LINUX_FPGA_DFL_H */ -- cgit v1.2.3-71-gd317 From 29de76240e861d52b75405166337e94184f1875d Mon Sep 17 00:00:00 2001 From: Kang Luwei Date: Sat, 30 Jun 2018 08:53:24 +0800 Subject: fpga: dfl: fme: add partial reconfiguration sub feature support Partial Reconfiguration (PR) is the most important function for FME. It allows reconfiguration for given Port/Accelerated Function Unit (AFU). It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges, and invokes fpga-region's interface (fpga_region_program_fpga) for PR operation once PR request received via ioctl. Below user space interface is exposed by this sub feature. Ioctl interface: * DFL_FPGA_FME_PORT_PR Do partial reconfiguration per information from userspace, including target port(AFU), buffer size and address info. It returns error code to userspace if failed. For detailed PR error information, user needs to read fpga-mgr's status sysfs interface. Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Kang Luwei Signed-off-by: Xiao Guangrong Signed-off-by: Wu Hao Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman --- drivers/fpga/Makefile | 2 +- drivers/fpga/dfl-fme-main.c | 43 +++- drivers/fpga/dfl-fme-pr.c | 479 ++++++++++++++++++++++++++++++++++++++++++ drivers/fpga/dfl-fme-pr.h | 84 ++++++++ drivers/fpga/dfl-fme.h | 38 ++++ include/uapi/linux/fpga-dfl.h | 27 +++ 6 files changed, 671 insertions(+), 2 deletions(-) create mode 100644 drivers/fpga/dfl-fme-pr.c create mode 100644 drivers/fpga/dfl-fme-pr.h create mode 100644 drivers/fpga/dfl-fme.h (limited to 'include') diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index db11f340ba0f..fd334d40aa1c 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -33,7 +33,7 @@ obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o obj-$(CONFIG_FPGA_DFL) += dfl.o obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o -dfl-fme-objs := dfl-fme-main.o +dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o # Drivers for FPGAs which implement DFL obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c index c83ff88e3bbb..086ad2420ade 100644 --- a/drivers/fpga/dfl-fme-main.c +++ b/drivers/fpga/dfl-fme-main.c @@ -19,6 +19,7 @@ #include #include "dfl.h" +#include "dfl-fme.h" static ssize_t ports_num_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -112,6 +113,10 @@ static struct dfl_feature_driver fme_feature_drvs[] = { .id = FME_FEATURE_ID_HEADER, .ops = &fme_hdr_ops, }, + { + .id = FME_FEATURE_ID_PR_MGMT, + .ops = &pr_mgmt_ops, + }, { .ops = NULL, }, @@ -187,6 +192,35 @@ static long fme_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return -EINVAL; } +static int fme_dev_init(struct platform_device *pdev) +{ + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); + struct dfl_fme *fme; + + fme = devm_kzalloc(&pdev->dev, sizeof(*fme), GFP_KERNEL); + if (!fme) + return -ENOMEM; + + fme->pdata = pdata; + + mutex_lock(&pdata->lock); + dfl_fpga_pdata_set_private(pdata, fme); + mutex_unlock(&pdata->lock); + + return 0; +} + +static void fme_dev_destroy(struct platform_device *pdev) +{ + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); + struct dfl_fme *fme; + + mutex_lock(&pdata->lock); + fme = dfl_fpga_pdata_get_private(pdata); + dfl_fpga_pdata_set_private(pdata, NULL); + mutex_unlock(&pdata->lock); +} + static const struct file_operations fme_fops = { .owner = THIS_MODULE, .open = fme_open, @@ -198,10 +232,14 @@ static int fme_probe(struct platform_device *pdev) { int ret; - ret = dfl_fpga_dev_feature_init(pdev, fme_feature_drvs); + ret = fme_dev_init(pdev); if (ret) goto exit; + ret = dfl_fpga_dev_feature_init(pdev, fme_feature_drvs); + if (ret) + goto dev_destroy; + ret = dfl_fpga_dev_ops_register(pdev, &fme_fops, THIS_MODULE); if (ret) goto feature_uinit; @@ -210,6 +248,8 @@ static int fme_probe(struct platform_device *pdev) feature_uinit: dfl_fpga_dev_feature_uinit(pdev); +dev_destroy: + fme_dev_destroy(pdev); exit: return ret; } @@ -218,6 +258,7 @@ static int fme_remove(struct platform_device *pdev) { dfl_fpga_dev_ops_unregister(pdev); dfl_fpga_dev_feature_uinit(pdev); + fme_dev_destroy(pdev); return 0; } diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c new file mode 100644 index 000000000000..fc9fd2d0482f --- /dev/null +++ b/drivers/fpga/dfl-fme-pr.c @@ -0,0 +1,479 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for FPGA Management Engine (FME) Partial Reconfiguration + * + * Copyright (C) 2017-2018 Intel Corporation, Inc. + * + * Authors: + * Kang Luwei + * Xiao Guangrong + * Wu Hao + * Joseph Grecco + * Enno Luebbers + * Tim Whisonant + * Ananda Ravuri + * Christopher Rauer + * Henry Mitchel + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dfl.h" +#include "dfl-fme.h" +#include "dfl-fme-pr.h" + +static struct dfl_fme_region * +dfl_fme_region_find_by_port_id(struct dfl_fme *fme, int port_id) +{ + struct dfl_fme_region *fme_region; + + list_for_each_entry(fme_region, &fme->region_list, node) + if (fme_region->port_id == port_id) + return fme_region; + + return NULL; +} + +static int dfl_fme_region_match(struct device *dev, const void *data) +{ + return dev->parent == data; +} + +static struct fpga_region *dfl_fme_region_find(struct dfl_fme *fme, int port_id) +{ + struct dfl_fme_region *fme_region; + struct fpga_region *region; + + fme_region = dfl_fme_region_find_by_port_id(fme, port_id); + if (!fme_region) + return NULL; + + region = fpga_region_class_find(NULL, &fme_region->region->dev, + dfl_fme_region_match); + if (!region) + return NULL; + + return region; +} + +static int fme_pr(struct platform_device *pdev, unsigned long arg) +{ + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); + void __user *argp = (void __user *)arg; + struct dfl_fpga_fme_port_pr port_pr; + struct fpga_image_info *info; + struct fpga_region *region; + void __iomem *fme_hdr; + struct dfl_fme *fme; + unsigned long minsz; + void *buf = NULL; + int ret = 0; + u64 v; + + minsz = offsetofend(struct dfl_fpga_fme_port_pr, buffer_address); + + if (copy_from_user(&port_pr, argp, minsz)) + return -EFAULT; + + if (port_pr.argsz < minsz || port_pr.flags) + return -EINVAL; + + if (!IS_ALIGNED(port_pr.buffer_size, 4)) + return -EINVAL; + + /* get fme header region */ + fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev, + FME_FEATURE_ID_HEADER); + + /* check port id */ + v = readq(fme_hdr + FME_HDR_CAP); + if (port_pr.port_id >= FIELD_GET(FME_CAP_NUM_PORTS, v)) { + dev_dbg(&pdev->dev, "port number more than maximum\n"); + return -EINVAL; + } + + if (!access_ok(VERIFY_READ, + (void __user *)(unsigned long)port_pr.buffer_address, + port_pr.buffer_size)) + return -EFAULT; + + buf = vmalloc(port_pr.buffer_size); + if (!buf) + return -ENOMEM; + + if (copy_from_user(buf, + (void __user *)(unsigned long)port_pr.buffer_address, + port_pr.buffer_size)) { + ret = -EFAULT; + goto free_exit; + } + + /* prepare fpga_image_info for PR */ + info = fpga_image_info_alloc(&pdev->dev); + if (!info) { + ret = -ENOMEM; + goto free_exit; + } + + info->flags |= FPGA_MGR_PARTIAL_RECONFIG; + + mutex_lock(&pdata->lock); + fme = dfl_fpga_pdata_get_private(pdata); + /* fme device has been unregistered. */ + if (!fme) { + ret = -EINVAL; + goto unlock_exit; + } + + region = dfl_fme_region_find(fme, port_pr.port_id); + if (!region) { + ret = -EINVAL; + goto unlock_exit; + } + + fpga_image_info_free(region->info); + + info->buf = buf; + info->count = port_pr.buffer_size; + info->region_id = port_pr.port_id; + region->info = info; + + ret = fpga_region_program_fpga(region); + + /* + * it allows userspace to reset the PR region's logic by disabling and + * reenabling the bridge to clear things out between accleration runs. + * so no need to hold the bridges after partial reconfiguration. + */ + if (region->get_bridges) + fpga_bridges_put(®ion->bridge_list); + + put_device(®ion->dev); +unlock_exit: + mutex_unlock(&pdata->lock); +free_exit: + vfree(buf); + if (copy_to_user((void __user *)arg, &port_pr, minsz)) + return -EFAULT; + + return ret; +} + +/** + * dfl_fme_create_mgr - create fpga mgr platform device as child device + * + * @pdata: fme platform_device's pdata + * + * Return: mgr platform device if successful, and error code otherwise. + */ +static struct platform_device * +dfl_fme_create_mgr(struct dfl_feature_platform_data *pdata, + struct dfl_feature *feature) +{ + struct platform_device *mgr, *fme = pdata->dev; + struct dfl_fme_mgr_pdata mgr_pdata; + int ret = -ENOMEM; + + if (!feature->ioaddr) + return ERR_PTR(-ENODEV); + + mgr_pdata.ioaddr = feature->ioaddr; + + /* + * Each FME has only one fpga-mgr, so allocate platform device using + * the same FME platform device id. + */ + mgr = platform_device_alloc(DFL_FPGA_FME_MGR, fme->id); + if (!mgr) + return ERR_PTR(ret); + + mgr->dev.parent = &fme->dev; + + ret = platform_device_add_data(mgr, &mgr_pdata, sizeof(mgr_pdata)); + if (ret) + goto create_mgr_err; + + ret = platform_device_add(mgr); + if (ret) + goto create_mgr_err; + + return mgr; + +create_mgr_err: + platform_device_put(mgr); + return ERR_PTR(ret); +} + +/** + * dfl_fme_destroy_mgr - destroy fpga mgr platform device + * @pdata: fme platform device's pdata + */ +static void dfl_fme_destroy_mgr(struct dfl_feature_platform_data *pdata) +{ + struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata); + + platform_device_unregister(priv->mgr); +} + +/** + * dfl_fme_create_bridge - create fme fpga bridge platform device as child + * + * @pdata: fme platform device's pdata + * @port_id: port id for the bridge to be created. + * + * Return: bridge platform device if successful, and error code otherwise. + */ +static struct dfl_fme_bridge * +dfl_fme_create_bridge(struct dfl_feature_platform_data *pdata, int port_id) +{ + struct device *dev = &pdata->dev->dev; + struct dfl_fme_br_pdata br_pdata; + struct dfl_fme_bridge *fme_br; + int ret = -ENOMEM; + + fme_br = devm_kzalloc(dev, sizeof(*fme_br), GFP_KERNEL); + if (!fme_br) + return ERR_PTR(ret); + + br_pdata.cdev = pdata->dfl_cdev; + br_pdata.port_id = port_id; + + fme_br->br = platform_device_alloc(DFL_FPGA_FME_BRIDGE, + PLATFORM_DEVID_AUTO); + if (!fme_br->br) + return ERR_PTR(ret); + + fme_br->br->dev.parent = dev; + + ret = platform_device_add_data(fme_br->br, &br_pdata, sizeof(br_pdata)); + if (ret) + goto create_br_err; + + ret = platform_device_add(fme_br->br); + if (ret) + goto create_br_err; + + return fme_br; + +create_br_err: + platform_device_put(fme_br->br); + return ERR_PTR(ret); +} + +/** + * dfl_fme_destroy_bridge - destroy fpga bridge platform device + * @fme_br: fme bridge to destroy + */ +static void dfl_fme_destroy_bridge(struct dfl_fme_bridge *fme_br) +{ + platform_device_unregister(fme_br->br); +} + +/** + * dfl_fme_destroy_bridge - destroy all fpga bridge platform device + * @pdata: fme platform device's pdata + */ +static void dfl_fme_destroy_bridges(struct dfl_feature_platform_data *pdata) +{ + struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata); + struct dfl_fme_bridge *fbridge, *tmp; + + list_for_each_entry_safe(fbridge, tmp, &priv->bridge_list, node) { + list_del(&fbridge->node); + dfl_fme_destroy_bridge(fbridge); + } +} + +/** + * dfl_fme_create_region - create fpga region platform device as child + * + * @pdata: fme platform device's pdata + * @mgr: mgr platform device needed for region + * @br: br platform device needed for region + * @port_id: port id + * + * Return: fme region if successful, and error code otherwise. + */ +static struct dfl_fme_region * +dfl_fme_create_region(struct dfl_feature_platform_data *pdata, + struct platform_device *mgr, + struct platform_device *br, int port_id) +{ + struct dfl_fme_region_pdata region_pdata; + struct device *dev = &pdata->dev->dev; + struct dfl_fme_region *fme_region; + int ret = -ENOMEM; + + fme_region = devm_kzalloc(dev, sizeof(*fme_region), GFP_KERNEL); + if (!fme_region) + return ERR_PTR(ret); + + region_pdata.mgr = mgr; + region_pdata.br = br; + + /* + * Each FPGA device may have more than one port, so allocate platform + * device using the same port platform device id. + */ + fme_region->region = platform_device_alloc(DFL_FPGA_FME_REGION, br->id); + if (!fme_region->region) + return ERR_PTR(ret); + + fme_region->region->dev.parent = dev; + + ret = platform_device_add_data(fme_region->region, ®ion_pdata, + sizeof(region_pdata)); + if (ret) + goto create_region_err; + + ret = platform_device_add(fme_region->region); + if (ret) + goto create_region_err; + + fme_region->port_id = port_id; + + return fme_region; + +create_region_err: + platform_device_put(fme_region->region); + return ERR_PTR(ret); +} + +/** + * dfl_fme_destroy_region - destroy fme region + * @fme_region: fme region to destroy + */ +static void dfl_fme_destroy_region(struct dfl_fme_region *fme_region) +{ + platform_device_unregister(fme_region->region); +} + +/** + * dfl_fme_destroy_regions - destroy all fme regions + * @pdata: fme platform device's pdata + */ +static void dfl_fme_destroy_regions(struct dfl_feature_platform_data *pdata) +{ + struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata); + struct dfl_fme_region *fme_region, *tmp; + + list_for_each_entry_safe(fme_region, tmp, &priv->region_list, node) { + list_del(&fme_region->node); + dfl_fme_destroy_region(fme_region); + } +} + +static int pr_mgmt_init(struct platform_device *pdev, + struct dfl_feature *feature) +{ + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); + struct dfl_fme_region *fme_region; + struct dfl_fme_bridge *fme_br; + struct platform_device *mgr; + struct dfl_fme *priv; + void __iomem *fme_hdr; + int ret = -ENODEV, i = 0; + u64 fme_cap, port_offset; + + fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev, + FME_FEATURE_ID_HEADER); + + mutex_lock(&pdata->lock); + priv = dfl_fpga_pdata_get_private(pdata); + + /* Initialize the region and bridge sub device list */ + INIT_LIST_HEAD(&priv->region_list); + INIT_LIST_HEAD(&priv->bridge_list); + + /* Create fpga mgr platform device */ + mgr = dfl_fme_create_mgr(pdata, feature); + if (IS_ERR(mgr)) { + dev_err(&pdev->dev, "fail to create fpga mgr pdev\n"); + goto unlock; + } + + priv->mgr = mgr; + + /* Read capability register to check number of regions and bridges */ + fme_cap = readq(fme_hdr + FME_HDR_CAP); + for (; i < FIELD_GET(FME_CAP_NUM_PORTS, fme_cap); i++) { + port_offset = readq(fme_hdr + FME_HDR_PORT_OFST(i)); + if (!(port_offset & FME_PORT_OFST_IMP)) + continue; + + /* Create bridge for each port */ + fme_br = dfl_fme_create_bridge(pdata, i); + if (IS_ERR(fme_br)) { + ret = PTR_ERR(fme_br); + goto destroy_region; + } + + list_add(&fme_br->node, &priv->bridge_list); + + /* Create region for each port */ + fme_region = dfl_fme_create_region(pdata, mgr, + fme_br->br, i); + if (!fme_region) { + ret = PTR_ERR(fme_region); + goto destroy_region; + } + + list_add(&fme_region->node, &priv->region_list); + } + mutex_unlock(&pdata->lock); + + return 0; + +destroy_region: + dfl_fme_destroy_regions(pdata); + dfl_fme_destroy_bridges(pdata); + dfl_fme_destroy_mgr(pdata); +unlock: + mutex_unlock(&pdata->lock); + return ret; +} + +static void pr_mgmt_uinit(struct platform_device *pdev, + struct dfl_feature *feature) +{ + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); + struct dfl_fme *priv; + + mutex_lock(&pdata->lock); + priv = dfl_fpga_pdata_get_private(pdata); + + dfl_fme_destroy_regions(pdata); + dfl_fme_destroy_bridges(pdata); + dfl_fme_destroy_mgr(pdata); + mutex_unlock(&pdata->lock); +} + +static long fme_pr_ioctl(struct platform_device *pdev, + struct dfl_feature *feature, + unsigned int cmd, unsigned long arg) +{ + long ret; + + switch (cmd) { + case DFL_FPGA_FME_PORT_PR: + ret = fme_pr(pdev, arg); + break; + default: + ret = -ENODEV; + } + + return ret; +} + +const struct dfl_feature_ops pr_mgmt_ops = { + .init = pr_mgmt_init, + .uinit = pr_mgmt_uinit, + .ioctl = fme_pr_ioctl, +}; diff --git a/drivers/fpga/dfl-fme-pr.h b/drivers/fpga/dfl-fme-pr.h new file mode 100644 index 000000000000..096a699089d3 --- /dev/null +++ b/drivers/fpga/dfl-fme-pr.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver + * + * Copyright (C) 2017-2018 Intel Corporation, Inc. + * + * Authors: + * Kang Luwei + * Xiao Guangrong + * Wu Hao + * Joseph Grecco + * Enno Luebbers + * Tim Whisonant + * Ananda Ravuri + * Henry Mitchel + */ + +#ifndef __DFL_FME_PR_H +#define __DFL_FME_PR_H + +#include + +/** + * struct dfl_fme_region - FME fpga region data structure + * + * @region: platform device of the FPGA region. + * @node: used to link fme_region to a list. + * @port_id: indicate which port this region connected to. + */ +struct dfl_fme_region { + struct platform_device *region; + struct list_head node; + int port_id; +}; + +/** + * struct dfl_fme_region_pdata - platform data for FME region platform device. + * + * @mgr: platform device of the FPGA manager. + * @br: platform device of the FPGA bridge. + * @region_id: region id (same as port_id). + */ +struct dfl_fme_region_pdata { + struct platform_device *mgr; + struct platform_device *br; + int region_id; +}; + +/** + * struct dfl_fme_bridge - FME fpga bridge data structure + * + * @br: platform device of the FPGA bridge. + * @node: used to link fme_bridge to a list. + */ +struct dfl_fme_bridge { + struct platform_device *br; + struct list_head node; +}; + +/** + * struct dfl_fme_bridge_pdata - platform data for FME bridge platform device. + * + * @cdev: container device. + * @port_id: port id. + */ +struct dfl_fme_br_pdata { + struct dfl_fpga_cdev *cdev; + int port_id; +}; + +/** + * struct dfl_fme_mgr_pdata - platform data for FME manager platform device. + * + * @ioaddr: mapped io address for FME manager platform device. + */ +struct dfl_fme_mgr_pdata { + void __iomem *ioaddr; +}; + +#define DFL_FPGA_FME_MGR "dfl-fme-mgr" +#define DFL_FPGA_FME_BRIDGE "dfl-fme-bridge" +#define DFL_FPGA_FME_REGION "dfl-fme-region" + +#endif /* __DFL_FME_PR_H */ diff --git a/drivers/fpga/dfl-fme.h b/drivers/fpga/dfl-fme.h new file mode 100644 index 000000000000..5394a216c5c0 --- /dev/null +++ b/drivers/fpga/dfl-fme.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Header file for FPGA Management Engine (FME) Driver + * + * Copyright (C) 2017-2018 Intel Corporation, Inc. + * + * Authors: + * Kang Luwei + * Xiao Guangrong + * Wu Hao + * Joseph Grecco + * Enno Luebbers + * Tim Whisonant + * Ananda Ravuri + * Henry Mitchel + */ + +#ifndef __DFL_FME_H +#define __DFL_FME_H + +/** + * struct dfl_fme - dfl fme private data + * + * @mgr: FME's FPGA manager platform device. + * @region_list: linked list of FME's FPGA regions. + * @bridge_list: linked list of FME's FPGA bridges. + * @pdata: fme platform device's pdata. + */ +struct dfl_fme { + struct platform_device *mgr; + struct list_head region_list; + struct list_head bridge_list; + struct dfl_feature_platform_data *pdata; +}; + +extern const struct dfl_feature_ops pr_mgmt_ops; + +#endif /* __DFL_FME_H */ diff --git a/include/uapi/linux/fpga-dfl.h b/include/uapi/linux/fpga-dfl.h index 858e4437c31c..9666af85a8f5 100644 --- a/include/uapi/linux/fpga-dfl.h +++ b/include/uapi/linux/fpga-dfl.h @@ -14,6 +14,7 @@ #ifndef _UAPI_LINUX_FPGA_DFL_H #define _UAPI_LINUX_FPGA_DFL_H +#include #include #define DFL_FPGA_API_VERSION 0 @@ -28,6 +29,7 @@ #define DFL_FPGA_MAGIC 0xB6 #define DFL_FPGA_BASE 0 +#define DFL_FME_BASE 0x80 /** * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) @@ -47,4 +49,29 @@ #define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) +/* IOCTLs for FME file descriptor */ + +/** + * DFL_FPGA_FME_PORT_PR - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 0, + * struct dfl_fpga_fme_port_pr) + * + * Driver does Partial Reconfiguration based on Port ID and Buffer (Image) + * provided by caller. + * Return: 0 on success, -errno on failure. + * If DFL_FPGA_FME_PORT_PR returns -EIO, that indicates the HW has detected + * some errors during PR, under this case, the user can fetch HW error info + * from the status of FME's fpga manager. + */ + +struct dfl_fpga_fme_port_pr { + /* Input */ + __u32 argsz; /* Structure length */ + __u32 flags; /* Zero for now */ + __u32 port_id; + __u32 buffer_size; + __u64 buffer_address; /* Userspace address to the buffer for PR */ +}; + +#define DFL_FPGA_FME_PORT_PR _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0) + #endif /* _UAPI_LINUX_FPGA_DFL_H */ -- cgit v1.2.3-71-gd317 From e4664c0ee4ac44993c62d10b048ab0a960691da5 Mon Sep 17 00:00:00 2001 From: Wu Hao Date: Sat, 30 Jun 2018 08:53:32 +0800 Subject: fpga: dfl: afu: add header sub feature support The port header register set is always present for port, it is mainly for capability, control and status of the ports that AFU connected to. This patch implements header sub feature support. Below user interfaces are created by this patch. Sysfs interface: * /sys/class/fpga_region///id Read-only. Port ID. Ioctl interface: * DFL_FPGA_PORT_RESET Reset the FPGA Port and its AFU. Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Xiao Guangrong Signed-off-by: Wu Hao Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman --- Documentation/ABI/testing/sysfs-platform-dfl-port | 7 ++ drivers/fpga/dfl-afu-main.c | 79 ++++++++++++++++++++++- include/uapi/linux/fpga-dfl.h | 17 +++++ 3 files changed, 102 insertions(+), 1 deletion(-) create mode 100644 Documentation/ABI/testing/sysfs-platform-dfl-port (limited to 'include') diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-port b/Documentation/ABI/testing/sysfs-platform-dfl-port new file mode 100644 index 000000000000..cb91165f5397 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-dfl-port @@ -0,0 +1,7 @@ +What: /sys/bus/platform/devices/dfl-port.0/id +Date: June 2018 +KernelVersion: 4.19 +Contact: Wu Hao +Description: Read-only. It returns id of this port. One DFL FPGA device + may have more than one port. Userspace could use this id to + distinguish different ports under same FPGA device. diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c index a38d6a825e7e..d36b3e9f3984 100644 --- a/drivers/fpga/dfl-afu-main.c +++ b/drivers/fpga/dfl-afu-main.c @@ -16,6 +16,7 @@ #include #include +#include #include "dfl.h" @@ -87,6 +88,41 @@ static int port_disable(struct platform_device *pdev) return 0; } +/* + * This function resets the FPGA Port and its accelerator (AFU) by function + * __port_disable and __port_enable (set port soft reset bit and then clear + * it). Userspace can do Port reset at any time, e.g. during DMA or Partial + * Reconfiguration. But it should never cause any system level issue, only + * functional failure (e.g. DMA or PR operation failure) and be recoverable + * from the failure. + * + * Note: the accelerator (AFU) is not accessible when its port is in reset + * (disabled). Any attempts on MMIO access to AFU while in reset, will + * result errors reported via port error reporting sub feature (if present). + */ +static int __port_reset(struct platform_device *pdev) +{ + int ret; + + ret = port_disable(pdev); + if (!ret) + port_enable(pdev); + + return ret; +} + +static int port_reset(struct platform_device *pdev) +{ + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); + int ret; + + mutex_lock(&pdata->lock); + ret = __port_reset(pdev); + mutex_unlock(&pdata->lock); + + return ret; +} + static int port_get_id(struct platform_device *pdev) { void __iomem *base; @@ -96,23 +132,63 @@ static int port_get_id(struct platform_device *pdev) return FIELD_GET(PORT_CAP_PORT_NUM, readq(base + PORT_HDR_CAP)); } +static ssize_t +id_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + int id = port_get_id(to_platform_device(dev)); + + return scnprintf(buf, PAGE_SIZE, "%d\n", id); +} +static DEVICE_ATTR_RO(id); + +static const struct attribute *port_hdr_attrs[] = { + &dev_attr_id.attr, + NULL, +}; + static int port_hdr_init(struct platform_device *pdev, struct dfl_feature *feature) { dev_dbg(&pdev->dev, "PORT HDR Init.\n"); - return 0; + port_reset(pdev); + + return sysfs_create_files(&pdev->dev.kobj, port_hdr_attrs); } static void port_hdr_uinit(struct platform_device *pdev, struct dfl_feature *feature) { dev_dbg(&pdev->dev, "PORT HDR UInit.\n"); + + sysfs_remove_files(&pdev->dev.kobj, port_hdr_attrs); +} + +static long +port_hdr_ioctl(struct platform_device *pdev, struct dfl_feature *feature, + unsigned int cmd, unsigned long arg) +{ + long ret; + + switch (cmd) { + case DFL_FPGA_PORT_RESET: + if (!arg) + ret = port_reset(pdev); + else + ret = -EINVAL; + break; + default: + dev_dbg(&pdev->dev, "%x cmd not handled", cmd); + ret = -ENODEV; + } + + return ret; } static const struct dfl_feature_ops port_hdr_ops = { .init = port_hdr_init, .uinit = port_hdr_uinit, + .ioctl = port_hdr_ioctl, }; static struct dfl_feature_driver port_feature_drvs[] = { @@ -154,6 +230,7 @@ static int afu_release(struct inode *inode, struct file *filp) pdata = dev_get_platdata(&pdev->dev); + port_reset(pdev); dfl_feature_dev_use_end(pdata); return 0; diff --git a/include/uapi/linux/fpga-dfl.h b/include/uapi/linux/fpga-dfl.h index 9666af85a8f5..e6b4dd26cc68 100644 --- a/include/uapi/linux/fpga-dfl.h +++ b/include/uapi/linux/fpga-dfl.h @@ -29,8 +29,11 @@ #define DFL_FPGA_MAGIC 0xB6 #define DFL_FPGA_BASE 0 +#define DFL_PORT_BASE 0x40 #define DFL_FME_BASE 0x80 +/* Common IOCTLs for both FME and AFU file descriptor */ + /** * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) * @@ -49,6 +52,20 @@ #define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) +/* IOCTLs for AFU file descriptor */ + +/** + * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0) + * + * Reset the FPGA Port and its AFU. No parameters are supported. + * Userspace can do Port reset at any time, e.g. during DMA or PR. But + * it should never cause any system level issue, only functional failure + * (e.g. DMA or PR operation failure) and be recoverable from the failure. + * Return: 0 on success, -errno of failure + */ + +#define DFL_FPGA_PORT_RESET _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0) + /* IOCTLs for FME file descriptor */ /** -- cgit v1.2.3-71-gd317 From 857a26222ff75eecf7d701ef0e91e4fbf6efa663 Mon Sep 17 00:00:00 2001 From: Xiao Guangrong Date: Sat, 30 Jun 2018 08:53:34 +0800 Subject: fpga: dfl: afu: add afu sub feature support User Accelerated Function Unit sub feature exposes the MMIO region of the AFU. After valid PR bitstream is programmed and the port is enabled, then this MMIO region could be accessed. This patch adds support to enumerate the AFU MMIO region and expose it to userspace via mmap file operation. Below interfaces are exposed to user: Sysfs interface: * /sys/class/fpga_region///afu_id Read-only. Indicate which PR bitstream is programmed to this AFU. Ioctl interfaces: * DFL_FPGA_PORT_GET_INFO Provide info to userspace on the number of supported region. Only UAFU region is supported now. * DFL_FPGA_PORT_GET_REGION_INFO Provide region information, including access permission, region size, offset from the start of device fd. Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Xiao Guangrong Signed-off-by: Wu Hao Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman --- Documentation/ABI/testing/sysfs-platform-dfl-port | 9 + drivers/fpga/Makefile | 2 +- drivers/fpga/dfl-afu-main.c | 219 +++++++++++++++++++++- drivers/fpga/dfl-afu-region.c | 166 ++++++++++++++++ drivers/fpga/dfl-afu.h | 71 +++++++ include/uapi/linux/fpga-dfl.h | 48 +++++ 6 files changed, 508 insertions(+), 7 deletions(-) create mode 100644 drivers/fpga/dfl-afu-region.c create mode 100644 drivers/fpga/dfl-afu.h (limited to 'include') diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-port b/Documentation/ABI/testing/sysfs-platform-dfl-port index cb91165f5397..6a92dda517b0 100644 --- a/Documentation/ABI/testing/sysfs-platform-dfl-port +++ b/Documentation/ABI/testing/sysfs-platform-dfl-port @@ -5,3 +5,12 @@ Contact: Wu Hao Description: Read-only. It returns id of this port. One DFL FPGA device may have more than one port. Userspace could use this id to distinguish different ports under same FPGA device. + +What: /sys/bus/platform/devices/dfl-port.0/afu_id +Date: June 2018 +KernelVersion: 4.19 +Contact: Wu Hao +Description: Read-only. User can program different PR bitstreams to FPGA + Accelerator Function Unit (AFU) for different functions. It + returns uuid which could be used to identify which PR bitstream + is programmed in this AFU. diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 1ac7749b2542..a44d50dd0b70 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -38,7 +38,7 @@ obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o -dfl-afu-objs := dfl-afu-main.o +dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o # Drivers for FPGAs which implement DFL obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c index 4074b97122e2..f67a78d7e9ad 100644 --- a/drivers/fpga/dfl-afu-main.c +++ b/drivers/fpga/dfl-afu-main.c @@ -16,18 +16,18 @@ #include #include +#include #include -#include "dfl.h" +#include "dfl-afu.h" /** * port_enable - enable a port * @pdev: port platform device. * * Enable Port by clear the port soft reset bit, which is set by default. - * The User AFU is unable to respond to any MMIO access while in reset. - * port_enable function should only be used after port_disable - * function. + * The AFU is unable to respond to any MMIO access while in reset. + * port_enable function should only be used after port_disable function. */ static void port_enable(struct platform_device *pdev) { @@ -191,11 +191,74 @@ static const struct dfl_feature_ops port_hdr_ops = { .ioctl = port_hdr_ioctl, }; +static ssize_t +afu_id_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); + void __iomem *base; + u64 guidl, guidh; + + base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_AFU); + + mutex_lock(&pdata->lock); + if (pdata->disable_count) { + mutex_unlock(&pdata->lock); + return -EBUSY; + } + + guidl = readq(base + GUID_L); + guidh = readq(base + GUID_H); + mutex_unlock(&pdata->lock); + + return scnprintf(buf, PAGE_SIZE, "%016llx%016llx\n", guidh, guidl); +} +static DEVICE_ATTR_RO(afu_id); + +static const struct attribute *port_afu_attrs[] = { + &dev_attr_afu_id.attr, + NULL +}; + +static int port_afu_init(struct platform_device *pdev, + struct dfl_feature *feature) +{ + struct resource *res = &pdev->resource[feature->resource_index]; + int ret; + + dev_dbg(&pdev->dev, "PORT AFU Init.\n"); + + ret = afu_mmio_region_add(dev_get_platdata(&pdev->dev), + DFL_PORT_REGION_INDEX_AFU, resource_size(res), + res->start, DFL_PORT_REGION_READ | + DFL_PORT_REGION_WRITE | DFL_PORT_REGION_MMAP); + if (ret) + return ret; + + return sysfs_create_files(&pdev->dev.kobj, port_afu_attrs); +} + +static void port_afu_uinit(struct platform_device *pdev, + struct dfl_feature *feature) +{ + dev_dbg(&pdev->dev, "PORT AFU UInit.\n"); + + sysfs_remove_files(&pdev->dev.kobj, port_afu_attrs); +} + +static const struct dfl_feature_ops port_afu_ops = { + .init = port_afu_init, + .uinit = port_afu_uinit, +}; + static struct dfl_feature_driver port_feature_drvs[] = { { .id = PORT_FEATURE_ID_HEADER, .ops = &port_hdr_ops, }, + { + .id = PORT_FEATURE_ID_AFU, + .ops = &port_afu_ops, + }, { .ops = NULL, } @@ -243,6 +306,64 @@ static long afu_ioctl_check_extension(struct dfl_feature_platform_data *pdata, return 0; } +static long +afu_ioctl_get_info(struct dfl_feature_platform_data *pdata, void __user *arg) +{ + struct dfl_fpga_port_info info; + struct dfl_afu *afu; + unsigned long minsz; + + minsz = offsetofend(struct dfl_fpga_port_info, num_umsgs); + + if (copy_from_user(&info, arg, minsz)) + return -EFAULT; + + if (info.argsz < minsz) + return -EINVAL; + + mutex_lock(&pdata->lock); + afu = dfl_fpga_pdata_get_private(pdata); + info.flags = 0; + info.num_regions = afu->num_regions; + info.num_umsgs = afu->num_umsgs; + mutex_unlock(&pdata->lock); + + if (copy_to_user(arg, &info, sizeof(info))) + return -EFAULT; + + return 0; +} + +static long afu_ioctl_get_region_info(struct dfl_feature_platform_data *pdata, + void __user *arg) +{ + struct dfl_fpga_port_region_info rinfo; + struct dfl_afu_mmio_region region; + unsigned long minsz; + long ret; + + minsz = offsetofend(struct dfl_fpga_port_region_info, offset); + + if (copy_from_user(&rinfo, arg, minsz)) + return -EFAULT; + + if (rinfo.argsz < minsz || rinfo.padding) + return -EINVAL; + + ret = afu_mmio_region_get_by_index(pdata, rinfo.index, ®ion); + if (ret) + return ret; + + rinfo.flags = region.flags; + rinfo.size = region.size; + rinfo.offset = region.offset; + + if (copy_to_user(arg, &rinfo, sizeof(rinfo))) + return -EFAULT; + + return 0; +} + static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { struct platform_device *pdev = filp->private_data; @@ -259,6 +380,10 @@ static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return DFL_FPGA_API_VERSION; case DFL_FPGA_CHECK_EXTENSION: return afu_ioctl_check_extension(pdata, arg); + case DFL_FPGA_PORT_GET_INFO: + return afu_ioctl_get_info(pdata, (void __user *)arg); + case DFL_FPGA_PORT_GET_REGION_INFO: + return afu_ioctl_get_region_info(pdata, (void __user *)arg); default: /* * Let sub-feature's ioctl function to handle the cmd @@ -277,13 +402,83 @@ static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return -EINVAL; } +static int afu_mmap(struct file *filp, struct vm_area_struct *vma) +{ + struct platform_device *pdev = filp->private_data; + struct dfl_feature_platform_data *pdata; + u64 size = vma->vm_end - vma->vm_start; + struct dfl_afu_mmio_region region; + u64 offset; + int ret; + + if (!(vma->vm_flags & VM_SHARED)) + return -EINVAL; + + pdata = dev_get_platdata(&pdev->dev); + + offset = vma->vm_pgoff << PAGE_SHIFT; + ret = afu_mmio_region_get_by_offset(pdata, offset, size, ®ion); + if (ret) + return ret; + + if (!(region.flags & DFL_PORT_REGION_MMAP)) + return -EINVAL; + + if ((vma->vm_flags & VM_READ) && !(region.flags & DFL_PORT_REGION_READ)) + return -EPERM; + + if ((vma->vm_flags & VM_WRITE) && + !(region.flags & DFL_PORT_REGION_WRITE)) + return -EPERM; + + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + return remap_pfn_range(vma, vma->vm_start, + (region.phys + (offset - region.offset)) >> PAGE_SHIFT, + size, vma->vm_page_prot); +} + static const struct file_operations afu_fops = { .owner = THIS_MODULE, .open = afu_open, .release = afu_release, .unlocked_ioctl = afu_ioctl, + .mmap = afu_mmap, }; +static int afu_dev_init(struct platform_device *pdev) +{ + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); + struct dfl_afu *afu; + + afu = devm_kzalloc(&pdev->dev, sizeof(*afu), GFP_KERNEL); + if (!afu) + return -ENOMEM; + + afu->pdata = pdata; + + mutex_lock(&pdata->lock); + dfl_fpga_pdata_set_private(pdata, afu); + afu_mmio_region_init(pdata); + mutex_unlock(&pdata->lock); + + return 0; +} + +static int afu_dev_destroy(struct platform_device *pdev) +{ + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); + struct dfl_afu *afu; + + mutex_lock(&pdata->lock); + afu = dfl_fpga_pdata_get_private(pdata); + afu_mmio_region_destroy(pdata); + dfl_fpga_pdata_set_private(pdata, NULL); + mutex_unlock(&pdata->lock); + + return 0; +} + static int port_enable_set(struct platform_device *pdev, bool enable) { struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); @@ -312,14 +507,25 @@ static int afu_probe(struct platform_device *pdev) dev_dbg(&pdev->dev, "%s\n", __func__); + ret = afu_dev_init(pdev); + if (ret) + goto exit; + ret = dfl_fpga_dev_feature_init(pdev, port_feature_drvs); if (ret) - return ret; + goto dev_destroy; ret = dfl_fpga_dev_ops_register(pdev, &afu_fops, THIS_MODULE); - if (ret) + if (ret) { dfl_fpga_dev_feature_uinit(pdev); + goto dev_destroy; + } + + return 0; +dev_destroy: + afu_dev_destroy(pdev); +exit: return ret; } @@ -329,6 +535,7 @@ static int afu_remove(struct platform_device *pdev) dfl_fpga_dev_ops_unregister(pdev); dfl_fpga_dev_feature_uinit(pdev); + afu_dev_destroy(pdev); return 0; } diff --git a/drivers/fpga/dfl-afu-region.c b/drivers/fpga/dfl-afu-region.c new file mode 100644 index 000000000000..0804b7a0c298 --- /dev/null +++ b/drivers/fpga/dfl-afu-region.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for FPGA Accelerated Function Unit (AFU) MMIO Region Management + * + * Copyright (C) 2017-2018 Intel Corporation, Inc. + * + * Authors: + * Wu Hao + * Xiao Guangrong + */ +#include "dfl-afu.h" + +/** + * afu_mmio_region_init - init function for afu mmio region support + * @pdata: afu platform device's pdata. + */ +void afu_mmio_region_init(struct dfl_feature_platform_data *pdata) +{ + struct dfl_afu *afu = dfl_fpga_pdata_get_private(pdata); + + INIT_LIST_HEAD(&afu->regions); +} + +#define for_each_region(region, afu) \ + list_for_each_entry((region), &(afu)->regions, node) + +static struct dfl_afu_mmio_region *get_region_by_index(struct dfl_afu *afu, + u32 region_index) +{ + struct dfl_afu_mmio_region *region; + + for_each_region(region, afu) + if (region->index == region_index) + return region; + + return NULL; +} + +/** + * afu_mmio_region_add - add a mmio region to given feature dev. + * + * @region_index: region index. + * @region_size: region size. + * @phys: region's physical address of this region. + * @flags: region flags (access permission). + * + * Return: 0 on success, negative error code otherwise. + */ +int afu_mmio_region_add(struct dfl_feature_platform_data *pdata, + u32 region_index, u64 region_size, u64 phys, u32 flags) +{ + struct dfl_afu_mmio_region *region; + struct dfl_afu *afu; + int ret = 0; + + region = devm_kzalloc(&pdata->dev->dev, sizeof(*region), GFP_KERNEL); + if (!region) + return -ENOMEM; + + region->index = region_index; + region->size = region_size; + region->phys = phys; + region->flags = flags; + + mutex_lock(&pdata->lock); + + afu = dfl_fpga_pdata_get_private(pdata); + + /* check if @index already exists */ + if (get_region_by_index(afu, region_index)) { + mutex_unlock(&pdata->lock); + ret = -EEXIST; + goto exit; + } + + region_size = PAGE_ALIGN(region_size); + region->offset = afu->region_cur_offset; + list_add(®ion->node, &afu->regions); + + afu->region_cur_offset += region_size; + afu->num_regions++; + mutex_unlock(&pdata->lock); + + return 0; + +exit: + devm_kfree(&pdata->dev->dev, region); + return ret; +} + +/** + * afu_mmio_region_destroy - destroy all mmio regions under given feature dev. + * @pdata: afu platform device's pdata. + */ +void afu_mmio_region_destroy(struct dfl_feature_platform_data *pdata) +{ + struct dfl_afu *afu = dfl_fpga_pdata_get_private(pdata); + struct dfl_afu_mmio_region *tmp, *region; + + list_for_each_entry_safe(region, tmp, &afu->regions, node) + devm_kfree(&pdata->dev->dev, region); +} + +/** + * afu_mmio_region_get_by_index - find an afu region by index. + * @pdata: afu platform device's pdata. + * @region_index: region index. + * @pregion: ptr to region for result. + * + * Return: 0 on success, negative error code otherwise. + */ +int afu_mmio_region_get_by_index(struct dfl_feature_platform_data *pdata, + u32 region_index, + struct dfl_afu_mmio_region *pregion) +{ + struct dfl_afu_mmio_region *region; + struct dfl_afu *afu; + int ret = 0; + + mutex_lock(&pdata->lock); + afu = dfl_fpga_pdata_get_private(pdata); + region = get_region_by_index(afu, region_index); + if (!region) { + ret = -EINVAL; + goto exit; + } + *pregion = *region; +exit: + mutex_unlock(&pdata->lock); + return ret; +} + +/** + * afu_mmio_region_get_by_offset - find an afu mmio region by offset and size + * + * @pdata: afu platform device's pdata. + * @offset: region offset from start of the device fd. + * @size: region size. + * @pregion: ptr to region for result. + * + * Find the region which fully contains the region described by input + * parameters (offset and size) from the feature dev's region linked list. + * + * Return: 0 on success, negative error code otherwise. + */ +int afu_mmio_region_get_by_offset(struct dfl_feature_platform_data *pdata, + u64 offset, u64 size, + struct dfl_afu_mmio_region *pregion) +{ + struct dfl_afu_mmio_region *region; + struct dfl_afu *afu; + int ret = 0; + + mutex_lock(&pdata->lock); + afu = dfl_fpga_pdata_get_private(pdata); + for_each_region(region, afu) + if (region->offset <= offset && + region->offset + region->size >= offset + size) { + *pregion = *region; + goto exit; + } + ret = -EINVAL; +exit: + mutex_unlock(&pdata->lock); + return ret; +} diff --git a/drivers/fpga/dfl-afu.h b/drivers/fpga/dfl-afu.h new file mode 100644 index 000000000000..11ce2cf99759 --- /dev/null +++ b/drivers/fpga/dfl-afu.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Header file for FPGA Accelerated Function Unit (AFU) Driver + * + * Copyright (C) 2017-2018 Intel Corporation, Inc. + * + * Authors: + * Wu Hao + * Xiao Guangrong + * Joseph Grecco + * Enno Luebbers + * Tim Whisonant + * Ananda Ravuri + * Henry Mitchel + */ + +#ifndef __DFL_AFU_H +#define __DFL_AFU_H + +#include + +#include "dfl.h" + +/** + * struct dfl_afu_mmio_region - afu mmio region data structure + * + * @index: region index. + * @flags: region flags (access permission). + * @size: region size. + * @offset: region offset from start of the device fd. + * @phys: region's physical address. + * @node: node to add to afu feature dev's region list. + */ +struct dfl_afu_mmio_region { + u32 index; + u32 flags; + u64 size; + u64 offset; + u64 phys; + struct list_head node; +}; + +/** + * struct dfl_afu - afu device data structure + * + * @region_cur_offset: current region offset from start to the device fd. + * @num_regions: num of mmio regions. + * @regions: the mmio region linked list of this afu feature device. + * @num_umsgs: num of umsgs. + * @pdata: afu platform device's pdata. + */ +struct dfl_afu { + u64 region_cur_offset; + int num_regions; + u8 num_umsgs; + struct list_head regions; + + struct dfl_feature_platform_data *pdata; +}; + +void afu_mmio_region_init(struct dfl_feature_platform_data *pdata); +int afu_mmio_region_add(struct dfl_feature_platform_data *pdata, + u32 region_index, u64 region_size, u64 phys, u32 flags); +void afu_mmio_region_destroy(struct dfl_feature_platform_data *pdata); +int afu_mmio_region_get_by_index(struct dfl_feature_platform_data *pdata, + u32 region_index, + struct dfl_afu_mmio_region *pregion); +int afu_mmio_region_get_by_offset(struct dfl_feature_platform_data *pdata, + u64 offset, u64 size, + struct dfl_afu_mmio_region *pregion); +#endif diff --git a/include/uapi/linux/fpga-dfl.h b/include/uapi/linux/fpga-dfl.h index e6b4dd26cc68..a3ccdfb115a5 100644 --- a/include/uapi/linux/fpga-dfl.h +++ b/include/uapi/linux/fpga-dfl.h @@ -66,6 +66,54 @@ #define DFL_FPGA_PORT_RESET _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0) +/** + * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1, + * struct dfl_fpga_port_info) + * + * Retrieve information about the fpga port. + * Driver fills the info in provided struct dfl_fpga_port_info. + * Return: 0 on success, -errno on failure. + */ +struct dfl_fpga_port_info { + /* Input */ + __u32 argsz; /* Structure length */ + /* Output */ + __u32 flags; /* Zero for now */ + __u32 num_regions; /* The number of supported regions */ + __u32 num_umsgs; /* The number of allocated umsgs */ +}; + +#define DFL_FPGA_PORT_GET_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1) + +/** + * FPGA_PORT_GET_REGION_INFO - _IOWR(FPGA_MAGIC, PORT_BASE + 2, + * struct dfl_fpga_port_region_info) + * + * Retrieve information about a device memory region. + * Caller provides struct dfl_fpga_port_region_info with index value set. + * Driver returns the region info in other fields. + * Return: 0 on success, -errno on failure. + */ +struct dfl_fpga_port_region_info { + /* input */ + __u32 argsz; /* Structure length */ + /* Output */ + __u32 flags; /* Access permission */ +#define DFL_PORT_REGION_READ (1 << 0) /* Region is readable */ +#define DFL_PORT_REGION_WRITE (1 << 1) /* Region is writable */ +#define DFL_PORT_REGION_MMAP (1 << 2) /* Can be mmaped to userspace */ + /* Input */ + __u32 index; /* Region index */ +#define DFL_PORT_REGION_INDEX_AFU 0 /* AFU */ +#define DFL_PORT_REGION_INDEX_STP 1 /* Signal Tap */ + __u32 padding; + /* Output */ + __u64 size; /* Region size (bytes) */ + __u64 offset; /* Region offset from start of device fd */ +}; + +#define DFL_FPGA_PORT_GET_REGION_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2) + /* IOCTLs for FME file descriptor */ /** -- cgit v1.2.3-71-gd317 From fa8dda1edef9ebc3af467c644c5533ac97171e12 Mon Sep 17 00:00:00 2001 From: Wu Hao Date: Sat, 30 Jun 2018 08:53:35 +0800 Subject: fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support DMA memory regions are required for Accelerated Function Unit (AFU) usage. These two ioctls allow user space applications to map user memory regions for dma, and unmap them after use. Iova is returned from driver to user space application via DFL_FPGA_PORT_DMA_MAP ioctl. Application needs to unmap it after use, otherwise, driver will unmap them in device file release operation. Each AFU has its own rb tree to keep track of its mapped DMA regions. Ioctl interfaces: * DFL_FPGA_PORT_DMA_MAP Do the dma mapping per user_addr and length provided by user. Return iova in provided struct dfl_fpga_port_dma_map. * DFL_FPGA_PORT_DMA_UNMAP Unmap the dma region per iova provided by user. Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Xiao Guangrong Signed-off-by: Wu Hao Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman --- drivers/fpga/Makefile | 2 +- drivers/fpga/dfl-afu-dma-region.c | 463 ++++++++++++++++++++++++++++++++++++++ drivers/fpga/dfl-afu-main.c | 61 ++++- drivers/fpga/dfl-afu.h | 31 ++- include/uapi/linux/fpga-dfl.h | 37 +++ 5 files changed, 591 insertions(+), 3 deletions(-) create mode 100644 drivers/fpga/dfl-afu-dma-region.c (limited to 'include') diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index a44d50dd0b70..7a2d73ba7122 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -38,7 +38,7 @@ obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o -dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o +dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o # Drivers for FPGAs which implement DFL obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o diff --git a/drivers/fpga/dfl-afu-dma-region.c b/drivers/fpga/dfl-afu-dma-region.c new file mode 100644 index 000000000000..0e81d33af856 --- /dev/null +++ b/drivers/fpga/dfl-afu-dma-region.c @@ -0,0 +1,463 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for FPGA Accelerated Function Unit (AFU) DMA Region Management + * + * Copyright (C) 2017-2018 Intel Corporation, Inc. + * + * Authors: + * Wu Hao + * Xiao Guangrong + */ + +#include +#include +#include + +#include "dfl-afu.h" + +static void put_all_pages(struct page **pages, int npages) +{ + int i; + + for (i = 0; i < npages; i++) + if (pages[i]) + put_page(pages[i]); +} + +void afu_dma_region_init(struct dfl_feature_platform_data *pdata) +{ + struct dfl_afu *afu = dfl_fpga_pdata_get_private(pdata); + + afu->dma_regions = RB_ROOT; +} + +/** + * afu_dma_adjust_locked_vm - adjust locked memory + * @dev: port device + * @npages: number of pages + * @incr: increase or decrease locked memory + * + * Increase or decrease the locked memory size with npages input. + * + * Return 0 on success. + * Return -ENOMEM if locked memory size is over the limit and no CAP_IPC_LOCK. + */ +static int afu_dma_adjust_locked_vm(struct device *dev, long npages, bool incr) +{ + unsigned long locked, lock_limit; + int ret = 0; + + /* the task is exiting. */ + if (!current->mm) + return 0; + + down_write(¤t->mm->mmap_sem); + + if (incr) { + locked = current->mm->locked_vm + npages; + lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT; + + if (locked > lock_limit && !capable(CAP_IPC_LOCK)) + ret = -ENOMEM; + else + current->mm->locked_vm += npages; + } else { + if (WARN_ON_ONCE(npages > current->mm->locked_vm)) + npages = current->mm->locked_vm; + current->mm->locked_vm -= npages; + } + + dev_dbg(dev, "[%d] RLIMIT_MEMLOCK %c%ld %ld/%ld%s\n", current->pid, + incr ? '+' : '-', npages << PAGE_SHIFT, + current->mm->locked_vm << PAGE_SHIFT, rlimit(RLIMIT_MEMLOCK), + ret ? "- execeeded" : ""); + + up_write(¤t->mm->mmap_sem); + + return ret; +} + +/** + * afu_dma_pin_pages - pin pages of given dma memory region + * @pdata: feature device platform data + * @region: dma memory region to be pinned + * + * Pin all the pages of given dfl_afu_dma_region. + * Return 0 for success or negative error code. + */ +static int afu_dma_pin_pages(struct dfl_feature_platform_data *pdata, + struct dfl_afu_dma_region *region) +{ + int npages = region->length >> PAGE_SHIFT; + struct device *dev = &pdata->dev->dev; + int ret, pinned; + + ret = afu_dma_adjust_locked_vm(dev, npages, true); + if (ret) + return ret; + + region->pages = kcalloc(npages, sizeof(struct page *), GFP_KERNEL); + if (!region->pages) { + ret = -ENOMEM; + goto unlock_vm; + } + + pinned = get_user_pages_fast(region->user_addr, npages, 1, + region->pages); + if (pinned < 0) { + ret = pinned; + goto put_pages; + } else if (pinned != npages) { + ret = -EFAULT; + goto free_pages; + } + + dev_dbg(dev, "%d pages pinned\n", pinned); + + return 0; + +put_pages: + put_all_pages(region->pages, pinned); +free_pages: + kfree(region->pages); +unlock_vm: + afu_dma_adjust_locked_vm(dev, npages, false); + return ret; +} + +/** + * afu_dma_unpin_pages - unpin pages of given dma memory region + * @pdata: feature device platform data + * @region: dma memory region to be unpinned + * + * Unpin all the pages of given dfl_afu_dma_region. + * Return 0 for success or negative error code. + */ +static void afu_dma_unpin_pages(struct dfl_feature_platform_data *pdata, + struct dfl_afu_dma_region *region) +{ + long npages = region->length >> PAGE_SHIFT; + struct device *dev = &pdata->dev->dev; + + put_all_pages(region->pages, npages); + kfree(region->pages); + afu_dma_adjust_locked_vm(dev, npages, false); + + dev_dbg(dev, "%ld pages unpinned\n", npages); +} + +/** + * afu_dma_check_continuous_pages - check if pages are continuous + * @region: dma memory region + * + * Return true if pages of given dma memory region have continuous physical + * address, otherwise return false. + */ +static bool afu_dma_check_continuous_pages(struct dfl_afu_dma_region *region) +{ + int npages = region->length >> PAGE_SHIFT; + int i; + + for (i = 0; i < npages - 1; i++) + if (page_to_pfn(region->pages[i]) + 1 != + page_to_pfn(region->pages[i + 1])) + return false; + + return true; +} + +/** + * dma_region_check_iova - check if memory area is fully contained in the region + * @region: dma memory region + * @iova: address of the dma memory area + * @size: size of the dma memory area + * + * Compare the dma memory area defined by @iova and @size with given dma region. + * Return true if memory area is fully contained in the region, otherwise false. + */ +static bool dma_region_check_iova(struct dfl_afu_dma_region *region, + u64 iova, u64 size) +{ + if (!size && region->iova != iova) + return false; + + return (region->iova <= iova) && + (region->length + region->iova >= iova + size); +} + +/** + * afu_dma_region_add - add given dma region to rbtree + * @pdata: feature device platform data + * @region: dma region to be added + * + * Return 0 for success, -EEXIST if dma region has already been added. + * + * Needs to be called with pdata->lock heold. + */ +static int afu_dma_region_add(struct dfl_feature_platform_data *pdata, + struct dfl_afu_dma_region *region) +{ + struct dfl_afu *afu = dfl_fpga_pdata_get_private(pdata); + struct rb_node **new, *parent = NULL; + + dev_dbg(&pdata->dev->dev, "add region (iova = %llx)\n", + (unsigned long long)region->iova); + + new = &afu->dma_regions.rb_node; + + while (*new) { + struct dfl_afu_dma_region *this; + + this = container_of(*new, struct dfl_afu_dma_region, node); + + parent = *new; + + if (dma_region_check_iova(this, region->iova, region->length)) + return -EEXIST; + + if (region->iova < this->iova) + new = &((*new)->rb_left); + else if (region->iova > this->iova) + new = &((*new)->rb_right); + else + return -EEXIST; + } + + rb_link_node(®ion->node, parent, new); + rb_insert_color(®ion->node, &afu->dma_regions); + + return 0; +} + +/** + * afu_dma_region_remove - remove given dma region from rbtree + * @pdata: feature device platform data + * @region: dma region to be removed + * + * Needs to be called with pdata->lock heold. + */ +static void afu_dma_region_remove(struct dfl_feature_platform_data *pdata, + struct dfl_afu_dma_region *region) +{ + struct dfl_afu *afu; + + dev_dbg(&pdata->dev->dev, "del region (iova = %llx)\n", + (unsigned long long)region->iova); + + afu = dfl_fpga_pdata_get_private(pdata); + rb_erase(®ion->node, &afu->dma_regions); +} + +/** + * afu_dma_region_destroy - destroy all regions in rbtree + * @pdata: feature device platform data + * + * Needs to be called with pdata->lock heold. + */ +void afu_dma_region_destroy(struct dfl_feature_platform_data *pdata) +{ + struct dfl_afu *afu = dfl_fpga_pdata_get_private(pdata); + struct rb_node *node = rb_first(&afu->dma_regions); + struct dfl_afu_dma_region *region; + + while (node) { + region = container_of(node, struct dfl_afu_dma_region, node); + + dev_dbg(&pdata->dev->dev, "del region (iova = %llx)\n", + (unsigned long long)region->iova); + + rb_erase(node, &afu->dma_regions); + + if (region->iova) + dma_unmap_page(dfl_fpga_pdata_to_parent(pdata), + region->iova, region->length, + DMA_BIDIRECTIONAL); + + if (region->pages) + afu_dma_unpin_pages(pdata, region); + + node = rb_next(node); + kfree(region); + } +} + +/** + * afu_dma_region_find - find the dma region from rbtree based on iova and size + * @pdata: feature device platform data + * @iova: address of the dma memory area + * @size: size of the dma memory area + * + * It finds the dma region from the rbtree based on @iova and @size: + * - if @size == 0, it finds the dma region which starts from @iova + * - otherwise, it finds the dma region which fully contains + * [@iova, @iova+size) + * If nothing is matched returns NULL. + * + * Needs to be called with pdata->lock held. + */ +struct dfl_afu_dma_region * +afu_dma_region_find(struct dfl_feature_platform_data *pdata, u64 iova, u64 size) +{ + struct dfl_afu *afu = dfl_fpga_pdata_get_private(pdata); + struct rb_node *node = afu->dma_regions.rb_node; + struct device *dev = &pdata->dev->dev; + + while (node) { + struct dfl_afu_dma_region *region; + + region = container_of(node, struct dfl_afu_dma_region, node); + + if (dma_region_check_iova(region, iova, size)) { + dev_dbg(dev, "find region (iova = %llx)\n", + (unsigned long long)region->iova); + return region; + } + + if (iova < region->iova) + node = node->rb_left; + else if (iova > region->iova) + node = node->rb_right; + else + /* the iova region is not fully covered. */ + break; + } + + dev_dbg(dev, "region with iova %llx and size %llx is not found\n", + (unsigned long long)iova, (unsigned long long)size); + + return NULL; +} + +/** + * afu_dma_region_find_iova - find the dma region from rbtree by iova + * @pdata: feature device platform data + * @iova: address of the dma region + * + * Needs to be called with pdata->lock held. + */ +static struct dfl_afu_dma_region * +afu_dma_region_find_iova(struct dfl_feature_platform_data *pdata, u64 iova) +{ + return afu_dma_region_find(pdata, iova, 0); +} + +/** + * afu_dma_map_region - map memory region for dma + * @pdata: feature device platform data + * @user_addr: address of the memory region + * @length: size of the memory region + * @iova: pointer of iova address + * + * Map memory region defined by @user_addr and @length, and return dma address + * of the memory region via @iova. + * Return 0 for success, otherwise error code. + */ +int afu_dma_map_region(struct dfl_feature_platform_data *pdata, + u64 user_addr, u64 length, u64 *iova) +{ + struct dfl_afu_dma_region *region; + int ret; + + /* + * Check Inputs, only accept page-aligned user memory region with + * valid length. + */ + if (!PAGE_ALIGNED(user_addr) || !PAGE_ALIGNED(length) || !length) + return -EINVAL; + + /* Check overflow */ + if (user_addr + length < user_addr) + return -EINVAL; + + if (!access_ok(VERIFY_WRITE, (void __user *)(unsigned long)user_addr, + length)) + return -EINVAL; + + region = kzalloc(sizeof(*region), GFP_KERNEL); + if (!region) + return -ENOMEM; + + region->user_addr = user_addr; + region->length = length; + + /* Pin the user memory region */ + ret = afu_dma_pin_pages(pdata, region); + if (ret) { + dev_err(&pdata->dev->dev, "failed to pin memory region\n"); + goto free_region; + } + + /* Only accept continuous pages, return error else */ + if (!afu_dma_check_continuous_pages(region)) { + dev_err(&pdata->dev->dev, "pages are not continuous\n"); + ret = -EINVAL; + goto unpin_pages; + } + + /* As pages are continuous then start to do DMA mapping */ + region->iova = dma_map_page(dfl_fpga_pdata_to_parent(pdata), + region->pages[0], 0, + region->length, + DMA_BIDIRECTIONAL); + if (dma_mapping_error(&pdata->dev->dev, region->iova)) { + dev_err(&pdata->dev->dev, "failed to map for dma\n"); + ret = -EFAULT; + goto unpin_pages; + } + + *iova = region->iova; + + mutex_lock(&pdata->lock); + ret = afu_dma_region_add(pdata, region); + mutex_unlock(&pdata->lock); + if (ret) { + dev_err(&pdata->dev->dev, "failed to add dma region\n"); + goto unmap_dma; + } + + return 0; + +unmap_dma: + dma_unmap_page(dfl_fpga_pdata_to_parent(pdata), + region->iova, region->length, DMA_BIDIRECTIONAL); +unpin_pages: + afu_dma_unpin_pages(pdata, region); +free_region: + kfree(region); + return ret; +} + +/** + * afu_dma_unmap_region - unmap dma memory region + * @pdata: feature device platform data + * @iova: dma address of the region + * + * Unmap dma memory region based on @iova. + * Return 0 for success, otherwise error code. + */ +int afu_dma_unmap_region(struct dfl_feature_platform_data *pdata, u64 iova) +{ + struct dfl_afu_dma_region *region; + + mutex_lock(&pdata->lock); + region = afu_dma_region_find_iova(pdata, iova); + if (!region) { + mutex_unlock(&pdata->lock); + return -EINVAL; + } + + if (region->in_use) { + mutex_unlock(&pdata->lock); + return -EBUSY; + } + + afu_dma_region_remove(pdata, region); + mutex_unlock(&pdata->lock); + + dma_unmap_page(dfl_fpga_pdata_to_parent(pdata), + region->iova, region->length, DMA_BIDIRECTIONAL); + afu_dma_unpin_pages(pdata, region); + kfree(region); + + return 0; +} diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c index f67a78d7e9ad..02baa6a227c0 100644 --- a/drivers/fpga/dfl-afu-main.c +++ b/drivers/fpga/dfl-afu-main.c @@ -293,7 +293,11 @@ static int afu_release(struct inode *inode, struct file *filp) pdata = dev_get_platdata(&pdev->dev); - port_reset(pdev); + mutex_lock(&pdata->lock); + __port_reset(pdev); + afu_dma_region_destroy(pdata); + mutex_unlock(&pdata->lock); + dfl_feature_dev_use_end(pdata); return 0; @@ -364,6 +368,55 @@ static long afu_ioctl_get_region_info(struct dfl_feature_platform_data *pdata, return 0; } +static long +afu_ioctl_dma_map(struct dfl_feature_platform_data *pdata, void __user *arg) +{ + struct dfl_fpga_port_dma_map map; + unsigned long minsz; + long ret; + + minsz = offsetofend(struct dfl_fpga_port_dma_map, iova); + + if (copy_from_user(&map, arg, minsz)) + return -EFAULT; + + if (map.argsz < minsz || map.flags) + return -EINVAL; + + ret = afu_dma_map_region(pdata, map.user_addr, map.length, &map.iova); + if (ret) + return ret; + + if (copy_to_user(arg, &map, sizeof(map))) { + afu_dma_unmap_region(pdata, map.iova); + return -EFAULT; + } + + dev_dbg(&pdata->dev->dev, "dma map: ua=%llx, len=%llx, iova=%llx\n", + (unsigned long long)map.user_addr, + (unsigned long long)map.length, + (unsigned long long)map.iova); + + return 0; +} + +static long +afu_ioctl_dma_unmap(struct dfl_feature_platform_data *pdata, void __user *arg) +{ + struct dfl_fpga_port_dma_unmap unmap; + unsigned long minsz; + + minsz = offsetofend(struct dfl_fpga_port_dma_unmap, iova); + + if (copy_from_user(&unmap, arg, minsz)) + return -EFAULT; + + if (unmap.argsz < minsz || unmap.flags) + return -EINVAL; + + return afu_dma_unmap_region(pdata, unmap.iova); +} + static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { struct platform_device *pdev = filp->private_data; @@ -384,6 +437,10 @@ static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return afu_ioctl_get_info(pdata, (void __user *)arg); case DFL_FPGA_PORT_GET_REGION_INFO: return afu_ioctl_get_region_info(pdata, (void __user *)arg); + case DFL_FPGA_PORT_DMA_MAP: + return afu_ioctl_dma_map(pdata, (void __user *)arg); + case DFL_FPGA_PORT_DMA_UNMAP: + return afu_ioctl_dma_unmap(pdata, (void __user *)arg); default: /* * Let sub-feature's ioctl function to handle the cmd @@ -460,6 +517,7 @@ static int afu_dev_init(struct platform_device *pdev) mutex_lock(&pdata->lock); dfl_fpga_pdata_set_private(pdata, afu); afu_mmio_region_init(pdata); + afu_dma_region_init(pdata); mutex_unlock(&pdata->lock); return 0; @@ -473,6 +531,7 @@ static int afu_dev_destroy(struct platform_device *pdev) mutex_lock(&pdata->lock); afu = dfl_fpga_pdata_get_private(pdata); afu_mmio_region_destroy(pdata); + afu_dma_region_destroy(pdata); dfl_fpga_pdata_set_private(pdata, NULL); mutex_unlock(&pdata->lock); diff --git a/drivers/fpga/dfl-afu.h b/drivers/fpga/dfl-afu.h index 11ce2cf99759..0c7630ae3cda 100644 --- a/drivers/fpga/dfl-afu.h +++ b/drivers/fpga/dfl-afu.h @@ -40,12 +40,32 @@ struct dfl_afu_mmio_region { struct list_head node; }; +/** + * struct fpga_afu_dma_region - afu DMA region data structure + * + * @user_addr: region userspace virtual address. + * @length: region length. + * @iova: region IO virtual address. + * @pages: ptr to pages of this region. + * @node: rb tree node. + * @in_use: flag to indicate if this region is in_use. + */ +struct dfl_afu_dma_region { + u64 user_addr; + u64 length; + u64 iova; + struct page **pages; + struct rb_node node; + bool in_use; +}; + /** * struct dfl_afu - afu device data structure * * @region_cur_offset: current region offset from start to the device fd. * @num_regions: num of mmio regions. * @regions: the mmio region linked list of this afu feature device. + * @dma_regions: root of dma regions rb tree. * @num_umsgs: num of umsgs. * @pdata: afu platform device's pdata. */ @@ -54,6 +74,7 @@ struct dfl_afu { int num_regions; u8 num_umsgs; struct list_head regions; + struct rb_root dma_regions; struct dfl_feature_platform_data *pdata; }; @@ -68,4 +89,12 @@ int afu_mmio_region_get_by_index(struct dfl_feature_platform_data *pdata, int afu_mmio_region_get_by_offset(struct dfl_feature_platform_data *pdata, u64 offset, u64 size, struct dfl_afu_mmio_region *pregion); -#endif +void afu_dma_region_init(struct dfl_feature_platform_data *pdata); +void afu_dma_region_destroy(struct dfl_feature_platform_data *pdata); +int afu_dma_map_region(struct dfl_feature_platform_data *pdata, + u64 user_addr, u64 length, u64 *iova); +int afu_dma_unmap_region(struct dfl_feature_platform_data *pdata, u64 iova); +struct dfl_afu_dma_region * +afu_dma_region_find(struct dfl_feature_platform_data *pdata, + u64 iova, u64 size); +#endif /* __DFL_AFU_H */ diff --git a/include/uapi/linux/fpga-dfl.h b/include/uapi/linux/fpga-dfl.h index a3ccdfb115a5..2e324e515c41 100644 --- a/include/uapi/linux/fpga-dfl.h +++ b/include/uapi/linux/fpga-dfl.h @@ -114,6 +114,43 @@ struct dfl_fpga_port_region_info { #define DFL_FPGA_PORT_GET_REGION_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2) +/** + * DFL_FPGA_PORT_DMA_MAP - _IOWR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3, + * struct dfl_fpga_port_dma_map) + * + * Map the dma memory per user_addr and length which are provided by caller. + * Driver fills the iova in provided struct afu_port_dma_map. + * This interface only accepts page-size aligned user memory for dma mapping. + * Return: 0 on success, -errno on failure. + */ +struct dfl_fpga_port_dma_map { + /* Input */ + __u32 argsz; /* Structure length */ + __u32 flags; /* Zero for now */ + __u64 user_addr; /* Process virtual address */ + __u64 length; /* Length of mapping (bytes)*/ + /* Output */ + __u64 iova; /* IO virtual address */ +}; + +#define DFL_FPGA_PORT_DMA_MAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3) + +/** + * DFL_FPGA_PORT_DMA_UNMAP - _IOW(FPGA_MAGIC, PORT_BASE + 4, + * struct dfl_fpga_port_dma_unmap) + * + * Unmap the dma memory per iova provided by caller. + * Return: 0 on success, -errno on failure. + */ +struct dfl_fpga_port_dma_unmap { + /* Input */ + __u32 argsz; /* Structure length */ + __u32 flags; /* Zero for now */ + __u64 iova; /* IO virtual address */ +}; + +#define DFL_FPGA_PORT_DMA_UNMAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 4) + /* IOCTLs for FME file descriptor */ /** -- cgit v1.2.3-71-gd317 From 45cd74cb5061781e793a098c420a7f548fdc9e7d Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 10 Jul 2018 17:15:38 +0200 Subject: eventpoll.h: wrap casts in () properly When importing the latest copy of the kernel headers into Bionic, Christpher and Elliott noticed that the eventpoll.h casts were not wrapped in (). As it is, clang complains about macros without surrounding (), so this makes it a pain for userspace tools. So fix it up by adding another () pair, and make them line up purty by using tabs. Fixes: 65aaf87b3aa2 ("add EPOLLNVAL, annotate EPOLL... and event_poll->event") Reported-by: Christopher Ferris Reported-by: Elliott Hughes Cc: stable Cc: Thomas Gleixner Cc: Al Viro Signed-off-by: Greg Kroah-Hartman --- include/uapi/linux/eventpoll.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/uapi/linux/eventpoll.h b/include/uapi/linux/eventpoll.h index bf48e71f2634..8a3432d0f0dc 100644 --- a/include/uapi/linux/eventpoll.h +++ b/include/uapi/linux/eventpoll.h @@ -42,7 +42,7 @@ #define EPOLLRDHUP (__force __poll_t)0x00002000 /* Set exclusive wakeup mode for the target file descriptor */ -#define EPOLLEXCLUSIVE (__force __poll_t)(1U << 28) +#define EPOLLEXCLUSIVE ((__force __poll_t)(1U << 28)) /* * Request the handling of system wakeup events so as to prevent system suspends @@ -54,13 +54,13 @@ * * Requires CAP_BLOCK_SUSPEND */ -#define EPOLLWAKEUP (__force __poll_t)(1U << 29) +#define EPOLLWAKEUP ((__force __poll_t)(1U << 29)) /* Set the One Shot behaviour for the target file descriptor */ -#define EPOLLONESHOT (__force __poll_t)(1U << 30) +#define EPOLLONESHOT ((__force __poll_t)(1U << 30)) /* Set the Edge Triggered behaviour for the target file descriptor */ -#define EPOLLET (__force __poll_t)(1U << 31) +#define EPOLLET ((__force __poll_t)(1U << 31)) /* * On x86-64 make the 64bit structure have the same alignment as the -- cgit v1.2.3-71-gd317 From d5e838275c80aeb96d4c0b81442a851dfef2e948 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 5 Jun 2018 13:21:26 +1000 Subject: devres: Add devm_of_iomap() There are still quite a few cases where a device might want to get to a different node of the device-tree, obtain the resources and map them. We have of_iomap() and of_io_request_and_map() but they both have shortcomings, such as not returning the size of the resource found (which can be useful) and not being "managed". This adds a devm_of_iomap() that provides all of these and should probably replace uses of the above in most drivers. Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Linus Walleij Reviewed-by: Joel Stanley --- include/linux/device.h | 4 ++++ lib/devres.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) (limited to 'include') diff --git a/include/linux/device.h b/include/linux/device.h index 055a69dbcd18..6aa8d51eabe9 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -696,6 +696,10 @@ extern void devm_free_pages(struct device *dev, unsigned long addr); void __iomem *devm_ioremap_resource(struct device *dev, struct resource *res); +void __iomem *devm_of_iomap(struct device *dev, + struct device_node *node, int index, + resource_size_t *size); + /* allows to add/remove a custom action to devres stack */ int devm_add_action(struct device *dev, void (*action)(void *), void *data); void devm_remove_action(struct device *dev, void (*action)(void *), void *data); diff --git a/lib/devres.c b/lib/devres.c index 5bec1120b392..faccf1a037d0 100644 --- a/lib/devres.c +++ b/lib/devres.c @@ -4,6 +4,7 @@ #include #include #include +#include enum devm_ioremap_type { DEVM_IOREMAP = 0, @@ -162,6 +163,41 @@ void __iomem *devm_ioremap_resource(struct device *dev, struct resource *res) } EXPORT_SYMBOL(devm_ioremap_resource); +/* + * devm_of_iomap - Requests a resource and maps the memory mapped IO + * for a given device_node managed by a given device + * + * Checks that a resource is a valid memory region, requests the memory + * region and ioremaps it. All operations are managed and will be undone + * on driver detach of the device. + * + * This is to be used when a device requests/maps resources described + * by other device tree nodes (children or otherwise). + * + * @dev: The device "managing" the resource + * @node: The device-tree node where the resource resides + * @index: index of the MMIO range in the "reg" property + * @size: Returns the size of the resource (pass NULL if not needed) + * Returns a pointer to the requested and mapped memory or an ERR_PTR() encoded + * error code on failure. Usage example: + * + * base = devm_of_iomap(&pdev->dev, node, 0, NULL); + * if (IS_ERR(base)) + * return PTR_ERR(base); + */ +void __iomem *devm_of_iomap(struct device *dev, struct device_node *node, int index, + resource_size_t *size) +{ + struct resource res; + + if (of_address_to_resource(node, index, &res)) + return IOMEM_ERR_PTR(-EINVAL); + if (size) + *size = resource_size(&res); + return devm_ioremap_resource(dev, &res); +} +EXPORT_SYMBOL(devm_of_iomap); + #ifdef CONFIG_HAS_IOPORT_MAP /* * Generic iomap devres -- cgit v1.2.3-71-gd317 From 6a794a27daca9c5a39de13c03b0748bb2d4a7a70 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 Jun 2018 09:55:04 +1000 Subject: fsi: master-ast-cf: Add new FSI master using Aspeed ColdFire The Aspeed AST2x00 can contain a ColdFire v1 coprocessor which is currently unused on OpenPower systems. This adds an alternative to the fsi-master-gpio driver that uses that coprocessor instead of bit banging from the ARM core itself. The end result is about 4 times faster. The firmware for the coprocessor and its source code can be found at https://github.com/ozbenh/cf-fsi and is system specific. Signed-off-by: Benjamin Herrenschmidt --- drivers/fsi/Kconfig | 9 + drivers/fsi/Makefile | 1 + drivers/fsi/cf-fsi-fw.h | 157 ++++ drivers/fsi/fsi-master-ast-cf.c | 1438 ++++++++++++++++++++++++++++++ include/trace/events/fsi_master_ast_cf.h | 150 ++++ 5 files changed, 1755 insertions(+) create mode 100644 drivers/fsi/cf-fsi-fw.h create mode 100644 drivers/fsi/fsi-master-ast-cf.c create mode 100644 include/trace/events/fsi_master_ast_cf.h (limited to 'include') diff --git a/drivers/fsi/Kconfig b/drivers/fsi/Kconfig index 9c08f467a7bb..8d82b1e60514 100644 --- a/drivers/fsi/Kconfig +++ b/drivers/fsi/Kconfig @@ -27,6 +27,15 @@ config FSI_MASTER_HUB allow chaining of FSI links to an arbitrary depth. This allows for a high target device fanout. +config FSI_MASTER_AST_CF + tristate "FSI master based on Aspeed ColdFire coprocessor" + depends on GPIOLIB + depends on GPIO_ASPEED + ---help--- + This option enables a FSI master using the AST2400 and AST2500 GPIO + lines driven by the internal ColdFire coprocessor. This requires + the corresponding machine specific ColdFire firmware to be available. + config FSI_SCOM tristate "SCOM FSI client device driver" ---help--- diff --git a/drivers/fsi/Makefile b/drivers/fsi/Makefile index 851182e1cd9e..a50d6ce22fb3 100644 --- a/drivers/fsi/Makefile +++ b/drivers/fsi/Makefile @@ -2,5 +2,6 @@ obj-$(CONFIG_FSI) += fsi-core.o obj-$(CONFIG_FSI_MASTER_HUB) += fsi-master-hub.o obj-$(CONFIG_FSI_MASTER_GPIO) += fsi-master-gpio.o +obj-$(CONFIG_FSI_MASTER_AST_CF) += fsi-master-ast-cf.o obj-$(CONFIG_FSI_SCOM) += fsi-scom.o obj-$(CONFIG_FSI_SBEFIFO) += fsi-sbefifo.o diff --git a/drivers/fsi/cf-fsi-fw.h b/drivers/fsi/cf-fsi-fw.h new file mode 100644 index 000000000000..712df0461911 --- /dev/null +++ b/drivers/fsi/cf-fsi-fw.h @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +#ifndef __CF_FSI_FW_H +#define __CF_FSI_FW_H + +/* + * uCode file layout + * + * 0000...03ff : m68k exception vectors + * 0400...04ff : Header info & boot config block + * 0500....... : Code & stack + */ + +/* + * Header info & boot config area + * + * The Header info is built into the ucode and provide version and + * platform information. + * + * the Boot config needs to be adjusted by the ARM prior to starting + * the ucode if the Command/Status area isn't at 0x320000 in CF space + * (ie. beginning of SRAM). + */ + +#define HDR_OFFSET 0x400 + +/* Info: Signature & version */ +#define HDR_SYS_SIG 0x00 /* 2 bytes system signature */ +#define SYS_SIG_SHARED 0x5348 +#define SYS_SIG_SPLIT 0x5350 +#define HDR_FW_VERS 0x02 /* 2 bytes Major.Minor */ +#define HDR_API_VERS 0x04 /* 2 bytes Major.Minor */ +#define API_VERSION_MAJ 2 /* Current version */ +#define API_VERSION_MIN 1 +#define HDR_FW_OPTIONS 0x08 /* 4 bytes option flags */ +#define FW_OPTION_TRACE_EN 0x00000001 /* FW tracing enabled */ +#define FW_OPTION_CONT_CLOCK 0x00000002 /* Continuous clocking supported */ +#define HDR_FW_SIZE 0x10 /* 4 bytes size for combo image */ + +/* Boot Config: Address of Command/Status area */ +#define HDR_CMD_STAT_AREA 0x80 /* 4 bytes CF address */ +#define HDR_FW_CONTROL 0x84 /* 4 bytes control flags */ +#define FW_CONTROL_CONT_CLOCK 0x00000002 /* Continuous clocking enabled */ +#define FW_CONTROL_DUMMY_RD 0x00000004 /* Extra dummy read (AST2400) */ +#define FW_CONTROL_USE_STOP 0x00000008 /* Use STOP instructions */ +#define HDR_CLOCK_GPIO_VADDR 0x90 /* 2 bytes offset from GPIO base */ +#define HDR_CLOCK_GPIO_DADDR 0x92 /* 2 bytes offset from GPIO base */ +#define HDR_DATA_GPIO_VADDR 0x94 /* 2 bytes offset from GPIO base */ +#define HDR_DATA_GPIO_DADDR 0x96 /* 2 bytes offset from GPIO base */ +#define HDR_TRANS_GPIO_VADDR 0x98 /* 2 bytes offset from GPIO base */ +#define HDR_TRANS_GPIO_DADDR 0x9a /* 2 bytes offset from GPIO base */ +#define HDR_CLOCK_GPIO_BIT 0x9c /* 1 byte bit number */ +#define HDR_DATA_GPIO_BIT 0x9d /* 1 byte bit number */ +#define HDR_TRANS_GPIO_BIT 0x9e /* 1 byte bit number */ + +/* + * Command/Status area layout: Main part + */ + +/* Command/Status register: + * + * +---------------------------+ + * | STAT | RLEN | CLEN | CMD | + * | 8 | 8 | 8 | 8 | + * +---------------------------+ + * | | | | + * status | | | + * Response len | | + * (in bits) | | + * | | + * Command len | + * (in bits) | + * | + * Command code + * + * Due to the big endian layout, that means that a byte read will + * return the status byte + */ +#define CMD_STAT_REG 0x00 +#define CMD_REG_CMD_MASK 0x000000ff +#define CMD_REG_CMD_SHIFT 0 +#define CMD_NONE 0x00 +#define CMD_COMMAND 0x01 +#define CMD_BREAK 0x02 +#define CMD_IDLE_CLOCKS 0x03 /* clen = #clocks */ +#define CMD_INVALID 0xff +#define CMD_REG_CLEN_MASK 0x0000ff00 +#define CMD_REG_CLEN_SHIFT 8 +#define CMD_REG_RLEN_MASK 0x00ff0000 +#define CMD_REG_RLEN_SHIFT 16 +#define CMD_REG_STAT_MASK 0xff000000 +#define CMD_REG_STAT_SHIFT 24 +#define STAT_WORKING 0x00 +#define STAT_COMPLETE 0x01 +#define STAT_ERR_INVAL_CMD 0x80 +#define STAT_ERR_INVAL_IRQ 0x81 +#define STAT_ERR_MTOE 0x82 + +/* Response tag & CRC */ +#define STAT_RTAG 0x04 + +/* Response CRC */ +#define STAT_RCRC 0x05 + +/* Echo and Send delay */ +#define ECHO_DLY_REG 0x08 +#define SEND_DLY_REG 0x09 + +/* Command data area + * + * Last byte of message must be left aligned + */ +#define CMD_DATA 0x10 /* 64 bit of data */ + +/* Response data area, right aligned, unused top bits are 1 */ +#define RSP_DATA 0x20 /* 32 bit of data */ + +/* Misc */ +#define INT_CNT 0x30 /* 32-bit interrupt count */ +#define BAD_INT_VEC 0x34 /* 32-bit bad interrupt vector # */ +#define CF_STARTED 0x38 /* byte, set to -1 when copro started */ +#define CLK_CNT 0x3c /* 32-bit, clock count (debug only) */ + +/* + * SRAM layout: GPIO arbitration part + */ +#define ARB_REG 0x40 +#define ARB_ARM_REQ 0x01 +#define ARB_ARM_ACK 0x02 + +/* Misc2 */ +#define CF_RESET_D0 0x50 +#define CF_RESET_D1 0x54 +#define BAD_INT_S0 0x58 +#define BAD_INT_S1 0x5c +#define STOP_CNT 0x60 + +/* Internal */ + +/* + * SRAM layout: Trace buffer (debug builds only) + */ +#define TRACEBUF 0x100 +#define TR_CLKOBIT0 0xc0 +#define TR_CLKOBIT1 0xc1 +#define TR_CLKOSTART 0x82 +#define TR_OLEN 0x83 /* + len */ +#define TR_CLKZ 0x84 /* + count */ +#define TR_CLKWSTART 0x85 +#define TR_CLKTAG 0x86 /* + tag */ +#define TR_CLKDATA 0x87 /* + len */ +#define TR_CLKCRC 0x88 /* + raw crc */ +#define TR_CLKIBIT0 0x90 +#define TR_CLKIBIT1 0x91 +#define TR_END 0xff + +#endif /* __CF_FSI_FW_H */ + diff --git a/drivers/fsi/fsi-master-ast-cf.c b/drivers/fsi/fsi-master-ast-cf.c new file mode 100644 index 000000000000..57afaae0b691 --- /dev/null +++ b/drivers/fsi/fsi-master-ast-cf.c @@ -0,0 +1,1438 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2018 IBM Corp +/* + * A FSI master controller, using a simple GPIO bit-banging interface + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fsi-master.h" +#include "cf-fsi-fw.h" + +#define FW_FILE_NAME "cf-fsi-fw.bin" + +/* Common SCU based coprocessor control registers */ +#define SCU_COPRO_CTRL 0x100 +#define SCU_COPRO_RESET 0x00000002 +#define SCU_COPRO_CLK_EN 0x00000001 + +/* AST2500 specific ones */ +#define SCU_2500_COPRO_SEG0 0x104 +#define SCU_2500_COPRO_SEG1 0x108 +#define SCU_2500_COPRO_SEG2 0x10c +#define SCU_2500_COPRO_SEG3 0x110 +#define SCU_2500_COPRO_SEG4 0x114 +#define SCU_2500_COPRO_SEG5 0x118 +#define SCU_2500_COPRO_SEG6 0x11c +#define SCU_2500_COPRO_SEG7 0x120 +#define SCU_2500_COPRO_SEG8 0x124 +#define SCU_2500_COPRO_SEG_SWAP 0x00000001 +#define SCU_2500_COPRO_CACHE_CTL 0x128 +#define SCU_2500_COPRO_CACHE_EN 0x00000001 +#define SCU_2500_COPRO_SEG0_CACHE_EN 0x00000002 +#define SCU_2500_COPRO_SEG1_CACHE_EN 0x00000004 +#define SCU_2500_COPRO_SEG2_CACHE_EN 0x00000008 +#define SCU_2500_COPRO_SEG3_CACHE_EN 0x00000010 +#define SCU_2500_COPRO_SEG4_CACHE_EN 0x00000020 +#define SCU_2500_COPRO_SEG5_CACHE_EN 0x00000040 +#define SCU_2500_COPRO_SEG6_CACHE_EN 0x00000080 +#define SCU_2500_COPRO_SEG7_CACHE_EN 0x00000100 +#define SCU_2500_COPRO_SEG8_CACHE_EN 0x00000200 + +#define SCU_2400_COPRO_SEG0 0x104 +#define SCU_2400_COPRO_SEG2 0x108 +#define SCU_2400_COPRO_SEG4 0x10c +#define SCU_2400_COPRO_SEG6 0x110 +#define SCU_2400_COPRO_SEG8 0x114 +#define SCU_2400_COPRO_SEG_SWAP 0x80000000 +#define SCU_2400_COPRO_CACHE_CTL 0x118 +#define SCU_2400_COPRO_CACHE_EN 0x00000001 +#define SCU_2400_COPRO_SEG0_CACHE_EN 0x00000002 +#define SCU_2400_COPRO_SEG2_CACHE_EN 0x00000004 +#define SCU_2400_COPRO_SEG4_CACHE_EN 0x00000008 +#define SCU_2400_COPRO_SEG6_CACHE_EN 0x00000010 +#define SCU_2400_COPRO_SEG8_CACHE_EN 0x00000020 + +/* CVIC registers */ +#define CVIC_EN_REG 0x10 +#define CVIC_TRIG_REG 0x18 + +/* + * System register base address (needed for configuring the + * coldfire maps) + */ +#define SYSREG_BASE 0x1e600000 + +/* Amount of SRAM required */ +#define SRAM_SIZE 0x1000 + +#define LAST_ADDR_INVALID 0x1 + +struct fsi_master_acf { + struct fsi_master master; + struct device *dev; + struct regmap *scu; + struct mutex lock; /* mutex for command ordering */ + struct gpio_desc *gpio_clk; + struct gpio_desc *gpio_data; + struct gpio_desc *gpio_trans; /* Voltage translator */ + struct gpio_desc *gpio_enable; /* FSI enable */ + struct gpio_desc *gpio_mux; /* Mux control */ + uint16_t gpio_clk_vreg; + uint16_t gpio_clk_dreg; + uint16_t gpio_dat_vreg; + uint16_t gpio_dat_dreg; + uint16_t gpio_tra_vreg; + uint16_t gpio_tra_dreg; + uint8_t gpio_clk_bit; + uint8_t gpio_dat_bit; + uint8_t gpio_tra_bit; + uint32_t cf_mem_addr; + size_t cf_mem_size; + void __iomem *cf_mem; + void __iomem *cvic; + struct gen_pool *sram_pool; + void __iomem *sram; + bool is_ast2500; + bool external_mode; + bool trace_enabled; + uint32_t last_addr; + uint8_t t_send_delay; + uint8_t t_echo_delay; + uint32_t cvic_sw_irq; +}; +#define to_fsi_master_acf(m) container_of(m, struct fsi_master_acf, master) + +struct fsi_msg { + uint64_t msg; + uint8_t bits; +}; + +#define CREATE_TRACE_POINTS +#include + +static void msg_push_bits(struct fsi_msg *msg, uint64_t data, int bits) +{ + msg->msg <<= bits; + msg->msg |= data & ((1ull << bits) - 1); + msg->bits += bits; +} + +static void msg_push_crc(struct fsi_msg *msg) +{ + uint8_t crc; + int top; + + top = msg->bits & 0x3; + + /* start bit, and any non-aligned top bits */ + crc = crc4(0, 1 << top | msg->msg >> (msg->bits - top), top + 1); + + /* aligned bits */ + crc = crc4(crc, msg->msg, msg->bits - top); + + msg_push_bits(msg, crc, 4); +} + +static void msg_finish_cmd(struct fsi_msg *cmd) +{ + /* Left align message */ + cmd->msg <<= (64 - cmd->bits); +} + +static bool check_same_address(struct fsi_master_acf *master, int id, + uint32_t addr) +{ + /* this will also handle LAST_ADDR_INVALID */ + return master->last_addr == (((id & 0x3) << 21) | (addr & ~0x3)); +} + +static bool check_relative_address(struct fsi_master_acf *master, int id, + uint32_t addr, uint32_t *rel_addrp) +{ + uint32_t last_addr = master->last_addr; + int32_t rel_addr; + + if (last_addr == LAST_ADDR_INVALID) + return false; + + /* We may be in 23-bit addressing mode, which uses the id as the + * top two address bits. So, if we're referencing a different ID, + * use absolute addresses. + */ + if (((last_addr >> 21) & 0x3) != id) + return false; + + /* remove the top two bits from any 23-bit addressing */ + last_addr &= (1 << 21) - 1; + + /* We know that the addresses are limited to 21 bits, so this won't + * overflow the signed rel_addr */ + rel_addr = addr - last_addr; + if (rel_addr > 255 || rel_addr < -256) + return false; + + *rel_addrp = (uint32_t)rel_addr; + + return true; +} + +static void last_address_update(struct fsi_master_acf *master, + int id, bool valid, uint32_t addr) +{ + if (!valid) + master->last_addr = LAST_ADDR_INVALID; + else + master->last_addr = ((id & 0x3) << 21) | (addr & ~0x3); +} + +/* + * Encode an Absolute/Relative/Same Address command + */ +static void build_ar_command(struct fsi_master_acf *master, + struct fsi_msg *cmd, uint8_t id, + uint32_t addr, size_t size, + const void *data) +{ + int i, addr_bits, opcode_bits; + bool write = !!data; + uint8_t ds, opcode; + uint32_t rel_addr; + + cmd->bits = 0; + cmd->msg = 0; + + /* we have 21 bits of address max */ + addr &= ((1 << 21) - 1); + + /* cmd opcodes are variable length - SAME_AR is only two bits */ + opcode_bits = 3; + + if (check_same_address(master, id, addr)) { + /* we still address the byte offset within the word */ + addr_bits = 2; + opcode_bits = 2; + opcode = FSI_CMD_SAME_AR; + trace_fsi_master_acf_cmd_same_addr(master); + + } else if (check_relative_address(master, id, addr, &rel_addr)) { + /* 8 bits plus sign */ + addr_bits = 9; + addr = rel_addr; + opcode = FSI_CMD_REL_AR; + trace_fsi_master_acf_cmd_rel_addr(master, rel_addr); + + } else { + addr_bits = 21; + opcode = FSI_CMD_ABS_AR; + trace_fsi_master_acf_cmd_abs_addr(master, addr); + } + + /* + * The read/write size is encoded in the lower bits of the address + * (as it must be naturally-aligned), and the following ds bit. + * + * size addr:1 addr:0 ds + * 1 x x 0 + * 2 x 0 1 + * 4 0 1 1 + * + */ + ds = size > 1 ? 1 : 0; + addr &= ~(size - 1); + if (size == 4) + addr |= 1; + + msg_push_bits(cmd, id, 2); + msg_push_bits(cmd, opcode, opcode_bits); + msg_push_bits(cmd, write ? 0 : 1, 1); + msg_push_bits(cmd, addr, addr_bits); + msg_push_bits(cmd, ds, 1); + for (i = 0; write && i < size; i++) + msg_push_bits(cmd, ((uint8_t *)data)[i], 8); + + msg_push_crc(cmd); + msg_finish_cmd(cmd); +} + +static void build_dpoll_command(struct fsi_msg *cmd, uint8_t slave_id) +{ + cmd->bits = 0; + cmd->msg = 0; + + msg_push_bits(cmd, slave_id, 2); + msg_push_bits(cmd, FSI_CMD_DPOLL, 3); + msg_push_crc(cmd); + msg_finish_cmd(cmd); +} + +static void build_epoll_command(struct fsi_msg *cmd, uint8_t slave_id) +{ + cmd->bits = 0; + cmd->msg = 0; + + msg_push_bits(cmd, slave_id, 2); + msg_push_bits(cmd, FSI_CMD_EPOLL, 3); + msg_push_crc(cmd); + msg_finish_cmd(cmd); +} + +static void build_term_command(struct fsi_msg *cmd, uint8_t slave_id) +{ + cmd->bits = 0; + cmd->msg = 0; + + msg_push_bits(cmd, slave_id, 2); + msg_push_bits(cmd, FSI_CMD_TERM, 6); + msg_push_crc(cmd); + msg_finish_cmd(cmd); +} + +static int do_copro_command(struct fsi_master_acf *master, uint32_t op) +{ + uint32_t timeout = 10000000; + uint8_t stat; + + trace_fsi_master_acf_copro_command(master, op); + + /* Send command */ + iowrite32be(op, master->sram + CMD_STAT_REG); + + /* Ring doorbell if any */ + if (master->cvic) + iowrite32(0x2, master->cvic + CVIC_TRIG_REG); + + /* Wait for status to indicate completion (or error) */ + do { + if (timeout-- == 0) { + dev_warn(master->dev, + "Timeout waiting for coprocessor completion\n"); + return -ETIMEDOUT; + } + stat = ioread8(master->sram + CMD_STAT_REG); + } while(stat < STAT_COMPLETE || stat == 0xff); + + if (stat == STAT_COMPLETE) + return 0; + switch(stat) { + case STAT_ERR_INVAL_CMD: + return -EINVAL; + case STAT_ERR_INVAL_IRQ: + return -EIO; + case STAT_ERR_MTOE: + return -ESHUTDOWN; + } + return -ENXIO; +} + +static int clock_zeros(struct fsi_master_acf *master, int count) +{ + while (count) { + int rc, lcnt = min(count, 255); + + rc = do_copro_command(master, + CMD_IDLE_CLOCKS | (lcnt << CMD_REG_CLEN_SHIFT)); + if (rc) + return rc; + count -= lcnt; + } + return 0; +} + +static int send_request(struct fsi_master_acf *master, struct fsi_msg *cmd, + unsigned int resp_bits) +{ + uint32_t op; + + trace_fsi_master_acf_send_request(master, cmd, resp_bits); + + /* Store message into SRAM */ + iowrite32be((cmd->msg >> 32), master->sram + CMD_DATA); + iowrite32be((cmd->msg & 0xffffffff), master->sram + CMD_DATA + 4); + + op = CMD_COMMAND; + op |= cmd->bits << CMD_REG_CLEN_SHIFT; + if (resp_bits) + op |= resp_bits << CMD_REG_RLEN_SHIFT; + + return do_copro_command(master, op); +} + +static int read_copro_response(struct fsi_master_acf *master, uint8_t size, + uint32_t *response, u8 *tag) +{ + uint8_t rtag = ioread8(master->sram + STAT_RTAG); + uint8_t rcrc = ioread8(master->sram + STAT_RCRC); + uint32_t rdata = 0; + uint32_t crc; + uint8_t ack; + + *tag = ack = rtag & 3; + + /* we have a whole message now; check CRC */ + crc = crc4(0, 1, 1); + crc = crc4(crc, rtag, 4); + if (ack == FSI_RESP_ACK && size) { + rdata = ioread32be(master->sram + RSP_DATA); + crc = crc4(crc, rdata, size); + if (response) + *response = rdata; + } + crc = crc4(crc, rcrc, 4); + + trace_fsi_master_acf_copro_response(master, rtag, rcrc, rdata, crc == 0); + + if (crc) { + /* + * Check if it's all 1's or all 0's, that probably means + * the host is off + */ + if ((rtag == 0xf && rcrc == 0xf) || (rtag == 0 && rcrc == 0)) + return -ENODEV; + dev_dbg(master->dev, "Bad response CRC !\n"); + return -EAGAIN; + } + return 0; +} + +static int send_term(struct fsi_master_acf *master, uint8_t slave) +{ + struct fsi_msg cmd; + uint8_t tag; + int rc; + + build_term_command(&cmd, slave); + + rc = send_request(master, &cmd, 0); + if (rc) { + dev_warn(master->dev, "Error %d sending term\n", rc); + return rc; + } + + rc = read_copro_response(master, 0, NULL, &tag); + if (rc < 0) { + dev_err(master->dev, + "TERM failed; lost communication with slave\n"); + return -EIO; + } else if (tag != FSI_RESP_ACK) { + dev_err(master->dev, "TERM failed; response %d\n", tag); + return -EIO; + } + return 0; +} + +static void dump_trace(struct fsi_master_acf *master) +{ + char trbuf[52]; + char *p; + int i; + + dev_dbg(master->dev, + "CMDSTAT:%08x RTAG=%02x RCRC=%02x RDATA=%02x #INT=%08x\n", + ioread32be(master->sram + CMD_STAT_REG), + ioread8(master->sram + STAT_RTAG), + ioread8(master->sram + STAT_RCRC), + ioread32be(master->sram + RSP_DATA), + ioread32be(master->sram + INT_CNT)); + + for (i = 0; i < 512; i++) { + uint8_t v; + if ((i % 16) == 0) + p = trbuf; + v = ioread8(master->sram + TRACEBUF + i); + p += sprintf(p, "%02x ", v); + if (((i % 16) == 15) || v == TR_END) + dev_dbg(master->dev, "%s\n", trbuf); + if (v == TR_END) + break; + } +} + +static int handle_response(struct fsi_master_acf *master, + uint8_t slave, uint8_t size, void *data) +{ + int busy_count = 0, rc; + int crc_err_retries = 0; + struct fsi_msg cmd; + uint32_t response; + uint8_t tag; +retry: + rc = read_copro_response(master, size, &response, &tag); + + /* Handle retries on CRC errors */ + if (rc == -EAGAIN) { + /* Too many retries ? */ + if (crc_err_retries++ > FSI_CRC_ERR_RETRIES) { + /* + * Pass it up as a -EIO otherwise upper level will retry + * the whole command which isn't what we want here. + */ + rc = -EIO; + goto bail; + } + trace_fsi_master_acf_crc_rsp_error(master, crc_err_retries); + if (master->trace_enabled) + dump_trace(master); + rc = clock_zeros(master, FSI_MASTER_EPOLL_CLOCKS); + if (rc) { + dev_warn(master->dev, + "Error %d clocking zeros for E_POLL\n", rc); + return rc; + } + build_epoll_command(&cmd, slave); + rc = send_request(master, &cmd, size); + if (rc) { + dev_warn(master->dev, "Error %d sending E_POLL\n", rc); + return -EIO; + } + goto retry; + } + if (rc) + return rc; + + switch (tag) { + case FSI_RESP_ACK: + if (size && data) { + if (size == 32) + *(__be32 *)data = cpu_to_be32(response); + else if (size == 16) + *(__be16 *)data = cpu_to_be16(response); + else + *(u8 *)data = response; + } + break; + case FSI_RESP_BUSY: + /* + * Its necessary to clock slave before issuing + * d-poll, not indicated in the hardware protocol + * spec. < 20 clocks causes slave to hang, 21 ok. + */ + dev_dbg(master->dev, "Busy, retrying...\n"); + if (master->trace_enabled) + dump_trace(master); + rc = clock_zeros(master, FSI_MASTER_DPOLL_CLOCKS); + if (rc) { + dev_warn(master->dev, + "Error %d clocking zeros for D_POLL\n", rc); + break; + } + if (busy_count++ < FSI_MASTER_MAX_BUSY) { + build_dpoll_command(&cmd, slave); + rc = send_request(master, &cmd, size); + if (rc) { + dev_warn(master->dev, "Error %d sending D_POLL\n", rc); + break; + } + goto retry; + } + dev_dbg(master->dev, + "ERR slave is stuck in busy state, issuing TERM\n"); + send_term(master, slave); + rc = -EIO; + break; + + case FSI_RESP_ERRA: + dev_dbg(master->dev, "ERRA received\n"); + if (master->trace_enabled) + dump_trace(master); + rc = -EIO; + break; + case FSI_RESP_ERRC: + dev_dbg(master->dev, "ERRC received\n"); + if (master->trace_enabled) + dump_trace(master); + rc = -EAGAIN; + break; + } + bail: + if (busy_count > 0) { + trace_fsi_master_acf_poll_response_busy(master, busy_count); + } + + return rc; +} + +static int fsi_master_acf_xfer(struct fsi_master_acf *master, uint8_t slave, + struct fsi_msg *cmd, size_t resp_len, void *resp) +{ + int rc = -EAGAIN, retries = 0; + + resp_len <<= 3; + while ((retries++) < FSI_CRC_ERR_RETRIES) { + rc = send_request(master, cmd, resp_len); + if (rc) { + if (rc != -ESHUTDOWN) + dev_warn(master->dev, "Error %d sending command\n", rc); + break; + } + rc = handle_response(master, slave, resp_len, resp); + if (rc != -EAGAIN) + break; + rc = -EIO; + dev_dbg(master->dev, "ECRC retry %d\n", retries); + + /* Pace it a bit before retry */ + msleep(1); + } + + return rc; +} + +static int fsi_master_acf_read(struct fsi_master *_master, int link, + uint8_t id, uint32_t addr, void *val, + size_t size) +{ + struct fsi_master_acf *master = to_fsi_master_acf(_master); + struct fsi_msg cmd; + int rc; + + if (link != 0) + return -ENODEV; + + mutex_lock(&master->lock); + dev_dbg(master->dev, "read id %d addr %x size %ud\n", id, addr, size); + build_ar_command(master, &cmd, id, addr, size, NULL); + rc = fsi_master_acf_xfer(master, id, &cmd, size, val); + last_address_update(master, id, rc == 0, addr); + if (rc) + dev_dbg(master->dev, "read id %d addr 0x%08x err: %d\n", + id, addr, rc); + mutex_unlock(&master->lock); + + return rc; +} + +static int fsi_master_acf_write(struct fsi_master *_master, int link, + uint8_t id, uint32_t addr, const void *val, + size_t size) +{ + struct fsi_master_acf *master = to_fsi_master_acf(_master); + struct fsi_msg cmd; + int rc; + + if (link != 0) + return -ENODEV; + + mutex_lock(&master->lock); + build_ar_command(master, &cmd, id, addr, size, val); + dev_dbg(master->dev, "write id %d addr %x size %ud raw_data: %08x\n", + id, addr, size, *(uint32_t *)val); + rc = fsi_master_acf_xfer(master, id, &cmd, 0, NULL); + last_address_update(master, id, rc == 0, addr); + if (rc) + dev_dbg(master->dev, "write id %d addr 0x%08x err: %d\n", + id, addr, rc); + mutex_unlock(&master->lock); + + return rc; +} + +static int fsi_master_acf_term(struct fsi_master *_master, + int link, uint8_t id) +{ + struct fsi_master_acf *master = to_fsi_master_acf(_master); + struct fsi_msg cmd; + int rc; + + if (link != 0) + return -ENODEV; + + mutex_lock(&master->lock); + build_term_command(&cmd, id); + dev_dbg(master->dev, "term id %d\n", id); + rc = fsi_master_acf_xfer(master, id, &cmd, 0, NULL); + last_address_update(master, id, false, 0); + mutex_unlock(&master->lock); + + return rc; +} + +static int fsi_master_acf_break(struct fsi_master *_master, int link) +{ + struct fsi_master_acf *master = to_fsi_master_acf(_master); + int rc; + + if (link != 0) + return -ENODEV; + + mutex_lock(&master->lock); + if (master->external_mode) { + mutex_unlock(&master->lock); + return -EBUSY; + } + dev_dbg(master->dev, "sending BREAK\n"); + rc = do_copro_command(master, CMD_BREAK); + last_address_update(master, 0, false, 0); + mutex_unlock(&master->lock); + + /* Wait for logic reset to take effect */ + udelay(200); + + return rc; +} + +static void reset_cf(struct fsi_master_acf *master) +{ + regmap_write(master->scu, SCU_COPRO_CTRL, SCU_COPRO_RESET); + usleep_range(20,20); + regmap_write(master->scu, SCU_COPRO_CTRL, 0); + usleep_range(20,20); +} + +static void start_cf(struct fsi_master_acf *master) +{ + regmap_write(master->scu, SCU_COPRO_CTRL, SCU_COPRO_CLK_EN); +} + +static void setup_ast2500_cf_maps(struct fsi_master_acf *master) +{ + /* + * Note about byteswap setting: the bus is wired backwards, + * so setting the byteswap bit actually makes the ColdFire + * work "normally" for a BE processor, ie, put the MSB in + * the lowest address byte. + * + * We thus need to set the bit for our main memory which + * contains our program code. We create two mappings for + * the register, one with each setting. + * + * Segments 2 and 3 has a "swapped" mapping (BE) + * and 6 and 7 have a non-swapped mapping (LE) which allows + * us to avoid byteswapping register accesses since the + * registers are all LE. + */ + + /* Setup segment 0 to our memory region */ + regmap_write(master->scu, SCU_2500_COPRO_SEG0, master->cf_mem_addr | + SCU_2500_COPRO_SEG_SWAP); + + /* Segments 2 and 3 to sysregs with byteswap (for SRAM) */ + regmap_write(master->scu, SCU_2500_COPRO_SEG2, SYSREG_BASE | + SCU_2500_COPRO_SEG_SWAP); + regmap_write(master->scu, SCU_2500_COPRO_SEG3, SYSREG_BASE | 0x100000 | + SCU_2500_COPRO_SEG_SWAP); + + /* And segment 6 and 7 to sysregs no byteswap */ + regmap_write(master->scu, SCU_2500_COPRO_SEG6, SYSREG_BASE); + regmap_write(master->scu, SCU_2500_COPRO_SEG7, SYSREG_BASE | 0x100000); + + /* Memory cachable, regs and SRAM not cachable */ + regmap_write(master->scu, SCU_2500_COPRO_CACHE_CTL, + SCU_2500_COPRO_SEG0_CACHE_EN | SCU_2500_COPRO_CACHE_EN); +} + +static void setup_ast2400_cf_maps(struct fsi_master_acf *master) +{ + /* Setup segment 0 to our memory region */ + regmap_write(master->scu, SCU_2400_COPRO_SEG0, master->cf_mem_addr | + SCU_2400_COPRO_SEG_SWAP); + + /* Segments 2 to sysregs with byteswap (for SRAM) */ + regmap_write(master->scu, SCU_2400_COPRO_SEG2, SYSREG_BASE | + SCU_2400_COPRO_SEG_SWAP); + + /* And segment 6 to sysregs no byteswap */ + regmap_write(master->scu, SCU_2400_COPRO_SEG6, SYSREG_BASE); + + /* Memory cachable, regs and SRAM not cachable */ + regmap_write(master->scu, SCU_2400_COPRO_CACHE_CTL, + SCU_2400_COPRO_SEG0_CACHE_EN | SCU_2400_COPRO_CACHE_EN); +} + +static void setup_common_fw_config(struct fsi_master_acf *master, + void __iomem *base) +{ + iowrite16be(master->gpio_clk_vreg, base + HDR_CLOCK_GPIO_VADDR); + iowrite16be(master->gpio_clk_dreg, base + HDR_CLOCK_GPIO_DADDR); + iowrite16be(master->gpio_dat_vreg, base + HDR_DATA_GPIO_VADDR); + iowrite16be(master->gpio_dat_dreg, base + HDR_DATA_GPIO_DADDR); + iowrite16be(master->gpio_tra_vreg, base + HDR_TRANS_GPIO_VADDR); + iowrite16be(master->gpio_tra_dreg, base + HDR_TRANS_GPIO_DADDR); + iowrite8(master->gpio_clk_bit, base + HDR_CLOCK_GPIO_BIT); + iowrite8(master->gpio_dat_bit, base + HDR_DATA_GPIO_BIT); + iowrite8(master->gpio_tra_bit, base + HDR_TRANS_GPIO_BIT); +} + +static void setup_ast2500_fw_config(struct fsi_master_acf *master) +{ + void __iomem *base = master->cf_mem + HDR_OFFSET; + + setup_common_fw_config(master, base); + iowrite32be(FW_CONTROL_USE_STOP, base + HDR_FW_CONTROL); +} + +static void setup_ast2400_fw_config(struct fsi_master_acf *master) +{ + void __iomem *base = master->cf_mem + HDR_OFFSET; + + setup_common_fw_config(master, base); + iowrite32be(FW_CONTROL_CONT_CLOCK|FW_CONTROL_DUMMY_RD, base + HDR_FW_CONTROL); +} + +static int setup_gpios_for_copro(struct fsi_master_acf *master) +{ + + int rc; + + /* This aren't under ColdFire control, just set them up appropriately */ + gpiod_direction_output(master->gpio_mux, 1); + gpiod_direction_output(master->gpio_enable, 1); + + /* Those are under ColdFire control, let it configure them */ + rc = aspeed_gpio_copro_grab_gpio(master->gpio_clk, &master->gpio_clk_vreg, + &master->gpio_clk_dreg, &master->gpio_clk_bit); + if (rc) { + dev_err(master->dev, "failed to assign clock gpio to coprocessor\n"); + return rc; + } + rc = aspeed_gpio_copro_grab_gpio(master->gpio_data, &master->gpio_dat_vreg, + &master->gpio_dat_dreg, &master->gpio_dat_bit); + if (rc) { + dev_err(master->dev, "failed to assign data gpio to coprocessor\n"); + aspeed_gpio_copro_release_gpio(master->gpio_clk); + return rc; + } + rc = aspeed_gpio_copro_grab_gpio(master->gpio_trans, &master->gpio_tra_vreg, + &master->gpio_tra_dreg, &master->gpio_tra_bit); + if (rc) { + dev_err(master->dev, "failed to assign trans gpio to coprocessor\n"); + aspeed_gpio_copro_release_gpio(master->gpio_clk); + aspeed_gpio_copro_release_gpio(master->gpio_data); + return rc; + } + return 0; +} + +static void release_copro_gpios(struct fsi_master_acf *master) +{ + aspeed_gpio_copro_release_gpio(master->gpio_clk); + aspeed_gpio_copro_release_gpio(master->gpio_data); + aspeed_gpio_copro_release_gpio(master->gpio_trans); +} + +static int load_copro_firmware(struct fsi_master_acf *master) +{ + const struct firmware *fw; + uint16_t sig = 0, wanted_sig; + const u8 *data; + size_t size = 0; + int rc; + + /* Get the binary */ + rc = request_firmware(&fw, FW_FILE_NAME, master->dev); + if (rc) { + dev_err( + master->dev, "Error %d to load firwmare '%s' !\n", + rc, FW_FILE_NAME); + return rc; + } + + /* Which image do we want ? (shared vs. split clock/data GPIOs) */ + if (master->gpio_clk_vreg == master->gpio_dat_vreg) + wanted_sig = SYS_SIG_SHARED; + else + wanted_sig = SYS_SIG_SPLIT; + dev_dbg(master->dev, "Looking for image sig %04x\n", wanted_sig); + + /* Try to find it */ + for (data = fw->data; data < (fw->data + fw->size);) { + sig = be16_to_cpup((__be16 *)(data + HDR_OFFSET + HDR_SYS_SIG)); + size = be32_to_cpup((__be32 *)(data + HDR_OFFSET + HDR_FW_SIZE)); + if (sig == wanted_sig) + break; + data += size; + } + if (sig != wanted_sig) { + dev_err(master->dev, "Failed to locate image sig %04x in FW blob\n", + wanted_sig); + return -ENODEV; + } + if (size > master->cf_mem_size) { + dev_err(master->dev, "FW size (%zd) bigger than memory reserve (%zd)\n", + fw->size, master->cf_mem_size); + rc = -ENOMEM; + } else { + memcpy_toio(master->cf_mem, data, size); + } + release_firmware(fw); + + return rc; +} + +static int check_firmware_image(struct fsi_master_acf *master) +{ + uint32_t fw_vers, fw_api, fw_options; + + fw_vers = ioread16be(master->cf_mem + HDR_OFFSET + HDR_FW_VERS); + fw_api = ioread16be(master->cf_mem + HDR_OFFSET + HDR_API_VERS); + fw_options = ioread32be(master->cf_mem + HDR_OFFSET + HDR_FW_OPTIONS); + master->trace_enabled = !!(fw_options & FW_OPTION_TRACE_EN); + + /* Check version and signature */ + dev_info(master->dev, "ColdFire initialized, firmware v%d API v%d.%d (trace %s)\n", + fw_vers, fw_api >> 8, fw_api & 0xff, + master->trace_enabled ? "enabled" : "disabled"); + + if ((fw_api >> 8) != API_VERSION_MAJ) { + dev_err(master->dev, "Unsupported coprocessor API version !\n"); + return -ENODEV; + } + + return 0; +} + +static int copro_enable_sw_irq(struct fsi_master_acf *master) +{ + int timeout; + uint32_t val; + + /* + * Enable coprocessor interrupt input. I've had problems getting the + * value to stick, so try in a loop + */ + for (timeout = 0; timeout < 10; timeout++) { + iowrite32(0x2, master->cvic + CVIC_EN_REG); + val = ioread32(master->cvic + CVIC_EN_REG); + if (val & 2) + break; + msleep(1); + } + if (!(val & 2)) { + dev_err(master->dev, "Failed to enable coprocessor interrupt !\n"); + return -ENODEV; + } + return 0; +} + +static int fsi_master_acf_setup(struct fsi_master_acf *master) +{ + int timeout, rc; + uint32_t val; + + /* Make sure the ColdFire is stopped */ + reset_cf(master); + + /* + * Clear SRAM. This needs to happen before we setup the GPIOs + * as we might start trying to arbitrate as soon as that happens. + */ + memset_io(master->sram, 0, SRAM_SIZE); + + /* Configure GPIOs */ + rc = setup_gpios_for_copro(master); + if (rc) + return rc; + + /* Load the firmware into the reserved memory */ + rc = load_copro_firmware(master); + if (rc) + return rc; + + /* Read signature and check versions */ + rc = check_firmware_image(master); + if (rc) + return rc; + + /* Setup coldfire memory map */ + if (master->is_ast2500) { + setup_ast2500_cf_maps(master); + setup_ast2500_fw_config(master); + } else { + setup_ast2400_cf_maps(master); + setup_ast2400_fw_config(master); + } + + /* Start the ColdFire */ + start_cf(master); + + /* Wait for status register to indicate command completion + * which signals the initialization is complete + */ + for (timeout = 0; timeout < 10; timeout++) { + val = ioread8(master->sram + CF_STARTED); + if (val) + break; + msleep(1); + } + if (!val) { + dev_err(master->dev, "Coprocessor startup timeout !\n"); + rc = -ENODEV; + goto err; + } + + /* Configure echo & send delay */ + iowrite8(master->t_send_delay, master->sram + SEND_DLY_REG); + iowrite8(master->t_echo_delay, master->sram + ECHO_DLY_REG); + + /* Enable SW interrupt to copro if any */ + if (master->cvic) { + rc = copro_enable_sw_irq(master); + if (rc) + goto err; + } + return 0; + err: + /* An error occurred, don't leave the coprocessor running */ + reset_cf(master); + + /* Release the GPIOs */ + release_copro_gpios(master); + + return rc; +} + + +static void fsi_master_acf_terminate(struct fsi_master_acf *master) +{ + unsigned long flags; + + /* + * A GPIO arbitration requestion could come in while this is + * happening. To avoid problems, we disable interrupts so it + * cannot preempt us on this CPU + */ + + local_irq_save(flags); + + /* Stop the coprocessor */ + reset_cf(master); + + /* We mark the copro not-started */ + iowrite32(0, master->sram + CF_STARTED); + + /* We mark the ARB register as having given up arbitration to + * deal with a potential race with the arbitration request + */ + iowrite8(ARB_ARM_ACK, master->sram + ARB_REG); + + local_irq_restore(flags); + + /* Return the GPIOs to the ARM */ + release_copro_gpios(master); +} + +static void fsi_master_acf_setup_external(struct fsi_master_acf *master) +{ + /* Setup GPIOs for external FSI master (FSP box) */ + gpiod_direction_output(master->gpio_mux, 0); + gpiod_direction_output(master->gpio_trans, 0); + gpiod_direction_output(master->gpio_enable, 1); + gpiod_direction_input(master->gpio_clk); + gpiod_direction_input(master->gpio_data); +} + +static int fsi_master_acf_link_enable(struct fsi_master *_master, int link) +{ + struct fsi_master_acf *master = to_fsi_master_acf(_master); + int rc = -EBUSY; + + if (link != 0) + return -ENODEV; + + mutex_lock(&master->lock); + if (!master->external_mode) { + gpiod_set_value(master->gpio_enable, 1); + rc = 0; + } + mutex_unlock(&master->lock); + + return rc; +} + +static int fsi_master_acf_link_config(struct fsi_master *_master, int link, + u8 t_send_delay, u8 t_echo_delay) +{ + struct fsi_master_acf *master = to_fsi_master_acf(_master); + + if (link != 0) + return -ENODEV; + + mutex_lock(&master->lock); + master->t_send_delay = t_send_delay; + master->t_echo_delay = t_echo_delay; + dev_dbg(master->dev, "Changing delays: send=%d echo=%d\n", + t_send_delay, t_echo_delay); + iowrite8(master->t_send_delay, master->sram + SEND_DLY_REG); + iowrite8(master->t_echo_delay, master->sram + ECHO_DLY_REG); + mutex_unlock(&master->lock); + + return 0; +} + +static ssize_t external_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fsi_master_acf *master = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE - 1, "%u\n", + master->external_mode ? 1 : 0); +} + +static ssize_t external_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct fsi_master_acf *master = dev_get_drvdata(dev); + unsigned long val; + bool external_mode; + int err; + + err = kstrtoul(buf, 0, &val); + if (err) + return err; + + external_mode = !!val; + + mutex_lock(&master->lock); + + if (external_mode == master->external_mode) { + mutex_unlock(&master->lock); + return count; + } + + master->external_mode = external_mode; + if (master->external_mode) { + fsi_master_acf_terminate(master); + fsi_master_acf_setup_external(master); + } else + fsi_master_acf_setup(master); + + mutex_unlock(&master->lock); + + fsi_master_rescan(&master->master); + + return count; +} + +static DEVICE_ATTR(external_mode, 0664, + external_mode_show, external_mode_store); + +static int fsi_master_acf_gpio_request(void *data) +{ + struct fsi_master_acf *master = data; + int timeout; + u8 val; + + /* Note: This doesn't require holding out mutex */ + + /* Write reqest */ + iowrite8(ARB_ARM_REQ, master->sram + ARB_REG); + + /* + * There is a race (which does happen at boot time) when we get an + * arbitration request as we are either about to or just starting + * the coprocessor. + * + * To handle it, we first check if we are running. If not yet we + * check whether the copro is started in the SCU. + * + * If it's not started, we can basically just assume we have arbitration + * and return. Otherwise, we wait normally expecting for the arbitration + * to eventually complete. + */ + if (ioread32(master->sram + CF_STARTED) == 0) { + unsigned int reg = 0; + + regmap_read(master->scu, SCU_COPRO_CTRL, ®); + if (!(reg & SCU_COPRO_CLK_EN)) + return 0; + } + + /* Ring doorbell if any */ + if (master->cvic) + iowrite32(0x2, master->cvic + CVIC_TRIG_REG); + + for (timeout = 0; timeout < 10000; timeout++) { + val = ioread8(master->sram + ARB_REG); + if (val != ARB_ARM_REQ) + break; + udelay(1); + } + + /* If it failed, override anyway */ + if (val != ARB_ARM_ACK) + dev_warn(master->dev, "GPIO request arbitration timeout\n"); + + return 0; +} + +static int fsi_master_acf_gpio_release(void *data) +{ + struct fsi_master_acf *master = data; + + /* Write release */ + iowrite8(0, master->sram + ARB_REG); + + /* Ring doorbell if any */ + if (master->cvic) + iowrite32(0x2, master->cvic + CVIC_TRIG_REG); + + return 0; +} + +static void fsi_master_acf_release(struct device *dev) +{ + struct fsi_master_acf *master = to_fsi_master_acf(dev_to_fsi_master(dev)); + + /* Cleanup, stop coprocessor */ + mutex_lock(&master->lock); + fsi_master_acf_terminate(master); + aspeed_gpio_copro_set_ops(NULL, NULL); + mutex_unlock(&master->lock); + + /* Free resources */ + gen_pool_free(master->sram_pool, (unsigned long)master->sram, SRAM_SIZE); + of_node_put(dev_of_node(master->dev)); + + kfree(master); +} + +static const struct aspeed_gpio_copro_ops fsi_master_acf_gpio_ops = { + .request_access = fsi_master_acf_gpio_request, + .release_access = fsi_master_acf_gpio_release, +}; + +static int fsi_master_acf_probe(struct platform_device *pdev) +{ + struct device_node *np, *mnode = dev_of_node(&pdev->dev); + struct genpool_data_fixed gpdf; + struct fsi_master_acf *master; + struct gpio_desc *gpio; + struct resource res; + uint32_t cf_mem_align; + int rc; + + master = kzalloc(sizeof(*master), GFP_KERNEL); + if (!master) + return -ENOMEM; + + master->dev = &pdev->dev; + master->master.dev.parent = master->dev; + master->last_addr = LAST_ADDR_INVALID; + + /* AST2400 vs. AST2500 */ + master->is_ast2500 = of_device_is_compatible(mnode, "aspeed,ast2500-cf-fsi-master"); + + /* Grab the SCU, we'll need to access it to configure the coprocessor */ + if (master->is_ast2500) + master->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2500-scu"); + else + master->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2400-scu"); + if (IS_ERR(master->scu)) { + dev_err(&pdev->dev, "failed to find SCU regmap\n"); + rc = PTR_ERR(master->scu); + goto err_free; + } + + /* Grab all the GPIOs we need */ + gpio = devm_gpiod_get(&pdev->dev, "clock", 0); + if (IS_ERR(gpio)) { + dev_err(&pdev->dev, "failed to get clock gpio\n"); + rc = PTR_ERR(gpio); + goto err_free; + } + master->gpio_clk = gpio; + + gpio = devm_gpiod_get(&pdev->dev, "data", 0); + if (IS_ERR(gpio)) { + dev_err(&pdev->dev, "failed to get data gpio\n"); + rc = PTR_ERR(gpio); + goto err_free; + } + master->gpio_data = gpio; + + /* Optional GPIOs */ + gpio = devm_gpiod_get_optional(&pdev->dev, "trans", 0); + if (IS_ERR(gpio)) { + dev_err(&pdev->dev, "failed to get trans gpio\n"); + rc = PTR_ERR(gpio); + goto err_free; + } + master->gpio_trans = gpio; + + gpio = devm_gpiod_get_optional(&pdev->dev, "enable", 0); + if (IS_ERR(gpio)) { + dev_err(&pdev->dev, "failed to get enable gpio\n"); + rc = PTR_ERR(gpio); + goto err_free; + } + master->gpio_enable = gpio; + + gpio = devm_gpiod_get_optional(&pdev->dev, "mux", 0); + if (IS_ERR(gpio)) { + dev_err(&pdev->dev, "failed to get mux gpio\n"); + rc = PTR_ERR(gpio); + goto err_free; + } + master->gpio_mux = gpio; + + /* Grab the reserved memory region (use DMA API instead ?) */ + np = of_parse_phandle(mnode, "memory-region", 0); + if (!np) { + dev_err(&pdev->dev, "Didn't find reserved memory\n"); + rc = -EINVAL; + goto err_free; + } + rc = of_address_to_resource(np, 0, &res); + of_node_put(np); + if (rc) { + dev_err(&pdev->dev, "Couldn't address to resource for reserved memory\n"); + rc = -ENOMEM; + goto err_free; + } + master->cf_mem_size = resource_size(&res); + master->cf_mem_addr = (uint32_t)res.start; + cf_mem_align = master->is_ast2500 ? 0x00100000 : 0x00200000; + if (master->cf_mem_addr & (cf_mem_align - 1)) { + dev_err(&pdev->dev, "Reserved memory has insufficient alignment\n"); + rc = -ENOMEM; + goto err_free; + } + master->cf_mem = devm_ioremap_resource(&pdev->dev, &res); + if (IS_ERR(master->cf_mem)) { + rc = PTR_ERR(master->cf_mem); + dev_err(&pdev->dev, "Error %d mapping coldfire memory\n", rc); + goto err_free; + } + dev_dbg(&pdev->dev, "DRAM allocation @%x\n", master->cf_mem_addr); + + /* AST2500 has a SW interrupt to the coprocessor */ + if (master->is_ast2500) { + /* Grab the CVIC (ColdFire interrupts controller) */ + np = of_parse_phandle(mnode, "aspeed,cvic", 0); + if (!np) { + dev_err(&pdev->dev, "Didn't find CVIC\n"); + rc = -EINVAL; + goto err_free; + } + master->cvic = devm_of_iomap(&pdev->dev, np, 0, NULL); + if (IS_ERR(master->cvic)) { + rc = PTR_ERR(master->cvic); + dev_err(&pdev->dev, "Error %d mapping CVIC\n", rc); + goto err_free; + } + rc = of_property_read_u32(np, "copro-sw-interrupts", + &master->cvic_sw_irq); + if (rc) { + dev_err(&pdev->dev, "Can't find coprocessor SW interrupt\n"); + goto err_free; + } + } + + /* Grab the SRAM */ + master->sram_pool = of_gen_pool_get(dev_of_node(&pdev->dev), "aspeed,sram", 0); + if (!master->sram_pool) { + rc = -ENODEV; + dev_err(&pdev->dev, "Can't find sram pool\n"); + goto err_free; + } + + /* Current microcode only deals with fixed location in SRAM */ + gpdf.offset = 0; + master->sram = (void __iomem *)gen_pool_alloc_algo(master->sram_pool, SRAM_SIZE, + gen_pool_fixed_alloc, &gpdf); + if (!master->sram) { + rc = -ENOMEM; + dev_err(&pdev->dev, "Failed to allocate sram from pool\n"); + goto err_free; + } + dev_dbg(&pdev->dev, "SRAM allocation @%lx\n", + (unsigned long)gen_pool_virt_to_phys(master->sram_pool, + (unsigned long)master->sram)); + + /* + * Hookup with the GPIO driver for arbitration of GPIO banks + * ownership. + */ + aspeed_gpio_copro_set_ops(&fsi_master_acf_gpio_ops, master); + + /* Default FSI command delays */ + master->t_send_delay = FSI_SEND_DELAY_CLOCKS; + master->t_echo_delay = FSI_ECHO_DELAY_CLOCKS; + master->master.n_links = 1; + if (master->is_ast2500) + master->master.flags = FSI_MASTER_FLAG_SWCLOCK; + master->master.read = fsi_master_acf_read; + master->master.write = fsi_master_acf_write; + master->master.term = fsi_master_acf_term; + master->master.send_break = fsi_master_acf_break; + master->master.link_enable = fsi_master_acf_link_enable; + master->master.link_config = fsi_master_acf_link_config; + master->master.dev.of_node = of_node_get(dev_of_node(master->dev)); + master->master.dev.release = fsi_master_acf_release; + platform_set_drvdata(pdev, master); + mutex_init(&master->lock); + + mutex_lock(&master->lock); + rc = fsi_master_acf_setup(master); + mutex_unlock(&master->lock); + if (rc) + goto release_of_dev; + + rc = device_create_file(&pdev->dev, &dev_attr_external_mode); + if (rc) + goto stop_copro; + + rc = fsi_master_register(&master->master); + if (!rc) + return 0; + + device_remove_file(master->dev, &dev_attr_external_mode); + put_device(&master->master.dev); + return rc; + + stop_copro: + fsi_master_acf_terminate(master); + release_of_dev: + aspeed_gpio_copro_set_ops(NULL, NULL); + gen_pool_free(master->sram_pool, (unsigned long)master->sram, SRAM_SIZE); + of_node_put(dev_of_node(master->dev)); + err_free: + kfree(master); + return rc; +} + + +static int fsi_master_acf_remove(struct platform_device *pdev) +{ + struct fsi_master_acf *master = platform_get_drvdata(pdev); + + device_remove_file(master->dev, &dev_attr_external_mode); + + fsi_master_unregister(&master->master); + + return 0; +} + +static const struct of_device_id fsi_master_acf_match[] = { + { .compatible = "aspeed,ast2400-cf-fsi-master" }, + { .compatible = "aspeed,ast2500-cf-fsi-master" }, + { }, +}; + +static struct platform_driver fsi_master_acf = { + .driver = { + .name = "fsi-master-acf", + .of_match_table = fsi_master_acf_match, + }, + .probe = fsi_master_acf_probe, + .remove = fsi_master_acf_remove, +}; + +module_platform_driver(fsi_master_acf); +MODULE_LICENSE("GPL"); diff --git a/include/trace/events/fsi_master_ast_cf.h b/include/trace/events/fsi_master_ast_cf.h new file mode 100644 index 000000000000..a0fdfa58622a --- /dev/null +++ b/include/trace/events/fsi_master_ast_cf.h @@ -0,0 +1,150 @@ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM fsi_master_ast_cf + +#if !defined(_TRACE_FSI_MASTER_ACF_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_FSI_MASTER_ACF_H + +#include + +TRACE_EVENT(fsi_master_acf_copro_command, + TP_PROTO(const struct fsi_master_acf *master, uint32_t op), + TP_ARGS(master, op), + TP_STRUCT__entry( + __field(int, master_idx) + __field(uint32_t, op) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + __entry->op = op; + ), + TP_printk("fsi-acf%d command %08x", + __entry->master_idx, __entry->op + ) +); + +TRACE_EVENT(fsi_master_acf_send_request, + TP_PROTO(const struct fsi_master_acf *master, const struct fsi_msg *cmd, u8 rbits), + TP_ARGS(master, cmd, rbits), + TP_STRUCT__entry( + __field(int, master_idx) + __field(uint64_t, msg) + __field(u8, bits) + __field(u8, rbits) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + __entry->msg = cmd->msg; + __entry->bits = cmd->bits; + __entry->rbits = rbits; + ), + TP_printk("fsi-acf%d cmd: %016llx/%d/%d", + __entry->master_idx, (unsigned long long)__entry->msg, + __entry->bits, __entry->rbits + ) +); + +TRACE_EVENT(fsi_master_acf_copro_response, + TP_PROTO(const struct fsi_master_acf *master, u8 rtag, u8 rcrc, __be32 rdata, bool crc_ok), + TP_ARGS(master, rtag, rcrc, rdata, crc_ok), + TP_STRUCT__entry( + __field(int, master_idx) + __field(u8, rtag) + __field(u8, rcrc) + __field(u32, rdata) + __field(bool, crc_ok) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + __entry->rtag = rtag; + __entry->rcrc = rcrc; + __entry->rdata = be32_to_cpu(rdata); + __entry->crc_ok = crc_ok; + ), + TP_printk("fsi-acf%d rsp: tag=%04x crc=%04x data=%08x %c\n", + __entry->master_idx, __entry->rtag, __entry->rcrc, + __entry->rdata, __entry->crc_ok ? ' ' : '!' + ) +); + +TRACE_EVENT(fsi_master_acf_crc_rsp_error, + TP_PROTO(const struct fsi_master_acf *master, int retries), + TP_ARGS(master, retries), + TP_STRUCT__entry( + __field(int, master_idx) + __field(int, retries) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + __entry->retries = retries; + ), + TP_printk("fsi-acf%d CRC error in response retry %d", + __entry->master_idx, __entry->retries + ) +); + +TRACE_EVENT(fsi_master_acf_poll_response_busy, + TP_PROTO(const struct fsi_master_acf *master, int busy_count), + TP_ARGS(master, busy_count), + TP_STRUCT__entry( + __field(int, master_idx) + __field(int, busy_count) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + __entry->busy_count = busy_count; + ), + TP_printk("fsi-acf%d: device reported busy %d times", + __entry->master_idx, __entry->busy_count + ) +); + +TRACE_EVENT(fsi_master_acf_cmd_abs_addr, + TP_PROTO(const struct fsi_master_acf *master, u32 addr), + TP_ARGS(master, addr), + TP_STRUCT__entry( + __field(int, master_idx) + __field(u32, addr) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + __entry->addr = addr; + ), + TP_printk("fsi-acf%d: Sending ABS_ADR %06x", + __entry->master_idx, __entry->addr + ) +); + +TRACE_EVENT(fsi_master_acf_cmd_rel_addr, + TP_PROTO(const struct fsi_master_acf *master, u32 rel_addr), + TP_ARGS(master, rel_addr), + TP_STRUCT__entry( + __field(int, master_idx) + __field(u32, rel_addr) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + __entry->rel_addr = rel_addr; + ), + TP_printk("fsi-acf%d: Sending REL_ADR %03x", + __entry->master_idx, __entry->rel_addr + ) +); + +TRACE_EVENT(fsi_master_acf_cmd_same_addr, + TP_PROTO(const struct fsi_master_acf *master), + TP_ARGS(master), + TP_STRUCT__entry( + __field(int, master_idx) + ), + TP_fast_assign( + __entry->master_idx = master->master.idx; + ), + TP_printk("fsi-acf%d: Sending SAME_ADR", + __entry->master_idx + ) +); + +#endif /* _TRACE_FSI_MASTER_ACF_H */ + +#include -- cgit v1.2.3-71-gd317 From 0ab5fe5374743d5a279b1ff6297ef2c54d06cd5f Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 20 Jun 2018 15:22:52 +1000 Subject: fsi: Add new central chardev support The various FSI devices (sbefifo, occ, scom, more to come) currently use misc devices. This is problematic as the minor device space for misc is limited and there can be a lot of them. Also it limits our ability to move them to a dedicated /dev/fsi directory or to be smart about device naming and numbering. It also means we have IDAs on every single of these drivers This creates a common fsi "device_type" for the optional /dev/fsi grouping and a dev_t allocator for all FSI devices. "Legacy" devices get to use a backward compatible numbering scheme (as long as chip id <16 and there's only one copy of a given unit type per chip). A single major number and a single IDA are shared for all FSI devices. This doesn't convert the FSI device drivers to use the new scheme yet, they will be converted individually. Signed-off-by: Benjamin Herrenschmidt --- drivers/fsi/Kconfig | 15 ++++++++ drivers/fsi/fsi-core.c | 95 ++++++++++++++++++++++++++++++++++++++++++++++++-- include/linux/fsi.h | 12 ++++++- 3 files changed, 119 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/drivers/fsi/Kconfig b/drivers/fsi/Kconfig index 8d82b1e60514..af3a20dd5aa4 100644 --- a/drivers/fsi/Kconfig +++ b/drivers/fsi/Kconfig @@ -12,6 +12,21 @@ menuconfig FSI if FSI +config FSI_NEW_DEV_NODE + bool "Create '/dev/fsi' directory for char devices" + default n + ---help--- + This option causes char devices created for FSI devices to be + located under a common /dev/fsi/ directory. Set to N unless your + userspace has been updated to handle the new location. + + Additionally, it also causes the char device names to be offset + by one so that chip 0 will have /dev/scom1 and chip1 /dev/scom2 + to match old userspace expectations. + + New userspace will use udev rules to generate predictable access + symlinks in /dev/fsi/by-path when this option is enabled. + config FSI_MASTER_GPIO tristate "GPIO-based FSI master" depends on GPIOLIB diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index eab6c5c4990e..faa1760a5a40 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -92,6 +92,13 @@ struct fsi_slave { static const int slave_retries = 2; static int discard_errors; +static dev_t fsi_base_dev; +static DEFINE_IDA(fsi_minor_ida); +#define FSI_CHAR_MAX_DEVICES 0x1000 + +/* Legacy /dev numbering: 4 devices per chip, 16 chips */ +#define FSI_CHAR_LEGACY_TOP 64 + static int fsi_master_read(struct fsi_master *master, int link, uint8_t slave_id, uint32_t addr, void *val, size_t size); static int fsi_master_write(struct fsi_master *master, int link, @@ -627,6 +634,7 @@ static void fsi_slave_release(struct device *dev) { struct fsi_slave *slave = to_fsi_slave(dev); + fsi_free_minor(slave->dev.devt); of_node_put(dev->of_node); kfree(slave); } @@ -729,6 +737,75 @@ static ssize_t chip_id_show(struct device *dev, static DEVICE_ATTR_RO(chip_id); +static char *fsi_cdev_devnode(struct device *dev, umode_t *mode, + kuid_t *uid, kgid_t *gid) +{ +#ifdef CONFIG_FSI_NEW_DEV_NODE + return kasprintf(GFP_KERNEL, "fsi/%s", dev_name(dev)); +#else + return kasprintf(GFP_KERNEL, "%s", dev_name(dev)); +#endif +} + +const struct device_type fsi_cdev_type = { + .name = "fsi-cdev", + .devnode = fsi_cdev_devnode, +}; +EXPORT_SYMBOL_GPL(fsi_cdev_type); + +/* Backward compatible /dev/ numbering in "old style" mode */ +static int fsi_adjust_index(int index) +{ +#ifdef CONFIG_FSI_NEW_DEV_NODE + return index; +#else + return index + 1; +#endif +} + +static int __fsi_get_new_minor(struct fsi_slave *slave, enum fsi_dev_type type, + dev_t *out_dev, int *out_index) +{ + int cid = slave->chip_id; + int id; + + /* Check if we qualify for legacy numbering */ + if (cid >= 0 && cid < 16 && type < 4) { + /* Try reserving the legacy number */ + id = (cid << 4) | type; + id = ida_simple_get(&fsi_minor_ida, id, id + 1, GFP_KERNEL); + if (id >= 0) { + *out_index = fsi_adjust_index(cid); + *out_dev = fsi_base_dev + id; + return 0; + } + /* Other failure */ + if (id != -ENOSPC) + return id; + /* Fallback to non-legacy allocation */ + } + id = ida_simple_get(&fsi_minor_ida, FSI_CHAR_LEGACY_TOP, + FSI_CHAR_MAX_DEVICES, GFP_KERNEL); + if (id < 0) + return id; + *out_index = fsi_adjust_index(id); + *out_dev = fsi_base_dev + id; + return 0; +} + +int fsi_get_new_minor(struct fsi_device *fdev, enum fsi_dev_type type, + dev_t *out_dev, int *out_index) +{ + return __fsi_get_new_minor(fdev->slave, type, out_dev, out_index); +} +EXPORT_SYMBOL_GPL(fsi_get_new_minor); + +void fsi_free_minor(dev_t dev) +{ + ida_simple_remove(&fsi_minor_ida, MINOR(dev)); +} +EXPORT_SYMBOL_GPL(fsi_free_minor); + static int fsi_slave_init(struct fsi_master *master, int link, uint8_t id) { uint32_t chip_id; @@ -953,7 +1030,7 @@ static int fsi_slave_remove_device(struct device *dev, void *arg) static int fsi_master_remove_slave(struct device *dev, void *arg) { device_for_each_child(dev, NULL, fsi_slave_remove_device); - device_unregister(dev); + put_device(dev); return 0; } @@ -1091,13 +1168,27 @@ EXPORT_SYMBOL_GPL(fsi_bus_type); static int __init fsi_init(void) { - return bus_register(&fsi_bus_type); + int rc; + + rc = alloc_chrdev_region(&fsi_base_dev, 0, FSI_CHAR_MAX_DEVICES, "fsi"); + if (rc) + return rc; + rc = bus_register(&fsi_bus_type); + if (rc) + goto fail_bus; + return 0; + + fail_bus: + unregister_chrdev_region(fsi_base_dev, FSI_CHAR_MAX_DEVICES); + return rc; } postcore_initcall(fsi_init); static void fsi_exit(void) { bus_unregister(&fsi_bus_type); + unregister_chrdev_region(fsi_base_dev, FSI_CHAR_MAX_DEVICES); + ida_destroy(&fsi_minor_ida); } module_exit(fsi_exit); module_param(discard_errors, int, 0664); diff --git a/include/linux/fsi.h b/include/linux/fsi.h index 141fd38d061f..ec3be0d5b786 100644 --- a/include/linux/fsi.h +++ b/include/linux/fsi.h @@ -76,8 +76,18 @@ extern int fsi_slave_read(struct fsi_slave *slave, uint32_t addr, extern int fsi_slave_write(struct fsi_slave *slave, uint32_t addr, const void *val, size_t size); +extern struct bus_type fsi_bus_type; +extern const struct device_type fsi_cdev_type; +enum fsi_dev_type { + fsi_dev_cfam, + fsi_dev_sbefifo, + fsi_dev_scom, + fsi_dev_occ +}; -extern struct bus_type fsi_bus_type; +extern int fsi_get_new_minor(struct fsi_device *fdev, enum fsi_dev_type type, + dev_t *out_dev, int *out_index); +extern void fsi_free_minor(dev_t dev); #endif /* LINUX_FSI_H */ -- cgit v1.2.3-71-gd317 From d3b26dd7cb0e3433bfd3c1d4dcf74c6039bb49fb Mon Sep 17 00:00:00 2001 From: Dexuan Cui Date: Thu, 2 Aug 2018 03:08:23 +0000 Subject: Drivers: hv: vmbus: Reset the channel callback in vmbus_onoffer_rescind() Before setting channel->rescind in vmbus_rescind_cleanup(), we should make sure the channel callback won't run any more, otherwise a high-level driver like pci_hyperv, which may be infinitely waiting for the host VSP's response and notices the channel has been rescinded, can't safely give up: e.g., in hv_pci_protocol_negotiation() -> wait_for_response(), it's unsafe to exit from wait_for_response() and proceed with the on-stack variable "comp_pkt" popped. The issue was originally spotted by Michael Kelley . In vmbus_close_internal(), the patch also minimizes the range protected by disabling/enabling channel->callback_event: we don't really need that for the whole function. Signed-off-by: Dexuan Cui Reviewed-by: Michael Kelley Cc: stable@vger.kernel.org Cc: K. Y. Srinivasan Cc: Stephen Hemminger Cc: Michael Kelley Signed-off-by: K. Y. Srinivasan Signed-off-by: Greg Kroah-Hartman --- drivers/hv/channel.c | 40 ++++++++++++++++++++++++---------------- drivers/hv/channel_mgmt.c | 6 ++++++ include/linux/hyperv.h | 2 ++ 3 files changed, 32 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/drivers/hv/channel.c b/drivers/hv/channel.c index ba0a092ae085..c3949220b770 100644 --- a/drivers/hv/channel.c +++ b/drivers/hv/channel.c @@ -558,11 +558,8 @@ static void reset_channel_cb(void *arg) channel->onchannel_callback = NULL; } -static int vmbus_close_internal(struct vmbus_channel *channel) +void vmbus_reset_channel_cb(struct vmbus_channel *channel) { - struct vmbus_channel_close_channel *msg; - int ret; - /* * vmbus_on_event(), running in the per-channel tasklet, can race * with vmbus_close_internal() in the case of SMP guest, e.g., when @@ -572,6 +569,29 @@ static int vmbus_close_internal(struct vmbus_channel *channel) */ tasklet_disable(&channel->callback_event); + channel->sc_creation_callback = NULL; + + /* Stop the callback asap */ + if (channel->target_cpu != get_cpu()) { + put_cpu(); + smp_call_function_single(channel->target_cpu, reset_channel_cb, + channel, true); + } else { + reset_channel_cb(channel); + put_cpu(); + } + + /* Re-enable tasklet for use on re-open */ + tasklet_enable(&channel->callback_event); +} + +static int vmbus_close_internal(struct vmbus_channel *channel) +{ + struct vmbus_channel_close_channel *msg; + int ret; + + vmbus_reset_channel_cb(channel); + /* * In case a device driver's probe() fails (e.g., * util_probe() -> vmbus_open() returns -ENOMEM) and the device is @@ -585,16 +605,6 @@ static int vmbus_close_internal(struct vmbus_channel *channel) } channel->state = CHANNEL_OPEN_STATE; - channel->sc_creation_callback = NULL; - /* Stop callback and cancel the timer asap */ - if (channel->target_cpu != get_cpu()) { - put_cpu(); - smp_call_function_single(channel->target_cpu, reset_channel_cb, - channel, true); - } else { - reset_channel_cb(channel); - put_cpu(); - } /* Send a closing message */ @@ -639,8 +649,6 @@ static int vmbus_close_internal(struct vmbus_channel *channel) get_order(channel->ringbuffer_pagecount * PAGE_SIZE)); out: - /* re-enable tasklet for use on re-open */ - tasklet_enable(&channel->callback_event); return ret; } diff --git a/drivers/hv/channel_mgmt.c b/drivers/hv/channel_mgmt.c index f3b551a50653..0f0e091c117c 100644 --- a/drivers/hv/channel_mgmt.c +++ b/drivers/hv/channel_mgmt.c @@ -892,6 +892,12 @@ static void vmbus_onoffer_rescind(struct vmbus_channel_message_header *hdr) return; } + /* + * Before setting channel->rescind in vmbus_rescind_cleanup(), we + * should make sure the channel callback is not running any more. + */ + vmbus_reset_channel_cb(channel); + /* * Now wait for offer handling to complete. */ diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h index 2330f08062c7..efda23cf32c7 100644 --- a/include/linux/hyperv.h +++ b/include/linux/hyperv.h @@ -1061,6 +1061,8 @@ extern int vmbus_establish_gpadl(struct vmbus_channel *channel, extern int vmbus_teardown_gpadl(struct vmbus_channel *channel, u32 gpadl_handle); +void vmbus_reset_channel_cb(struct vmbus_channel *channel); + extern int vmbus_recvpacket(struct vmbus_channel *channel, void *buffer, u32 bufferlen, -- cgit v1.2.3-71-gd317 From 72755eed6c1c5312425ad3d78bf0b916769e6125 Mon Sep 17 00:00:00 2001 From: Roman Kiryanov Date: Mon, 23 Jul 2018 15:47:26 -0700 Subject: goldfish: Add missing includes to goldfish.h goldfish.h refers to external symbols such as dma_addr_t and writel. This causes compilation errors if this file is included before other header files. The mentioned symbols are defined in types.h (dma_addr_t) and io.h (writel). Signed-off-by: Roman Kiryanov Signed-off-by: Greg Kroah-Hartman --- include/linux/goldfish.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/linux/goldfish.h b/include/linux/goldfish.h index 2835c150c3ff..159b4191f15d 100644 --- a/include/linux/goldfish.h +++ b/include/linux/goldfish.h @@ -2,6 +2,9 @@ #ifndef __LINUX_GOLDFISH_H #define __LINUX_GOLDFISH_H +#include +#include + /* Helpers for Goldfish virtual platform */ static inline void gf_write_ptr(const void *ptr, void __iomem *portl, -- cgit v1.2.3-71-gd317 From 68275680ea12e9f378e51ff525dacbb76f006764 Mon Sep 17 00:00:00 2001 From: Roman Kiryanov Date: Mon, 23 Jul 2018 15:47:27 -0700 Subject: goldfish: Use dedicated macros instead of manual bit shifting There are dedicated macros (lower_32_bits and upper_32_bits) available to extract the lower and upper 32 bits. They provide better readability and could prevent some compilation warnings. Signed-off-by: Roman Kiryanov Signed-off-by: Greg Kroah-Hartman --- include/linux/goldfish.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/linux/goldfish.h b/include/linux/goldfish.h index 159b4191f15d..265a099cd3b8 100644 --- a/include/linux/goldfish.h +++ b/include/linux/goldfish.h @@ -2,6 +2,7 @@ #ifndef __LINUX_GOLDFISH_H #define __LINUX_GOLDFISH_H +#include #include #include @@ -10,9 +11,11 @@ static inline void gf_write_ptr(const void *ptr, void __iomem *portl, void __iomem *porth) { - writel((u32)(unsigned long)ptr, portl); + const unsigned long addr = (unsigned long)ptr; + + writel(lower_32_bits(addr), portl); #ifdef CONFIG_64BIT - writel((unsigned long)ptr >> 32, porth); + writel(upper_32_bits(addr), porth); #endif } @@ -20,9 +23,9 @@ static inline void gf_write_dma_addr(const dma_addr_t addr, void __iomem *portl, void __iomem *porth) { - writel((u32)addr, portl); + writel(lower_32_bits(addr), portl); #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT - writel(addr >> 32, porth); + writel(upper_32_bits(addr), porth); #endif } -- cgit v1.2.3-71-gd317