cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

ioport.c (2551B)

      1/*
      2 * QEMU IDE disk and CD/DVD-ROM Emulator
      3 *
      4 * Copyright (c) 2003 Fabrice Bellard
      5 * Copyright (c) 2006 Openedhand Ltd.
      6 *
      7 * Permission is hereby granted, free of charge, to any person obtaining a copy
      8 * of this software and associated documentation files (the "Software"), to deal
      9 * in the Software without restriction, including without limitation the rights
     10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     11 * copies of the Software, and to permit persons to whom the Software is
     12 * furnished to do so, subject to the following conditions:
     13 *
     14 * The above copyright notice and this permission notice shall be included in
     15 * all copies or substantial portions of the Software.
     16 *
     17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     23 * THE SOFTWARE.
     24 */
     25
     26#include "qemu/osdep.h"
     27#include "hw/isa/isa.h"
     28#include "qemu/error-report.h"
     29#include "qemu/timer.h"
     30#include "sysemu/blockdev.h"
     31#include "sysemu/dma.h"
     32#include "hw/block/block.h"
     33#include "sysemu/block-backend.h"
     34#include "qapi/error.h"
     35#include "qemu/cutils.h"
     36#include "sysemu/replay.h"
     37
     38#include "hw/ide/internal.h"
     39#include "trace.h"
     40
     41static const MemoryRegionPortio ide_portio_list[] = {
     42    { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
     43    { 0, 1, 2, .read = ide_data_readw, .write = ide_data_writew },
     44    { 0, 1, 4, .read = ide_data_readl, .write = ide_data_writel },
     45    PORTIO_END_OF_LIST(),
     46};
     47
     48static const MemoryRegionPortio ide_portio2_list[] = {
     49    { 0, 1, 1, .read = ide_status_read, .write = ide_ctrl_write },
     50    PORTIO_END_OF_LIST(),
     51};
     52
     53int ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
     54{
     55    int ret;
     56
     57    /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
     58       bridge has been setup properly to always register with ISA.  */
     59    ret = isa_register_portio_list(dev, &bus->portio_list,
     60                                   iobase, ide_portio_list, bus, "ide");
     61
     62    if (ret == 0 && iobase2) {
     63        ret = isa_register_portio_list(dev, &bus->portio2_list,
     64                                       iobase2, ide_portio2_list, bus, "ide");
     65    }
     66
     67    return ret;
     68}