cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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slotid_cap.c (1501B)

      1#include "qemu/osdep.h"
      2#include "hw/pci/slotid_cap.h"
      3#include "hw/pci/pci.h"
      4#include "qemu/error-report.h"
      5#include "qapi/error.h"
      6
      7#define SLOTID_CAP_LENGTH 4
      8#define SLOTID_NSLOTS_SHIFT ctz32(PCI_SID_ESR_NSLOTS)
      9
     10int slotid_cap_init(PCIDevice *d, int nslots,
     11                    uint8_t chassis,
     12                    unsigned offset,
     13                    Error **errp)
     14{
     15    int cap;
     16
     17    if (!chassis) {
     18        error_setg(errp, "Bridge chassis not specified. Each bridge is required"
     19                   " to be assigned a unique chassis id > 0.");
     20        return -EINVAL;
     21    }
     22    if (nslots < 0 || nslots > (PCI_SID_ESR_NSLOTS >> SLOTID_NSLOTS_SHIFT)) {
     23        /* TODO: error report? */
     24        return -EINVAL;
     25    }
     26
     27    cap = pci_add_capability(d, PCI_CAP_ID_SLOTID, offset,
     28                             SLOTID_CAP_LENGTH, errp);
     29    if (cap < 0) {
     30        return cap;
     31    }
     32    /* We make each chassis unique, this way each bridge is First in Chassis */
     33    d->config[cap + PCI_SID_ESR] = PCI_SID_ESR_FIC |
     34        (nslots << SLOTID_NSLOTS_SHIFT);
     35    d->cmask[cap + PCI_SID_ESR] = 0xff;
     36    d->config[cap + PCI_SID_CHASSIS_NR] = chassis;
     37    /* Note: Chassis number register is non-volatile,
     38       so we don't reset it. */
     39    /* TODO: store in eeprom? */
     40    d->wmask[cap + PCI_SID_CHASSIS_NR] = 0xff;
     41
     42    d->cap_present |= QEMU_PCI_CAP_SLOTID;
     43    return 0;
     44}
     45
     46void slotid_cap_cleanup(PCIDevice *d)
     47{
     48    /* TODO: cleanup config space? */
     49    d->cap_present &= ~QEMU_PCI_CAP_SLOTID;
     50}