cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

virt.c (4962B)

      1/*
      2 * Copyright (c) 2019, Max Filippov, Open Source and Linux Lab.
      3 * All rights reserved.
      4 *
      5 * Redistribution and use in source and binary forms, with or without
      6 * modification, are permitted provided that the following conditions are met:
      7 *     * Redistributions of source code must retain the above copyright
      8 *       notice, this list of conditions and the following disclaimer.
      9 *     * Redistributions in binary form must reproduce the above copyright
     10 *       notice, this list of conditions and the following disclaimer in the
     11 *       documentation and/or other materials provided with the distribution.
     12 *     * Neither the name of the Open Source and Linux Lab nor the
     13 *       names of its contributors may be used to endorse or promote products
     14 *       derived from this software without specific prior written permission.
     15 *
     16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
     20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
     25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26 */
     27
     28#include "qemu/osdep.h"
     29#include "qapi/error.h"
     30#include "sysemu/reset.h"
     31#include "hw/boards.h"
     32#include "hw/loader.h"
     33#include "hw/pci-host/gpex.h"
     34#include "net/net.h"
     35#include "elf.h"
     36#include "exec/memory.h"
     37#include "qemu/error-report.h"
     38#include "xtensa_memory.h"
     39#include "xtensa_sim.h"
     40
     41static void create_pcie(CPUXtensaState *env, int irq_base, hwaddr addr_base)
     42{
     43    hwaddr base_ecam = addr_base + 0x00100000;
     44    hwaddr size_ecam =             0x03f00000;
     45    hwaddr base_pio  = addr_base + 0x00000000;
     46    hwaddr size_pio  =             0x00010000;
     47    hwaddr base_mmio = addr_base + 0x04000000;
     48    hwaddr size_mmio =             0x08000000;
     49
     50    MemoryRegion *ecam_alias;
     51    MemoryRegion *ecam_reg;
     52    MemoryRegion *pio_alias;
     53    MemoryRegion *pio_reg;
     54    MemoryRegion *mmio_alias;
     55    MemoryRegion *mmio_reg;
     56
     57    DeviceState *dev;
     58    PCIHostState *pci;
     59    qemu_irq *extints;
     60    int i;
     61
     62    dev = qdev_new(TYPE_GPEX_HOST);
     63    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     64
     65    /* Map only the first size_ecam bytes of ECAM space. */
     66    ecam_alias = g_new0(MemoryRegion, 1);
     67    ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
     68    memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
     69                             ecam_reg, 0, size_ecam);
     70    memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
     71
     72    /*
     73     * Map the MMIO window into system address space so as to expose
     74     * the section of PCI MMIO space which starts at the same base address
     75     * (ie 1:1 mapping for that part of PCI MMIO space visible through
     76     * the window).
     77     */
     78    mmio_alias = g_new0(MemoryRegion, 1);
     79    mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
     80    memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
     81                             mmio_reg, base_mmio, size_mmio);
     82    memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
     83
     84    /* Map IO port space. */
     85    pio_alias = g_new0(MemoryRegion, 1);
     86    pio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 2);
     87    memory_region_init_alias(pio_alias, OBJECT(dev), "pcie-pio",
     88                             pio_reg, 0, size_pio);
     89    memory_region_add_subregion(get_system_memory(), base_pio, pio_alias);
     90
     91    /* Connect IRQ lines. */
     92    extints = xtensa_get_extints(env);
     93
     94    for (i = 0; i < GPEX_NUM_IRQS; i++) {
     95        void *q = extints[irq_base + i];
     96
     97        sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, q);
     98        gpex_set_irq_num(GPEX_HOST(dev), i, irq_base + i);
     99    }
    100
    101    pci = PCI_HOST_BRIDGE(dev);
    102    if (pci->bus) {
    103        for (i = 0; i < nb_nics; i++) {
    104            NICInfo *nd = &nd_table[i];
    105
    106            if (!nd->model) {
    107                nd->model = g_strdup("virtio");
    108            }
    109
    110            pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
    111        }
    112    }
    113}
    114
    115static void xtensa_virt_init(MachineState *machine)
    116{
    117    XtensaCPU *cpu = xtensa_sim_common_init(machine);
    118    CPUXtensaState *env = &cpu->env;
    119
    120    create_pcie(env, 0, 0xf0000000);
    121    xtensa_sim_load_kernel(cpu, machine);
    122}
    123
    124static void xtensa_virt_machine_init(MachineClass *mc)
    125{
    126    mc->desc = "virt machine (" XTENSA_DEFAULT_CPU_MODEL ")";
    127    mc->init = xtensa_virt_init;
    128    mc->max_cpus = 32;
    129    mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
    130}
    131
    132DEFINE_MACHINE("virt", xtensa_virt_machine_init)