cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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pnv_occ.h (1833B)

      1/*
      2 * QEMU PowerPC PowerNV Emulation of a few OCC related registers
      3 *
      4 * Copyright (c) 2015-2017, IBM Corporation.
      5 *
      6 * This library is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU Lesser General Public
      8 * License as published by the Free Software Foundation; either
      9 * version 2.1 of the License, or (at your option) any later version.
     10 *
     11 * This library is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14 * Lesser General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU Lesser General Public
     17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18 */
     19
     20#ifndef PPC_PNV_OCC_H
     21#define PPC_PNV_OCC_H
     22
     23#include "hw/ppc/pnv_psi.h"
     24#include "qom/object.h"
     25
     26#define TYPE_PNV_OCC "pnv-occ"
     27OBJECT_DECLARE_TYPE(PnvOCC, PnvOCCClass,
     28                    PNV_OCC)
     29#define TYPE_PNV8_OCC TYPE_PNV_OCC "-POWER8"
     30DECLARE_INSTANCE_CHECKER(PnvOCC, PNV8_OCC,
     31                         TYPE_PNV8_OCC)
     32#define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9"
     33DECLARE_INSTANCE_CHECKER(PnvOCC, PNV9_OCC,
     34                         TYPE_PNV9_OCC)
     35
     36#define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000
     37#define PNV_OCC_SENSOR_DATA_BLOCK_SIZE   0x00025800
     38
     39struct PnvOCC {
     40    DeviceState xd;
     41
     42    /* OCC Misc interrupt */
     43    uint64_t occmisc;
     44
     45    PnvPsi *psi;
     46
     47    MemoryRegion xscom_regs;
     48    MemoryRegion sram_regs;
     49};
     50
     51
     52struct PnvOCCClass {
     53    DeviceClass parent_class;
     54
     55    int xscom_size;
     56    const MemoryRegionOps *xscom_ops;
     57    int psi_irq;
     58};
     59
     60#define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i)                               \
     61    (PNV_OCC_SENSOR_DATA_BLOCK_OFFSET + (i) * PNV_OCC_SENSOR_DATA_BLOCK_SIZE)
     62
     63#endif /* PPC_PNV_OCC_H */