cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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tcg-mo.h (2028B)

      1/*
      2 * Tiny Code Generator for QEMU
      3 *
      4 * Copyright (c) 2008 Fabrice Bellard
      5 *
      6 * Permission is hereby granted, free of charge, to any person obtaining a copy
      7 * of this software and associated documentation files (the "Software"), to deal
      8 * in the Software without restriction, including without limitation the rights
      9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10 * copies of the Software, and to permit persons to whom the Software is
     11 * furnished to do so, subject to the following conditions:
     12 *
     13 * The above copyright notice and this permission notice shall be included in
     14 * all copies or substantial portions of the Software.
     15 *
     16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22 * THE SOFTWARE.
     23 */
     24
     25#ifndef TCG_MO_H
     26#define TCG_MO_H
     27
     28typedef enum {
     29    /* Used to indicate the type of accesses on which ordering
     30       is to be ensured.  Modeled after SPARC barriers.
     31
     32       This is of the form TCG_MO_A_B where A is before B in program order.
     33    */
     34    TCG_MO_LD_LD  = 0x01,
     35    TCG_MO_ST_LD  = 0x02,
     36    TCG_MO_LD_ST  = 0x04,
     37    TCG_MO_ST_ST  = 0x08,
     38    TCG_MO_ALL    = 0x0F,  /* OR of the above */
     39
     40    /* Used to indicate the kind of ordering which is to be ensured by the
     41       instruction.  These types are derived from x86/aarch64 instructions.
     42       It should be noted that these are different from C11 semantics.  */
     43    TCG_BAR_LDAQ  = 0x10,  /* Following ops will not come forward */
     44    TCG_BAR_STRL  = 0x20,  /* Previous ops will not be delayed */
     45    TCG_BAR_SC    = 0x30,  /* No ops cross barrier; OR of the above */
     46} TCGBar;
     47
     48#endif /* TCG_MO_H */