cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

tcg-opc.h (11946B)

      1/*
      2 * Tiny Code Generator for QEMU
      3 *
      4 * Copyright (c) 2008 Fabrice Bellard
      5 *
      6 * Permission is hereby granted, free of charge, to any person obtaining a copy
      7 * of this software and associated documentation files (the "Software"), to deal
      8 * in the Software without restriction, including without limitation the rights
      9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10 * copies of the Software, and to permit persons to whom the Software is
     11 * furnished to do so, subject to the following conditions:
     12 *
     13 * The above copyright notice and this permission notice shall be included in
     14 * all copies or substantial portions of the Software.
     15 *
     16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22 * THE SOFTWARE.
     23 */
     24
     25/*
     26 * DEF(name, oargs, iargs, cargs, flags)
     27 */
     28
     29/* predefined ops */
     30DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
     31DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
     32
     33/* variable number of parameters */
     34DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT)
     35
     36DEF(br, 0, 0, 1, TCG_OPF_BB_END)
     37
     38#define IMPL(X) (__builtin_constant_p(X) && (X) <= 0 ? TCG_OPF_NOT_PRESENT : 0)
     39#if TCG_TARGET_REG_BITS == 32
     40# define IMPL64  TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
     41#else
     42# define IMPL64  TCG_OPF_64BIT
     43#endif
     44
     45DEF(mb, 0, 0, 1, 0)
     46
     47DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
     48DEF(setcond_i32, 1, 2, 1, 0)
     49DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
     50/* load/store */
     51DEF(ld8u_i32, 1, 1, 1, 0)
     52DEF(ld8s_i32, 1, 1, 1, 0)
     53DEF(ld16u_i32, 1, 1, 1, 0)
     54DEF(ld16s_i32, 1, 1, 1, 0)
     55DEF(ld_i32, 1, 1, 1, 0)
     56DEF(st8_i32, 0, 2, 1, 0)
     57DEF(st16_i32, 0, 2, 1, 0)
     58DEF(st_i32, 0, 2, 1, 0)
     59/* arith */
     60DEF(add_i32, 1, 2, 0, 0)
     61DEF(sub_i32, 1, 2, 0, 0)
     62DEF(mul_i32, 1, 2, 0, 0)
     63DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
     64DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
     65DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
     66DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
     67DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
     68DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
     69DEF(and_i32, 1, 2, 0, 0)
     70DEF(or_i32, 1, 2, 0, 0)
     71DEF(xor_i32, 1, 2, 0, 0)
     72/* shifts/rotates */
     73DEF(shl_i32, 1, 2, 0, 0)
     74DEF(shr_i32, 1, 2, 0, 0)
     75DEF(sar_i32, 1, 2, 0, 0)
     76DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
     77DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
     78DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
     79DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
     80DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
     81DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
     82
     83DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
     84
     85DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
     86DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
     87DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
     88DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
     89DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
     90DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
     91DEF(brcond2_i32, 0, 4, 2,
     92    TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL(TCG_TARGET_REG_BITS == 32))
     93DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
     94
     95DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
     96DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
     97DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
     98DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
     99DEF(bswap16_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap16_i32))
    100DEF(bswap32_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap32_i32))
    101DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
    102DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
    103DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
    104DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
    105DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
    106DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
    107DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
    108DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz_i32))
    109DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32))
    110DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32))
    111
    112DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
    113DEF(setcond_i64, 1, 2, 1, IMPL64)
    114DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
    115/* load/store */
    116DEF(ld8u_i64, 1, 1, 1, IMPL64)
    117DEF(ld8s_i64, 1, 1, 1, IMPL64)
    118DEF(ld16u_i64, 1, 1, 1, IMPL64)
    119DEF(ld16s_i64, 1, 1, 1, IMPL64)
    120DEF(ld32u_i64, 1, 1, 1, IMPL64)
    121DEF(ld32s_i64, 1, 1, 1, IMPL64)
    122DEF(ld_i64, 1, 1, 1, IMPL64)
    123DEF(st8_i64, 0, 2, 1, IMPL64)
    124DEF(st16_i64, 0, 2, 1, IMPL64)
    125DEF(st32_i64, 0, 2, 1, IMPL64)
    126DEF(st_i64, 0, 2, 1, IMPL64)
    127/* arith */
    128DEF(add_i64, 1, 2, 0, IMPL64)
    129DEF(sub_i64, 1, 2, 0, IMPL64)
    130DEF(mul_i64, 1, 2, 0, IMPL64)
    131DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
    132DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
    133DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
    134DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
    135DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
    136DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
    137DEF(and_i64, 1, 2, 0, IMPL64)
    138DEF(or_i64, 1, 2, 0, IMPL64)
    139DEF(xor_i64, 1, 2, 0, IMPL64)
    140/* shifts/rotates */
    141DEF(shl_i64, 1, 2, 0, IMPL64)
    142DEF(shr_i64, 1, 2, 0, IMPL64)
    143DEF(sar_i64, 1, 2, 0, IMPL64)
    144DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
    145DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
    146DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
    147DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
    148DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
    149DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64))
    150
    151/* size changing ops */
    152DEF(ext_i32_i64, 1, 1, 0, IMPL64)
    153DEF(extu_i32_i64, 1, 1, 0, IMPL64)
    154DEF(extrl_i64_i32, 1, 1, 0,
    155    IMPL(TCG_TARGET_HAS_extrl_i64_i32)
    156    | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
    157DEF(extrh_i64_i32, 1, 1, 0,
    158    IMPL(TCG_TARGET_HAS_extrh_i64_i32)
    159    | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
    160
    161DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL64)
    162DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
    163DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
    164DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
    165DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
    166DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
    167DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
    168DEF(bswap16_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
    169DEF(bswap32_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
    170DEF(bswap64_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
    171DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
    172DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
    173DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
    174DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
    175DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
    176DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
    177DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
    178DEF(clz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_clz_i64))
    179DEF(ctz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctz_i64))
    180DEF(ctpop_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctpop_i64))
    181
    182DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
    183DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
    184DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
    185DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
    186DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64))
    187DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64))
    188
    189#define TLADDR_ARGS  (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
    190#define DATA64_ARGS  (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
    191
    192/* QEMU specific */
    193DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS,
    194    TCG_OPF_NOT_PRESENT)
    195DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
    196DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
    197DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
    198
    199DEF(plugin_cb_start, 0, 0, 3, TCG_OPF_NOT_PRESENT)
    200DEF(plugin_cb_end, 0, 0, 0, TCG_OPF_NOT_PRESENT)
    201
    202DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1,
    203    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
    204DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1,
    205    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
    206DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
    207    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
    208DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
    209    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
    210
    211/* Only used by i386 to cope with stupid register constraints. */
    212DEF(qemu_st8_i32, 0, TLADDR_ARGS + 1, 1,
    213    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS |
    214    IMPL(TCG_TARGET_HAS_qemu_st8_i32))
    215
    216/* Host vector support.  */
    217
    218#define IMPLVEC  TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec)
    219
    220DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
    221
    222DEF(dup_vec, 1, 1, 0, IMPLVEC)
    223DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32))
    224
    225DEF(ld_vec, 1, 1, 1, IMPLVEC)
    226DEF(st_vec, 0, 2, 1, IMPLVEC)
    227DEF(dupm_vec, 1, 1, 1, IMPLVEC)
    228
    229DEF(add_vec, 1, 2, 0, IMPLVEC)
    230DEF(sub_vec, 1, 2, 0, IMPLVEC)
    231DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec))
    232DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
    233DEF(abs_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_abs_vec))
    234DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
    235DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
    236DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
    237DEF(ussub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
    238DEF(smin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
    239DEF(umin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
    240DEF(smax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
    241DEF(umax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
    242
    243DEF(and_vec, 1, 2, 0, IMPLVEC)
    244DEF(or_vec, 1, 2, 0, IMPLVEC)
    245DEF(xor_vec, 1, 2, 0, IMPLVEC)
    246DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
    247DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
    248DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
    249
    250DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
    251DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
    252DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
    253DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec))
    254
    255DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
    256DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
    257DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
    258DEF(rotls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rots_vec))
    259
    260DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
    261DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
    262DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
    263DEF(rotlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec))
    264DEF(rotrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec))
    265
    266DEF(cmp_vec, 1, 2, 1, IMPLVEC)
    267
    268DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec))
    269DEF(cmpsel_vec, 1, 4, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_cmpsel_vec))
    270
    271DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
    272
    273#if TCG_TARGET_MAYBE_vec
    274#include "tcg-target.opc.h"
    275#endif
    276
    277#ifdef TCG_TARGET_INTERPRETER
    278/* These opcodes are only for use between the tci generator and interpreter. */
    279DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT)
    280DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT)
    281#endif
    282
    283#undef TLADDR_ARGS
    284#undef DATA64_ARGS
    285#undef IMPL
    286#undef IMPL64
    287#undef IMPLVEC
    288#undef DEF