cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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neon-ls.decode (2022B)

      1# AArch32 Neon load/store instruction descriptions
      2#
      3#  Copyright (c) 2020 Linaro, Ltd
      4#
      5# This library is free software; you can redistribute it and/or
      6# modify it under the terms of the GNU Lesser General Public
      7# License as published by the Free Software Foundation; either
      8# version 2.1 of the License, or (at your option) any later version.
      9#
     10# This library is distributed in the hope that it will be useful,
     11# but WITHOUT ANY WARRANTY; without even the implied warranty of
     12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     13# Lesser General Public License for more details.
     14#
     15# You should have received a copy of the GNU Lesser General Public
     16# License along with this library; if not, see <http://www.gnu.org/licenses/>.
     17
     18#
     19# This file is processed by scripts/decodetree.py
     20#
     21
     22# Encodings for Neon load/store instructions where the T32 encoding
     23# is a simple transformation of the A32 encoding.
     24# More specifically, this file covers instructions where the A32 encoding is
     25#   0b1111_0100_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
     26# and the T32 encoding is
     27#   0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
     28# This file works on the A32 encoding only; calling code for T32 has to
     29# transform the insn into the A32 version first.
     30
     31%vd_dp  22:1 12:4
     32
     33# Neon load/store multiple structures
     34
     35VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
     36               vd=%vd_dp
     37
     38# Neon load single element to all lanes
     39
     40VLD_all_lanes  1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
     41               vd=%vd_dp
     42
     43# Neon load/store single structure to one lane
     44%imm1_5_p1 5:1 !function=plus_1
     45%imm1_6_p1 6:1 !function=plus_1
     46
     47VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
     48               vd=%vd_dp size=0 stride=1
     49VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 . align:1 rm:4 \
     50               vd=%vd_dp size=1 stride=%imm1_5_p1
     51VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 . align:2 rm:4 \
     52               vd=%vd_dp size=2 stride=%imm1_6_p1