cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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cpu-param.h (1201B)


      1/*
      2 * QEMU AVR CPU
      3 *
      4 * Copyright (c) 2016-2020 Michael Rolnik
      5 *
      6 * This library is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU Lesser General Public
      8 * License as published by the Free Software Foundation; either
      9 * version 2.1 of the License, or (at your option) any later version.
     10 *
     11 * This library is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14 * Lesser General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU Lesser General Public
     17 * License along with this library; if not, see
     18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
     19 */
     20
     21#ifndef AVR_CPU_PARAM_H
     22#define AVR_CPU_PARAM_H
     23
     24#define TARGET_LONG_BITS 32
     25/*
     26 * TARGET_PAGE_BITS cannot be more than 8 bits because
     27 * 1.  all IO registers occupy [0x0000 .. 0x00ff] address range, and they
     28 *     should be implemented as a device and not memory
     29 * 2.  SRAM starts at the address 0x0100
     30 */
     31#define TARGET_PAGE_BITS 8
     32#define TARGET_PHYS_ADDR_SPACE_BITS 24
     33#define TARGET_VIRT_ADDR_SPACE_BITS 24
     34#define NB_MMU_MODES 2
     35
     36#endif