cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

attribs_def.h.inc (4270B)


      1/*
      2 *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
      3 *
      4 *  This program is free software; you can redistribute it and/or modify
      5 *  it under the terms of the GNU General Public License as published by
      6 *  the Free Software Foundation; either version 2 of the License, or
      7 *  (at your option) any later version.
      8 *
      9 *  This program is distributed in the hope that it will be useful,
     10 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
     11 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     12 *  GNU General Public License for more details.
     13 *
     14 *  You should have received a copy of the GNU General Public License
     15 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
     16 */
     17
     18/* Keep this as the first attribute: */
     19DEF_ATTRIB(AA_DUMMY, "Dummy Zeroth Attribute", "", "")
     20
     21/* Misc */
     22DEF_ATTRIB(EXTENSION, "Extension instruction", "", "")
     23
     24DEF_ATTRIB(PRIV, "Not available in user or guest mode", "", "")
     25DEF_ATTRIB(GUEST, "Not available in user mode", "", "")
     26
     27DEF_ATTRIB(FPOP, "Floating Point Operation", "", "")
     28
     29DEF_ATTRIB(EXTENDABLE, "Immediate may be extended", "", "")
     30
     31DEF_ATTRIB(ARCHV2, "V2 architecture", "", "")
     32DEF_ATTRIB(ARCHV3, "V3 architecture", "", "")
     33DEF_ATTRIB(ARCHV4, "V4 architecture", "", "")
     34DEF_ATTRIB(ARCHV5, "V5 architecture", "", "")
     35
     36DEF_ATTRIB(SUBINSN, "sub-instruction", "", "")
     37
     38/* Load and Store attributes */
     39DEF_ATTRIB(LOAD, "Loads from memory", "", "")
     40DEF_ATTRIB(STORE, "Stores to memory", "", "")
     41DEF_ATTRIB(MEMLIKE, "Memory-like instruction", "", "")
     42DEF_ATTRIB(MEMLIKE_PACKET_RULES, "follows Memory-like packet rules", "", "")
     43
     44
     45/* Change-of-flow attributes */
     46DEF_ATTRIB(JUMP, "Jump-type instruction", "", "")
     47DEF_ATTRIB(INDIRECT, "Absolute register jump", "", "")
     48DEF_ATTRIB(CALL, "Function call instruction", "", "")
     49DEF_ATTRIB(COF, "Change-of-flow instruction", "", "")
     50DEF_ATTRIB(CONDEXEC, "May be cancelled by a predicate", "", "")
     51DEF_ATTRIB(DOTNEWVALUE, "Uses a register value generated in this pkt", "", "")
     52DEF_ATTRIB(NEWCMPJUMP, "Compound compare and jump", "", "")
     53
     54/* access to implicit registers */
     55DEF_ATTRIB(IMPLICIT_WRITES_LR, "Writes the link register", "", "UREG.LR")
     56DEF_ATTRIB(IMPLICIT_WRITES_SP, "Writes the stack pointer", "", "UREG.SP")
     57DEF_ATTRIB(IMPLICIT_WRITES_FP, "Writes the frame pointer", "", "UREG.FP")
     58DEF_ATTRIB(IMPLICIT_WRITES_LC0, "Writes loop count for loop 0", "", "UREG.LC0")
     59DEF_ATTRIB(IMPLICIT_WRITES_LC1, "Writes loop count for loop 1", "", "UREG.LC1")
     60DEF_ATTRIB(IMPLICIT_WRITES_SA0, "Writes start addr for loop 0", "", "UREG.SA0")
     61DEF_ATTRIB(IMPLICIT_WRITES_SA1, "Writes start addr for loop 1", "", "UREG.SA1")
     62DEF_ATTRIB(IMPLICIT_WRITES_P0, "Writes Predicate 0", "", "UREG.P0")
     63DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "", "UREG.P1")
     64DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2")
     65DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3")
     66DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the PC register", "", "")
     67DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "")
     68
     69DEF_ATTRIB(CRSLOT23, "Can execute in slot 2 or slot 3 (CR)", "", "")
     70DEF_ATTRIB(IT_NOP, "nop instruction", "", "")
     71DEF_ATTRIB(IT_EXTENDER, "constant extender instruction", "", "")
     72
     73
     74/* Restrictions to make note of */
     75DEF_ATTRIB(RESTRICT_SLOT0ONLY, "Must execute on slot0", "", "")
     76DEF_ATTRIB(RESTRICT_SLOT1ONLY, "Must execute on slot1", "", "")
     77DEF_ATTRIB(RESTRICT_SLOT2ONLY, "Must execute on slot2", "", "")
     78DEF_ATTRIB(RESTRICT_SLOT3ONLY, "Must execute on slot3", "", "")
     79DEF_ATTRIB(RESTRICT_NOSLOT1, "No slot 1 instruction in parallel", "", "")
     80DEF_ATTRIB(RESTRICT_PREFERSLOT0, "Try to encode into slot 0", "", "")
     81
     82DEF_ATTRIB(ICOP, "Instruction cache op", "", "")
     83
     84DEF_ATTRIB(HWLOOP0_END, "Ends HW loop0", "", "")
     85DEF_ATTRIB(HWLOOP1_END, "Ends HW loop1", "", "")
     86DEF_ATTRIB(DCZEROA, "dczeroa type", "", "")
     87DEF_ATTRIB(ICFLUSHOP, "icflush op type", "", "")
     88DEF_ATTRIB(DCFLUSHOP, "dcflush op type", "", "")
     89DEF_ATTRIB(DCFETCH, "dcfetch type", "", "")
     90
     91DEF_ATTRIB(L2FETCH, "Instruction is l2fetch type", "", "")
     92
     93DEF_ATTRIB(ICINVA, "icinva", "", "")
     94DEF_ATTRIB(DCCLEANINVA, "dccleaninva", "", "")
     95
     96/* Keep this as the last attribute: */
     97DEF_ATTRIB(ZZ_LASTATTRIB, "Last attribute in the file", "", "")