cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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cpu-qom.h (1504B)

      1/*
      2 * QEMU MIPS CPU
      3 *
      4 * Copyright (c) 2012 SUSE LINUX Products GmbH
      5 *
      6 * This library is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU Lesser General Public
      8 * License as published by the Free Software Foundation; either
      9 * version 2.1 of the License, or (at your option) any later version.
     10 *
     11 * This library is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14 * Lesser General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU Lesser General Public
     17 * License along with this library; if not, see
     18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
     19 */
     20#ifndef QEMU_MIPS_CPU_QOM_H
     21#define QEMU_MIPS_CPU_QOM_H
     22
     23#include "hw/core/cpu.h"
     24#include "qom/object.h"
     25
     26#ifdef TARGET_MIPS64
     27#define TYPE_MIPS_CPU "mips64-cpu"
     28#else
     29#define TYPE_MIPS_CPU "mips-cpu"
     30#endif
     31
     32OBJECT_DECLARE_TYPE(MIPSCPU, MIPSCPUClass,
     33                    MIPS_CPU)
     34
     35/**
     36 * MIPSCPUClass:
     37 * @parent_realize: The parent class' realize handler.
     38 * @parent_reset: The parent class' reset handler.
     39 *
     40 * A MIPS CPU model.
     41 */
     42struct MIPSCPUClass {
     43    /*< private >*/
     44    CPUClass parent_class;
     45    /*< public >*/
     46
     47    DeviceRealize parent_realize;
     48    DeviceReset parent_reset;
     49    const struct mips_def_t *cpu_def;
     50
     51    /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
     52    bool no_data_aborts;
     53};
     54
     55
     56#endif